• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors
• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge
• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
• 5V/3.3V Regulator and Current Limitation Function
• Reset Derived From 5V/3.3V Regulator Output Voltage
• Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2
or on LIN Interface
• A Programmable Window Watchdog
• Battery Overvoltage Protection and Battery Undervoltage Management
• Overtemperature Warning and Protection (Shutdown)
• LIN 2.0 Compliant
• 3.3V/5V Regulator with Trimmed Band Gap
• QFN32 Package
1.Description
The ATA6823 is designed for several body and powertrain applications. The IC is
used to drive a continuous current motor in a full H-bridge configuration. An external
microcontroller controls the driving function of the IC by providing a PWM signal and a
direction signal and allows the use of the IC in a motor-control application. The PWM
control is performed by the low-side switch; the high-side switch is permanently on in
the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for
regulator and interface high level). The window watchdog has a programmable time,
programmable by choosing a certain value of the external watchdog resistor RWD,
internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is
integrated.
H-bridge Motor
Driver
ATA6823
Preliminary
4856E–AUTO–07/07
Figure 1-1.Block Diagram
M
CP
VRESH2
CPLO
Charge
Pump
CPIH
VG
PBAT
VBAT
CP
VINT
VBAT
VBATSW
12V
Regulator
Vint 5V
Regulator
VCC 5V
Regulator
VCC
R
GATE
HS Driver 2
OTP
12 bit
Oscillator
VBG
Bandgap
VMODE/RESET
R
GATE
H1
HS Driver 1
Logic Control
EN1
WD
S1S2L2
DIR
R
GATE
LS Driver 1
PWM
R
GATE
LS Driver 2
OT
UV
Supervisor
OV
CC timer
WD timer
LIN
TXRX
PGNDL1
VBAT
VCC
GND
DG3
DG2
DG1
CC
EN2
LIN
Microcontroller
Battery
2
ATA6823 [Preliminary]
4856E–AUTO–07/07
2.Pin Configuration
/
Figure 2-1.Pinning QFN32
VMODE
VINT
RWD
CC
RESET
WD
GND
LIN
EN2
VBATSW
VBAT
VCC
PGNDL1L2
32 31 30 29 28 27 26 25
1
2
3
Atmel YWW
4
5
6
7
8
ATA6823
ZZZZZ-AL
9 10 11 12 13 14 15 16
PBAT
24
23
22
21
20
19
18
17
ATA6823 [Preliminary]
VG
CPLO
CPHI
VRES
H2
S2
H1
S1
Table 2-1.Pin Description
PinSymbolI/OFunction
1VMODEISelector for V
2VINTI/OBlocking capacitor 220 nF/10V/X7R
3RWDIResistor defining the watchdog interval
4CCI/ORC combination to adjust cross conduction time
5/RESETOReset signal for microcontroller
6WDIWatchdog trigger signal
7GNDIGround for chip core
8LINI/OLIN-bus terminal
9TXITransmit signal to LIN bus from microcontroller
10DIRIDefines the rotation direction for the motor
11PWMIPWM input controls motor speed
12EN1IMicrocontroller output to keep the chip in Active mode
13RXOReceive signal from LIN bus for microcontroller
14DG3ODiagnostic output 3
15DG2ODiagnostic output 2
16DG1ODiagnostic output 1
17S1I/OSource voltage H-bridge, high-side 1
18H1OGate voltage H-bridge, high-side 1
19S2I/OSource voltage H-bridge, high-side 2
20H2OGate voltage H-bridge, high-side 2
21VRESI/OGate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R
TX
DIR
EN1
PWM
RX
DG3
DG2
DG1
Note:YWW Date code (Y = Year - above 2000, WW = week number)
ATA6823 Product name
ZZZZZ Wafer lot number
AL Assembly sub-lot number
and interface logic voltage level
CC
4856E–AUTO–07/07
3
Table 2-1.Pin Description (Continued)
PinSymbolI/OFunction
22CPHII
23CPLOO
24VGI/OBlocking capacitor 470 nF/25V/X7R
25PBATIPower supply (after reverse protection) for charge pump and H-bridge
26L2OGate voltage H-bridge, low-side 2
27L1OGate voltage H-bridge, low-side 1
28PGNDIPower ground for H-bridge and charge pump
29VCCO5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R
30VBATISupply voltage for IC core (after reverse protection)
31VBATSWO100Ω PMOS switch from V
32EN2I Enable input
Charge pump capacitor 220 nF/25V/X7R
BAT
3.General Statement and Conventions
• Parameter values given without tolerances are indicative only and not to be tested in
production
• Parameters given with tolerances but without a parameter number in the first column of
parameter table are “guaranteed by design” (mainly covered by measurement of other
specified parameters). These parameters are not to be tested in production. The tolerances
are given if the knowledge of the parameter tolerances is important for the application
• The lowest power supply voltage is named GND
• All voltage specifications are referred to GND if not otherwise stated
• Sinking current means that the current is flowing into the pin (value is positive)
• Sourcing current means that the current is flowing out of the pin (value is negative)
3.1Related Documents
• Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100
• AEC-Q100-004 and JESD78 (Latch-up)
• ESD STM 5.1-1998
• CEI 801-2 (only for information regarding ESD requirements of the PCB)
4
ATA6823 [Preliminary]
4856E–AUTO–07/07
4.Application
4.1General Remark
This chapter describes the principal application for which the ATA6823 was designed. Because
Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given.
Table 4-1.Typical External Components
ATA6823 [Preliminary]
Component FunctionValueTolerance
C
C
C
R
C
C
C
R
C
VINT
VCC
CC
CC
VG
CP
VRES
RWD
LIN
Blocking capacitor at VINT220 nF, 10V, X7R10%
Blocking capacitor at VCC2.2 µF, 10V, X7R10%
Cross conduction time definition capacitorTypical 330 pF, 100V, COG
Cross conduction time definition resistorTypical 10 kΩ
Blocking capacitor at VG470 nF, 25V, X7R10%
Charge pump capacitor220 nF, 25V, X7R10%
Reservoir capacitor470 nF, 25V, X7R10%
Watchdog time definition resistorTypical 51 kΩ1%
Filter capacitor for LIN busTypical 220 pF, 100V10%
5.Functional Description
5.1Power Supply Unit with Supervisor Functions
5.1.1Power Supply
The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper
external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT
pin of the IC (see Figure 1-1 on page 2).
A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor
provides the necessary low-voltage supply needed for the wake-up process. The low-power
band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks
are supplied by the internal regulator.
Note:The internal supply voltage V
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V
VCC regulator.
A power-good comparator checks the output voltage of the V
chip in reset as long as the voltage is too low.
There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a
watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on
external voltage regulators, etc.
must not be used for any other supply purpose!
INT
regulator and keeps the whole
INT
4856E–AUTO–07/07
5
5.1.2Voltage Supervisor
This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it.
Function: in case of both overvoltage alarm (V
nal NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2.
No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz.
5.1.3Temperature Supervisor
There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a
failure in the external circuitry and to protect the external NMOSFET transistors.
In case of detected overtemperature (150°C), the diagnostic pin DG3 will be switched to “H” to
signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165°C), the V
including the LIN transceiver will be switched OFF immediately and /RESET will go LOW.
Both temperature thresholds are correlated. The absolute tolerance is ±10°C and there is a
built-in hysteresis of about 10°C to avoid fast oscillations. After cooling down below the 155°C
threshold; the IC will go into Active mode.
The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically
165°C.
5.2Sleep Mode
To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep
mode, the following blocks are active:
) and of undervoltage alarm (V
THOV
CC
) the exter-
THUV
regulator and all drivers
• Band gap
• Internal 5V regulator (VINT) with external blocking capacitor of 220 nF
• Input structure for detecting the EN2 pins threshold
• Wake-up block of the LIN receive part
5.3Wake-up and Sleep Mode Strategy
The IC has two modes: Sleep and Active. The change between the modes is described below.
The default state after power-on is Active mode.
The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active).
The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver
are permanently active to ensure a proper startup of the system.
The Go to Active and Go to Sleep procedures are implemented as follows:
• Go to Active by activating pin EN2
The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists
of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and V
this reason the input voltage level must be positive and not higher than V
BAT
; for
BAT
.
6
ATA6823 [Preliminary]
4856E–AUTO–07/07
ATA6823 [Preliminary]
Pulling the EN2 pin up to the V
level will drive the IC into Active mode. EN2 is debounced with
BAT
a time constant of 20 µs, based on a 100 kHz clock.
• Go to Active using the LIN interface
The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode,
the LIN receiver is partially active.
The wake-up by LIN requires 2 steps:
1. If the voltage on pin LIN is below a value of V
/DATwake
(about V
– 2V) the receive part
VBAT
of the LIN interface is active (not to be confused with Active mode of the whole IC). The
active receive part is able to detect a valid LOW on the LIN pin.
2. If LIN = LOW during a filter time t
(typically 70 µs) the IC will change to Active
wakeLIN
mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode
If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without
disturbing the Active mode.
• Stay in Active via EN1
The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller.
The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must
be positive and not higher than V
the VCC regulator is off in the Sleep mode and V
. EN1 cannot be used to switch from Sleep to Active because
CC
will be zero.
CC
• Go to Sleep
A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t
gotosleep
(typically 20 µs) switches the IC to Sleep mode.
Figure 5-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the acti-
vated receive block of the LIN interface. After going to Active mode, the V
regulator starts
CC
working.
Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for
longer than t
) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before.
db
4856E–AUTO–07/07
7
Figure 5-1.Wake-up by pin LIN
LIN
VBAT
EN1
RX
t < t
wake LIN
45% VBAT
t
wake LIN
VBAT - 1.5V
activating
55% VBAT
"PREWAKE"
t
t
db
t
STATUS
ACTIVE
SLEEP
t
t
db
t
8
ATA6823 [Preliminary]
4856E–AUTO–07/07
5.45V/3.3V VCC Regulator
/
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for
stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be
selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to
be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The
logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.
ATA6823 [Preliminary]
The output voltage accuracy is in general < ±3%; in the 5V mode with V
<5%.
To prevent destruction of the IC, the current delivered by the regulator is limited to maximum
160 mA to 320 mA. The delivered voltage will break down and a reset may occur.
Please note that this regulator is the main heat source on the chip. The maximum output current
at maximum battery voltage and high ambient temperature can only guaranteed if the IC is
mounted on an efficient heat sink.
A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low.
5.5Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period T
adjustable via the external resistor R
The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD
input within a period time window of T
switched off during Sleep mode.
Figure 5-2.Timing Diagram of the Watchdog Function
res
< 8V it is limited to
VBAT
.
WD
. In order to save current consumption, the watchdog is
WD
t
resshortt
OSC
is
RESET
WD
5.5.1Timing Sequence
4856E–AUTO–07/07
t
d
t
1
t
2
For example, with an external resistor R
of the watchdog.
= 68 ms and td= 68 ms are fixed values with a tolerance of 10%.
res
t
d
t
1
=33kΩ ±1% we get the following typical parameters
WD
t
2
9
After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The
0
reset output, /RESET, stays low for the time t
initial lead time t
(typically 68 ms for setups in the controller) the watchdog waits for a rising
d
(typically 68 ms), then switches to high. For an
res
edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the
watchdog will reset the microcontroller for t
Times t
(close window) and t2 (open window) form the window watchdog sequence. To avoid
1
and wait td for the rising edge on WD.
res
receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the
timeframe of t
= 9.61 ms. The trigger event will restart the watchdog sequence.
2
Figure 5-3.T
versus RWD
WD
60
50
40
30
TWD (ms)
20
10
max
min
0
10203040506070809010
RWD (kΩ)
typ
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms.
The watchdog start sequence is similar to the power-on reset.
The internal oscillator is trimmed to a tolerance of < ±10%. This means that t
and t2 can also
1
vary by ±10%. The following calculation shows the worst case calculation of the watchdog
period T
t
= 0.90 × t1 = 10.87 ms, t
1min
t
= 0.90 × t2 = 8.65ms, t
2min
T
wdmax
T
wdmin
T
= 16.42 ms ±3.15 ms (±19.1%)
wd
Figure 5-3 above shows the typical watchdog period T
resistor R
A reset will be active for V
which the microcontroller has to provide.
wd
= 1.10 × t1 = 13.28 ms
1max
= 1.10 × t2 = 10.57 ms
2max
= t
+ t
= 10.87 ms + 8.65 ms = 19.52 ms
2min
= 13.28 ms
.
CC
< V
tHRESx
; the level V
= t
1min
1max
OSC
depending on the value of the external
WD
is realized with a hysteresis (HYS
tHRESx
RESth
).
5.6LIN Transceiver
10
ATA6823 [Preliminary]
A bi-directional bus interface is implemented for data transfer between the LIN bus and the local
LIN protocol controller.
The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the
receiver.
4856E–AUTO–07/07
5.6.1Transmit Mode
During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus
signal on pin LIN.
To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew
rate control and wave-shaping unit. Transmission will be interrupted in the following cases:
• Thermal shutdown active or overtemperature LIN active
• Sleep mode
Figure 5-4.Definition of Bus Timing Parameters
ATA6823 [Preliminary]
TXD
(input to transmitting Node)
TH
Rec(max)
V
S
(Transceiver
supply
of transmitting
node)
TH
TH
TH
Dom(max)
Rec(min)
Dom(min)
RXD
(output of receiving Node 1)
RXD
(output of receiving Node 2)
t
Bit
LIN Bus Signal
t
rx_pdf(1)
t
Bus_dom(max)
t
Bus_dom(min)
t
Bit
t
Bus_rec(min)
t
Bit
Thresholds of
receiving node 1
Thresholds of
receiving node 2
t
Bus_rec(max)
t
rx_pdr(1)
t
rx_pdr(2)
t
rx_pdf(2)
The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an
active diode. This diode prevents the reverse current of VBUS during differential voltage
between VSUP and BUS (V
No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC
is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 kΩ
resistor in series with a diode to VBAT.
5.6.2TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from
being driven permanently in dominant state. If TXD is forced low longer than t
pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 µs)
before switching LIN to dominant again.
4856E–AUTO–07/07
BUS>VSUP
).
> 18.4 ms, the
dom
11
5.7Control Inputs EN1, EN2, DIR, PWM
5.7.1Pins EN1, EN2
Any of the enable pins may be used to activate the IC with a HIGH. EN1 is a low level input, EN2
has to withstand a voltage up to 40V. Internal pull-down resistors are included.
5.7.2Pin DIR
Logical input to control the direction of the external motor to be controlled by the IC. An internal
pull-down resistor is included.
5.7.3Pin PWM
Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.
Table 5-1.Status of the IC Depending on Control Inputs and Detected Failures
Control InputsDriver Stage for External Power MOSComments
ONDIRPWMH1L1H2L2
0XXOFFOFFOFFOFFStandby mode
10PWMONOFF/PWMPWM Motor PWM forward
11PWM/PWMPWMONOFFMotor PWM reverse
The internal signal ON is high when
• At least one valid trigger has been accepted (SYNC = 1)
•V
is inside the specified range (UV = 0 and nOV = 1)
BAT
• The charge pump has reached its minimum voltage (CPOK = 1) and
• The device is not overheated (OT2 = 0)
In case of a short circuit, the appropriate transistor is switched off after a debounce time of about
10 µs. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination.
OT1: Overtemperature warning
OV: Overvoltage of VBAT
UV: Undervoltage of VBAT
SC: Short circuit
CPOK: Charge pump OK
12
In order to be able to distinguish between a wake-up from LIN or from EN2, the source of
wake-up is flagged in DG1 until the first valid trigger (LIN = 0, EN2 = 1).
ATA6823 [Preliminary]
4856E–AUTO–07/07
5.8VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage
will be used as one input for the charge pump, which generates the gate voltage for the
high-side driver. The purpose of the regulator is to limit the gate voltage for the external power
MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
5.9Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the
output voltage on the reservoir capacitor is V
dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC
level.
5.10Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning
level will be reached at 150°C. At this point the IC stays fully functional and a warning will be
sent to the microcontroller. At junction temperature 165°C the VCC regulator will be switched off
and a reset occurs.
ATA6823 [Preliminary]
plus VG. The charge pump is clocked with a
BAT
5.11H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side
drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is
possible to control the external load (motor) in the forward and reverse direction (see Table 5-1
on page 12). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in
both directions.
5.11.1Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in
the following way:
The RC combination is charged to 5V and the switching level of the internal comparator is 67%
of the start level.
The resistor R
value has to be ≤ 5 nF. Use of COG capacitor material is recommended.
The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the C
CC
CC
4856E–AUTO–07/07
13
Figure 5-5.Timing of the Drivers
PWM or
DIR
Lx
Hx
t
LxHLtLxf
t
HxLH
t
CC
50%
t
Hxr
80%
20%
80%
t
LxLH
t
CC
t
HxHLtHxf
t
t
Lxr
t
The delays t
5.12Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference
between source and drain of the external power NMOS. If the transistors are switched ON and
the source-drain voltage difference is higher than the value V
>t
(typically 10 µs) the signal SC (short circuit) will be set and the drivers will be switched off
SC
immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the
bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on
again.
There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT
during a short circuit. If the voltage at PBAT falls under V
>t
the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as
SC
above.
HxLH
and t
20%
include the cross conduction time tCC.
LxLH
(4V with tolerances) for a time
SC
(5.6V with tolerances) for a time
SCPB
t
14
ATA6823 [Preliminary]
4856E–AUTO–07/07
ATA6823 [Preliminary]
6.Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin DescriptionPin NameMinMaxUnit
GroundGND00V
Power groundPGND–0.3+0.3V
Reverse protected battery voltageVBAT–0.3+40V
Reverse protected battery voltagePBAT–0.3+40V
Digital output/RESET–0.3V
Digital outputDG1, DG2, DG3–0.3V
4.9V output, external blocking capacitorVINT–0.3+5.5V
Cross conduction time capacitor/resistor
combination
CC–0.3V
Digital input coming from microcontrollerWD–0.3V
Watchdog timing resistorRWD–0.3V
Digital input direction controlDIR–0.3V
Digital input PWM control + Test modePWM–0.3V
Digital input for enable controlEN1–0.3V
Digital input for enable controlEN2–0.3V
5V regulator outputVCC–0.3+5.5V
Digital inputVMODE–0.3V
12V output, external blocking capacitorVG–0.3+16V
Digital outputRX–0.3V
Digital inputTX–0.3V
LIN data pinLIN–27
Charge pumpCPLO–0.3V
Charge pumpCPHI–0.3V
Charge pump outputVRES–0.3+30V
Switched VBATVBATSW–0.3V
Power dissipationP
Storage temperatureϑ
Soldering temperature (10s)ϑ
Notes: 1. For V
VBAT
≤ 13.5V
tot
STORE
SOLDERING
–40+150°C
2. May be additionally limited by external thermal resistance
+ 0.3V
VCC
+ 0.3V
VCC
+ 0.3V
VINT
+ 0.3V
VINT
+ 0.3V
VCC
+ 0.3V
VCC
+ 0.3V
VCC
+ 0.3V
VCC
+ 0.3V
VBAT
+ 0.3V
VINT
+ 0.3V
VCC
+ 0.3V
VCC
V
+ 2V
VBAT
+ 0.3V
VG
+ 0.3V
PBAT
+ 0.3V
VRES
+ 0.3V
VBAT
(2)
1.4
240°C
W
4856E–AUTO–07/07
15
7.Thermal Resistance
ParametersSymbolValueUnit
Thermal resistance junction to heat slugR
Thermal resistance junction to ambient when heat
slug is soldered to PCB
thjc
R
thja
<5K/W
25K/W
8.Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these
limits is not implied unless otherwise stated explicitly.
ParametersSymbolMinMaxUnit
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
Operating supply voltage
(1)
(2)
(3)
(4)
(5)
Ambient temperature range under biasT
Normal functionalityT
Normal functionality, overtemperature warningT
Drivers for H1, H2, L1, L2, and LIN are switched
OFF, VCC regulator is OFF
Note:1. Full functionality
2. H-bridge drivers may be switched off (undervoltage detection)
3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly
4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct
5. H-bridge drivers are switched off
V
V
V
V
V
VBAT1
VBAT2
VBAT3
VBAT4
VBAT5
a
a
a
T
a
718V
6< 7V
3< 6V
0< 3V
> 2040V
–40+125°C
–40+125°C
150165°C
165180°C
16
ATA6823 [Preliminary]
4856E–AUTO–07/07
ATA6823 [Preliminary]
9.Electrical Characteristics
All parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 125°C unless stated otherwise.
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. EN, DIR, PWM = high
2. The use of X7R material is recommended
3. For higher values, stability at zero load is not guaranteed
4. Tested during qualification only
5. Value depends on T
6. Tested during characterization only
7. Supplied by charge pump
8. See section “Cross Conduction Time”
9. Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < t
CC
(9)
(10)
(6)
(6)
(6)
= 0.4V
DG
= VCC – 0.4V
DG
; function tested with digital test pattern
OSC
(6)
V
swtcc
V
SC
t
SC
V
V
0.653 ×
V
3.544.5V
IL
IH
2.33.6V
2.84.0V
VCC
0.667 ×
V
VCC
0.68 ×
V
VCC
51015ms
HYS0.47V
PD
rf
t
db
50100200kΩ
100ns
2 × T
100
3 × T
100
IL4mA
IH4mA
sc
V
µs
4856E–AUTO–07/07
23
10. Schaffner and Electromagnetic Compatibility
10.1Transients on Power-supply Rail (Battery)
The application (including IC and external protection circuitry, see Figure 1-1 on page 2) has to
withstand the test pulses in Table 10-1.
Table 10-1.Test Pulses
Test
Pulse No.
1–100V10 minR
2150V10 minR
3a–200V10 minR
3b200V10 minR
44V/5.5V15 ms/2sR
540V
Test
Level
Duration or Number
of PulsesSpecs
5 pulses, 1 minute
recurrence period
Acceptance
= 10ΩA
i
= 10ΩA
i
= 50ΩA
i
= 50ΩA
i
= 0.01ΩA
i
R
= 0.5Ω, td = 400 ms, tr = 5 msB
i
level
Figure 10-1. Pulse 1 (R
V
12V
-100V
Figure 10-2. Pulse 2 (R
150V
= 10Ω)
i
90%
= 10Ω)
i
V
200 ms
< 100 µs
t10%
1 µs
1 ms
5s
200 ms
50 µs
2 µs
90%
24
12V
ATA6823 [Preliminary]
10%
50 µs
t
4856E–AUTO–07/07
Figure 10-3. Pulse 3a (Ri = 50Ω)
V
12V
-200V
10 ms
100 µs
90 ms
ATA6823 [Preliminary]
100 ns
5 ns
t
10%
90%
Figure 10-4. Pulse 3b (R
V
200V
12V
100 µs
Figure 10-5. Pulse 4 (R
12V
= 50Ω)
i
= 0.01Ω)
i
90%
10%
90 ms10 ms
t
5 ns
100 ns
4856E–AUTO–07/07
5.5V
4.0V
0V
t
15 ms2000 ms50 ms100 ms< 5 ms
25
10.2Transients on Pin LIN
Transients to these pins are coupled capacitively to the IC and are valid for the application with
external circuitry concerning figure 6.
Values: Pulse 3a, Pulse 3b (see Figure 10-3 and Figure 10-4 on page 25) coupled via 1 nF to
LIN, R
Acceptance level A
=50Ω
i
10.3Conducted Emissions, Radiated Emissions and Susceptibility
The application using the IC described in this specification has to fulfill the demands of the following specifications:
• GM GMW3100 (2001-08)
• TL82166 (1998-02)
• TL82366 (2002-03)
• TL965 (1999-10)
It is the responsibility of both the deliverer and the user of the described IC to meet the mentioned specifications.
11. ESD and Latch-up Requirements
The device withstands pulses when tested according to ESD STM 5.1-1998:
• Constant voltage 2 kV
• R = 1.5 kΩ
• C = 100 pF
1 pulse per polarity and per pin
3 samples, 0 failures
Electrical post stress testing at room temperature
Static latch-up tested according to AEC-Q100-004 and JESD78.
• 3 to 6 samples, 0 failures
• Electrical post stress testing at room temperature
In test, the voltage at the pins VBAT, LIN, CP, VBATSW, Hx, and Sx must not exceed 45V when
not able to drive the specified current.
26
ATA6823 [Preliminary]
4856E–AUTO–07/07
ATA6823 [Preliminary]
12. Ordering Information
Extended Type NumberPackageRemarks
ATA6823-PHQYQFN32Pb-free
13. Package Information
Package: QFN 32 - 7 x 7
Exposed pad 4.7 x 4.7
Dimensions in mm
Not indicated tolerances ± 0.05
32
1
8
Drawing-No.: 6.543-5097.01-4
Issue: 1; 24.02.03
14. Revision History
0.9±0.1
+0
0.05-0.05
0.3
0.6
24
17
7
4.7
3225
1
technical drawings
according to DIN
specifications
8
916
0.65 nom.
4.55
4856E–AUTO–07/07
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.History
4856E-AUTO-07/07• Put datasheet in a new template
27
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