Rainbow Electronics ATA6823 User Manual

Features

• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors

• A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge

• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply

the Gate of the External Battery Reverse Protection NMOS

• 5V/3.3V Regulator and Current Limitation Function

• Reset Derived From 5V/3.3V Regulator Output Voltage

• Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2

or on LIN Interface

• A Programmable Window Watchdog

• Battery Overvoltage Protection and Battery Undervoltage Management

• Overtemperature Warning and Protection (Shutdown)

• LIN 2.0 Compliant

• 3.3V/5V Regulator with Trimmed Band Gap

• QFN32 Package

1. Description

The ATA6823 is designed for several body and powertrain applications. The IC is used to drive a continuous current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the IC by providing a PWM signal and a direction signal and allows the use of the IC in a motor-control application. The PWM control is performed by the low-side switch; the high-side switch is permanently on in the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for regulator and interface high level). The window watchdog has a programmable time, programmable by choosing a certain value of the external watchdog resistor RWD, internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is integrated.

H-bridge Motor Driver

ATA6823

Preliminary

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Figure 1-1. Block Diagram

VRES H2

CPLO

Charge

Pump

CPIH

PBAT

VBAT

VINT

VBAT

VBATSW

12V

Regulator

Vint 5V

Regulator

VCC 5V

Regulator

VCC

GATE

HS Driver 2

OTP

12 bit

Oscillator

VBG

Bandgap

VMODE /RESET

GATE

HS Driver 1

Logic Control

EN1

S1 S2 L2

DIR

GATE

LS Driver 1

PWM

GATE

LS Driver 2

Supervisor

CC timer

WD timer

LIN

TXRX

PGNDL1

VBAT

VCC

GND

DG3

DG2

DG1

EN2

LIN

Microcontroller

Battery

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2. Pin Configuration

Figure 2-1. Pinning QFN32

VMODE

VINT RWD

RESET

GND

LIN

EN2

VBATSW

VBAT

VCC

PGNDL1L2

32 31 30 29 28 27 26 25

1 2 3

Atmel YWW

4 5 6 7 8

ATA6823

ZZZZZ-AL

9 10 11 12 13 14 15 16

PBAT

24 23 22 21 20 19 18 17

ATA6823 [Preliminary]

VG CPLO CPHI VRES H2 S2 H1 S1

Table 2-1. Pin Description

Pin Symbol I/O Function

1 VMODE I Selector for V 2 VINT I/O Blocking capacitor 220 nF/10V/X7R 3 RWD I Resistor defining the watchdog interval 4 CC I/O RC combination to adjust cross conduction time 5 /RESET O Reset signal for microcontroller 6 WD I Watchdog trigger signal 7 GND I Ground for chip core 8 LIN I/O LIN-bus terminal

9 TX I Transmit signal to LIN bus from microcontroller 10 DIR I Defines the rotation direction for the motor 11 PWM I PWM input controls motor speed 12 EN1 I Microcontroller output to keep the chip in Active mode 13 RX O Receive signal from LIN bus for microcontroller 14 DG3 O Diagnostic output 3 15 DG2 O Diagnostic output 2 16 DG1 O Diagnostic output 1 17 S1 I/O Source voltage H-bridge, high-side 1 18 H1 O Gate voltage H-bridge, high-side 1 19 S2 I/O Source voltage H-bridge, high-side 2 20 H2 O Gate voltage H-bridge, high-side 2 21 VRES I/O Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R

DIR

EN1

PWM

DG3

DG2

DG1

Note: YWW Date code (Y = Year - above 2000, WW = week number)

ATA6823 Product name ZZZZZ Wafer lot number AL Assembly sub-lot number

and interface logic voltage level

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Table 2-1. Pin Description (Continued)

Pin Symbol I/O Function

22 CPHI I 23 CPLO O 24 VG I/O Blocking capacitor 470 nF/25V/X7R 25 PBAT I Power supply (after reverse protection) for charge pump and H-bridge 26 L2 O Gate voltage H-bridge, low-side 2 27 L1 O Gate voltage H-bridge, low-side 1 28 PGND I Power ground for H-bridge and charge pump 29 VCC O 5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R 30 VBAT I Supply voltage for IC core (after reverse protection) 31 VBATSW O 100Ω PMOS switch from V 32 EN2 I Enable input

Charge pump capacitor 220 nF/25V/X7R

BAT

3. General Statement and Conventions

• Parameter values given without tolerances are indicative only and not to be tested in production

• Parameters given with tolerances but without a parameter number in the first column of parameter table are “guaranteed by design” (mainly covered by measurement of other specified parameters). These parameters are not to be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the application

• The lowest power supply voltage is named GND

• All voltage specifications are referred to GND if not otherwise stated

• Sinking current means that the current is flowing into the pin (value is positive)

• Sourcing current means that the current is flowing out of the pin (value is negative)

3.1 Related Documents

• Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100

• AEC-Q100-004 and JESD78 (Latch-up)

• ESD STM 5.1-1998

• CEI 801-2 (only for information regarding ESD requirements of the PCB)

ATA6823 [Preliminary]

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4. Application

4.1 General Remark

This chapter describes the principal application for which the ATA6823 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given.

Table 4-1. Typical External Components

ATA6823 [Preliminary]

Component Function Value Tolerance

C C C R C C C R C

VINT

VCC

VRES

RWD

LIN

Blocking capacitor at VINT 220 nF, 10V, X7R 10% Blocking capacitor at VCC 2.2 µF, 10V, X7R 10% Cross conduction time definition capacitor Typical 330 pF, 100V, COG Cross conduction time definition resistor Typical 10 kΩ Blocking capacitor at VG 470 nF, 25V, X7R 10% Charge pump capacitor 220 nF, 25V, X7R 10% Reservoir capacitor 470 nF, 25V, X7R 10% Watchdog time definition resistor Typical 51 kΩ 1% Filter capacitor for LIN bus Typical 220 pF, 100V 10%

5. Functional Description

5.1 Power Supply Unit with Supervisor Functions

5.1.1 Power Supply

The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2).

A fully-internal low-power and low-drop regulator, stabilized by an external blocking capacitor provides the necessary low-voltage supply needed for the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator.

Note: The internal supply voltage V

Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator.

A power-good comparator checks the output voltage of the V chip in reset as long as the voltage is too low.

There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset going to sleep mode, VBATSW turns OFF. The signal can be used to switch on external voltage regulators, etc.

must not be used for any other supply purpose!

INT

regulator and keeps the whole

INT

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5.1.2 Voltage Supervisor

This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it.

Function: in case of both overvoltage alarm (V nal NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz.

5.1.3 Temperature Supervisor

There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors.

In case of detected overtemperature (150°C), the diagnostic pin DG3 will be switched to “H” to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (165°C), the V including the LIN transceiver will be switched OFF immediately and /RESET will go LOW.

Both temperature thresholds are correlated. The absolute tolerance is ±10°C and there is a built-in hysteresis of about 10°C to avoid fast oscillations. After cooling down below the 155°C threshold; the IC will go into Active mode.

The LIN interface has a separate thermal shutdown with disabled the low-side driver at typically 165°C.

5.2 Sleep Mode

To be able to guarantee the low quiescent current of the inactive IC, a Sleep mode is established. In Sleep mode it is possible to wake-up the IC by using the pins EN2 or LIN. In Sleep mode, the following blocks are active:

) and of undervoltage alarm (V

THOV

) the exter-

THUV

regulator and all drivers

• Band gap

• Internal 5V regulator (VINT) with external blocking capacitor of 220 nF

• Input structure for detecting the EN2 pins threshold

• Wake-up block of the LIN receive part

5.3 Wake-up and Sleep Mode Strategy

The IC has two modes: Sleep and Active. The change between the modes is described below.

The default state after power-on is Active mode.

The wake-up procedure brings the IC from a standby mode (Sleep) to an active mode (Active). The internal 5V supply VINT, the EN2 pin input structure and a certain part of the LIN receiver are permanently active to ensure a proper startup of the system.

The Go to Active and Go to Sleep procedures are implemented as follows:

• Go to Active by activating pin EN2

The input EN2 is intended as a switch-on pin from an external signal. Its input structure consists of a comparator with built-in hysteresis. It is ESD-protected by diodes against GND and V this reason the input voltage level must be positive and not higher than V

BAT

; for

BAT

ATA6823 [Preliminary]

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ATA6823 [Preliminary]

Pulling the EN2 pin up to the V

level will drive the IC into Active mode. EN2 is debounced with

BAT

a time constant of 20 µs, based on a 100 kHz clock.

• Go to Active using the LIN interface

The second possibility for wake-up can be performed using the LIN transceiver. In Sleep mode, the LIN receiver is partially active.

The wake-up by LIN requires 2 steps:

1. If the voltage on pin LIN is below a value of V

/DATwake

(about V

– 2V) the receive part

VBAT

of the LIN interface is active (not to be confused with Active mode of the whole IC). The active receive part is able to detect a valid LOW on the LIN pin.

2. If LIN = LOW during a filter time t

(typically 70 µs) the IC will change to Active

wakeLIN

mode. A short change back to HIGH during the filter time will reset the filter. This information is stored in a latch after entering Active mode

If the change to Active mode was caused by LIN, the EN1 or EN2 pins may remain LOW without disturbing the Active mode.

• Stay in Active via EN1

The input EN1 is intended to keep the IC in Active Mode via a signal from the microcontroller. The input is ESD-protected by diodes against GND and VCC. Therefore, the input voltage must be positive and not higher than V the VCC regulator is off in the Sleep mode and V

. EN1 cannot be used to switch from Sleep to Active because

will be zero.

• Go to Sleep

A HIGH to LOW transition at pin EN1 and a following permanent LOW for the time t

gotosleep

(typically 20 µs) switches the IC to Sleep mode.

Figure 5-1 illustrates the wake-up by LIN. The status PREWAKE is characterized by the acti-

vated receive block of the LIN interface. After going to Active mode, the V

regulator starts

working.

Go to Sleep is possible with a valid HIGH to LOW transition at pin EN1 (permanent LOW for longer than t

) if EN1 was in a valid HIGH state (HIGH for longer than tdb) before.

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Figure 5-1. Wake-up by pin LIN

LIN

VBAT

EN1

t < t

wake LIN

45% VBAT

wake LIN

VBAT - 1.5V

activating

55% VBAT

"PREWAKE"

STATUS

ACTIVE

SLEEP

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5.4 5V/3.3V VCC Regulator

The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.

ATA6823 [Preliminary]

The output voltage accuracy is in general < ±3%; in the 5V mode with V <5%.

To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 160 mA to 320 mA. The delivered voltage will break down and a reset may occur.

Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink.

A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low.

5.5 Reset and Watchdog Management

The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period T adjustable via the external resistor R

The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of T switched off during Sleep mode.

Figure 5-2. Timing Diagram of the Watchdog Function

res

< 8V it is limited to

VBAT

. In order to save current consumption, the watchdog is

resshortt

OSC

RESET

5.5.1 Timing Sequence

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For example, with an external resistor R of the watchdog.

= 12.32 µs, t1= 12.1 ms, t2= 9.61 ms, TWD= 16.88 ms ±10%

OSC

The times t

= 68 ms and td= 68 ms are fixed values with a tolerance of 10%.

res

=33kΩ ±1% we get the following typical parameters

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