Rainbow Electronics ATA6631 User Manual

Features

• Supply Voltage up to 40V

• Operating Voltage V

• Typically 10 µA Supply Current During Sleep Mode

• Typically 40 µA Supply Current in Silent Mode

• Linear Low-drop Voltage Regulator:

– Normal, Fail-safe, and Silent Mode – ATA6629: V – ATA6631: VCC = 5.0V ±2% – Sleep Mode: V

• V

Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)

• Voltage Regulator is Short-circuit and Over-temperature Protected

• LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2

• Wake-up Capability via LIN Bus (90 µs Dominant)

• TXD Time-out Timer

• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery

• Advanced EMC and ESD Performance

• ESD HBM 8 kV at Pins LIN and VS Following STM5.1

• Interference and Damage Protection According to ISO/CD7637

• Package: SO8

= 5V to 27V

= 3.3V ±2%

is Switched Off

LIN Bus Transceiver with Integrated Voltage Regulator

ATA6629

1. Description

ATA6629/ATA6631 is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, 2.1 and SAEJ2602-2, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6629/ATA6631 is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep Mode (voltage regulator switched off) and Silent Mode (communication off; V age on) guarantee minimized current consumption.

volt-

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Figure 1-1. Block Diagram

GND

TXD

RXD

VCC

NRES

Short-circuit and overtemperature protection

Normal/Silent/

Fail-safe Mode

3.3V/50 mA/±2% 5V/50 mA/±2%

Control

unit

Normal and

Fail-safe

Mode

RF-filter

LIN

VS1

TXD

Time-out

timer

Slew rate control

Undervoltage reset

Sleep mode

VCC

switched

off

Wake-up bus timer

ATA6629/ATA6631

Receiver

5 kΩ

VCC

3 4

TXD

NRES

RXD

VS 8

7 6 5

GND

LIN

2. Pin Configuration

Figure 2-1. Pinning SO8

Table 2-1. Pin Description

Pin Symbol Function

1 VS Battery supply 2 EN Enables Normal Mode if the input is high 3 GND Ground, heat sink 4 LIN LIN bus line input/output 5 RXD Receive data output 6 TXD Transmit data input 7 NRES Output undervoltage reset, low at reset 8 VCC Output voltage regulator 3.3V/5V/50 mA

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3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions.

3.2 Supply Pin (VS)

LIN operating voltage is VS= 5V to 27V. An undervoltage detection is implemented to disable transmission if V the IC starts with the Fail-safe Mode and the voltage regulator is switched on (i.e.,

3.3V/5V/50 mA).

The supply current in Sleep Mode is typically 10 µA and 40 µA in Silent Mode.

3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of V

ATA6629/ATA6631

falls below 5V, in order to avoid false bus messages. After switching on VS,

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V

3.5 Undervoltage Reset Output (NRES)

If the VCC voltage falls below the undervoltage detection threshold V after tres_f (Figure 6-1 on page 14). Even if V nally driven from the V

voltage. If VS voltage ramps down, NRES stays low until VS< 1.5V and

then becomes highly resistant.

The implemented undervoltage delay keeps NRES low for t nominal value.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to V GND shift or V col specification.

The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.

disconnection. The LIN receiver thresholds are compatible with the LIN proto-

Batt

, NRES switches to low

thun

= 0V the NRES stays low, because it is inter-

= 4 ms after VCC reaches its

Reset

, even in the event of a

thun

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3.7 Input/Output (TXD)

In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe source.

3.8 Dominant Time-out Function (TXD)

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than t LIN bus driver is switched to the recessive state. Nevertheless, when switching to Sleep Mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver, switch TXD to high (> 10 µs).

3.9 Output Pin (RXD)

This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 kΩ to V sured with an external load capacitor of 20 pF.

>27ms, the

DOM

. The AC characteristics are mea-

The output is short-circuit protected. In Unpowered Mode (that is, V

3.10 Enable Input Pin (EN)

The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/50 mA output capability.

If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to I regulator has its full functionality.

If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off.

= 0V), RXD is switched off.

typ. 40 µA. The VCC

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4. Mode of Operation

Unpowered Mode

(See section 4.5)

a: V

> VS

thF

b: VS < VS

thU

c: Bus wake-up event d: NRES switches to low

Fail-safe Mode

Normal Mode

VCC: 3.3V/5V/50 mA

with undervoltage

monitoring

Communication: ON

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

Silent Mode

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

Sleep Mode

VCC: switched off

Communication: OFF

Go to silent command

TXD = 0

EN = 0

TXD = 1

EN = 0

EN = 1

c + d

Local wake-up event

Go to sleep command

Figure 4-1. Mode of Operation

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Table 4-1. Mode of Operation

Mode of Operation Transceiver V

Fail safe OFF 3.3V/5V Recessive

Normal ON 3.3V/5V TXD depending

Silent OFF 3.3V/5V Recessive Sleep OFF 0V Recessive

LIN

4.1 Normal Mode

4.2 Silent Mode

This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.x. The V

voltage regulator operates with a 3.3V/5V output voltage, with a low

tolerance of ±2% and a maximum output current of 50 mA.

If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to Fail-safe Mode.

A falling edge at EN while TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (Figure 4-3 on page 7). The transmission path is disabled in Silent Mode. The overall supply current from V I

= 40 µA plus the VCC regulator output current I

VSsi

VCCs

is a combination of the

Batt

Figure 4-2. Switch to Silent Mode

Normal Mode

TXD

NRES

VCC

LIN

Mode select window

= 3.2 µs

Delay time silent mode

_silent = maximum 20 µs

LIN switches directly to recessive mode

Silent Mode

The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent Mode the internal slave termination between pin LIN and pin VS is disabled to minimize the current consumption in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent Mode can be activated independently from the current level on pin LIN.

If an undervoltage condition occurs, NRES is switched to low and the ATA6629/ATA6631 changes its state to Fail-safe Mode.

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ATA6629/ATA6631

A voltage less than the LIN Pre-wake detection V

at pin LIN activates the internal LIN

LINL

receiver and starts the wake-up detection timer.

A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t

) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a

bus

remote wake-up request. The device switches from Silent Mode to Fail-safe Mode, then the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD and TXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be used to switch directly to Normal Mode.

Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode

Bus wake-up filtering time

LIN bus

RXD

bus

High

Fail-safe mode Normal mode

Low

VCC

NRES

HighTXD

Silent mode 3.3V/5V/50 mA Fail-safe mode 3.3V/5V/50 mA

Undervoltage detection active

High

Normal mode

EN High

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4.3 Sleep Mode

Delay time sleep mode

d_sleep

= maximum 20 µs

LIN switches directly to recessive mode

= 3.2 µs

LIN

VCC

NRES

TXD

Sleep Mode

Normal Mode

Mode select window

A falling edge at EN while TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-5 on page 9).

Figure 4-4. Switch to Sleep Mode

In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs earlier to Low than the TXD. Therefore, the best an easiest way are two falling edges at TXD and EN at the same time.

In Sleep Mode the transmission path is disabled. Supply current from V I

=10µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave

VSsleep

is typically

Batt

termination between pin LIN and pin VS is disabled to minimize the current consumption in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Sleep Mode can be activated independently from the current level on pin LIN.

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