Rainbow Electronics ATA6630 User Manual

Features

• Master and Slave Operation Possible

• Supply Voltage up to 40V

• Operating voltage V

• Typically 10 µA Supply Current During Sleep Mode

• Typically 40 µA Supply Current in Silent Mode

• Linear Low-drop Voltage Regulator:

– Normal, Fail-safe, and Silent Mode

• ATA6628 V

• ATA6630 V

– In Sleep Mode V

• VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical

Combined at Open Drain Output NRES

• High-speed Mode Up to 115 kBaud

• Internal 1:6 Voltage Divider for V

• Negative Trigger Input for Watchdog

• Boosting the Voltage Regulator Possible with an External NPN Transistor

• LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2

• Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin

• INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up

Resistor

• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery

• Adjustable Watchdog Time via External Resistor

• Advanced EMC and ESD Performance

• ESD HBM 8 kV at Pins LIN and VS According to STM5.1

• Package: QFN 5 mm × 5 mm with 20 Pins

= 5V to 27V

= 3.3V ±2%

= 5.0V ±2%

is Switched Off

Battery

Sensing

LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog

ATA6628 ATA6630

Preliminary

1. Description

The ATA6628 is a fully integrated LIN transceiver, which complies with the LIN 2.0,

2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for

3.3V/50 mA output and a window watchdog. The ATA6630 has the same functionality as the ATA6628; however, it uses a 5V/50 mA regulator. The voltage regulator is able to source 50 mA, but the output current can be boosted by using an external NPN transistor. This chip combination makes it possible to develop inexpensive, simple, yet powerful slave and master nodes for LIN-bus systems. ATA6628/ATA6630 are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption.

9117C–AUTO–10/09

Figure 1-1. Block Diagram

High

Speed

Mode

Adjustable

Watchdog

Oscillator

Short Circuit and Overtemperature

Protection

TXD

Time-out

Timer

Edge

Detection

Debounce

Time

Internal Testing

Unit

Control Unit

Slew Rate Control

Wake-up

Bus Timer

Mode Select

Undervoltage

Reset

Normal/Silent/

Fail-safe Mode

3.3V/50 mA/

±2%

5V/50 mA/

±2%

RF Filter

Watchdog

RXD

NTRIGGNDPV

PVCC

TMMODE

TXD

SP_MODE

KL_15

WAKE

Receiver

59163

Normal and

Fail-safe

Mode

LIN

WD_OSC

NRES

PVCC

VCC

DIV_ON

VBATT

Normal and

Fail-safe

Mode

INH

ATA6628/ATA6630 [Preliminary]

9117C–AUTO–10/09

2. Pin Configuration

Figure 2-1. Pinning QFN20

ATA6628/ATA6630 [Preliminary]

MODE

KL15

PVCC

VCC

VBATT

NTRIG

WAKE

GND

20 19 18

67 8 109

LIN

ATA6628/30

QFN 5 mm 5 mm

0.65 mm pitch 20 lead

RXD

DIV_ON

SP_MODE

WD_OSC

NRES

TXD

INH

Table 2-1. Pin Description

Pin Symbol Function

1 VBATT Battery supply for the voltage divider 2 EN Enables the device into Normal Mode 3 NTRIG Low-level watchdog trigger input from microcontroller; if not needed, connect to PVCC 4 WAKE High-voltage input for local wake-up request; if not needed, connect to VS 5 GND System ground 6 LIN LIN-bus line input/output 7 RXD Receive data output 8 DIV_ON Input to switch on the internal voltage divider, active high

9 PV Voltage divider output 10 SP_MODE Input to switch the transceiver in High-speed Mode, active high 11 INH Battery related High-side switch 12 TXD Transmit data input; active low output (strong pull down) after a local wake up request 13 NRES Output undervoltage and watchdog reset (open drain) 14 WD_OSC External resistor for adjustable watchdog timing; if not needed, connect to GND 15 TM For factory testing only (tie to ground) 16 MODE For Debug Mode: Low watchdog is on; high watchdog is off 17 KL_15 Ignition detection (edge sensitive) 18 PVCC 3.3V/5V regulator sense input pin, connect to VCC 19 VCC 3.3V/5V regulator output/driver pin, connect to PVCC 20 VS Battery supply

Backside Heat slug is connected to GND

9117C–AUTO–10/09

3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.

3.2 Supply Pin (VS)

The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if V switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,

3.3V/5V/50 mA output capability).

The supply current is typically 10 µA in Sleep Mode and 40 µA in Silent Mode.

3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5.

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads up to 50 mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its emitter connected to PVCC.

falls below VSth in order to avoid false bus messages. After

thun

3.5 Voltage Regulator Sense Pin (PVCC)

The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal output transistor), this pin must be connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled.

ATA6628/ATA6630 [Preliminary]

9117C–AUTO–10/09

3.7 Input/Output Pin (TXD)

In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe source. It is current-limited to < 8 mA.

3.8 TXD Dominant Time-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than t LIN-bus driver is switched to recessive state. Nevertheless, when switching to Sleep Mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver, switch TXD to high (> 10 µs).

3.9 Output Pin (RXD)

Tis output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 kΩ to PVCC. The AC characteristics can be defined with an external load capacitor of 20 pF.

ATA6628/ATA6630 [Preliminary]

>27ms, the

DOM

The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., V

During Fail-safe Mode it is signalling the fail-safe source.

3.10 Enable Input Pin (EN)

The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/50 mA output capability.

If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to I regulator has its full functionality.

If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off.

3.11 Wake Input Pin (WAKE)

The WAKE Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10 µA, is implemented.

If a local wake-up is not needed for the application, connect the WAKE pin directly to the VS pin.

3.12 Mode Input Pin (MODE)

Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect MODE pin to PVCC and the watchdog is switched off.

= 0V).

typ. 40 µA. The VCC

9117C–AUTO–10/09

Note: If you do not use the watchdog, connect pin MODE directly to PVCC.

3.13 TM Input Pin

3.14 KL_15 Pin

3.15 INH Output Pin

The TM pin is used for final production measurements at Atmel®. In normal application, it has to be always connected to GND.

The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge-sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high voltage (V directly to GND if you do not need it. A debounce timer with a typical Tdb implemented.

The input voltage threshold can be adjusted by varying the external resistor due to the input current I

KL_15

capacitor of 100 nF are recommended. With this RC combination you can increase the wake-up time Tw

You can also increase the wake-up time using external capacitors with higher values.

The INH Output pin is used to switch an external voltage regulator on during Normal and Fail-safe Mode. The INH Output is a high-side switch, which is switched-off in Sleep and Silent Mode. It is possible to switch off the external 1 kΩ master resistor via the INH pin for master node applications.

), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin

Batt

of 160 µs is

Kl_15

. To protect this pin against voltage transients, a serial resistor of 47 kΩ and a ceramic

and, therefore, the sensitivity against transients on the ignition KL_15.

KL_15

3.16 Reset Output Pin (NRES)

The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure.

3.17 WD_OSC Output Pin

The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34 kΩ and 120 kΩ to adjust the watchdog oscillator time.

If the watchdog is disabled, this voltage is switched off and you can either tie to GND or leave this pin open.

3.18 NTRIG Input Pin

The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time t

to generate a watchdog trigger.

trigmin

3.19 Wake-up Events from Sleep or Silent Mode

•LIN-bus

• WAKE pin

•EN pin

• KL_15

ATA6628/ATA6630 [Preliminary]

9117C–AUTO–10/09

3.20 DIV_ON Input Pin

The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time limitation (see Table 3-1 on page 7). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented.

3.21 VBATT Input Pin

The VBATT is a high voltage input pin to supply the internal voltage divider. In an application with battery voltage monitoring, this pin is connected to V 10 nF capacitor to GND (see Figure 9-2 on page 31). The the divider ratio is 1:6.

3.22 PV Output Pin

For applications with battery monitoring, this pin is directly connected to the ADC of a microcontroller. For buffering the ADC input an external capacitor might be needed. This pin guarantees a voltage and temperature stable output of a V DIV_ON input pin.

Table 3-1. Table of Voltage Divider

ATA6628/ATA6630 [Preliminary]

via a 47Ω resistor in series and a

Battery

ratio. The PV output pin is controlled by the

Battery

Mode of Operation Input DiV_ON Voltage Divider Output PV

Fail-safe/Normal/

High-speed/Silent

Sleep

0Off 1On 0Off 1Off

3.23 SP_MODE Input Pin

The SP_MODE pin is a low-voltage input. High-speed Mode of the transceiver can be activated via a high level during Normal Mode. Return to LIN 2.x Transceiver Mode with slope control is possible if you switch the SP_MODE pin to low.

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4. Modes of Operation

Unpowered Mode

(See Section 4.5)

a: V

> VS

thF

b: VS < VS

thU

c: Bus wake-up event d: Wake up from WAKE or KL_15 pin

Fail-safe Mode

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

Watchdog: ON

Silent Mode

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

Watchdog: OFF

Sleep Mode

VCC: switched off

Communication: OFF

Watchdog: OFF

Go to silent command

TXD = 0

EN = 0

TXD = 1

EN = 0

EN = 1

c + d + e

c + d

Normal Mode

VCC: 3.3V/5V/50 mA

with undervoltage detection

watchdog: ON

High level at

pin SP_MODE:

High-speed Mode

Transceiver ≤ 115 kBaud

LIN 2.1

Transceiver

≤ 20 kBaud

TXD time-out

timer on

Go to sleep command

e: NRES switches to low

Go to normal command

Figure 4-1. Modes of Operation

Table 4-1. Table of Modes

Mode of

Operation Transceiver Pin LIN V

Unpowered Off Recessive On GND On On Off

Fail-safe Off Recessive 3.3V/5V GND On 1.23V On

Normal/

High-speed

Silent Off Recessive 3.3V/5V GND Off 0V Off

Sleep Off Recessive 0V GND Off 0V Off

ATA6628/ATA6630 [Preliminary]

Pin Mode Watchdog Pin WD_OSC Pin INH

On TXD depending 3.3V/5V GND On 1.23V On

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4.1 Normal Mode

4.2 Silent Mode

ATA6628/ATA6630 [Preliminary]

This is the normal transmitting and receiving mode. The voltage regulator is active and can source up to 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.

A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 4-2 on page 9). The transmission path is disabled in Silent Mode. The INH output is switched off and the voltage divider is enabled. The overall supply current from V put current I

VCC

The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode to minimize the current consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode.

is a combination of the I

Batt

= 40 µA plus the VCC regulator out-

VSsi

A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer.

Figure 4-2. Switch to Silent Mode

Normal Mode

TXD

NRES

VCC

LIN

Mode select window

= 3.2 µs

Delay time silent mode

_silent = maximum 20 µs

Silent Mode

9117C–AUTO–10/09

LIN switches directly to recessive mode

A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t

) and the following rising edge at the LIN pin (see Figure 4-3 on page 10) result in a

bus

remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 4-3 on page 10). EN high can be used to switch directly to Normal Mode.

Figure 4-3. LIN Wake-up from Silent Mode

LIN bus

RXD

TXD

Watchdog

VCC

voltage

regulator

Bus wake-up filtering time

Node in silent mode

Silent mode 3.3V/5V/50 mA Fail safe mode 3.3V/5V/50 mA

bus

Watchdog off Start watchdog lead time t

Fail-safe mode Normal mode

Don't care

Low

HighHigh

Normal mode

NRES

Undervoltage detection active

ATA6628/ATA6630 [Preliminary]

EN High

9117C–AUTO–10/09

4.3 Sleep Mode

Delay time sleep mode

d_sleep

= maximum 20 µs

LIN switches directly to recessive mode

= 3.2 µs

LIN

VCC

NRES

TXD

Sleep Mode

Normal Mode

Mode select window

ATA6628/ATA6630 [Preliminary]

A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 11). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs earlier to Low than the TXD. Therefore, the best an easiest way are two falling edges at TXD and EN at the same time. The transmission path is disabled in Sleep Mode. The supply current I

from V

VSsleep

The INH output, the PV output and the VCC regulator are switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled to minimize the current consumption in the event that the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin.

A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer.

Figure 4-4. Switch to Sleep Mode

is typically 10 µA.

Batt

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