Rainbow Electronics ATA6625 User Manual
Features
• Supply Voltage up to 40V
• Operating Voltage V
• Typically 10 µA Supply Current During Sleep Mode
• Typically 57 µA Supply Current in Silent Mode
• Linear Low-drop Voltage Regulator:
– Normal, Fail-safe, and Silent Mode
– ATA6623: V
– ATA6625: VCC = 5.0V ±2%
– Sleep Mode: V
• V
Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)
CC
• Voltage Regulator is Short-circuit and Over-temperature Protected
• LIN Physical Layer According to LIN Specification Revision 2.0 and SAEJ2602-2
• Wake-up Capability via LIN Bus (90 µs Dominant)
• TXD Time-out Timer
• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
• Advanced EMC and ESD Performance
• ESD HBM 8 kV at Pins LIN and VS Following STM5.1
• Interference and Damage Protection According to ISO/CD7637
• Package: SO8
= 5V to 27V
S
= 3.3V ±2%
CC
is Switched Off
CC
LIN Bus
Transceiver
with Integrated
Voltage
Regulator
ATA6623
1. Description
ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination
of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is designed to handle the
low-speed data communication in vehicles (for example, in convenience electronics).
Improved slope control at the LIN driver ensures secure data communication up to
20 kBaud with an RC oscillator for the protocol handling. The bus output is designed
to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent
mode (communication off; V
voltage on) guarantee minimized current consumption.
CC
ATA6625
4957E–AUTO–10/07
Figure 1-1. Block Diagram
RXD
TXD
EN
GND
V
ATA6623/25
CC
5
V
CC
6
2
3
Receiver
TXD
Time-out
timer
+
-
Wake-up bus timer
Slew rate control
Normal/Silent/
Fail-safe mode
3.3V/50 mA/2%
5V/50 mA/2%
Undervoltage reset
Control
unit
Sleep
mode
VCC
switched
off
Normal and
Fail-safe
mode
RF-filter
Short circuit and
overtemperature
protection
VS1
4
LIN
8
VCC
7
NRES
2. Pin Configuration
Figure 2-1. Pinning SO8
GND
LIN
Table 2-1. Pin Description
Pin Symbol Function
1 VS Battery supply
2 EN Enables Normal mode if the input is high
3 GND Ground, heat sink
4 LIN LIN bus line input/output
5 RXD Receive data output
6 TXD Transmit data input
7 NRES Output undervoltage reset, low at reset
8 VCC Output voltage regulator 3.3V/5V/50 mA
VS 8
EN
1
2
3
4
VCC
NRES
7
TXD
6
5
RXD
2
ATA6623/ATA6625
4957E–AUTO–10/07
3. Functional Description
3.1 Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all
nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any
restrictions.
3.2 Supply Pin (VS)
LIN operating voltage is VS= 5V to 27V. An undervoltage detection is implemented to disable
transmission if V
the IC starts with the Fail-safe mode and the voltage regulator is switched on (i.e.,
3.3V/5V/50 mA).
The supply current in Sleep mode is typically 10 µA and 57 µA in Silent mode.
3.3 Ground Pin (GND)
The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground
shift up to 11.5% of V
ATA6623/ATA6625
falls below 5V, in order to avoid false bus messages. After switching on VS,
S
.
S
3.4 Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying
the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold V
3.5 Undervoltage Reset Output (NRES)
If the VCC voltage falls below the undervoltage detection threshold of V
low after tres_f (Figure 6-1 on page 11). Even if V
internally driven from the V
and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for t
nominal value.
3.6 Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–27V to +40V. This pin exhibits no reverse current from the LIN bus to V
GND shift or V
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled.
disconnection. The LIN receiver thresholds are compatible with the LIN proto-
Batt
thun
, NRES switches to
thun
= 0V the NRES stays low, because it is
CC
voltage. If VS voltage ramps down, NRES stays low until VS<1.5V
S
= 4 ms after VCC reaches its
Reset
, even in the event of a
S
.
4957E–AUTO–10/07
3
3.7 Input Pin (TXD)
In Normal mode the TXD pin is the microcontroller interface to control the state of the LIN output.
TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected
(internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive
state.
3.8 Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than t
LIN bus driver is switched to the recessive state. Nevertheless, when switching to Sleep mode,
the actual level at the TXD pin is relevant.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
3.9 Output Pin (RXD)
The pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is
reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The
output has an internal pull-up structure with typically 5 kΩ to V
measured with an external load capacitor of 20 pF.
>6ms, the
DOM
. The AC characteristics are
CC
The output is short-circuit protected. In Unpowered mode (that is, V
3.10 Enable Input Pin (EN)
This pin controls the Operation mode of the interface. After power up of VS (battery), the IC
switches to Fail-safe mode, even if EN is low or unconnected (internal pull-down resistor). If EN
is high, the interface is in Normal mode.
A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN
while TXD is low forces the device to Sleep mode.
= 0V), RXD is switched off.
S
4
ATA6623/ATA6625
4957E–AUTO–10/07
4. Mode of Operation
Figure 4-1. Mode of Operation
b
ATA6623/ATA6625
a: V
> 5V
Unpowered Mode
Pre-normal Mode
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
d
Communication: OFF
= 0V
V
Batt
b
a
c + d
S
< 4V
b: V
S
c: Bus wake-up event
d: NRES switches to low
b
Normal Mode
VCC: 3.3V/5V/50 mA
with undervoltage
monitoring
Communication: ON
EN = 1
EN = 0
TXD = 1
EN = 1
EN = 0
TXD = 0
Go to silent command
Local wake-up event
Go to sleep command
EN = 1
c
b
Sleep Mode
VCC: switched off
Communication: OFF
Silent Mode
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
4957E–AUTO–10/07
5
4.1 Normal Mode
4.2 Silent Mode
Table 4-1. Mode of Operation
Mode of
Operation Transceiver V
Fail safe OFF 3.3V/5V High Recessive
Normal ON 3.3V/5V High TXD depending
Silent OFF 3.3V/5V High Recessive
Sleep OFF 0V 0V Recessive
CC
RXD LIN
This is the normal transmitting and Receiving mode of the LIN Interface, in accordance with LIN
specification 2.0. The V
voltage regulator operates with a 3.3V/5V output voltage, with a low
CC
tolerance of ±2% and a maximum output current of 50 mA.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to
Fail-safe mode. All features are available.
A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to
be logic high during the Mode Select window (Figure 4-2 on page 7). The transmission path is
disabled in Silent mode. The overall supply current from V
I
= 57 µA plus the VCC regulator output current I
VSsi
VCCs
.
is a combination of the
Batt
The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent mode the internal
slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in
case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin
LIN and pin VS is present. The Silent mode can be activated independently from the current
level on pin LIN.
If an undervoltage condition occurs, NRES is switched to low and the ATA6623/ATA6625
changes its state to Fail-safe mode.
A voltage less than the LIN Pre-wake detection V
at pin LIN activates the internal LIN
LINL
receiver.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (t
) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a
bus
remote wake-up request. The device switches from Silent mode to Fail-safe mode, then the
internal LIN slave termination resistor is switched on. The remote wake-up request is indicated
by a low level at pin RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be
used to switch directly to Normal mode.
6
ATA6623/ATA6625
4957E–AUTO–10/07
Figure 4-2. Switch to Silent Mode
e
Normal Mode Silent Mode
EN
ATA6623/ATA6625
TXD
NRES
VCC
LIN
LIN switches directly to recessive mode
Mode select window
t
= 3.2 µs
d
Delay time silent mode
t
_sleep = maximum 20 µs
d
Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode
Bus wake-up filtering time
t
bus
Fail-safe mode Normal mod
4957E–AUTO–10/07
LIN bus
RXD
VCC
EN
NRES
High
Silent mode 3.3V/5V/50 mA Fail-safe mode 3.3V/5V/50 mA
Undervoltage detection active
Low
Normal mode
EN High
7
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