Rainbow Electronics ATA6625 User Manual

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Features

• Supply Voltage up to 40V

• Operating Voltage V

• Typically 10 µA Supply Current During Sleep Mode

• Typically 57 µA Supply Current in Silent Mode

• Linear Low-drop Voltage Regulator:

– Normal, Fail-safe, and Silent Mode – ATA6623: V – ATA6625: VCC = 5.0V ±2% – Sleep Mode: V

• V

Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)

• Voltage Regulator is Short-circuit and Over-temperature Protected

• LIN Physical Layer According to LIN Specification Revision 2.0 and SAEJ2602-2

• Wake-up Capability via LIN Bus (90 µs Dominant)

• TXD Time-out Timer

• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery

• Advanced EMC and ESD Performance

• ESD HBM 8 kV at Pins LIN and VS Following STM5.1

• Interference and Damage Protection According to ISO/CD7637

• Package: SO8

= 5V to 27V

= 3.3V ±2%

is Switched Off

LIN Bus Transceiver with Integrated Voltage Regulator

ATA6623

1. Description

ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication off; V

voltage on) guarantee minimized current consumption.

ATA6625

4957E–AUTO–10/07

Figure 1-1. Block Diagram

RXD

TXD

GND

ATA6623/25

Receiver

TXD

Time-out

timer

Wake-up bus timer

Slew rate control

Normal/Silent/

Fail-safe mode

3.3V/50 mA/2% 5V/50 mA/2%

Undervoltage reset

Control

unit

Sleep mode

VCC

switched

off

Normal and

Fail-safe

mode

RF-filter

Short circuit and overtemperature protection

VS1

LIN

VCC

NRES

2. Pin Configuration

Figure 2-1. Pinning SO8

GND

LIN

Table 2-1. Pin Description

Pin Symbol Function

1 VS Battery supply 2 EN Enables Normal mode if the input is high 3 GND Ground, heat sink 4 LIN LIN bus line input/output 5 RXD Receive data output 6 TXD Transmit data input 7 NRES Output undervoltage reset, low at reset 8 VCC Output voltage regulator 3.3V/5V/50 mA

VS 8

1 2 3 4

VCC NRES

TXD

6 5

RXD

ATA6623/ATA6625

4957E–AUTO–10/07

3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions.

3.2 Supply Pin (VS)

LIN operating voltage is VS= 5V to 27V. An undervoltage detection is implemented to disable transmission if V the IC starts with the Fail-safe mode and the voltage regulator is switched on (i.e.,

3.3V/5V/50 mA).

The supply current in Sleep mode is typically 10 µA and 57 µA in Silent mode.

3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of V

ATA6623/ATA6625

falls below 5V, in order to avoid false bus messages. After switching on VS,

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V

3.5 Undervoltage Reset Output (NRES)

If the VCC voltage falls below the undervoltage detection threshold of V low after tres_f (Figure 6-1 on page 11). Even if V internally driven from the V and then becomes highly resistant.

The implemented undervoltage delay keeps NRES low for t nominal value.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to V GND shift or V col specification.

The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.

disconnection. The LIN receiver thresholds are compatible with the LIN proto-

Batt

thun

, NRES switches to

thun

= 0V the NRES stays low, because it is

voltage. If VS voltage ramps down, NRES stays low until VS<1.5V

= 4 ms after VCC reaches its

Reset

, even in the event of a

4957E–AUTO–10/07

3.7 Input Pin (TXD)

In Normal mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state.

3.8 Dominant Time-out Function (TXD)

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than t LIN bus driver is switched to the recessive state. Nevertheless, when switching to Sleep mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver, switch TXD to high (> 10 µs).

3.9 Output Pin (RXD)

The pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 kΩ to V measured with an external load capacitor of 20 pF.

>6ms, the

DOM

. The AC characteristics are

The output is short-circuit protected. In Unpowered mode (that is, V

3.10 Enable Input Pin (EN)

This pin controls the Operation mode of the interface. After power up of VS (battery), the IC switches to Fail-safe mode, even if EN is low or unconnected (internal pull-down resistor). If EN is high, the interface is in Normal mode.

A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN while TXD is low forces the device to Sleep mode.

= 0V), RXD is switched off.

ATA6623/ATA6625

4957E–AUTO–10/07

4. Mode of Operation

Figure 4-1. Mode of Operation

ATA6623/ATA6625

a: V

> 5V

Unpowered Mode

Pre-normal Mode

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

= 0V

Batt

c + d

< 4V

b: V

c: Bus wake-up event d: NRES switches to low

Normal Mode

VCC: 3.3V/5V/50 mA

with undervoltage

monitoring

Communication: ON

EN = 1

EN = 0

TXD = 1

EN = 1

EN = 0

TXD = 0

Go to silent command

Local wake-up event

Go to sleep command

EN = 1

Sleep Mode

VCC: switched off

Communication: OFF

Silent Mode

VCC: 3.3V/5V/50 mA

with undervoltage monitoring

Communication: OFF

4957E–AUTO–10/07

4.1 Normal Mode

4.2 Silent Mode

Table 4-1. Mode of Operation

Mode of

Operation Transceiver V

Fail safe OFF 3.3V/5V High Recessive

Normal ON 3.3V/5V High TXD depending

Silent OFF 3.3V/5V High Recessive

Sleep OFF 0V 0V Recessive

RXD LIN

This is the normal transmitting and Receiving mode of the LIN Interface, in accordance with LIN specification 2.0. The V

voltage regulator operates with a 3.3V/5V output voltage, with a low

tolerance of ±2% and a maximum output current of 50 mA.

If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to Fail-safe mode. All features are available.

A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to be logic high during the Mode Select window (Figure 4-2 on page 7). The transmission path is disabled in Silent mode. The overall supply current from V I

= 57 µA plus the VCC regulator output current I

VSsi

VCCs

is a combination of the

Batt

The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent mode the internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent mode can be activated independently from the current level on pin LIN.

If an undervoltage condition occurs, NRES is switched to low and the ATA6623/ATA6625 changes its state to Fail-safe mode.

A voltage less than the LIN Pre-wake detection V

at pin LIN activates the internal LIN

LINL

receiver.

A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t

) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a

bus

remote wake-up request. The device switches from Silent mode to Fail-safe mode, then the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be used to switch directly to Normal mode.

ATA6623/ATA6625

4957E–AUTO–10/07

Figure 4-2. Switch to Silent Mode

Normal Mode Silent Mode

ATA6623/ATA6625

TXD

NRES

VCC

LIN

LIN switches directly to recessive mode

Mode select window

= 3.2 µs

Delay time silent mode

_sleep = maximum 20 µs

Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode

Bus wake-up filtering time

bus

Fail-safe mode Normal mod

4957E–AUTO–10/07

LIN bus

RXD

VCC

NRES

High

Silent mode 3.3V/5V/50 mA Fail-safe mode 3.3V/5V/50 mA

Undervoltage detection active

Low

Normal mode

EN High

4.3 Sleep Mode

A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 8).

In Sleep mode the transmission path is disabled. Supply current from V I

=10µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave

VSsleep

is typically

Batt

termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Sleep mode can be activated independently from the current level on pin LIN.

A voltage less than the LIN Pre-wake detection V

at pin LIN activates the internal LIN

LINL

receiver.

A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t

) and a following rising edge at pin LIN respectively results in a remote wake-up

bus

request. The device switches from Sleep mode to Fail-safe mode.

The V

regulator is activated, and the internal LIN slave termination resistor is switched on. The

remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (Figure 4-5 on page 9).

EN high can be used to switch directly from Sleep/Silent to Fail-safe mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to Normal mode.

Figure 4-4. Switch to Sleep Mode

Sleep ModeNormal Mode

TXD

NRES

VCC

LIN

Mode select window

= 3.2 µs

Delay time sleep mode

= maximum 20 µs

d_sleep

LIN switches directly to recessive mode

ATA6623/ATA6625

4957E–AUTO–10/07

Figure 4-5. LIN Wake-up Diagram from Sleep Mode

ATA6623/ATA6625

LIN bus

RXD

VCC

voltage

regulator

NRES

Bus wake-up filtering time

bus

Low or floating

Off state

Low or floating

Fail-safe Mode Normal Mode

Low

On state

Regulator wake-up time

EN High

Reset

time

Microcontroller

start-up time delay

4.4 Fail-safe Mode

At system power-up the device automatically switches to Fail-safe mode. The voltage regulator is switched on (V to low for t The IC stays in this mode until EN is switched to high, and changes then to the Normal mode. A power down of V mode after power up. A logic low at NRES switches the IC into Fail-safe mode directly.

4.5 Unpowered Mode

If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 6-1 on page 11). After VS is higher than the VS undervoltage threshold VS The VCC output voltage reaches its nominal value after t VCC capacitor and the load.

NRES is low for the reset time delay t

= 3.3V/5V/50 mA), (see Figure 6-1 on page 11). The NRES output switches

= 4 ms and gives a reset to the microcontroller. LIN communication is switched off.

res

(VS< 4V) during Silent- or Sleep mode switches the IC into the Fail-safe

Batt

, the IC mode changes from Unpowered mode to Fail-safe mode.

. This time, t

VCC

; no mode change is possible during this time.

Reset

, depends on the

VCC

4957E–AUTO–10/07

5. Fail-safe Features

• During a short-circuit at LIN to V the power dissipation, the chip temperature exceeds T The chip cools down and after a hysteresis of T on high because LIN is high. During LIN overtemperature switch-off, the V

, the output limits the output current to I

Battery

and the LIN output is switched off.

LINoff

, switches the output on again. RXD stays

hys

BUS_LIM

regulator is

. Due to

working independently.

• During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent mode. If the short-circuit disappears, the IC starts with a remote wake-up.

• The reverse current is very low < 15 µA at pin LIN during loss of V

or GND. This is optimal

Batt

behavior for bus systems where some slave nodes are supplied from battery or ignition.

• During a short circuit at VCC, the output limits the output current to I

. Because of

VCCn

undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Fail-safe mode. If the chip temperature exceeds the value T output switches off. The chip cools down and after a hysteresis of T again. Because of Fail-safe mode, the V

voltage will switch on again although EN is

, switches the output on

hys

VCCoff

, the VCC

switched off from the microcontroller.The microcontroller can then start with normal operation.

• Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.

• Pin RXD is set floating if V

is disconnected.

Batt

• Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.

• If TXD is short-circuited to GND, it is possible to switch to Sleep mode via ENABLE after tdom > 20 ms.

ATA6623/ATA6625

4957E–AUTO–10/07

6. Voltage Regulator

Figure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage

12V

5.5V/3.8V

VCC

5V/3.3V

thun

ATA6623/ATA6625

res_f

NRES

5V/3.3V

VCC

Reset

The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application.

With this special SO8 package (fused lead frame to pin3) an R

of 80 K/W is achieved.

thja

Therefore, it is recommended to connect pin 3 with a wide GND plate on the printed board to get a good heat sink.

The main power dissipation of the IC is created from the V

output current I

, which is

VCC

needed for the application.

Figure 6-2 shows the safe operating area of the ATA6623/ATA6625.

4957E–AUTO–10/07

Figure 6-2. Power Dissipation: Save Operating Area versus VCC Output Current and Supply

Voltage V

60.00

at Different Ambient Temperatures Due to R

= 80 K/W

thja

50.00

40.00

30.00

(mA)

VCC

20.00

10.00

Iout_85: T

Iout_105: T

0.00 8 9 10 11 12 13 14 15 18 1916 17567

amb

= 85°C

= 95°C

= 105°C

VS (V)

For programming purposes of the microcontroller it is potentially neccessary to supply the V

output via an external power supply while the VS Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip.

ATA6623/ATA6625

4957E–AUTO–10/07

ATA6623/ATA6625

7. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Typ. Max. Unit

Supply voltage V

Pulse time ≤ 500 ms

=25°C

Output current I

VCC

≤ 50 mA

Pulse time ≤ 2min T

=25°C

Output current I

VCC

≤ 50 mA

Logic pins (RxD, TxD, EN, NRES) –0.3 +5.5 V Output current NRES I

NRES

LIN

- DC voltage –27 +40 V V

- DC voltage –0.3 +5.5 V According to IBEE LIN EMC

Test specification 1.0 following IEC 61000-4-2

- Pin VS, LIN to GND ±6 KV

ESD HBM following STM5.1 with 1.5 kΩ/100 pF

- Pin VS, LIN to GND ±8 KV

HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002)

CDM ESD STM 5.3.1 ±750 V Junction temperature T Storage temperature T Operating ambient temperature T Thermal resistance junction to ambient

(free air) Special heat sink at GND (pin 3) on PCB R Thermal shutdown of V

regulator T

Thermal shutdown of LIN output T Thermal shutdown hysteresis T

thja

VCCoff

LINoff

hys

–0.3 +40 V

+40 V

27 V

+2 mA

±3 KV

–40 +150 °C –55 +150 °C –40 +125 °C

145 K/W

80 K/W 150 160 170 °C 150 160 170 °C

10 °C

4957E–AUTO–10/07

8. Electrical Characteristics

5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 VS Pin

Nominal DC voltage

1.1 range

VS V

Sleep mode V

Supply current in Sleep

1.2 mode

> VS – 0.5V

LIN

VS < 14V (Tj = 25°C) Sleep mode

> VS – 0.5V

LIN

VS I

VSsleep

VS < 14V (Tj = 125°C) Bus recessive

Supply current in Silent

1.3 mode

< 14V (Tj = 25°C)

Without load at VCC Bus recessive

< 14V (Tj = 125°C)

VSsi

Without load at VCC

Supply current in Normal

1.4 mode

Supply current in Normal

1.5 mode

undervoltage

1.6

1.7

threshold VS undervoltage

threshold hysteresis

Bus recessive

< 14V

Without load at VCC Bus dominant

< 14V

load current 50 mA

VS I

VS V

VSrec

VSdom

Sth

Sth_hys

2 RXD Output Pin

Normal mode

2.1 Low level input current

2.2 Low level output voltage I

2.3 Internal resistor to V

=0V

LIN

=0.4V

RXD

= 1 mA RXD V

RXD

RXD R

RXD I

RXD

RXDL

RXD

3 TXD Input Pin

3.1 Low level voltage input TXD V

3.2 High level voltage input TXD V

3.3 Pull-up resistor V High level leakage

3.4 current

=0V TXD R

TXD

=5V TXD I

TXD

TXDL

TXDH

TXD

4EN Input Pin

4.1 Low level voltage input EN V

4.2 High level voltage input EN V

4.3 Pull-down resistor V

4.4 Low level input current V

= 5V EN R

= 0V EN I

ENL

ENH

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

513.527 VA

31014µAA

51116µAA

47 57 67 µA A

56 66 76 µA A

0.3 0.8 mA A

50 53 mA A

4.0 4.5 5 V A

0.2 V A

1.3 2.5 8 mA A

0.4 V A

357kΩ A

–0.3 +0.8 V A

0.3V

125 250 400 kΩ A

–3 +3 µA A

–0.3 +0.8 V A

0.3V

50 125 200 kΩ A –3 +3 µA A

ATA6623/ATA6625

4957E–AUTO–10/07

ATA6623/ATA6625

8. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

5 NRES Open Drain Output Pin

≥ 5.5V

5.1 Low level output voltage

5.2 Low level output low

5.3 Undervoltage reset time

Reset debounce time for

5.4 falling edge

=1mA

NRES

= 250 µA

NRES

10 kΩ to VCC

=0V

VVS≥ 5.5V C

=20pF

NRES

VVS≥ 5.5V C

=20pF

NRES

6 VCC Voltage Regulator ATA6623

6.1 Output voltage V

Output voltage VCC at

6.2 low V

6.3 Regulator drop voltage VS > 3V, I

6.4 Regulator drop voltage VS > 3V, I Line regulation

6.5 maximum

Load regulation

6.6 maximum

Power supply ripple

6.7 rejection

4V < VS < 18V (0 mA to 50 mA)

3V < VS < 4V VCC VCC

= –15 mA VCC V

VCC

= –50 mA VCC V

VCC

4V < VS < 18V VCC VCC

5 mA < I

< 50 mA VCC VCC

VCC

10 Hz to 100 kHz C

= 10 µF

VCC

VS = 14V, I

=–15mA

VCC

6.8 Output current limitation VS > 4V VCC I

6.9 Load capacity 1Ω < ESR < 5Ω @ 100 kHz VCC C VCC undervoltage

6.10 threshold

Hysteresis of

6.11 undervoltage threshold

Ramp up time VS > 4V

6.12 to VCC = 3.3V

Referred to VCC VS > 4V

= 2.2 µF

VCC

= –5 mA at VCC

load

7 VCC Voltage Regulator ATA6625

7.1 Output voltage V

Output voltage V

7.2 low V

7.3 Regulator drop voltage VS > 4V, I

7.4 Regulator drop voltage VS > 4V, I

7.5 Regulator drop voltage VS > 3.3V, I Line regulation

7.6 maximum

5.5V < VS < 18V (0 mA to 50 mA)

4V < VS < 5.5V VCC VCC

= –20 mA VCC V

VCC

= –50 mA VCC V

VCC

= –15 mA VCC V

VCC

5.5V < VS < 18V VCC VCC

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

NRES V

NRES t

VCC VCC

VCC V

VCC Vhys

VCC t

VCC VCC

NRESL NRESL

NRESLL

Reset

res_f

nor

low

Drop1

Drop2

line

load

VCCs

load

thunN

thun

VCC

nor

low

line

0.2

0.14

V V

0.2 V A

246msA

1.5 10 µs A

3.234 3.366 V A

VVS –

Drop

3.366 V A

200 mV A

500 700 mV A

1%A

0.5 2 % A

50 dB C

–200 –160 mA A

1.8 10 µF D

2.8 3.2 V A

150 mV A

100 250 µs A

4.9 5.1 V A

VVS – V

5.1 V A

250 mV A

400 600 mV A

200 mV A

1%A

A A

4957E–AUTO–10/07

8. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

Load regulation

7.7 maximum

7.8 Output current limitation VS > 5.5V VCC I

7.9 Load capacity 1Ω < ESR < 5Ω @ 100 kHz VCC C VCC undervoltage

7.10 threshold

Hysteresis of

7.11 undervoltage threshold

Ramp up time VS > 5.5V

7.12 to VCC = 5V

LIN Bus Driver: Bus Load Conditions:

Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; R

10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps

Driver recessive output

8.1 voltage

8.2 Driver dominant voltage

8.3 Driver dominant voltage

8.4 Driver dominant voltage

8.5 Driver dominant voltage

8.6 Pull–up resistor to V

LIN current limitation

8.7 V

= V

BUS

Batt_max

Input leakage current at the receiver including

8.8 pull-up resistor as

specified

Leakage current LIN

8.9 recessive

Leakage current when control unit disconnected from ground.

8.10

Loss of local ground must not affect communication in the residual network

Node has to sustain the current that can flow

8.11

under this condition. Bus must remain operational under this condition.

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

5mA < I

< 50 mA VCC VCC

VCC

Referred to VCC VS > 5.5V

= 2.2 µF

VCC

= –5 mA at VCC

load

Load1/Load2 LIN V

= 7V

= 500Ω

load

= 18V

= 500Ω

load

= 7V

= 1000Ω

load

= 18V

= 1000Ω

load

The serial diode is

mandatory

Input Leakage current Driver off

= 0V

BUS

= 12V

Batt

Driver off 8V < V 8V < V V

BUS

GND V

Batt

0V < V

Batt

SUP_Device

0V < V

< 18V

Batt

< 18V

BUS

≥ V

Batt

= V

Device

= 12V

< 18V

BUS

disconnected

= GND

< 18V

BUS

VCCs

VCC V

thunN

VCC Vhys

VCC T

= 5 kΩ; C

RXD

BUSrec

LIN V

_LoSUP

_HiSUP

_LoSUP_1k

_HiSUP_1k

LIN R

LIN I

BUS_LIM

BUS_PAS_dom

BUS_PAS_rec

BUS_NO_gnd

BUS

load

VCC

LIN

load

thun

0.5 2 % A

–200 –160 mA A

1.8 10 µF D

4.2 4.8 V A

250 mV A

130 300 µs A

= 20 pF

RXD

0.9 × V

1.2 V A

2VA

0.6 V A

0.8 V A

20 30 60 kΩ A

40 120 200 mA A

–1 –0.35 mA A

15 20 µA A

–10 +0.5 +10 µA A

515µAA

ATA6623/ATA6625

4957E–AUTO–10/07

ATA6623/ATA6625

8. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

9 LIN Bus Receiver

Center of receiver

9.1 threshold

9.2 Receiver dominant state VEN = 5V LIN V

9.3 Receiver recessive state V Receiver input

9.4 hysteresis

Pre-wake detection LIN

9.5 High level input voltage

Pre-wake detection LIN

9.6 Low level input voltage

10 Internal Timers

Dominant time for

10.1 wake–up via LIN bus

Time delay for mode change from Pre-normal

10.2 into Normal mode via pin

EN Time delay for mode

change from Normal

10.3 mode to Sleep mode via

pin EN TXD dominant time out

10.4 timer

10.5 Duty cycle 1

10.6 Duty cycle 2

10.7 Duty cycle 3

10.8 Duty cycle 4

Slope time falling and

10.9 rising edge at LIN

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

BUS_CNT

hys

th_dom

+ Vth_

rec

)/2

LIN V

= 5V LIN V

= V

th_rec

– V

th_dom

LIN V

BUS_CNT

LIN V

Activates the LIN receiver LIN V

= 0V t

LIN

= 5V t

= 0V t

TXD

TH TH

Rec(max) Dom(max)

= 0.744 × V

= 0.581 × V

VS = 7.0V to 18V

= 50 ms

Bit

D1 = t TH

Rec(min)

Dom(min)

bus_rec(min)

/(2 × t

= 0.422 × V

= 0.284 × V

)

Bit

VS = 7.6V to 18V t

= 50 ms

Bit

D2 = t TH

Rec(max)

Dom(max)

bus_rec(max)

/(2 × t

= 0.778 × V

= 0.616 × V

)

Bit

VS = 7.0V to 18V

= 96 ms

Bit

D3 = t TH

Rec(min)

Dom(min)

bus_rec(min)

/(2 × t

= 0.389 × V

= 0.251 × V

)

Bit

VS = 7.6V to 18V t

= 96 ms

Bit

D4 = t

bus_rec(max)

= 7.0V to 18V

/(2 × t

)

Bit

SLOPE_fall

SLOPE_rise

BUSdom

BUSrec

BUShys

LINH

LINL

bus

norm

sleep

dom

0.475 ×

–27 0.4 × V

0.6 × V

0.028 ×

VS – 1V

–27 VS – 3.3V V A

30 90 150 µs A

520µsA

2 7 15 µs A

61320msA

0.5 ×

0.1 x V

0.525 ×

40 V A

0.175 ×

0.3V

D1 0.396 A

D2 0.581 A

D3 0.417 A

D4 0.590 A

3.5 22.5 µs A

4957E–AUTO–10/07

8. Electrical Characteristics (Continued)

5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

Receiver Electrical AC Parameters of the LIN Physical Layer

LIN Receiver, RXD Load Conditions (C

Propagation delay of

11.1 receiver Figure 8-1

Symmetry of receiver

11.2

propagation delay rising edge minus falling edge

= 7.0V to 18V

= max(t

rx_pd

= 7.0V to 18V

= t

rx_sym

rx_pdr

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Figure 8-1. Definition of Bus Timing Characteristics

RXD

rx_pdr

– t

): 20 pF; R

, t

)

rx_pdf

pull-up

= 2.4 kΩ

rx_sym

rx_pd

6µsA

–2 +2 µs A

(Input to transmitting node)

TXD

(Transceiver supply

of transmitting node)

RXD

(Output of receiving node1)

Rec(max)

Dom(max)

Rec(min)

Dom(min)

rx_pdf(1)

Bit

Bus_dom(max)

LIN Bus Signal

Bus_dom(min)

Bit

Bus_rec(min)

Bit

Thresholds of

receiving node1

Thresholds of

receiving node2

Bus_rec(max)

rx_pdr(1)

(Output of receiving node2)

ATA6623/ATA6625

RXD

rx_pdr(2)

rx_pdf(2)

4957E–AUTO–10/07

Figure 8-2. Application Circuit

ATA6623/ATA6625

VCC

Micro-

controller

RXD

TXD

GND

ATA6623/25

Receiver

Normal and

fail-safe

mode

RF filter

TXD

Time-out

timer

Wake-up bus timer

Slew rate control

Sleep

unit

mode

VCC

switched

off

Control

Short circuit and overtemperature protection

Normal Mode

and

silent mode

3.3V/50 mA/2% 5V/50 mA/2%

Undervoltage reset

100 nF

22 µF

LIN

220 pF

VCC

NRES

10 kΩ

100 nF

LIN-BUS

10 µF

4957E–AUTO–10/07

9. Ordering Information

Extended Type Number Package Remarks

ATA6623-TAPY SO8 3.3V LIN system basis chip, Pb-free, 1k, taped and reeled ATA6625-TAPY SO8 5V LIN system basis chip, Pb-free, 1k, taped and reeled ATA6623-TAQY SO8 3.3V LIN system basis chip, Pb-free, 4k, taped and reeled ATA6625-TAQY SO8 5V LIN system basis chip, Pb-free, 4k, taped and reeled

10. Package Information

Package: SO 8

Dimensions in mm

4.9±0.1

1.4

5±0.2

3.7±0.1

0.2

0.4

1.27

3.81

Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06

+0.15

0.1

3.8±0.1

6±0.2

technical drawings according to DIN specifications

ATA6623/ATA6625

4957E–AUTO–10/07

11. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.

Revision No. History

4957E-AUTO-10/07 • Section 9 “Ordering Information” on page 20 changed

4957D-AUTO-07/07

4957C-AUTO-02/07

ATA6623/ATA6625

• Features changed

• Block diagram changed

• Application diagram changed

• Text changed under the headings:

3.2, 3.3, 3.4, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 5.5, 5.6, 6

• Figure 4-2, 4-3, 4-4, 4-5, 8-2: changed

• Figure title 6-1: text changed

• Abs. Max. Ratings: row “Output current NRES” added

• El. Char. table: values changed in the following rows:

1.3, 5.1, 5.3, 5.4, 6.9, 6.12, 7.9, 11.1

• Features on page 1 changed

• Table 2-1 “Pin Description” on page 2 changed

• Section 3-1 “Physical Layer Compatibility” on page 3 added

• Section 3-2 “Supply Pin (VS) on page 3 changed

• Section 3-3 “Ground Pin (GND) on page 3 changed

• Section 3-8 “Dominant Time-out Function (TXD)” on page 4 changed

• Section 4-1 “Normal Mode” on page 5 changed

• Section 4-2 “Silent Mode” on page 5 changed

• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page

6 changed

• Section 4.3 “Sleep Mode” on page 7 changed

• Section 4-5 “Unpowered Mode” on page 7 changed

• Figure 4-4 “Switch to Sleep Mode” on page 8 changed

• Figure 4-6 “V

9 changed

• Section 5 “Fail-safe Features on page 9 changed

• Section 6 “Voltage Regulator” on page 10 changed

• Section 7 “Absolute Maximum Ratings” on page 11 changed

• Section 8 “Electrical Characteristics” on pages 12 to 16 changed

• Section 9 “Ordering Information” on page 18 changed

Voltage Regulator: Ramp up and Undervoltage” on page

4957E–AUTO–10/07

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4957E–AUTO–10/07

Rainbow Electronics ATA6625 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

2. Pin Configuration

3. Functional Description

3.1 Physical Layer Compatibility

3.2 Supply Pin (VS)

3.3 Ground Pin (GND)

3.4 Voltage Regulator Output Pin (VCC)

3.5 Undervoltage Reset Output (NRES)

3.6 Bus Pin (LIN)

3.7 Input Pin (TXD)

3.8 Dominant Time-out Function (TXD)

3.9 Output Pin (RXD)

3.10 Enable Input Pin (EN)

4. Mode of Operation

4.1 Normal Mode

4.2 Silent Mode

4.3 Sleep Mode

4.4 Fail-safe Mode

4.5 Unpowered Mode

5. Fail-safe Features

6. Voltage Regulator

7. Absolute Maximum Ratings

8. Electrical Characteristics

9. Ordering Information

10. Package Information

11. Revision History