Rainbow Electronics ATA5812 User Manual

Features

• High FSK Sensitivity: -106 dBm at 20 kBaud/-109.5 dBm at 2.4 kBaud (433.92 MHz)

• High ASK Sensitivity: -112.5 dBm at 10 kBaud/-116.5 dBm at 2.4 kBaud (433.92 MHz)

• Low Supply Current: 10.5 mA in RX and TX Mode (3 V/TX with 5 dBm)

• Data Rate 1 to 20 kBaud Manchester FSK, 1 to 10 kBaud Manchester ASK

• ASK/FSK Receiver Uses a Low-IF Architecture with High Selectivity, Blocking and Low

Intermodulation (Typical Blocking 55

dB at ±10 MHz, System I1dBCP = -30 dBm/System IIP3 = -20 dBm)

70

• 226 kHz IF Frequency with 30 dB Image Rejection and 170 kHz Usable IF Bandwidth

• Transmitter Uses Closed Loop Fractional-N Synthesizer for FSK Modulation with a

High PLL Bandwidth and an Excellent Isolation between PLL and PA

• Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF

Resolution

• Integrated RX/TX-Switch, Single-ended RF Input and Output

• RSSI (Received Signal Strength Indicator)

• Communication to Microcontroller with SPI Interface Working at Maximum 500 kBit/s

• Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of

Received and Transmitted Data

• 5 Push Button Inputs and One Wake-up Input are Active in Power-down Mode

• Integrated XTAL Capacitors

• PA Efficiency: up to 38% (433 MHz/10 dBm/3 V)

• Low Inband Sensitivity Change of Typically ±1.8 dB within ±58 kHz Center Frequency

Change in the Complete Temperature and Supply Voltage Range

• Supply Voltage Switch, Supply Voltage Regulator, Reset Generation, Clock/Interrupt

Generation and Low Battery Indicator for Microcontroller

• Fully Integrated PLL with Low Phase Noise VCO and PLL Loop Filter

• Sophisticated Threshold Control and Quasi Peak Detector Circuit in the Data Slicer

• Power Management via Different Operation Modes

• 433.92 MHz, 868.3 MHz and 315 MHz without External VCO and PLL Components

• Inductive Supply with Voltage Regulator if Battery is Empty (AUX Mode)

• Efficient XTO Start-up Circuit (> -1.5 kΩ Worst Case Start Impedance)

• Changing of Modulation Type ASK/FSK and Data Rate without Component Changes

• Minimal External Circuitry Requirements for Complete System Solution

• Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor

• ESD Protection at all Pins (2 kV HBM, 200 V MM)

• Supply Voltage Range: 2.4 V to 3.6 V or 4.4 V to 6.6 V

• Temperature Range: -40°C to +105°C

• Small 7 × 7 mm QFN48 Package

dB at ±750 kHz/61 dB at ±1.5 MHz and

UHF ASK/FSK
Transceiver

ATA5811
ATA5812

Preliminary

Applications

• Automotive Keyless Entry and Passive Entry Go Systems

• Access Control Systems

• Remote Control Systems

• Alarm and Telemetry Systems

• Energy Metering

• Home Automation

Benefits

• No SAW Device Needed in Key Fob Designs to Meet Automotive Specifications

• Low System Cost Due to Very High System Integration Level

• Only One Crystal Needed in System

• Less Demanding Specification for the Microcontroller Due to Handling of Power-down

Mode, Delivering of Clock, Reset, Low Battery Indication and Complete Handling of
Receive/Transmit Protocol and Polling

• Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply

Allows a Loop Antenna in the Key Fob to Surround the Whole Application

Rev. 4689B–RKE–04/04

General Description The ATA5811/ATA5812 is a highly integrated UHF ASK/FSK single-channel half-duplex

transceiver with low power consumption supplied in a small QFN48 package. The
receive part is built as a fully integrated low-IF receiver, whereas direct PLL modulation
with the fractional-N synthesizer is used for FSK transmission and switching of the
power amplifier for ASK transmission.

The device supports data rates of 1 kBaud to 20 kBaud (FSK) and 1 kBaud to 10 kBaud
(ASK) in Manchester, Bi-phase and other codes in transparent mode. The ATA5811 can
be used in the 433 MHz to 435 MHz and the 868 MHz to 870 MHz band, the ATA5812
in the 314 MHz to 316 MHz band. The very high system integration level results in few
numbers of external components needed.

Due to its blocking and selectivity performance, together with the additional 15 dB to
20 dB loss and the narrow bandwidth of a typical key fob loop antenna, a bulky blocking
SAW is not needed in the key fob or sensor application. Additionally, the building blocks
needed for a typical RKE and access control system on both sides, the base and the
mobile stations, are fully integrated.

Its digital control logic with self polling and protocol generation enables a fast challenge
response systems without using a high-performance microcontroller. Therefore, the
ATA5811/ATA5812 contains a FIFO buffer RAM and can compose and receive the
physical messages themselves. This provides more time for the microcontroller to carry
out other functions such as calculating crypto algorithms, composing the logical mes­sages and controlling other devices. Due to that, a standard 4-/8-bit microcontroller
without special periphery and clocked with the CLK output of about 4.5 MHz is sufficient
to control the communication link. This is especially valid for passive entry and access
control systems, where within less than 100 ms several challenge response communi­cations with arbitration of the communication partner have to be handled.

Figure 1. System Block Diagram

Antenna

Matching

It is hence possible to design bi-directional RKE and access control systems with a fast
challenge response crypto function with the same PCB board size and with the same
current consumption as uni-directional RKE systems.

ATA5811/ATA5812

RF transceiver

Digital Control

Logic

XTO

Power Supply

Micorcontroller

Interface

Microcontroller

4 ... 8

2

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

Figure 2. Pinning QFN48

NC
NC
NC

RF_IN

NC

433_N868

NC
R_PWR
PWR_H

RF_OUT

NC

NC

ATA5811/ATA5812 [Preliminary]

NC

NC

RX_ACTIVET1T2T3T4T5PWR_ON

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6

ATA5811/ATA5812

7
8
9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

RX_TX1

RX_TX2

CDEM

36

RSSI

35

CS

34

DEM_OUT

33

SCK

32

SDI_TMDI

31

SDO_TMDO

30

CLK

29

IRQ

28

N_RESET

27

VSINT

26

NC

25

XTAL2

NCNCNC

VS2

VS1

AVCC

VAUX

DVCC

TEST1

VSOUT

XTAL1

TEST2

Pin Description

Pin Symbol Function

1 NC Not connected
2 NC Not connected
3 NC Not connected
4RF_INRF input
5 NC Not connected
6 433_N868 Selects RF input/output frequency range
7 NC Not connected
8 R_PWR Resistor to adjust output power

9 PWR_H Pin to select output power
10 RF_OUT RF output
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 AVCC Blocking of the analog voltage supply
17 VS2 Power supply input for voltage range 4.4 V to 6.6 V
18 VS1 Power supply input for voltage range 2.4 V to 3.6 V

4689B–RKE–04/04

3

Pin Description (Continued)

Pin Symbol Function

19 VAUX Auxiliary supply voltage input
20 TEST1 Test input, at GND during operation
21 DVCC Blocking of the digital voltage supply
22 VSOUT Output voltage power supply for external devices
23 TEST2 Test input, at GND during operation
24 XTAL1 Reference crystal
25 XTAL2 Reference crystal
26 NC Not connected
27 VSINT Microcontroller Interface supply voltage
28 N_RESET Output pin to reset a connected microcontroller
29 IRQ Interrupt request
30 CLK Output to clock a connected microcontroller
31 SDO_TMDO Serial data out/transparent mode data out
32 SDI_TMDI Serial data in/transparent mode data in
33 SCK Serial clock
34 DEM_OUT Demodulator open drain output signal
35 CS Chip select for serial interface
36 RSSI Output of the RSSI amplifier
37 CDEM Capacitor to adjust the lower cut-off frequency data filter
38 RX_TX2 GND pin to decouple LNA in TX mode
39 RX_TX1 Switch pin to decouple LNA in TX mode
40 PWR_ON Input to switch on the system (active high)
41 T1 Key input 1 (can also be used to switch on the system (active low)
42 T2 Key input 2 (can also be used to switch on the system (active low)
43 T3 Key input 3 (can also be used to switch on the system (active low)
44 T4 Key input 4 (can also be used to switch on the system (active low)
45 T5 Key input 5 (can also be used to switch on the system (active low)
46 RX_ACTIVE Indicates RX operation mode
47 NC Not connected
48 NC Not connected

GND Ground/backplane

4

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

Figure 3. Block Diagram

ATA5811/ATA5812 [Preliminary]

433_N868

R_PWR

RF_OUT

PWR_H

RX_TX1

RX_TX2

RF_IN

CDEM

RSSI
XTAL1
XTAL2

DEM_OUT

CLK

N_RESET

IRQ

CS

SCK

SDI_TMDI

SDO_TMDO

AVCC

RF transceiver Digital Control Logic

PA

Fract.-N-

Frequency

TX

LNA

Microcontroller

Interface

Synthesizer

Signal
Processing
(Mixer, IF -

Filter, IF -

Amp.,

Demodulator,

Data Filter

Data Slicer)

Frontend Enable
PA_Enable (ASK)

TX_DATA (FSK)

RX/TX
FREQ 9
FREF

Demod_Out

RX_ACTIVE

TX/RX - Data Buffer

Control Register

Status Register

Bit-Check Logic

DVCC

Polling Circuit

XTO

SPI

Power
Supply

Switches

Regulators

Wakeup

Reset

Reset

VS2
VS1
VAUX
VSOUT

PWR_ON
T1
T2
T3
T4
T5

TEST1
TEST2

4689B–RKE–04/04

VSINT

GND

5

Typical Key Fob or Sensor Application with 1 Battery

Figure 4. Typical RKE Key Fob or Sensor Application, 433.92 MHz, 1 Battery

AVCC

C

10

Loop antenna

C

11

L

1

C

5

L

2

C

8

C

9

C

7

T2

T3

VS2

+

T4

VS1

VAUX

C

4

Litihum-

T5

TEST1

RX_TX1

PWR_ON

SDO_TMDO

DVCC

VSOUT

NC

NC

20 mm x 0.4 mm

NC

NC

RF_IN

NC

433_N868

NC

R

1

R_PWR

PWR_H
RF_OUT

NC

NC

NC

T1

NC

RX_ACTIVE

ATA5811/ATA5812

NC

NC

AVCC

C

1

C

2

CDEM

RSSI

RX_TX2

CS

DEM_OUT

SCK

SDI_TMDI

CLK

IRQ

N_RESET

VSINT

NC

TEST2

XTAL1

C

XTAL2

6

Microcontroller

VCC

VSS

13.25311 MHz

C

3

Cell

Figure 4 shows a typical 433.92 MHz RKE key fob or sensor application with one battery
The external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C

are 68 nF voltage supply blocking capacitors. C5 is a 10 nF supply blocking capaci-

C

4

is a 15 nF fixed capacitor used for the internal quasi peak detector and for the

tor. C

6

highpass frequency of the data filter. C
of 1 pF to 33 pF. L1 is a matching inductor of about 5.6 nH to 56 nH. L
tor of about 120 nH. A load capacitor of 9 pF for the crystal is integrated. R

to C11 are RF matching capacitors in the range

7

is a feed induc-

2

is typically

1

1

to

22 kΩ and sets the output power to about 5.5 dBm. The loop antenna’s quality factor is
somewhat reduced by this application due to the quality factor of L

and the RX/TX

2

switch. On the other hand, this lower quality factor is necessary to have a robust design
with a bandwidth that is broad enough for production tolerances. Due to the single­ended and ground-referenced design, the loop antenna can be a free-form wire around
the application as it is usually employed in RKE uni-directional systems. The
ATA5811/ATA5812 provides sufficient isolation and robust pulling behavior of internal
circuits from the supply voltage as well as an integrated VCO inductor to allow this.
Since the efficiency of a loop antenna is proportional to the square of the surrounded
area it is beneficial to have a large loop around the application board with a lower quality
factor to relax the tolerance specification of the RF components and to get a high
antenna efficiency in spite of their lower quality factor.

6

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Typical Car or Sensor Base-station Application

Figure 5. Typical RKE Car or Sensor Base-station Application, 433.92 MHz

SAW-Filter

L

4

C

50 Ω

connector

RF

OUT

11

AVCC

C

10

L

3

C

5

R

L

2

C

L

8

1

C

9

C

7

NC

NC

T1

NC

20 mm x 0.4 mm

NC

NC

RF_IN

NC

433_N868

NC

1

R_PWR

PWR_H
RF_OUT

NC

NC

NC

NC

T2T3T4

RX_ACTIVE

ATA5811/ATA5812

AVCC

VS2

NC

VS1

T5

RX_TX1

PWR_ON

SDO_TMDO

VAUX

DVCC

TEST1

VSOUT

CDEM

RSSI

RX_TX2

CS

DEM_OUT

SCK

SDI_TMDI

CLK

IRQ

N_RESET

VSINT

NC

TEST2

XTAL1

C

6

XTAL2

Microcontroller

VCC

VSS

13.25311 MHz

C

C

1

C

2

C

4

12

C

3

VCC = 4.75 V..5.25 V

Figure 5 shows a typical 433.92 MHz VCC = 4.75 V to 5.25 V RKE car or sensor base­station application. The external components are 12 capacitors, 1 resistor, 4 inductors, a
SAW filter and a crystal. C

and C12 are 2.2 µF supply blocking capacitors for the internal voltage regulators. C

C

2

and C3 to C4 are 68 nF voltage supply blocking capacitors.

1

is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor used for the internal
quasi peak detector and for the highpass frequency of the data filter. C
matching capacitors in the range of 1 pF to 33 pF. L

to L4 are matching inductors of

2

about 5.6 nH to 56 nH. A load capacitor for the crystal of 9 pF is integrated. R

to C11 are RF

7

is typi-

1

cally 22 kΩ and sets the output power at RF_OUT to about 10 dBm. Since a quarter
wave or PCB antenna, which has high efficiency and wide band operation, is typically
used here, it is recommended to use a SAW filter to achieve high sensitivity in case of
powerful out-of-band blockers. L

, C10 and C9 together form a lowpass filter, which is

1

needed to filter out the harmonics in the transmitted signal to meet regulations. An inter­nally regulated voltage at pin VSOUT can be used in case the microcontroller only
supports 3.3

V operation, a blocking capacitor with a value of C

= 2.2 µF has to be

12

connected to VSOUT in any case.

5

4689B–RKE–04/04

7

Typical Key Fob Application, 2 Batteries

Figure 6. Typical RKE Key Fob Application, 433.92 MHz, 2 Batteries

AVCC

C

Loop antenna

C

11

L

1

C

5

L

2

C

8

10

C

9

C

7

T2

T3T4T5

NC

NC
NC

20 mm x 0.4 mm

NC

RF_IN
NC

433_N868

R

NC

1

R_PWR

PWR_H

RF_OUT
NC

NC

NC

T1

NC

RX_ACTIVE

ATA5811/ATA5812

NC

AVCC

NC

C

VS2

1

C

VS1

2

PWR_ON

SDO_TMDO

VAUX

DVCC

TEST1

C

4

CDEM

RSSI

RX_TX1

RX_TX2

DEM_OUT

SDI_TMDI

N_RESET

VSINT

TEST2

VSOUT

CS

SCK

CLK

IRQ

NC

XTAL1

C

6

XTAL2

Microcontroller

VCC

VSS

13.25311 MHz

C

3

+

Litihum Cells

+

Figure 6 shows a typical 433.92 MHz 2-battery RKE key fob or sensor application. The
external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C

and C

1

4

are 68 nF voltage supply blocking capacitors. C2 and C3 are 2.2 µF supply blocking
capacitors for the internal voltage regulators. C

is a 10 nF supply blocking capacitor. C

5

6

is a 15 nF fixed capacitor used for the internal quasi peak detector and for the highpass
frequency of the data filter. C
33 pF. L

is a matching inductor of about 5.6 nH to 56 nH. L2 is a feed inductor of about

1

120 nH. A load capacitor for the crystal of 9 pF is integrated. R

to C11 are RF matching capacitors in the range of 1 pF to

7

is typically 22 kΩ and

1

sets the output power to about 5.5 dBm.

8

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

RF Transceiver According to Figure 3 on page 5, the RF transceiver consists of an LNA (Low-Noise

Amplifier), PA (Power Amplifier), RX/TX switch, fractional-N frequency synthesizer and
the signal processing part with mixer, IF filter, IF amplifier, FSK/ASK demodulator, data
filter and data slicer.

In receive mode the LNA pre-amplifies the received signal which is converted down to
226 kHz, filtered and amplified before it is fed into an FSK/ASK demodulator, data filter
and data slicer. The RSSI (Received Signal Strength Indicator) signal and the raw digital
output signal of the demodulator are available at the pins RSSI and DEM_OUT. The
demodulated data signal Demod_Out is fed to the digital control logic where it is evalu­ated and buffered as described in section “Digital Control Logic”.

In transmit mode the fractional-N frequency synthesizer generates the TX frequency
which is fed to the PA. In ASK mode the PA is modulated by the signal PA_Enable. In
FSK mode the PA is enabled and the signal TX_DATA (FSK) modulates the fractional-N
frequency synthesizer. The frequency deviation is digitally controlled and internally fixed
to about ±16 kHz (see Table 12 on page 24 for exact values). The transmit data can
also be buffered as described in section “Digital Control Logic”. A lock detector within
the synthesizer ensures that the transmission will only start if the synthesizer is locked.

The RX/TX switch can be used to combine the LNA input and the PA output to a single
antenna with a minimum of losses.

Transparent modes without buffering of RX and TX data are also available to allow pro­tocols and coding schemes other than the internal supported Manchester encoding.

Low-IF Receiver The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity,

blocking, selectivity, supply voltage and supply current specification needed to manu­facture an automotive key fob without the use of SAW blocking filter (see Figure 4 on
page 6). The receiver can be connected to the roof antenna in the car when using an
additional blocking SAW front-end filter as shown in Figure 5 on page 7.

At 433.92 MHz the receiver has a typical system noise figure of 7.0 dB, a system
I1dBCP of -30 dBm and a system IIP3 of -20 dBm. There is no AGC or switching of the
LNA needed, thus, a better blocking performance is achieved. This receiver uses an IF
(Intermediate Frequency) of 226 kHz, the typical image rejection is 30 dB and the typical
3 dB IF filter bandwidth is 185 kHz (f

= 318.5 kHz). The demodulator needs a signal to Gaussian noise ratio of 8 dB for

f

hi_IF

= 226 kHz ±92.5 kHz, f

IF

20 kBaud Manchester with ±16 kHz frequency deviation in FSK mode, thus, the result­ing sensitivity at 433.92 MHz is typically -106 dBm at 20 kBaud Manchester.

Due to the low phase noise and spurious of the synthesizer in receive mode
with the eighth order integrated IF filter the receiver has a better selectivity and blocking
performance than more complex double superhet receivers but without external compo­nents and without numerous spurious receiving frequencies.

A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than
direct conversion receivers where every pulse or AM-modulated signal (especially the
signals from TDMA systems like GSM) demodulates to the receiving signal band at sec­ond-order non-linearities.

Note: 1. -120 dBC/Hz at ±1 MHz and -75 dBC at ±FREF at 433.92 MHz

= 133.5 kHz and

lo_IF

(1)

together

4689B–RKE–04/04

9

Input Matching at RF_IN The measured input impedances as well as the values of a parallel equivalent circuit of

these impedances can be seen in Table 1. The highest sensitivity is achieved with
power matching of these impedances to the source impedance of 50 Ω

Table 1. Measured Input Impedances of the RF_IN Pin

fRF/MHz Z(RF_IN) Rp//C

315 (44-j233)Ω 1278 Ω//2.1 pF

433.92 (32-j169)Ω 925 Ω//2.1 pF

868.3 (21-j78)Ω 311 Ω//2.2 pF

The matching of the LNA Input to 50 Ω was done with the circuit according to Figure 7
and with the values given in Table 2. The reflection coefficients were always ≤ 10 dB.
Note that value changes of C
board layouts. The measured typical FSK and ASK Manchester code sensitivities with a
Bit Error Rate (BER) of 10

and L1 may be necessary to for compensate individual

1

-3

are shown in Table 3 on page 11 and Table 4 on page 11.
These measurements were done with inductors having a quality factor according to
Table 2, resulting in estimated matching losses of 1.0 dB at 315 MHz, 1.2 dB at

433.92 MHz and 0.6 dB at 868.3 MHz. These losses can be estimated when calculating
the parallel equivalent resistance of the inductor with R
matching loss with 10 log(1+R

p/Rloss

).

= 2 × π × f × L × QL and the

loss

With an ideal inductor, for example, the sensitivity at 433.92 MHz/FSK/20 kBaud/
±16 kHz/Manchester can be improved from -106 dBm to -107.2 dBm. The sensitivity
depends on the control logic which examines the incoming data stream. The exami­nation limits must be programmed in control registers 5 and 6. The measurements in
Table 3 on page 11 and Table 4 on page 11 are based on the values of registers 5 and
6 according to Table 39 on page 57.

p

Figure 7. Input Matching to 50 Ω

RF

IN

Table 2. Input Matching to 50 Ω

fRF/MHz C1/pF L1/nH Q

315 2.2 56 43

433.92 1.8 27 40

868.3 1.2 6.8 58

C

1

ATA5811/ATA5812

4

RF_IN

L

1

L1

10

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Table 3. Measured Sensitivity FSK, ±16 kHz, Manchester, dBm, BER = 10

RF Frequency

BR_Range_0

1.0 kBaud

BR_Range_0

2.4 kBaud

BR_Range_1

5.0 kBaud

-3

BR_Range_2

10 kBaud

BR_Range_3

20 kBaud

315 MHz -110.0 dBm -110.5 dBm -109.0 dBm -108.0 dBm -107.0 dBm

433.92 MHz -109.0 dBm -109.5 dBm -108.0 dBm -107.0 dBm -106.0 dBm

868.3 MHz -106.0 dBm -106.5 dBm -105.5 dBm -104.0 dBm -103.5 dBm

Table 4. Measured Sensitivity 100% ASK, Manchester, dBm, BER = 10

RF Frequency

BR_Range_0

1.0 kBaud

BR_Range_0

2.4 kBaud

BR_Range_1

5.0 kBaud

-3

BR_Range_2

10 kBaud

315 MHz -117.0 dBm -117.5 dBm -115 dBm -113.5 dBm

433.92 MHz -116.0 dBm -116.5 dBm -114.0 dBm -112.5 dBm

868.3 MHz -112.5 dBm -113.0 dBm -111.5 dBm -109.5 dBm

Sensitivity versus Supply Voltage, Temperature and Frequency Offset

To calculate the behavior of a transmission system it is important to know the reduction
of the sensitivity due to several influences. The most important are frequency offset due
to crystal oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply
voltage dependency of the noise figure and IF filter bandwidth of the receiver. Figure 8
shows the typical sensitivity at 433.92 MHz/FSK/20kBaud/±16 kHz/Manchester versus
the frequency offset between transmitter and receiver with T

= -40°C, +25°C and

amb

+105°C and supply voltage VS1 = VS2 = 2.4 V, 3.0 V and 3.6 V.

Figure 8. Measured Sensitivity 433.92 MHz/FSK/20 kBaud/±16 kHz/Manchester versus Frequency Offset, Temperature
and Supply Voltage

-110.0

-109.0

-108.0

-107.0

-106.0

-105.0

-104.0

-103.0

-102.0

-101.0

Sensitivity (dBm)

-100.0

-99.0

-98.0

-97.0

-96.0

-95.0

-100 -80 -60 -40 -20 0 20 40 60 80 100

Frequency Offset (kHz)

VS = 2.4 V T

VS = 3.0 V T

VS = 3.6 V T
VS = 2.4 V T
VS = 3.0 V T
VS = 3.6 V T

VS = 2.4 V T
VS = 3.0 V T
VS = 3.6 V T

= -40°C

amb

= -40°C

amb

= -40°C

amb

= +25°C

amb

= +25°C

amb

= +25°C

amb

= +105°C

amb

= +105°C

amb

= +105°C

amb

4689B–RKE–04/04

11

As can be seen in Figure 8 on page 11 the supply voltage has almost no influence. The
temperature has an influence of about +1.5/-0.7 dB and a frequency offset of ±65 kHz
also influences by about ±1 dB. All these influences, combined with the sensitivity of a
typical IC, are then within a range of -103.7 dBm and -107.3 dBm over temperature,
supply voltage and frequency offset which is -105.5 dBm ±1.8dB. The integrated IF filter
has an additional production tolerance of only ±7 kHz, hence, a frequency offset
between the receiver and the transmitter of ±58 kHz can be accepted for XTAL and XTO
tolerances.

Note: For the demodulator used in the ATA5811/ATA5812, the tolerable frequency offset does

not change with the data frequency, hence, the value of ±58 kHz is valid for up to
1 kBaud.

This small sensitivity spread over supply voltage, frequency offset and temperature is
very unusual in such a receiver. It is achieved by an internal, very fast and automatic fre­quency correction in the FSK demodulator after the IF filter, which leads to a higher
system margin. This frequency correction tracks the input frequency very quickly, if how­ever, the input frequency makes a larger step (e.g., if the system changes between
different communication partners), the receiver has to be restarted. This can be done by
switching back to Idle mode and then again to RX mode. For that purpose, an automatic
mode is also available. This automatic mote switches to Idle mode and back into RX
mode every time a bit error occurs (see section “Digital Control Logic”).

Frequency Accuracy of the Crystals

RX Supply Current versus Temperature and Supply Voltage

The XTO is an amplitude regulated Pierce oscillator with integrated load capacitors. The
initial tolerances (due to the frequency tolerance of the XTAL, the integrated capacitors
on XTAL1, XTAL2 and the XTO’s initial transconductance gm) can be compensated to a
value within ±0.5 ppm by measuring the CLK output frequency and programming the
control registers 2 and 3 (see Table 20 on page 35 and Table 23 on page 36). The XTO
then has a remaining influence of less than ±2 ppm over temperature and supply volt­age due to the bandgap controlled gm of the XTO.

The needed frequency stability of the used crystals over temperature and aging is hence
±58 kHz/433.92 MHz - 2 × ±2.5 ppm = ±128.66 ppm for 433.92 MHz and
±58 kHz/868.3 MHz - 2 × ±2.5 ppm = ±61.8 ppm for 868.3 MHz. Thus, the used crys-
tals in receiver and transmitter each need to be better than ±64.33 ppm for 433.92 MHz
and ±30.9 ppm for 868.3 MHz. In access control systems it may be advantageous to
have a more tight tolerance at the base-station in order to relax the requirement for the
key fob.

Table 5 shows the typical supply current at 433.92 MHz of the transceiver in RX mode
versus supply voltage and temperature with VS = VS1 = VS2. As you can see the sup­ply current at 2.4 V and -40°C is less than the typical one which helps because this is
also the operation point where a lithium cell has the worst performance. The typical sup­ply current at 315 MHz or 868.3 MHz in RX mode is about the same as for 433.92 MHz.

Table 5. Measured 433.92 MHz Receive Supply Current in FSK Mode

VS = 2.4 V 3.0 V 3.6 V

T

= -40°C 8.4 mA 8.8 mA 9.2 mA

amb

T

= 25°C 9.9 mA 10.3 mA 10.8 mA

amb

T

= 105°C 11.4 mA 11.9 mA 12.4 mA

amb

Blocking, Selectivity As can be seen in Figure 9 on page 13 and Figure 10 on page 13, the receiver can

receive signals 3 dB higher than the sensitivity level in presence of very large blockers
of -47 dBm/-34 dBm with small frequency offsets of ±1/±10 MHz.

12

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Figure 9 shows narrow band blocking and Figure 10 wide band blocking characteristics.
The measurements were done with a useful signal of 433.92 MHz/FSK/

kBaud/±16 kHz/Manchester with a level of -106 dBm + 3 dB = -103 dBm which is

20

dB above the sensitivity level. The figures show how much a continuous wave signal

3
can be larger than -103
done at the 50

Ω input according to Figure 7 on page 10. At 1 MHz, for example, the

blocker can be 56 dB higher than -103 dBm which is -103 dBm + 56 dB = -47 dBm.
These values, together with the good intermodulation performance, avoid the need for a
SAW filter in the key fob application.

Figure 9. Narrow Band 3 dB Blocking Characteristic at 433.92 MHz

70,0

60,0

50,0

40,0

30,0

20,0

Blocking Level [dBC]

-10,0

dBm until the BER is higher than 10-3. The measurements were

10,0

0,0

-5,0 -4,0 -3,0 -2,0 -1,0 0,0 1,0 2,0 3,0 4,0 5,0

Distance of Interfering to Receiving Signal [MHz]

Figure 10. Wide Band 3 dB Blocking Characteristic at 433.92 MHz

80,0

70,0

60,0

50,0

40,0

30,0

20,0

10,0

Blocking Level [dBC]

0,0

-10,0

-50,0 -40,0 -30,0 -20,0 -10,0 0,0 10,0 20,0 30,0 40,0 50,0

Distance of Interfering to Receiving Signal [MHz]

Figure 11 on page 14 shows the blocking measurement close to the received frequency
to illustrate the selectivity and image rejection. This measurement was done 6 dB above
the sensitivity level with a useful signal of 433.92 MHz/FSK/20kBaud/±16 kHz/
Manchester with a level of -106 dBm + 6 dB = -100 dBm. The figure shows to which
extent a continuous wave signal can surpass -100 dBm until the BER is higher than

-3

. For example, at 1 MHz the blocker can than be 59 dB higher than -100 dBm which

10
is -100 dBm + 59 dB = -41 dBm.

4689B–RKE–04/04

13

Table 6 shows the blocking performance measured relative to -100 dBm for some other
frequencies. Note that sometimes the blocking is measured relative to the sensitivity
level (dBS) instead of the carrier (dBC).

Table 6. Blocking 6 dB Above Sensitivity Level with BER < 10

Frequency Offset Blocker Level Blocking

+0.75 MHz -45 dBm 55 dBC/61 dBS

-0.75 MHz -45 dBm 55 dBC/61 dBS

+1.5 MHz -38 dBm 62 dBC/68 dBS

-1.5 MHz -38 dBm 62 dBC/68 dBS

+10 MHz -30 dBm 70 dBC/76 dBS

-10 MHz -30 dBm 70 dBC/76 dBS

-3

The ATA5811/ATA5812 can also receive FSK and ASK modulated signals if they are
much higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is
often referred to as the nonlinear dynamic range which is the maximum to minimum
receiving signal which is 116 dB for 20 kBaud Manchester. This value is useful if two
transceivers have to communicate and are very close to each other.

Figure 11. Close In 6 dB Blocking Characteristic and Image Response at 433.92 MHz

70.0

60.0

50.0

40.0

30.0

20.0

10.0

Blocking Level [dBC]

0.0

-10.0

-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

Distance of Interfering to Receiving Signal [MHz]

Inband Disturbers, Data Filter, Quasi Peak Detector, Data Slicer

14

ATA5811/ATA5812 [Preliminary]

This high blocking performance makes it even possible for some applications using
quarter wave whip antennas to use a simple LC band-pass filter instead of a SAW filter
in the receiver. When designing such an LC filter take into account that the 3 dB block­ing at 433.92 MHz/2 = 216.96 MHz is 43 dBC and at 433.92 MHz/3 = 144.64 MHz is
48 dBC and at 2 × (433.92 MHz + 226 kHz) + -226 kHz = 868.066 MHz/868.518 MHz is
56 dBC. And especially that at 3 × (433.92 MHz + 226 kHz)+226 kHz = 1302.664 MHz
the receiver has its second LO harmonic receiving frequency with only 12 dBC blocking.

If a disturbing signal falls into the received band or a blocker is not continuous wave the
performance of a receiver strongly depends on the circuits after the IF filter. Hence the
demodulator, data filter and data slicer are important in that case.

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

The data filter of the ATA5811/ATA5812 implies a quasi peak detector. This results in a
good suppression of the above mentioned disturbers and exhibits a good carrier to
Gaussian noise performance. The required useful signal to disturbing signal ratio to be
received with a BER of 10
(BR_Range_0 ... BR_Range_2)/6 dB (BR_Range_3) in FSK mode. Due to the many dif­ferent waveforms possible these numbers are measured for signal as well as for
disturbers with peak amplitude values. Note that these values are worst case values and
are valid for any type of modulation and modulating frequency of the disturbing signal as
well as the receiving signal. For many combinations, lower carrier to disturbing signal
ratios are needed.

DEM_OUT Output The internal raw output signal of the demodulator Demod_Out is available at pin

DEM_OUT. DEM_OUT is an open drain output and must be connected to a pull-up
resistor if it is used (typically 100 kΩ) otherwise no signal is present at that pin.

RSSI Output The output voltage of the pin RSSI is an analog voltage, proportional to the input power

level. Using the RSSI output signal, the signal strength of different transmitters can be
distinguished. The usable dynamic range of the RSSI amplifier is 70 dB, the input power
range P(RF
RSSI characteristic of a typical device at 433.92 MHz with VS1 = VS2 = 2, 4 V to 3, 6 V
and T

amb

Figure 7 on page 10. At 868.3 MHz about 2.7 dB more signal level and at 315 MHz
about 1 dB less signal level is needed for the same RSSI results.

) is -115 dBm to -45 dBm and the gain is 8 mV/dB. Figure 12 shows the

IN

= -40°C to +105°C with a matched input according to Table 2 on page 10 and

-3

is less than 12 dB in ASK mode and less than 3 dB

Figure 12. Typical RSSI Characteristic versus Temperature and Supply Voltage

1100

1000

900

800

(mV)

700

RSSI

V

600

500

400

-120 -110 -100 -90 -80 -70 -60 -50 -40

Min.

P

RF_IN

Typ.

(dBm)

Max.

Frequency Synthesizer The synthesizer is a fully integrated fractional-N design with internal loop filters for

receive and transmit mode. The XTO frequency f
for the synthesizer. The bits FR0 to FR8 in control registers 2 and 3 (see Table 20 on
page 35 and Table 23 on page 36) are used to adjust the deviation of f
mode, at 433.92 MHz, the carrier has a phase noise of -111 dBC/Hz at 1 MHz and spu­rious at FREF of -66 dBC with a high PLL loop bandwidth allowing the direct modulation
of the carrier with 20 kBaud Manchester data. Due to the closed loop modulation any
spurious caused by this modulation are effectively filtered out as can be seen in Figure
15 on page 17. In RX mode the synthesizer has a phase noise of -120 dBC/Hz at 1 MHz
and spurious of -75 dBC.

is the reference frequency FREF

XTO

. In transmit

XTO

4689B–RKE–04/04

15

The initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor
tolerances and the parasitics of the board have to be compensated at manufacturing
setup with control registers 2 and 3 as can be seen in

Table 12 on page 24. The other
control words for the synthesizer needed for ASK, FSK and receive/transmit switching
are calculated internally. The RF (Radio Frequency) resolution is equal to the XTO fre
quency divided by 16384 which is 777.1 Hz at 315.0 MHz, 808.9 Hz at 433.92 MHz and

818.59

Hz at 868.3 MHz.

FSK/ASK Transmission Due to the fast modulation capability of the synthesizer and the high resolution, the car-

rier can be internally FSK modulated which simplifies the application of the transceiver.
The deviation of the transmitted signal is ±20 digital frequency steps of the synthesizer
which is equal to ±15.54 kHz for 315 MHz, ±16.17 kHz for 433.92 MHz and ±16.37 kHz
for 868.3 MHz.

Due to closed loop modulation with PLL filtering the modulated spectrum is very clean,
meeting ETSI and CEPT regulations when using a simple LC filter for the power ampli­fier harmonics as it is shown in Figure 5 on page 7. In ASK mode the frequency is
internally connected to the center of the FSK transmission and the power amplifier is
switched on and off to perform the modulation. Figure 13 to Figure 15 on page 17 show
the spectrum of the FSK modulation with pseudo random data with
20 kBaud/±16.17 kHz/Manchester and 5 dBm output power.

Figure 13. FSK-modulated TX Spectrum (20 kBaud/±16.17 kHz/Manchester Code)

Ref 10 dBm Atten 20 dB
Samp
Log
10
dB/

-

16

VAvg
50
W1 S2
S3 FC

Center 433.92 MHz
Res BW 100 kHz VBW 100 kHz

ATA5811/ATA5812 [Preliminary]

Span 30 MHz
Sweep 7.5 ms (401 pts)

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Figure 14. Unmodulated TX Spectrum f

Ref 10 dBm
Samp

Log
10
dB/

VAvg
50
W1 S2
S3 FC

Center 433.92 MHz
Res BW 10 kHz

FSK_L

Atten 20 dB

VBW 10 kHz

Span 1 MHz

Sweep 27.5 ms (401 pts)

Figure 15. FSK-modulated TX Spectrum (20 kBaud/±16.17 kHz/Manchester Code)

Ref 10 dBm Atten 20 dB
Samp
Log
10
dB/

VAvg
50
W1 S2
S3 FC

Center 433.92 MHz
Res BW 10 kHz VBW 10 kHz

Span 1 MHz
Sweep 27.5 ms (401 pts)

4689B–RKE–04/04

17

Output Power Setting and PA Matching at RF_OUT

The Power Amplifier (PA) is a single-ended open collector stage which delivers a cur­rent pulse which is nearly independent of supply voltage, temperature and tolerances
due to bandgap stabilization. Resistor R

, see Figure 16 on page 19, sets a reference

1

current which controls the current in the PA. A higher resistor value results in a lower
reference current, a lower output power and a lower current consumption of the PA. The
usable range of R

is 15 kΩ to 56 kΩ. Pin PWR_H switches the output power range

1

between about 0 dBm to 5 dBm (PWR_H = GND) and 5 dBm to 10 dBm (PWR_H =
AVCC) by multiplying this reference current with a factor 1 (PWR_H = GND) and 2.5
(PWR_H = AVCC) which corresponds to about 5 dB more output power.

If the PA is switched off in TX mode, the current consumption without output stage with
VS1 = VS2 = 3 V, T

= 25°C is typically 6.5 mA for 868.3 MHz and 6.95 mA for

amb

315 MHz and 433.92 MHz.
The maximum output power is achieved with optimum load resistances R

according

Lopt

to Table 7 on page 19 with compensation of the 1.0 pF output capacitance of the
RF_OUT pin by absorbing it into the matching network consisting of L

, C1, C3 as shown

1

in Figure 16 on page 19. There must be also a low resistive DC path to AVCC to deliver
the DC current of the power amplifier's last stage. The matching of the PA output was
done with the circuit according to Figure 16 on page 19 with the values in Table 7 on
page 19. Note that value changes of these elements may be necessary to compensate
for individual board layouts.

Example:
According to Table 7 on page 19, with a frequency of 433.92 MHz and output power of
11 dBm the overall current consumption is typically 17.8 mA hence the PA needs

17.8 mA - 6.95 mA = 10.85 mA in this mode which corresponds to an overall power
amplifier efficiency of the PA of (10

(11dBm/10)

× 1 mW)/(3 V × 10.85 mA) × 100% = 38.6%

in this case.
Using a higher resistor in this example of R

= 1.091 × 22 kΩ = 24 kΩ results in 9.1%

1

less current in the PA of 10.85 mA/1.091 = 9.95 mA and 10 × log(1.091) = 0.38 dB
less output power if using a new load resistance of 300 Ω × 1.091 = 327 Ω. The result-
ing output power is then 11 dBm - 0.38 dB = 10.6 dBm and the overall current
consumption is 6.95 mA + 9.95 mA = 16.9 mA.

The values of Table 7 on page 19 were measured with standard multi-layer chip induc­tors with quality factors Q according to Table 7 on page 19. Looking to the 433.92
MHz/11 dBm case with the quality factor of Q
mated with the parallel equivalent resistance of the inductor R
and the matching loss with 10 log (1 + R

Lopt/Rloss

= 43 the loss in this inductor is esti-

L1

= 2 × π × f × L × Q

loss

) which is equal to 0.32 dB losses in

L1

this inductor. Taking this into account the PA efficiency is then 42% instead of 38.6%.

18

Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply
voltage higher than 2.7 V, whereas the low power mode (PWR_H = GND) can be used
down to 2.4 V as can be seen in the section “Electrical Characteristics”.

The supply blocking capacitor C

(10 nF) has to be placed close to the matching net-

2

work because of the RF current flowing through it.

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Figure 16. Power Setting and Output Matching

AVCC

L

1

C

1

RF

OUT

C

3

R

VPWR_H

Table 7. Measured Output Power and Current Consumption with VS1 = VS2 = 3 V, T

Frequency (MHz) TX Current (mA) Output Power (dBm) R1 (kΩ) VPWR_H R

C

2

ATA5811/ATA5812

10

RF_OUT

8

R_PWR

1

9

PWR_H

= 25°C

amb

(Ω)L1 (nH) QL1 C1 (pF) C3 (pF)

Lopt

315 8.5 0.4 56 GND 2500 82 28 1.5 0
315 10.5 5.7 27 GND 920 68 32 2.2 0
315 16.7 10.5 27 AVCC 350 56 35 3.9 0

433.92 8.6 0.1 56 GND 2300 56 40 0.75 0

433.92 11.2 6.2 22 GND 890 47 38 1.5 0

433.92 17.8 11 22 AVCC 300 33 43 2.7 0

868.3 9.3 -0.3 33 GND 1170 12 58 1.0 3.3

868.3 11.5 5.4 15 GND 471 15 54 1.0 0

868.3 16.3 9.5 22 AVCC 245 10 57 1.5 0

Output Power and TX Supply Current versus Supply Voltage and Temperature

4689B–RKE–04/04

Table 8 on page 20 shows the measurement of the output power for a typical device
with VS1 = VS2 = VS in the 433.92 MHz and 6.2 dBm case versus temperature and
supply voltage measured according to Figure 16 on page 19 with components according
to Table 7. As opposed to the receiver sensitivity the supply voltage has here the major
impact on output power variations because of the large signal behavior of a power
amplifier. Thus, a two battery system with voltage regulator or a 5 V system shows
much less variation than a 2.4 V to 3.6 V one battery system because the supply voltage
is then well within 3.0 V and 3.6 V.

The reason is that the amplitude at the output RF_OUT with optimum load resistance is

2

AVCC - 0.4 V and the power is proportional to (AVCC - 0.4 V)
not changed. This means that the theoretical output power reduction if reducing the sup­ply voltage from 3.0 V to 2.4 V is 10 log ((3 V - 0.4 V)

2

/(2.4 V - 0.4 V)2) = 2.2 dB. Table 8

if the load impedance is

on page 20 shows that principle behavior in the measurement. This is not the same
case for higher voltages since here increasing the supply voltage from 3 V to 3.6 V
should theoretical increase the power by 1.8 dB but only 0.8 dB in the measurement
shows that the amplitude does not increase with the supply voltage because the load
impedance is optimized for 3 V and the output amplitude stays more constant.

19

Table 8. Measured Output Power and Supply Current at 433.92 MHz, PWR_H = GND

VS = 2.4 V 3.0 V 3.6 V

T

T

T

amb

amb

amb

= -40°C

= +25°C

= +105°C

10.19 mA

3.8 dBm

10.62 mA

4.6 dBm

11.4 mA

3.8 dBm

10.19 mA

5.5 dBm

11.19 mA

6.2 dBm

12.02 mA

5.4 dBm

10.78 mA

6.2 dBm

11.79 mA

7.1 dBm

12.73 mA

6.3 dBm

Table 9 shows the relative changes of the output power of a typical device compared to

3.0 V/25°C. As can be seen a temperature change to -40° as well as to +105° reduces
the power by less than 1 dB due to the bandgap regulated output current. Measure­ments of all the cases in Table 7 on page 19 over temperature and supply voltage have
shown about the same relative behavior as shown in Table 9

Table 9. Measurements of Typical Output Power Relative to 3 V/25°

VS = 2.4 V 3.0 V 3.6 V

= -40°C -2.4 dB -0.7 dB 0 dB

T

amb

= +25°C -1.6 dB 0 dB +0.9 dB

T

amb

= +105°C -2.4 dB -0.8 dB +0.1 dB

T

amb

RX/TX Switch The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received

power to the LNA in RX mode. To do this, it has a low impedance to GND in TX mode
and a high impedance to GND in RX mode. To design a proper RX/TX decoupling
a linear simulation tool for radio frequency design together with the measured device
impedances of Table 1 on page 10, Table 7 on page 19, Table 10 and Table 11 on page
22 should be used, but the exact element values have to be found on board. Figure 17
on page 21 shows an approximate equivalent circuit of the switch. The principal switch­ing operation is described here according to the application of Figure 4 on page 6. The
application of Figure 5 on page 7 works similarly.

20

Table 10. Impedance of the RX/TX Switch RX_TX2 Shorted to GND

Frequency Z(RX_TX1) TX Mode Z(RX_TX1) RX Mode

MHz (4.8 + j3.2) Ω (11.3 - j214) Ω

315

MHz (4.5 + j4.3) Ω (10.3 - j153) Ω

433.92

MHz (5 + j9) Ω (8.9 - j73) Ω

868.3

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

Figure 17. Equivalent Circuit of the Switch

1.6 nH

RX_TX1

Matching Network in TX Mode

Matching Network in RX Mode

2.5 pF

11 Ω

TX

5 Ω

In TX mode the 20 mm long and 0.4 mm wide transmission line which is much shorter
than λ/4 is approximately switched in parallel to the capacitor C
connection between C
mission line into the loop antenna with pin RF_OUT, L
(using a C

without the added 7.6 pF as discussed later). The transmission line can be

9

approximated with a 16

and C9 has an impedance of about 50 Ω locking from the trans-

8

2

nH inductor in series with a 1.5 Ω resistor, the closed switch can

to GND. The antenna

9

, C10, C8 and C9 connected

be approximated according to Table 10 on page 20 with the series connection of 1.6 nH
and 5 Ω in this mode. To have a parallel resonant high impedance circuit with little RF
power going into it looking from the loop antenna into the transmission line a capacitor of
about 7.6 pF to GND is needed at the beginning of the transmission line (this capacitor
is later absorbed into C
keep the 50 Ω impedance in RX mode at the end of this transmission line C

which is then higher as needed for 50 Ω transformation). To

9

has to be

7

also about 7.6 pF. This reduces the TX power by about 0.5 dB at 433.92 MHz compared
to the case the where the LNA path is completely disconnected.

In RX mode the RF_OUT pin has a high impedance of about 7 kΩ in parallel with 1.0 pF
at 433.92
the inductor L

MHz as can be seen in Table 11 on page 22. This together with the losses of

with 120 nH and Q

2

= 25 gives about 3.7 kΩ loss impedance at

L2

RF_OUT. Since the optimum load impedance in TX mode for the power amplifier at
RF_OUT is 890 Ω the loss associated with the inductor L

and the RF_OUT pin can be

2

estimated to be 10 × log(1 + 890/3700) = 0.95 dB compared to the optimum matched
loop antenna without L

and RF_OUT. The switch represents, in this mode at

2

433.92 MHz, about an inductor of 1.6 nH in series with the parallel connection of 2.5 pF
and 2.0 kΩ. Since the impedance level at pin RX_TX1 in RX mode is about 50 Ω this
only negligiblably dampens the received signal by about 0.1 dB. When matching the
LNA to the loop antenna the transmission line and the 7.6 pF part of C
into account when choosing the values of C

and L1 so that the impedance seen from

11

has to be taken

9

the loop antenna into the transmission line with the 7.6 pF capacitor connected is 50 Ω.
Since the loop antenna in RX mode is loaded by the LNA input impedance the loaded Q
of the loop antenna is lowered by about a factor of 2 in RX mode hence the antenna
bandwidth is higher than in TX mode.

4689B–RKE–04/04

21

Table 11. Impedance RF_OUT Pin in RX Mode

Frequency Z(RF_OUT)RX RP//C

315 MHz 36 Ω − j 502 Ω 7 kΩ / / 1.0 pF

MHz 19 Ω − j 366 Ω 7 kΩ / / 1.0 pF

433.92

MHz 2.8 Ω − j 141Ω 7 kΩ / / 1.3 pF

868.3

P

Note that if matching to 50 Ω, like in Figure 5 on page 7, a high Q wire wound inductor
with a Q > 70 should be used for L

to minimize its contribution to RX losses which will

2

otherwise be dominant. The RX and TX losses will be in the range of 1.0 dB there.

XTO The XTO is an amplitude regulated Pierce oscillator type with integrated load capaci-

tances (2 × 18 pF with a tolerance of ±17%) hence C
The XTO oscillation frequency f

is the reference frequency FREF for the fractional-N

XTO

= 7.4 pF and C

Lmin

synthesizer. When designing the system in terms of receiving and transmitting fre­quency offset the accuracy of the crystal and XTO have to be considered.

The synthesizer can adjust the local oscillator frequency for more than ±150 ppm at

433.92 MHz/315 MHz and up to ±118 ppm at 868.3 MHz of initial frequency error in

. This is done at nominal supply voltage and temperature with the control registers 2

f

XTO

and 3 (see Table 20 on page 35 and Table 23 on page 36). The remaining local oscilla­tor tolerance at nominal supply voltage and temperature is then < ±0.5 ppm. A XTO
frequency error of ±150 ppm/±118 ppm can hence be tolerated due to the crystal toler­ance at 25°C and the tolerances of C

and CL2. The XTO’s gm has very low influence of

L1

less than ±2 ppm on the frequency at nominal supply voltage and temperature.

= 10.6 pF.

Lmax

Over temperature and supply voltage, the XTO's additional pulling is only ±2 ppm if

≤ 7 fF. The XTAL versus temperature and its aging is then the main source of fre-

C

m

quency error in the local oscillator.
The XTO frequency depends on XTAL properties and the load capacitances C

XTAL1 and XTAL2. The pulling of f

from the nominal f

XTO

is calculated using the fol-

XTAL

L1, 2

at pin

lowing formula:

C

m

--------

P

C

is the crystal's motional, C0 the shunt and CLN the nominal load capacitance of the

m

----------- ------------- ------------- ---------- --------------

× 10

C

2

0CLN

XTAL found in its data sheet. C
circuit and consists of C

C

LNCL

+()C0CL+()×

–

and CL2 in series connection.

L1

6

ppm.

×=

is the total actual load capacitance of the crystal in the

L

Figure 18. XTAL with Load Capacitance

Crystal equivalent circuit

XTAL

C

L1

C

L2

C

0

C

L

m

R

m

m

22

ATA5811/ATA5812 [Preliminary]

CL = CL1 CL2/(CL1 + (CL2)

×

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

With C
to P
pulling is P

≤ 14 fF, C0 ≥ 1.5 pF, C

m

≤ ±100 ppm and with Cm ≤ 7 fF, C0 ≥ 1.5 pF, C

≤ ±50 ppm.

= 9 pF and CL = 7.6 pF to 10.6 pF the pulling amounts

LN

= 9 pF and CL = 7.4 pF to 10.6 pF the

LN

Since typical crystals have less than ±50 ppm tolerance at 25° the compensation is not
critical.

C

of the XTAL has to be lower than C

0

/2 = 3.8 pF for a Pierce oscillator type in order

Lmin

to not enter the steep region of pulling versus load capacitance where there is a risk of
an unstable oscillation.

To ensure proper start-up behavior the small signal gain and thus the negative resis­tance provided by this XTO at start is very large, for example oscillation starts up even in
worst case with a crystal series resistance of 1.5

kΩ at C0 ≤ 2.2 pF with this XTO. The

negative resistance is approximately given by

Z

⎧⎫

1Z3Z2Z3Z1

Re Z

{}Re

xtocore

with Z

, Z2 as complex impedances at pin XTAL1 and XTAL2 hence

1

Z1 = -j/(2 × π × f
Z

consists of crystals C0 in parallel with an internal 110 kΩ resistor hence

3

Z3 = -j/(2 × π × f

------------- ------------- ------------ ----------- ------------- ------------- ------------ ------------- --

=

⎨⎬

Z

⎩⎭

1Z2Z3Z1Z2

× CL1) + 5 Ω and Z2 = -j/(2 × π × f

XTO

× C0) /110 kΩ, gm is the internal transconductance between

XTO

+ Z2× Z3gm×××+×

× gm×+++

× CL2) + 5 Ω.

XTO

XTAL1 and XTAL2 with typically 19 ms at 25°C.
With f

= 13.5 MHz, gm = 19 ms, CL = 9 pF, C0 = 2.2 pF this results in a negative

XTO

resistance of about 2 kΩ. The worst case for technological, supply voltage and tempera­ture variations is then for C

≤ 2.2 pF always higher than 1.5 kΩ.

0

Due to the large gain at start the XTO is able to meet a very low start-up time. The oscil­lation start-up time can be estimated with the time constant τ.

------------ ------------- ------------ ----------- ------------- ------------- ------------ ------------- -----=

τ

× f

4 π

After 10

2

2

× Cm× Re Z

m

τ to 20 τ an amplitude detector detects the oscillation amplitude and sets

2

()Rm+()×

xtocore

XTO_OK to High if the amplitude is large enough, this sets N_RESET to High and acti­vates the CLK output if CLK_ON in control register 3 is High (see Table 20 on page 35).
Note that the necessary conditions of the VSOUT and DVCC voltage also have to be ful­filled (see Figure 19 on page 24 and Figure 21 on page 26).

To save current in Idle and sleep mode, the load capacitors partially are switched off in
this modes with S1 and S2 seen in Figure 19 on page 24.

It is recommended to use a crystal with C
and C

= 1.5 pF to 2.2 pF.

0

= 4.0 fF to 7.0 fF, CLN = 9 pF, Rm < 120 Ω

m

4689B–RKE–04/04

23

Figure 19. XTO Block Diagram

XTAL1 XTAL2

C

L1

C

8 pF 8 pF

S1 S2

In IDLE mode and during Sleep mode (RX_Polling) the
switches S1 and S2 are open.

10 pF 10 pF

L2

f

XTO

Amplitude

Detector

Baud1

Divider

/3

Divider

/16

Divider

/1

/2
/4

/8

/16

Baud0

CLK_ON
(Control
Register 3)

XLim

CLK

&

VSOUT_OK
(from power supply)

f

DCLK

f

XDCLK

DVCC_OK
(from power supply)

XTO_OK

(to Reset Logic)

To find the right values used in the control registers 2 and 3 (see Table 20 on page 35
and Table 23 on page 36) the relationship between f

and the fRF is shown in

XTO

Table 12. To determine the right content the frequency at pin CLK as well as the output
frequency at RF_OUT in ASK mode can be measured, than the FREQ value can be cal­culated according to Table 12 so that f

Table 12. Calculation of f

Frequency (MHz)

433.92 AVCC 0 13.25311 f

868.3 GND 0 13.41191 fRF - 16.37 kHz fRF + 16.37 kHz

315.0 AVCC 1 12.73193 fRF - 15.54 kHz fRF + 15.54 kHz

RF

Pin 6

433_N868

CREG1

Bit(4)

FS f

(MHz) f

XTO

= f

RF

⎛⎞

f

f

f

32 5

×

XTO

⎝⎠

⎛⎞

64 5

×

XTO

⎝⎠

⎛⎞

24 5

×

XTO

⎝⎠

is exactly the desired radio frequency

RF

TX_ASK

FREQ 20,5+

------------ ------------ ----------+,

FREQ 20,5+

------------- ------------- --------+,

FREQ 20,5+

------------- ------------- --------+,

= f

RX

16384

16384

16384

f

TX_FSK_L

- 16.17 kHz f

RF

f

TX_FSK_H

+ 16.17 kHz

RF

24

ATA5811/ATA5812 [Preliminary]

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0
to FR8 in control register 2 and 3 and is calculated as follows:

FREQ = 3584 + FREQ2 + FREQ3
Only the range of FREQ = 3803 to 4053 of this register should be used because other-

wise harmonics of f

XTO

and f

(FREQ_min = 3803, FREQ_max = 4053). The resulting tuning range is

MHz and more than ±150 ppm at 433.92 MHz or 315 MHz.

868.3

can cause interference with the received signals

CLK

±118 ppm at

Pin CLK Pin CLK is an output to clock a connected microcontroller. The clock frequency f

calculated as follows:

f

XTO

-----------=

3

V

= 2.3 V (typically)

Thres_1

Figure 20. Clock Timing

VSOUT

CLK

N_RESET

CLK_ON

(Control Register 3)

f

CLK

Because the enabling of pin CLK is asynchronous the first clock cycle may be incom­plete. The signal at CLK output has a nominal 50% duty cycle.

V

= 2.38 V (typically)

Thres_2

CLK

is

Basic Clock Cycle of the Digital Circuitry

4689B–RKE–04/04

The complete timing of the digital circuitry is derived from one clock. According to
Figure 19 on page 24, this clock cycle T

is derived from the crystal oscillator (XTO)

DCLK

in combination with a divider.

f

f

DCLK

T

DCLK

XTO

-----------=

16

controls the following application relevant parameters:

• Timing of the polling circuit including Bit-check

• TX baud rate
The clock cycle of the Bit-check and the TX baud rate depends on the selected baud-

rate range (BR_Range) which is defined in control register 6 (see Table 33 on page 38)
and XLim which is defined in control register 4 (see Table 26 on page 36). This clock
cycle T

BR_Range ⇒ BR_Range 0: T

is defined by the following formulas for further reference:

XDCLK

BR_Range 1: T
BR_Range 2: T
BR_Range 3: T

XDCLK
XDCLK
XDCLK
XDCLK

= 8 × T
= 4 × T
= 2 × T
= 1 × T

DCLK
DCLK
DCLK
DCLK

× XLim
× XLim
× XLim
× XLim

25

Power Supply

Figure 21. Power Supply

VS1

VS2

VSINT

(Control Register 1)

AVCC_EN

PWR_ON

T1

T5

DVCC_OK

OFFCMD

(Command via SPI)

VS1+

0.55V

VAUX

typ.

IN

≥ 1

≥ 1

S R Q
0 0 no change
0 1 0
1 0 1
1 1 1

P_On_Aux

(Status Register)

V_REG2

3.25 V typ.

V_REG1

IN OUT

3.25 V typ.

EN

FF1

Q

S

R

and

OUT

SW_VSOUT

SW_AVCC

SW_DVCC

V_Monitor

(1.5 V typ.)

V_Monitor
(2.3 V/

2.38 V typ.)

AVCC

DVCC

DVCC_OK

(to XTO and
Reset Logic )

VSOUT_OK
(to XTO and

Reset Logic)

Low_Batt

(Status Register

and Reset Logic)

VSOUT

26

VSOUT_EN

(Control Register 3)

EN

The supply voltage range of the ATA5811/ATA5812 is 2.4 V to 3.6 V or 4.4 V to 6.6 V.
Pin VS1 is the supply voltage input for the range 2.4 V to 3.6 V and is used in battery

applications using a single lithium 3 V cell. Pin VS2 is the voltage input for the range

4.4 V to 6.6 V (2 Battery Application and Car Applications) in this case the voltage regu­lator V_REG1 regulates VS1 to typically 3.25 V. If the voltage regulator is active a
blocking capacitor of 2.2 µF has to be connected to VS1.

Pin VAUX is an input for an additional auxiliary voltage supply and can be connected
e.g., to an inductive supply (see Figure 26 on page 32). This input can only be used
together with a rectifier or as in the application of Figure 5 on page 7 and must otherwise
be left open.

Pin VSINT is the voltage input for the Microcontoller_Interface and must be connected
to the power supply of the microcontroller. The voltage range of V
(see Figure 25 on page 31 and Figure 26 on page 32).

ATA5811/ATA5812 [Preliminary]

is 2.4 V to 5.25 V

VSINT

4689B–RKE–04/04

ATA5811/ATA5812 [Preliminary]

AVCC is the internal operation voltage of the RF transceiver and is feed via the switch
SW_AVCC by VS1. AVCC must be blocked with a 68 nF capacitor (see Figure 4 on
page 6, Figure 5 on page 7 and Figure 6 on page 8).

DVCC is the internal operation voltage of the digital control logic and is feed via the
switch SW_DVCC by VS1 or VSOUT. DVCC must be blocked on pin DVCC with 68 nF
(see Figure 4 on page 6, Figure 5 on page 7 and Figure 6 on page 8).

Pin VSOUT is a power supply output voltage for external devices (e.g., microcontroller)
and is fed via the switch SW_VSOUT by VS1 or via V_REG2 by the a auxiliary voltage
supply VAUX. The voltage regulator V_REG2 regulates VSOUT to typically 3.25 V. If
the voltage regulator is active a blocking capacitor of 2.2 µF has to be connected to
VSOUT. VSOUT can be switched off by the VSOUT_EN bit in control register 3 and is
then reactivated by conditions found in Figure 22 on page 28.

Pin N_RESET is set to low if the voltage V

at pin VSOUT drops below 2.3 V (typi-

VSOUT

cally) and can be used as a reset signal for a connected microcontroller (see Figure 23
on page 30 and Figure 24 on page 31).

Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the trans-

ceiver (active low).
For current consumption reasons it is recommended to set T1 to T5 to GND or

PWR_ON to VCC only temporarily. Otherwise an additional current flows.
There are two voltage monitors generating the following signals (see Figure 21 on page

26):

• DVCC_OK if DVCC > 1.5 V typically

• VSOUT_OK if VSOUT > V

• Low_Batt if VSOUT < V

Thres2

(2.3 V typically)

Thres1

(2.38 V typically)

4689B–RKE–04/04

27