Features
• Contactless Power Supply
• Contactless Read/Write Data Transmission
• Radio Frequency f
• Basic Mode or Extended Mode
• Compatible with T5557, ATA5567
• Replacement for e5551/T5551 in Most Common Operation Modes
• Configurable for ISO/IEC 11784/785 Compatibility
• Total 363 Bits EEPROM Memory: 11 Blocks (32 Bits + 1 Lock Bit)
• High Q-antenna Tolerance Due to Build in Options
• Adaptable to Different Applications: Access Control, Animal ID and Waste
Management
• On-chip Trimmed Antenna Capacitor
• Pad Options
– ATA5577M1
• 100 µm × 100 µm for Wire Bonding or Flip Chip
– ATA5577M2
• 200 µm × 400 µm for Direct Coil Bonding
from 100 kHz to 150 kHz
RF
Read/Write LF
RFID IDIC
100 to 150 kHz
ATA5577
1. Description
The ATA5577 is a contactless read/write identification IC (IDIC®) for applications in
the 125-kHz or 134-kHz frequency band. A single coil connected to the chip serves as
the IC’s power supply and bi-directional communication interface. The antenna and
chip together form a transponder or tag.
The on-chip 363-bit EEPROM (11 blocks with 33 bits each) can be read and written
block-wise from a base station (reader).
Data is transmitted from the IDIC (uplink) using load modulation. This is achieved by
damping the RF field with a resistive load between the two terminals Coil 1 and Coil 2.
The IC receives and decodes serial base station commands (downlink), which are
encoded as 100% amplitude modulated (OOK) pulse-interval-encoded bit streams.
A complete datasheet with further technical data is available on request. Please contact your local sales office.
Summary
Preliminary
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4967DS–RFID–10/08
2. Compatibility
Data
Reader
or
Base station
ATA5577
Power
1
) Mask option
1
)
Transponder
Coil interface
Controller
Memory
Memory
(363-bit EEPROM)
Modulator
Option register
Analog front end
Data-rate
generator
Write
decoder
POR
Coil 2
Coil 1
Controller
Test logic HV generator
Input register
Mode register
1
) Mask option
1
)
The ATA5577 is designed to be compatible with the T5557/ATA5567. The structure of the configuration register is identical. The two modes, Basic mode and Extended mode, are also
available. The ATA5577 is able to replace the e5551/T5551 in most common operation modes.
In all applications, the correct functionality of the replacements must be evaluated and proved.
For further details, refer to Atmel
3. System Block Diagram
Figure 3-1. RFID System Using ATA5577 Tag
®
’s web site for product-relevant application notes.
4. ATA5577 - Functional Blocks
Figure 4-1. Block Diagram
2
ATA5577 [Preliminary]
4967DS–RFID–10/08
4.1 Analog Front End (AFE)
The AFE includes all circuits that are directly connected to the coil terminals. It generates the
IC's power supply and handles the bi-directional data communication with the reader. It consists
of the following blocks:
• Rectifier to generate a DC supply voltage from the AC coil voltage
• Clock extractor
• Switchable load between Coil 1 and Coil 2 for data transmission from the tag to the reader
• Field-gap detector for data transmission from the base station to the tag
• ESD-protection circuitry
4.2 Data-rate Generator
The data rate is binary programmable to operate at any even-numbered data rate between RF/2
and RF/128 or to any of the fixed Basic mode data rates (RF/8, RF/16, RF/32, RF/40, RF/50,
RF/64, RF/100 and RF/128).
4.3 Write Decoder
The write decoder detects the write gaps and verifies the validity of the data stream according to
the Atmel e555x downlink protocol (pulse interval encoding).
ATA5577 [Preliminary]
4.4 HV Generator
This on-chip charge pump circuit generates the high voltage required to program the EEPROM.
4.5 DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regulates this RF source and uses it to generate its supply voltage.
4.6 Power-On Reset (POR)
The power-on reset circuit blocks the voltage supply to the IDIC until an acceptable voltage
threshold has been reached.
4.7 Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
4.8 Controller
The control logic module executes the following functions:
• Load mode register with configuration data from EEPROM block 0 after power-on and during
reading
• Load option register with the settings for the analog front end stored in EEPROM page 1
block 3 after power-on and during reading
• Control all EEPROM memory read/write access and data protection
• Handles the downlink command decoding detecting protocol violations and error conditions
4967DS–RFID–10/08
3