Rainbow Electronics AT93C86 User Manual

Features

• Low-voltage and Standard-voltage Operation

–2.7(V

=2.7Vto5.5V)

CC

• User Selectable Internal Organization

– 16K:2048x8or1024 x 16

• 3-wire Serial Interface

• Sequential Read Operation

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• 2 MHz Clock Rate (5V) Compatibility

• Self-timed Write Cycle (10 ms max)

• High Reliability

– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages

Description

3-wire Serial
EEPROM

16K (2048 x 8 or 1024 x 16)

The AT93C86 provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pin
is connected to V

and 2048 words of 8 bits each when it is tied to ground. The

CC

device is optimized for use in many industrial and commercial applications where low
power and low voltage operations are essential. The AT93C86 is available in space
saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages.

The AT93C86 is enabled through the Chip Select pin (CS), and accessed via a 3-wire
serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).

(continued)

Pin Configurations

CS
SK

DI

DO

8-lead PDIP

1
2
3
4

8-lead SOIC

1
2
3
4

VCC

8

DC

7

ORG

6

GND

5

VCC

8

DC

7

ORG

6

GND

5

Pin Name Function

CS Chip Select

SK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

GND Ground

VCC Power Supply

ORG Internal Organization

DC Don’t Connect

CS
SK

DI

DO

AT93C86

CS
SK

DI

DO

8-lead TSSOP

1
2
3
4

8

VCC

7

DC

6

ORG

5

GND

Rev. 1237D–SEEPR–08/02

1

Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin
DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle
is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of
a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C86 is available in a 2.7V to 5.5V
version.

Absolute Maximum Ratings*

Operating Temperature .................................. -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

Voltage on any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current ........................................................ 5.0 mA

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

Block Diagram

Vcc GND

MEMORY ARRAY

ORG

DI

CS

SK

Note: 1. When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-

tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.

2048 x 8

OR

1024 x 16

DATA

REGISTER

MODE

DECODE

LOGIC

CLOCK

GENERATOR

ADDRESS
DECODER

OUTPUT
BUFFER

DO

2

AT93C86

1237D–SEEPR–08/02

AT93C86

Pin Capacitance

(1)

Applicable over recommended operating range from TA=25°C, f = 1.0 MHz, VCC= +5.0V (unless otherwise noted).

Symbol Test Conditions Max Units Conditions

C

OUT

C

IN

Output Capacitance (DO) 5 pF V

OUT

=0V

Input Capacitance (CS, SK, DI) 5 pF VIN=0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +2.7V to +5.5V,
T

=0°Cto+70°C, VCC= +2.7V to +5.5V (unless otherwise noted).

AC

Symbol Parameter Test Condition Min Typ Max Unit

V

CC1

V

CC2

I

CC

I

SB1

I

SB2

I

IL

I

OL

(1)

V

IL1

(1)

V

IH1

(1)

V

IL2

(1)

V

IH2

V

OL1

V

OH1

V

OL2

V

OH2

Note: 1. V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

READ at 1.0 MHz 0.5 2.0 mA

Supply Current VCC=5.0V

WRITE at 1.0 MHz 0.5 2.0 mA

Standby Current VCC= 2.7V CS = 0V 6.0 10.0 µA

Standby Current VCC= 5.0V CS = 0V 17 30 µA

Input Leakage VIN=0VtoV

Output Leakage VIN=0VtoV

Input Low Voltage
Input High Voltage

Input Low Voltage
Input High Voltage

Output Low Voltage
Output High Voltage

Output Low Voltage
Output High Voltage

min and VIHmax are reference only and are not tested.

IL

4.5V ≤ V

V

≤ 2.7V

CC

4.5V ≤ V

V

≤ 2.7V

CC

CC

CC

CC

CC

≤ 5.5V

≤ 5.5V

=2.1mA 0.4 V

I

OL

I

=-0.4mA 2.4 V

OH

I

=0.15mA 0.2 V

OL

I

= -100 µA VCC-0.2 V

OH

-0.6

V

x0.7

CC

-0.6

V

x0.7

CC

0.1 1.0 µA

0.1 1.0 µA

x0.3

V

CC

V

+1

CC

x0.3

V

CC

V

+1

CC

V

V

1237D–SEEPR–08/02

3

AC Characteristics

Applicable over recommended operating range from TA=-40°Cto+85°C, VCC= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

f

SK

t

SKH

t

SKL

t

CS

t

CSS

t

DIS

t

CSH

t

DIH

t

PD1

t

PD0

t

SV

t

DF

t

WP

Endurance

SK Clock
Frequency

SK High Time

SK Low Time

Minimum CS
Low Time

CSSetupTime RelativetoSK

DISetupTime RelativetoSK

CS Hold Time Relative to SK 0 ns

DI Hold Time Relative to SK

Output Delay to ‘1’ AC Test

Output Delay to ‘0’ AC Test

CS to Status Valid AC Test

CS to DO in High
Impedance

WriteCycleTime

(1)

5.0V, 25°C, Page Mode 1M Write Cycles

4.5V ≤ V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

4.5V ≤ V

≤ VCC ≤ 5.5V

2.7V

AC Test
CS = V

IL

CC

CC

≤ 5.5V

≤ 5.5V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V

4.5V

≤ VCC ≤ 5.5V

2.7V

4.5V ≤ V

≤ VCC ≤ 5.5V

2.7V

≤ VCC ≤ 5.5V 4 ms

4.5V

Note: 1. This parameter is characterized and is not 100% tested.

CC

0
0

250
250

250
250

250
250

50
50

100
100

100
100

≤ 5.5V

2
1

250
250

250
250

250
250

100
100

10 ms

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

4

AT93C86

1237D–SEEPR–08/02

Instruction Set for the AT93C86

Address Data

AT93C86

Instruction SB Op Code

READ 1 10 A

EWEN 1 00 11XXXXXXXX 11XXXXXXXX Write enable must precede all

ERASE 1 11 A

WRITE 1 01 A

ERAL 1 00 10XXXXXXXX 10XXXXXXXX Erases all memory locations.

WRAL 1 00 01XXXXXXXX 01XXXXXXXX D

EWDS 1 00 00XXXXXXXX 00XXXXXXXX Disables all programming instructions.

Functional Description

10-A0

10-A0

10-A0

The AT93C86 is accessed via a simple and versatile 3-wire serial communication inter­face. Device operation is controlled by seven instructions issued by the host processor.
A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic

A9-A

A9-A

A9-A

0

0

0

D7-D0D15-D0Writes memory location An-A0.

7-D0

D15-D0Writes all memory locations.

Commentsx8 x16 x8 x16

Reads data stored in memory,
at specified address.

programming modes.

Erases memory location An-A0.

Valid only at V

Valid when V
Disable Register cleared.

= 4.5V to 5.5V.

CC

= 4.5V to 5.5V and

CC

“1”) followed by the appropriate Op Code and the desired memory Address location.

READ (READ): The Read (READ) instruction contains the Address code for the mem­ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

1237D–SEEPR–08/02

ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V

CC

power is removed from the part.

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t

CS

A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, t

,starts

WP

after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (t

). A logic “0” at DO indicates that programming is still in progress. A logic

CS

“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A

READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, t

WP

.

).

5