• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2MHzClockRate(5V)
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
=2.7Vto5.5V)
CC
=2.5Vto5.5V)
CC
3-Wire
Serial EEPROM
Description
The AT93C46C provides 1024 bits of serial electrically-erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46C is available in space saving 8lead PDIP and 8-lead JEDEC SOIC packages.
TheAT93C46CisenabledthroughtheChipSelectpin(CS),andaccessedviaa3wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely selftimed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” following the initiation of a WRITE cycle, the DO pin outputs the
READY/BUSY status of the part.
The AT93C46C is available in 2.7V to 5.5V and 2.5V to 5.5V versions.
Pin Configurations
Pin NameFunction
CSChip Select
SKSerial Data Clock
DISerial Data Input
DOSerial Data Output
GNDGround
CS
SK
DI
DO
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
DC
NC
GND
1K (64 x 16)
AT93C46C
VCCPower Supply
NCNo Connect
DCDon’t Connect
CS
SK
DO
DI
8-lead SOIC
1
2
3
4
VCC
8
DC
7
NC
6
GND
5
Rev. 1122D–SEEPR–08/02
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°Cto+125°C
Storage Temperature ..................................... -65°Cto+150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current ........................................................ 5.0 mA
Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT93C46C
1122D–SEEPR–08/02
AT93C46C
Pin Capacitance
(1)
Applicable over recommended operating range from TA=25°C, f = 1.0 MHz, VCC= +5.0V (unless otherwise noted).
SymbolTest ConditionsMaxUnitsConditions
C
OUT
C
IN
Output Capacitance (DO)5pFV
OUT
=0V
Input Capacitance (CS, SK, DI)5pFVIN=0V
Note:1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +2.5V to +5.5V,
T
=0°Cto+70°C, VCC= +2.5V to +5.5V (unless otherwise noted).
AC
SymbolParameterTest ConditionMinTypMaxUnits
V
CC1
V
CC2
V
CC3
I
CC
I
SB1
I
SB2
I
SB3
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
V
OL1
V
OH1
V
OL2
V
OH2
Note:1. V
Supply Voltage2.55.5V
Supply Voltage2.75.5V
Supply Voltage4.55.5V
READ at 1.0 MHz0.52.0mA
Supply CurrentVCC=5.0V
WRITE at 1.0 MHz0.52.0mA
Standby CurrentVCC= 2.5VCS = 0V14.020.0µA
Standby CurrentVCC= 2.7VCS = 0V14.020.0µA
Standby CurrentVCC= 5.0VCS = 0V35.050.0µA
Input LeakageVIN=0VtoV
Output LeakageVIN=0VtoV
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
min and VIHmax are reference only and are not tested.
IL
2.5V ≤ V
4.5V ≤ V
2.5V ≤ V
CC
CC
CC
CC
CC
≤ 5.5V
≤ 5.5V
≤ 2.7V
I
=2.1mA0.4V
OL
I
=-0.4mA2.4V
OH
=0.15mA0.2V
I
OL
I
=-100µAV
OH
-0.6
x0.7
V
CC
-0.2V
CC
0.11.0µA
0.11.0µA
V
x0.3
CC
+1
V
CC
V
1122D–SEEPR–08/02
3
AC Characteristics
Applicable over recommended operating range from TA=-40°Cto+85°C, VCC=+2.5Vto+5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
SymbolParameterTest ConditionMinTypMaxUnits
f
SK
t
SKH
t
SKL
t
CS
t
CSS
SK Clock Frequency4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
SK High Time4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
SK Low Time4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
Minimum CS Low Time4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
CS Setup Time
Relative to SK
t
DIS
DI Setup Time
Relative to SK
t
CSH
t
DIH
CS Hold TimeRelative to SK0ns
DI Hold Time
Relative to SK
t
PD1
Output Delay to ‘1’
AC Test
t
PD0
Output Delay to ‘0’
AC Test
t
SV
CS to Status Valid
AC Test
t
DF
t
WP
Endurance
CS to DO in High Impedance
AC Test
CS = V
IL
Write Cycle Time10ms
5.0V, 25°C, Page Mode
(1)
Note:1. This parameter is characterized and is not 100% tested.
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
CC
CC
≤ 5.5V
≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V3ms
CC
0
0
0
250
250
500
250
250
500
250
250
500
50
50
100
100
100
200
100
100
200
1M
2
1
0.5
250
250
500
250
250
500
250
250
500
100
100
200
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
Cycle
4
AT93C46C
1122D–SEEPR–08/02
Instruction Set for the AT93C46C
Address
AT93C46C
InstructionSBOp Code
READ110A
EWEN10011XXXXWrite enable must precede all programming modes.
ERASE111A
WRITE101A
ERAL10010XXXXErases all memory locations. Valid only at V
WRAL10001XXXXWrites all memory locations. Valid only at V
EWDS10000XXXXDisables all programming instructions.
Functional
Description
5-A0
5-A0
5-A0
The AT93C46C is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
Commentsx16
Reads data stored in memory, at specified address.
Erase memory location An-A0.
Writes memory location An-A0.
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V
power is removed from the part.
= 4.5V to 5.5V.
CC
= 4.5V to 5.5V.
CC
CC
1122D–SEEPR–08/02
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into the specified memory location. The self-timed programming cycle t
WP
starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (t
). A logic “0” at DO indicates that programming is still in progress. A logic
CS
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy Status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, t
WP
.
).
5
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