Features
General
• High-performance, Low-power secureAVR
– 135 Powerful Instructions (Most Executed in a Single Clock Cycle)
• Low Power Idle and Power-down Modes
• Bond Pad Locations Conforming to ISO 7816-2
• ESD Protection to ± 6000V
• Operating Ranges: 1.62 to 5.5V
• Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible
• Available in Wafers, Modules, and Industry-standard Packages
™
RISC Architecture
Memory
• 96K Bytes of ROM Program Memory plus 32KBytes of ROM with specific access
• 18K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area
– 1 to 64-byte Program / Erase
– 2 ms Program / 2 ms Erase
– Typically More than 500,000 Write/Erase Cycles at a Temperature of 25
– 10 Years Data Retention
• 4K Bytes of RAM
o
C
Peripherals
• One ISO 7816 Controller
– Up to 625 kbps at 5 MHz
– Compliant with T=0 and T=1 Protocols
• One I/O Port
• Programmable Internal Oscillator (up to 20 MHz for Internal CPU Clock)
• Two 16-bit Timers
• Random Number Generator (RNG)
• 2-level, 7-vector Interrupt Controller
• Hardware DES and Triple DES DPA Resistant
• Checksum Accelerator
• CRC 16 & 32 Engine (Compliant with ISO/IEC 3309)
Secure
Microcontroller
for Smart Cards
AT90SC
9618RT
Summary
Security
• Dedicated Hardware for Protection Against SPA/DPA Attacks
• Advanced Protection Against Physical Attack, Including Active Shield
• Environmental Protection Systems
• V oltage Monitor
• Frequency Monitor
• Temperature Monitor
• Light Protection
• Secure Memory Management/Access Protection (Supervisor Mode)
Certification
• EAL4+
• VISA
• CAST
6555AS–SPD–15May0 7
Note: This is a summary document. A complete document will be
available under NDA. For more information, please contact your
local Atmel sales office.
AT90SC9618RT
Development Tools
• Voyager Emulation Platform (ATV4) to Support Software Development
• IAR Embedded Workbench
• Software Libraries and Application Notes
®
V3.20 Debugger or Atmel’s AVR Studio® Version 4.07 or Above
Description
The AT90SC9618RT is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory and EEPROM
data memory, based on the secureAVR RISC architecture. By executing powerful instructions in a single clock cycle, the
AT90SC9618RT achi eves throughpu ts close to 1 M IPS pe r MHz . Its Harv ard ar chitec ture in cludes 32 ge neral p urpos e
working regi sters d irectl y connec ted to th e ALU, al lowin g two ind epende nt regis ters t o be acces sed in on e sing le ins truction executed in one clock cycle.
The AT90SC9618RT uses the secureAVR that allows the linear addressing of up to 8M bytes of code and up to 16M bytes
of data as well as a number of new functional and security features.
The AT90SC9618RT includes 18K bytes of Atmel’s high density, non volatile memory.
Additional security features include power and frequency protection logic, logical scrambling on program data and
addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode.
Figure 1 shows the AT90SC9618RT secureAVR RISC Architecture.
Figure 1. AT90SC9618RT secureAVR RISC Architecture
Data B us
8-bit
PC
OTP
EEPROM
User Memory
Program
Memory
16
Instruction
Reg ist er
16
Instruction
Decoder
16
Control
Lines
Access
Control
General
Purpose
Reg ist ers
X
Y
Z
88
ALU
8
St at us
Reg ist er
Access
Control
RNG
RAM
Data Memory
Interrupt
Unit
IS O 7816
Controller
IS O 7816
I/O Port 0
Timer
DE S
DPA C ounter
measures
CRC and
Checksum
Accelerator
Secu re
Control
Reset
Circuit
CLK
GND
VCC
IN/OUT0
RST
2
6555AS–SPD–15May07
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