Features
®
• AVR
• Data and Nonvolatile Program Memories
• Peripheral Features
• Special Microcontroller Features
• Power Consumption at 4 MHz, 3V, 20°C
• I/O and Packages
• Operating Voltages
• Speed Grades:
– High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
– 8K Bytes of In-System Programmable Flash
SPI Serial Interface for In-System Programming
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
– 8-channel, 10-bit ADC
– Programmable UART
– Master/Slave SPI Serial Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset Circuit
– Real-time Clock (RTC) with Separate Oscillator and Counter Mode
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power Save and Power-down
– Active: 6.4 mA
– Idle Mode: 1.9 mA
– Power-down Mode: <1 µA
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF
–V
: 4.0 - 6.0V AT90S8535
CC
: 2.7 - 6.0V AT90LS8535
–V
CC
– 0 - 8 MHz for the AT90S8535
– 0 - 4 MHz for the AT90LS8535
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8535
AT90LS8535
Rev. 1041H–11/01
1
Pin Configurations
2
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Description The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8535
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Block Diagram Figure 1. The AT90S8535 Block Diagram
PA0 - PA7
VCC
PC0 - PC7
GND
AVCC
AGND
AREF
DATA REGISTER
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PORTA DRIVERS
DATA DIR.
PORTA
ANALOG MUX ADC
REG. PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
8-BIT DATA BUS
PORTC DRIVERS
DATA REGISTER
PORTC
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
DATA DIR.
REG. PORTC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
XTAL1
XTAL2
RESET
1041H–11/01
PROGRAMMING
LOGIC
-
ANALOG
DATA REGISTER
ARATOR
COMP
+
PORTB
PORTB DRIVERS
STATUS
REGISTER
SPI
PB0 - PB7
DATA DIR.
REG. PORTB
UART
DATA REGISTER
PORTD
PORTD DRIVERS
PD0 - PD7
DATA DIR.
REG. PORTD
3
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90S8535 provides the following features: 8K bytes of In-System Programmable
Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 generalpurpose working registers, Real-time Clock (RTC), three flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, 8-channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial
port and three software-selectable power-saving modes. The Idle Mode stops the CPU
while allowing the SRAM, timer/counters, SPI port and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power
Save Mode, the timer oscillator continues to run, allowing the user to maintain a timer
base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic
chip, the Atmel AT90S8535 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The AT90S8535 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators and evaluation kits.
Pin Descriptions
VCC Digital supply voltage.
GND Digital ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated.
Port A also serves as the analog inputs to the A/D Converter.
The Port A pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. Port B also serves the functions of various
special features of the AT90S8535 as listed on page 78.
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
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AT90S/LS8535
1041H–11/01
AT90S/LS8535
current if the pull-up resistors are activated. Two Port C pins can alternatively be used
as oscillator for Timer/Counter2.
The Port C pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S8535 as listed
on page 86.
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
RESET
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used,
AREF AREF is the analog reference input for the A/D Converter. For ADC operations, a volt-
AGND Analog ground. If the board has a separate analog ground plane, this pin should be con-
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
this pin must be connected to VCC. If the ADC is used, this pin must be connected to
VCC via a low-pass filter. See page 68 for details on operation of the ADC.
age in the range 2V to AV
nected to this ground plane. Otherwise, connect to GND.
must be applied to this pin.
CC
1041H–11/01
5
Clock Options
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used.
Figure 2. Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
External Clock To drive the device from an external clock source, XTAL2 should be left unconnected
while XTAL1 is driven as shown in Figure 3.
Figure 3. External Clock Drive Configuration
XTAL2
XTAL1
GND
Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly
between the pins. No external capacitors are needed. The oscillator is optimized for use
with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not
recommended.
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AT90S/LS8535
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle,
one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from
the register file, the operation is executed and the result is stored back in the register file
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing, enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-register, Y-register, and Z-register.
Figure 4. The AT90S8535 AVR RISC Architecture
Data Bus 8-bit
4K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
512 x 8
Data
SRAM
Interrupt
Unit
SPI
Unit
Serial
UART
8-bit
Timer/Counter
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
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512 x 8
EEPROM
32
I/O Lines
Analog to Digital
Converter
Analog
Comparator
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S8535 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the register file as well. This is enabled by the fact that the register file is
7
assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can
be accessed directly or as the Data Space locations following those of the register file,
$20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The program memory is executed with a two-stage pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM and
consequently, the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 10-bit stack pointer (SP) is read/write-accessible in the
I/O space.
The 512 bytes data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 5. Memory Maps
Program Flash
(4K x 16)
$000
$FFF
Data MemoryProgram Memory
32 Gen. Purpose
Working Registers
64 I/O Registers
Internal SRAM
(512 x 8)
$0000
$001F
$0020
$005F
$0060
$025F
Data Memory
$000
EEPROM
(512 x 8)
$1FF
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program
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AT90S/LS8535
memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority.
General-purpose Register File
Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 6. AVR CPU General-purpose Working Registers
70Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND,
and OR and all other operations between two registers or on a single register apply to
the entire register file.
1041H–11/01
As shown in Figure 6, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
9
X-register, Y-register and Zregister
The registers R26..R31 have some added functions to their general-purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers, X, Y, and Z, are defined in Figure 7.
Figure 7. X-, Y-, and Z-register
15 0
X-register 7 0
R27 ($1B) R26 ($1A)
15 0
Y-register
Z-register
7 0 7 0
R29 ($1D) R28 ($1C)
15 0
7 0 7 0
R31 ($1F) R30 ($1E)
7 0
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions).
ALU – Arithmetic Logic Unit
In-System Programmable Flash Program Memory
The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories: arithmetic, logical and bit functions.
The AT90S8535 contains 8K bytes On-chip, In-System Programmable Flash memory
for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 4K x 16. The Flash memory has an endurance of at least 1000 write/erase
cycles. The AT90S8535 Program Counter (PC) is 12 bits wide, thus addressing the
4096 program memory addresses.
See page 99 for a detailed description on Flash data downloading.
See page 12 for the different program memory addressing modes.
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AT90S/LS8535
SRAM Data Memory Figure 8 shows how the AT90S8535 SRAM memory is organized.
Figure 8. SRAM Organization
Register File
R0
R1
R2
...
Data Address Space
$0000
$0001
$0002
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$025E
$025F
The lower 608 data memory locations address the Register file, the I/O memory and the
internal data SRAM. The first 96 locations address the Register file + I/O memory, and
the next 512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the
register file, registers R26 to R31 feature the indirect addressing pointer registers.
1041H–11/01
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- or Z-registers.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.
The 32 general-purpose working registers, 64 I/O registers and the 512 bytes of internal
data SRAM in the AT90S8535 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
11
Program and Data Addressing Modes
The AT90S8535 AVR RISC microcontroller supports powerful and efficient addressing
modes for access to the program memory (Flash) and data memory (SRAM, register file
and I/O memory). This section describes the different addressing modes supported by
the AVR architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single Register Rd
Register Direct, Two Registers Rd And Rr
Figure 9. Direct Single Register Addressing
The operand is contained in register d (Rd).
Figure 10. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
I/O Direct Figure 11. I/O Direct Addressing
Operand address is contained in six bits of the instruction word. n is the destination or
source register address.
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Data Direct Figure 12. Direct Data Addressing
31
OP Rr/Rd
15 0
20 19
16 LSBs
A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify
the destination or source register.
AT90S/LS8535
Data Space
16
$0000
$025F
Data Indirect with
Figure 13. Data Indirect with Displacement
Displacement
15
Y OR Z - REGISTER
15
OP an
Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.
Data Indirect Figure 14. Data Indirect Addressing
X, Y OR Z - REGISTER
Data Space
0
05610
Data Space
015
$0000
025F
$0000
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$025F
Operand address is the contents of the X-, Y-, or the Z-register.
13
Data Indirect with Predecrement
Figure 15. Data Indirect Addressing with Pre-decrement
Data Space
015
X, Y OR Z - REGISTER
-1
$0000
$025F
The X-, Y-, or the Z-register is decremented before the operation. Operand address is
the decremented contents of the X-, Y-, or the Z-register.
Data Indirect with Postincrement
Constant Addressing Using the LPM Instruction
Figure 16. Data Indirect Addressing with Post-increment
Data Space
015
X, Y OR Z - REGISTER
1
$0000
$025F
The X-, Y-, or the Z-register is incremented after the operation. Operand address is the
content of the X-, Y-, or the Z-register prior to incrementing.
Figure 17. Code Memory Constant Addressing
14
$FFF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 4K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =
1).
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Indirect Program Addressing, IJMP and ICALL
Relative Program Addressing, RJMP and RCALL
Figure 18. Indirect Program Memory Addressing
$FFF
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Figure 19. Relative Program Memory Addressing
+1
$FFF
Program execution continues at address PC + k + 1. The relative address k is from 2048 to 2047.
EEPROM Data Memory The AT90S8535 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 51 specifying the EEPROM address registers, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 99 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power-unit.
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15
Figure 20. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 21 shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed and the result is stored back
to the destination register.
Figure 21. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 22.
Figure 22. On-chip Data SRAM Access Cycles
T1 T2 T3 T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
Write
Read
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AT90S/LS8535
I/O Memory The I/O space definition of the AT90S8535 is shown in Table 1.
Table 1. AT90S8535 I/O Space
I/O Address
(SRAM Address) Name Function
$3F ($5F) SREG Status REGister
$3E ($5E) SPH Stack Pointer High
$3D ($5D) SPL Stack Pointer Low
$3B ($5B) GIMSK General Interrupt MaSK register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK register
$38 ($58) TIFR Timer/Counter Interrupt Flag register
$35 ($55) MCUCR MCU general Control Register
$34 ($45) MCUSR MCU general Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
$2D ($4D) TCNT1H Timer/Counter1 High Byte
$2C ($4C) TCNT1L Timer/Counter1 Low Byte
$2B ($4B) OCR1AH Timer/Counter1 Output Compare Register A High Byte
$2A ($4A) OCR1AL Timer/Counter1 Output Compare Register A Low Byte
$29 ($49) OCR1BH Timer/Counter1 Output Compare Register B High Byte
$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low Byte
$27 ($47) ICR1H T/C 1 Input Capture Register High Byte
$26 ($46) ICR1L T/C 1 Input Capture Register Low Byte
$25 ($45) TCCR2 Timer/Counter2 Control Register
$24 ($44) TCNT2 Timer/Counter2 (8-bit)
$23 ($43) OCR2 Timer/Counter2 Output Compare Register
$22 ($42) ASSR Asynchronous Mode Status Register
$21 ($41) WDTCR Watchdog Timer Control Register
$1F ($3E) EEARH EEPROM Address Register High Byte
$1E ($3E) EEARL EEPROM Address Register Low Byte
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
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$1B ($3B) PORTA Data Register, Port A
$1A ($3A) DDRA Data Direction Register, Port A
$19 ($39) PINA Input Pins, Port A
$18 ($38) PORTB Data Register, Port B
17
Table 1. AT90S8535 I/O Space (Continued)
I/O Address
(SRAM Address) Name Function
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
$15 ($35) PORTC Data Register, Port C
$14 ($34) DDRC Data Direction Register, Port C
$13 ($33) PINC Input Pins, Port C
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) USR UART Status Register
$0A ($2A) UCR UART Control Register
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
$06 ($26) ADCSR ADC Control and Status Register
$05 ($25) ADCH ADC Data Register High
$04 ($24) ADCL ADC Data Register Low
Note: Reserved and unused locations are not shown in the table.
All AT90S8535 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer
to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as
SRAM, $20 must be added to these addresses. All I/O register addresses throughout
this document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
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Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊄⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logic operation. See the
Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
1041H–11/01
19
Stack Pointer – SP The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). As the AT90S8535 data memory has $25F locations, 10 bits are used.
Bit 151413121110 9 8
$3E ($5E) ––––––SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/WriteRRRRRRR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the stack with the PUSH instruction and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
Reset and Interrupt Handling
The AT90S8535 provides 16 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space.
All interrupts are assigned individual enable bits that must be set (one) together with the
I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 (the External
Interrupt Request 0), etc.
Table 2. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
Hardware Pin, Power-on Reset and
1 $000 RESET
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 TIMER2 COMP Timer/Counter2 Compare Match
5 $004 TIMER2 OVF Timer/Counter2 Overflow
6 $005 TIMER1 CAPT Timer/Counter1 Capture Event
7 $006 TIMER1 COMPA Timer/Counter1 Compare Match A
8 $007 TIMER1 COMPB Timer/Counter1 Compare Match B
Watchdog Reset
20
9 $008 TIMER1 OVF Timer/Counter1 Overflow
10 $009 TIMER0 OVF Timer/Counter0 Overflow
11 $00A SPI, STC SPI Serial Transfer Complete
12 $00B UART, RX UART, Rx Complete
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Table 2. Reset and Interrupt Vectors (Continued)
Vector No. Program Address Source Interrupt Definition
13 $00C UART, UDRE UART Data Register Empty
14 $00D UART, TX UART, Tx Complete
15 $00E ADC ADC Conversion Complete
16 $00F EE_RDY EEPROM Ready
17 $010 ANA_COMP Analog Comparator
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM2_COMP ; Timer2 Compare Handler
$004 rjmp TIM2_OVF ; Timer2 Overflow Handler
$005 rjmp TIM1_CAPT ; Timer1 Capture Handler
$006 rjmp TIM1_COMPA ; Timer1 CompareA Handler
$007 rjmp TIM1_COMPB ; Timer1 CompareB Handler
$008 rjmp TIM1_OVF ; Timer1 Overflow Handler
$009 rjmp TIM0_OVF ; Timer0 Overflow Handler
$00a rjmp SPI_STC; ; SPI Transfer Complete Handler
$00b rjmp UART_RXC ; UART RX Complete Handler
$00c rjmp UART_DRE ; UDR Empty Handler
$00d rjmp UART_TXC ; UART TX Complete Handler
$00e rjmp ADC ; ADC Conversion Complete Interrupt
Handler
$00f rjmp EE_RDY ; EEPROM Ready Handler
$010 rjmp ANA_COMP ; Analog Comparator Handler
$011 MAIN: ldi r16, high(RAMEND); Main program start
$012 out SPH,r16
$013 ldi r16, low(RAMEND) ;
$014 out SPL,r16
$015 <instr> xxx
…… ……
Reset Sources The AT90S8535 has three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
During reset, all I/O registers are set to their initial values and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the interrupt vectors are not used and regular program code can be
1041H–11/01
21
placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3
defines the timing and electrical parameters of the reset circuitry.
Figure 23. Reset Logic
Table 3. Reset Characteristics (V
Symbol Parameter Min Typ Max Units
(1)
V
POT
V
RST
t
TOUT
t
TOUT
Note: 1. The Power-on Reset will not work unless the supply voltage has been below V
Power-on Reset Threshold (rising) 1.0 1.4 1.8 V
Power-on Reset Threshold (falling) 0.4 0.6 0.8 V
RESET Pin Threshold Voltage 0.6 V
Reset Delay Time-out Period
FSTRT Unprogrammed
Reset Delay Time-out Period
FSTRT Programmed
(falling).
= 5.0V)
CC
CC
11.0 16.0 21.0 ms
1.0 1.1 1.2 ms
V
POT
Table 4. Number of Watchdog Oscillator Cycles
FSTRT Time-out at VCC = 5V Number of WDT Cycles
Programmed 1.1 ms 1K
Unprogrammed 16.0 ms 16K
Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer clocked from the Watchdog Timer oscillator prevents the MCU from starting until after a certain period after V
on Threshold voltage (V
), regardless of the VCC rise time (see Figure 24).
POT
has reached the Power-
CC
The user can select the start-up time according to typical oscillator start-up time. The
number of WDT oscillator cycles is shown in Table 4. The frequency of the Watchdog
oscillator is voltage-dependent as shown in “Typical Characteristics” on page 107.
22
If the built-in start-up delay is sufficient, RESET
an external pull-up resistor. By holding the pin low for a period after V
applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing
example of this.
AT90S/LS8535
can be connected to VCC directly or via
has been
CC
1041H–11/01
Figure 24. MCU Start-up, RESET Tied to VCC.
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
V
RST
t
TOUT
AT90S/LS8535
Figure 25. MCU Start-up, RESET
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
Controlled Externally
V
RST
t
TOUT
External Reset An external reset is generated by a low level on the RESET
than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage (V
period t
) on its positive edge, the delay timer starts the MCU after the Time-out
RST
has expired.
TOUT
Figure 26. External Reset during Operation
pin. Reset pulses longer
1041H–11/01
23
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
. Refer to page 49 for details on operation of the Watchdog.
t
TOUT
Figure 27. Watchdog Reset during Operation
MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit 76543210
$34 ($54) ––––––EXTRF PORF MCUSR
Read/WriteRRRRRRR/WR/W
Initial Value000000See Bit Description
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
• Bit 1 – EXTRF: External Reset Flag
After a power-on reset, this bit is undefined (X). It can only be set by an External Reset.
A Watchdog Reset will leave this bit unchanged. The bit is cleared by writing a logical
zero to the bit.
• Bit 0 – PORF: Power-on Reset Flag
This bit is only set by a Power-on Reset. A Watchdog Reset or an External Reset will
leave this bit unchanged. The bit is cleared by writing a logical zero to the bit.
To summarize, Table 5 shows the value of these two bits after the three modes of reset.
Table 5. PORF and EXTRF Values after Reset
Reset Source EXTRF PORF
Power-on Reset Undefined 1
External Reset 1 Unchanged
24
Watchdog Reset Unchanged Unchanged
To make use of these bits to identify a reset condition, the user software should clear
both the PORF and EXTRF bits as early as possible in the program. Checking the
PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before
an External or Watchdog Reset occurs, the source of reset can be found by using Table
6.
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Table 6. Reset Source Identification
EXTRF PORF Reset Source
0 0 Watchdog Reset
0 1 Power-on Reset
1 0 External Reset
1 1 Power-on Reset
Interrupt Handling The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Inter-
rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding
interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until
the interrupt is enabled or the flag is cleared by software.
General Interrupt Mask Register – GIMSK
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one) and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
Bit 7 6 5 4 3 2 1 0
$3B ($5B) INT1 INT0 –– ––––GIMSK
Read/Write R/W R/W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts.”
1041H–11/01
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
25
General Interrupt Flag Register – GIFR
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5.0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
Bit 7 6 5 4 3 2 1 0
$3A ($5A) INTF1 INTF0 –– ––––GIFR
Read/Write R/W R/W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – INTF1: External Interrupt Flag1
When an edge or logical change on the INT1 pin triggers an interrupt request, INTF1
becomes set (one). This flag is always cleared (0) when the pin is configured for lowlevel interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $002. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bit 6 – INTF0: External Interrupt Flag0
When an edge or logical change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). This flag is always cleared (0) when the pin is configured for lowlevel interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
Timer/Counter Interrupt Mask Register – TIMSK
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $001. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
Bit 7 6 5 4 3 2 1 0
$39 ($59) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
26
AT90S/LS8535
1041H–11/01
AT90S/LS8535
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
(at vector $005) is executed if a capture-triggering event occurs on pin 20, PD6 (ICP)
(i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at
vector $006) is executed if a CompareA match in Timer/Counter1 occurs (i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at
vector $007) is executed if a CompareB match in Timer/Counter1 occurs (i.e., when the
OCF1B bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$008) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 1 – Res: Reserved Bit
Timer/Counter Interrupt Flag Register – TIFR
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$009) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit 7 6 5 4 3 2 1 0
$38 ($58) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIF R
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2
and the data in OCR2 (Output Compare Register2). OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2
Compare Match Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2
Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2
(Timer/Counter2 Overflow Interrupt Enable) and TOV2 are set (one), the
Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
1041H–11/01
27
• Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match Interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare Match B Interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
(Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the
Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the
Timer/Counter0 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
External Interrupts The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The external interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the external interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
28
The external interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is
decremented by 2. The vector is normally a relative jump to the interrupt routine and this
jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in
SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit 76543210
$35 ($55) – SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 6 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
• Bits 5, 4 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes as shown in Table 7.
Table 7. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
01Reserved
1 0 Power-down
1041H–11/01
11Power Save
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bits 1 and 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK is set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 8.
29
Table 8. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
01Reserved
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
The value on the INT pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bits 1 and 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask is set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 9.
Table 9. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
01Reserved
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
The value on the INT pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
Sleep Modes To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM0 and SM1 bits in the MCUCR register
select which sleep mode (Idle, Power-down or Power Save) will be activated by the
SLEEP instruction. See Table 7.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up,
executes the interrupt routine and resumes execution from the instruction following
SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset
occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.
Idle Mode When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the
Idle Mode, stopping the CPU but allowing SPI, UARTs, Analog Comparator, ADC,
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables
the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog
30
AT90S/LS8535
1041H–11/01
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