Rainbow Electronics AT90LS4433 User Manual

Features

• High-performance and Low-power AVR

– 118 Powerful Instructions – Most Single Cycle Execution – 32x8GeneralPurposeWorkingRegisters – Up to 8 MIPS Throughput at 8 MHz

• Data and Non-volatile Program Memory

– 4K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles – 128 Bytes of SRAM – 256 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler – Expanded 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9-, or 10-bit PWM – On-chip Analog Comparator – Programmable Watchdog Timer with Separate On-chip Oscillator – Programmable UART – 6-channel, 10-bit ADC – Master/Slave SPI Serial Interface

• Special Microcontroller Features

– Brown-out Reset Circuit – Enhanced Power-on Reset Circuit – Low-power Idle and Power-down Modes

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 3.4 mA – Idle Mode: 1.4 mA – Power-down Mode: <1 µA

• I/O and Packages

– 20 Programmable I/O Lines – 28-lead PDIP and 32-lead TQFP

• Operating Voltage

– 2.7V - 6.0V for the AT90LS4433 – 4.0V - 6.0V for the AT90S4433

• Speed Grades

– 0 - 4 MHz for the AT90LS4433 – 0 - 8 MHz for the AT90S4433

8-bit RISC Architecture

8-bit Microcontroller with 4K Bytes of In-System Programmable Flash

AT90S4433 AT90LS4433

Not Recommend for New Designs. Use ATmega8.

Rev. 1042G–AVR–09/02

Pin Configurations TQFP Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

RESET

PC5 (ADC5)

PC4 (ADC4)

PC3 (ADC3)

PC2 (ADC2)

(INT1) PD3

(T0) PD4

VCC

GND

NC XTAL1 XTAL2

(RXD) PD0

(TXD) PD1 (INT0) PD2 (INT1) PD3

(T0) PD4

(T1) PD5 (AIN0) PD6 (AIN1) PD7

(ICP) PB0

1 2 3 4 5 6 7 8

RESET

VCC

GND XTAL1 XTAL2

32313029282726

10111213141516

(T1) PD5

(AIN0) PD6

(AIN1) PD7

1 2 3 4 5 6 7 8 9 10 11 12 13 14

PDIP

(SS) PB2

(ICP) PB0

(OC1) PB1

28 27 26 25 24 23 22 21 20 19 18 17 16 15

(MOSI) PB3

PC1 (ADC1)

PC0 (ADC0)

AGND

AREF

AVCC

PB5 (SCK)

(MISO) PB4

PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) AGND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI) PB2 (SS) PB1 (OC1)

AT90S/LS4433

1042G–AVR–09/02

AT90S/LS4433

Description The AT90S4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S4433 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90S4433 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM, 128 bytes of SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC, programmable Watchdog Timer with internal Oscillator, an SPI serial port and two software-selectable Power-saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset.

The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip Flash Program memory can be re-programmed In-System through an SPI serial interface or by a conventional non-volatile memory programmer. By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S4433 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.

The AT90S4433 AVR is supported with a full suite of program and system development tools including: C Compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators and evaluation kits.

Table 1. Comparison Table

Device Flash EEPROM SRAM Voltage Range Frequency

AT90S4433 4K 256B 128B 4.0V - 6.0V 0 - 8 MHz

AT90LS4433 4K 256B 128B 2.7V - 6.0V 0 - 4 MHz

1042G–AVR–09/02

Block Diagram Figure 1. The AT90S4433 Block Diagram

PC0 - PC5

VCC

PORTC DRIVERS

GND

AVCC

AGND AREF

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA REGISTER

PORTC

ANALOG MUX ADC

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

8-BIT DATA BUS

DATA DIR.

REG. PORTC

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

EEPROM

UNIT

OSCILLATOR

TIMING AND

CONTROL

XTAL1

XTAL2

RESET

PROGRAMMING

LOGIC

DATA REGISTER

PORTB

PORTB DRIVERS

AT90S/LS4433

PB0 - PB5

SPI

DATA DIR.

REG. PORTB

UART

DATA REGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

COMPARATOR

ANALOG

1042G–AVR–09/02

AT90S/LS4433

Pin Descriptions

VCC Supply voltage.

GND Ground.

Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features of the AT90S4433 as listed on page 73.

The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C (PC5..PC0) Port C is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the analog inputs to the A/D Converter.

The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S4433 as listed on page 81.

The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

RESET

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit

XTAL2 Output from the inverting oscillator amplifier

AVCC AVCC is the supply voltage for Port A and the A/D Converter. If the ADC is not used,

AREF AREF is the analog reference input for the A/D Converter. For ADC operations, a volt-

AGND If the board has a separate analog ground plane, this pin should be connected to this

Reset input. An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

this pin must be connected to V V

via a low-pass filter. See page 64 for details on operation of the ADC.

age in the range 2.0V to AVCC must be applied to this pin.

ground plane. Otherwise, connect to GND.

. If the ADC is used, this pin should be connected to

1042G–AVR–09/02

Clock Options

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which

can be configured for use as an On-chip Oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used.

External Clock If the Oscillator is to be used as a clock for an external device, the clock signal from

XTAL2 may be routed to one HC buffer while reducing the load capacitor by 5 pF, as shown in Figure 3. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 4.

Figure 2. Oscillator Connections

Figure 3. Using MCU Oscillator as a Clock for an External Device

XTAL1

XTAL2

REDUCE BY 5

MAX 1 HC BUFFER

Figure 4. External Clock Drive Configuration

AT90S/LS4433

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AT90S/LS4433

Architectural Overview

The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S4433 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File as well. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.

Figure 5. The AT90S4433 AVR RISC Architecture

Data Bus 8-bit

2K X 16 Program Memory

Program

Counter

Status

and Control

Interrupt

Unit

Instruction

Decoder

Control Lines

Direct Addressing

Indirect Addressing

32 x 8 General Purpose

Registrers

ALU

128 x 8

Data

SRAM

256 x 8

EEPROM

I/O Lines

SPI

Unit

Serial

UART

8-bit

Timer/Counter

16-bit

Timer/Counter

with PWM

Watchdog

Timer

Analog to Digital

Converter

Analog

Comparator

1042G–AVR–09/02

The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.

The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle.

The Program memory is In-System Programmable Flash memory.

With the relative jump and call instructions, the whole 2K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM and, consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit Stack Pointer (SP) is read/write accessible in the I/O space.

The 128 bytes of data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

AT90S/LS4433

1042G–AVR–09/02

Figure 6. AT90S4433 Memory Maps

AT90S/LS4433

Data MemoryProgram Memory

Program Flash

(2K x 16)

$000

32 Gen. Purpose

Working Registers

64 I/O Registers

Internal SRAM

(128 x 8)

$0000

$001F $0020

$005F $0060

$00DF

$7FF

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

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General Purpose Register File

Figure 7 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File (R16..R31). The general SBC, SUB, CP, AND, and OR, and all other operations between two registers or on a single register apply to the entire Register File.

X-register, Y-register and Zregister

As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- ,and Z-registers can be set to index any register in the file.

The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as:

Figure 8. X-, Y-, and Z-registers

15 0

X - register 7070

R27 ($1B) R26 ($1A)

15 0

Y - register

Z-register

7070

R29 ($1D) R28 ($1 C)

15 0

7070

R31 ($1F) R30 ($1E)

AT90S/LS4433

1042G–AVR–09/02

AT90S/LS4433

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

ALU – Arithmetic Logic Unit

In-System Programmable Flash Program Memory

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main categories: arithmetic, logical, and bit functions.

The AT90S4433 contains 4K bytes of On-chip, In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 2K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The AT90S4433 Program Counter (PC) is 11 bits wide, thus addressing the 2,048 program memory addresses. See page 93 for a detailed description of Flash data downloading. See page 12 for the different program memory addressing modes.

Figure 9. SRAM Organization

R0 $0000

R1 $0001

R2 $0002

º º

R29 $001D

R30 $001E

R31 $001F

I/O Registers

$00 $0020

$01 $0021

$02 $0022

……

$3D $005D

$3E $005E

$3F $005F

SRAM Data Memory Figure 9 shows how the AT90S4433 SRAM memory is organized.

The lower 224 data memory locations address the Register File, the I/O memory and the internal data SRAM. The first 96 locations address the Register File and I/O memory, and the next 128 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

1042G–AVR–09/02

Internal SRAM

$0060

$0061

$00DE

$00DF

The direct addressing reaches the entire data space. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.

The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data SRAM in the AT90S4433 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

Register Direct, Single Register Rd

Register Direct, Two Registers Rd and Rr

The AT90S4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash Program memory, SRAM, Register File, and I/O data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

Figure 10. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 11. Direct Register Addressing, Two Registers

Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd).

AT90S/LS4433

1042G–AVR–09/02

I/O Direct Figure 12. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or source register address.

Data Direct Figure 13. Direct Data Addressing

OP Rr/Rd

15 0

20 19

16 LSBs

AT90S/LS4433

Data Space

$0000

Data Indirect with Displacement

$00DF

A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.

Figure 14. Data Indirect with Displacement

Y OR Z - REGISTER

OP an

Data Space

05610

$0000

$00DF

Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.

1042G–AVR–09/02

Data Indirect Figure 15. Data Indirect Addressing

X, Y, OR Z - REGISTER

Operand address is the contents of the X-, Y-, or the Z-register.

Data Space

015

$0000

$00DF

Data Indirect with Predecrement

Data Indirect with Postincrement

Figure 16. Data Indirect Addressing with Pre-decrement

Data Space

015

X, Y, OR Z - REGISTER

-1

$0000

$00DF

The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register.

Figure 17. Data Indirect Addressing with Post-increment

Data Space

015

X, Y, OR Z - REGISTER

$0000

$00DF

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing.

AT90S/LS4433

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AT90S/LS4433

Constant Addressing Using the LPM Instruction

Indirect Program Addressing, IJMP and ICALL

Figure 18. Code Memory Constant Addressing

PROGRAM MEMORY

$000

$7FF

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 2K), the LSB selects Low Byte if cleared (LSB = 0) or High Byte if set (LSB = 1).

Figure 19. Indirect Program Memory Addressing

PROGRAM MEMORY

$000

Relative Program Addressing, RJMP and RCALL

$7FF

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

Figure 20. Relative Program Memory Addressing

PROGRAM MEMORY

$000

$7FF

Program execution continues at address PC + k + 1. The relative address k is from

-2048 to 2047.

1042G–AVR–09/02

EEPROM Data Memory The AT90S4433 contains 256 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The access between the EEPROM and the CPU is described on page 53, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register.

For the SPI Data downloading, see page 93 for a detailed description. The EEPROM Data memory is In-System Programmable through the SPI port. Please refer to the “EEPROM Read/Write Access” section on page 45 for a thorough description of EEPROM access.

Memory Access Times and Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

TheAVRCPUisdrivenbytheSystemClockØ, directly generated from the external clock crystal for the chip. No internal clock division is used.

Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register.

Figure 22. Single Cycle ALU Operation

T1 T2 T3 T4

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 23.

AT90S/LS4433

1042G–AVR–09/02

Figure 23. On-chip Data SRAM Access Cycles

T1 T2 T3 T4

System Clock Ø

AT90S/LS4433

Address

Data

Prev. Address

Address

I/O Memory The I/O space definition of the AT90S4433 is shown in Table 2.

Table 2. AT90S4433 I/O Space

I/O Address

(SRAM Address) Name Function

$3F ($5F) SREG Status Register

$3D ($5D) SP Stack Pointer

$3B ($5B) GIMSK General Interrupt MaSK Register

$3A ($5A) GIFR General Interrupt Flag Register

$39 ($59) TIMSK Timer/Counter Interrupt MaSK Register

$38 ($58) TIFR Timer/Counter Interrupt Flag Register

$35 ($55) MCUCR MCU general Control Register

$34 ($54) MCUSR MCU general Status Register

(1)

Write

Read

1042G–AVR–09/02

$33 ($53) TCCR0 Timer/Counter0 Control Register

$32 ($52) TCNT0 Timer/Counter0 (8-bit)

$2F ($4F) TCCR1A Timer/Counter1 Control Register A

$2E ($4E) TCCR1B Timer/Counter1 Control Register B

$2D ($4D) TCNT1H Timer/Counter1 High Byte

$2C ($4C) TCNT1L Timer/Counter1 Low Byte

$2B ($4B) OCR1H Timer/Counter1 Output Compare Register High Byte

$2A ($4A) OCR1L Timer/Counter1 Output Compare Register Low Byte

$27 ($47) ICR1H Timer/Counter1 Input Capture Register High Byte

$26 ($46) ICR1L Timer/Counter 1 Input Capture Register Low Byte

$21 ($41) WDTCR Watchdog Timer Control Register

$1E ($3E) EEAR EEPROM Address Register

$1D ($3D) EEDR EEPROM Data Register

$1C ($3C) EECR EEPROM Control Register

$18 ($38) PORTB Data Register, Port B

Table 2. AT90S4433 I/O Space

I/O Address

(SRAM Address) Name Function

$17 ($37) DDRB Data Direction Register, Port B

$16 ($36) PINB Input Pins, Port B

$15 ($35) PORTC Data Register, Port C

$14 ($34) DDRC Data Direction Register, Port C

$13 ($33) PINC Input Pins, Port C

$12 ($32) PORTD Data Register, Port D

$11 ($31) DDRD Data Direction Register, Port D

$10 ($30) PIND Input Pins, Port D

$0F ($2F) SPDR SPI I/O Data Register

$0E ($2E) SPSR SPI Status Register

$0D ($2D) SPCR SPI Control Register

$0C ($2C) UDR UART I/O Data Register

$0B ($2B) UCSRA UART Control and Status Register A

$0A ($2A) UCSRB UART Control and Status Register B

$09 ($29) UBRR UART Baud Rate Register

(1)

(Continued)

$08 ($28) ACSR Analog Comparator Control and Status Register

$07 ($27) ADMUX ADC Multiplexer Select Register

$06 ($26) ADCSR ADC Control and Status Register

$05 ($25) ADCH ADC Data Register High

$04 ($24) ADCL ADC Data Register Low

$03 ($23) UBRRHI UART Baud Rate Register High

Note: 1. Reserved and unused locations are not shown in the table.

All AT90S4433 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as SRAM, $20 must be added to this address. All I/O Register addresses throughout this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero when accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in the following sections.

AT90S/LS4433

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AT90S/LS4433

Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit 76543210

$3F ($5F) I THSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

InitialValue00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 – T: Bit Copy Storage

The Bit Copy Instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetical operations. See the Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

• Bit 0 – C: Carry Flag

1042G–AVR–09/02

The Carry Flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Stack Pointer – SP The AT90S4433 Stack Pointer is implemented as an 8-bit register in the I/O space loca-

tion $3D ($5D). As the AT90S4433 data memory has $0DF locations, eight bits are used.

76543210

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

InitialValue00000000

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI.

Reset and Interrupt Handling

The AT90S4433 provides 13 different interrupt sources. These interrupts and the separate reset vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits, which must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are automatically defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc.

Table 3. Reset and Interrupt Vectors

Program

Vector No.

1 $000 RESET

2 $001 INT0 External Interrupt Request 0

3 $002 INT1 External Interrupt Request 1

4 $003 TIMER1 CAPT Timer/Counter1 Capture Event

5 $004 TIMER1 COMP Timer/Counter1 Compare Match

6 $005 TIMER1 OVF Timer/Counter1 Overflow

7 $006 TIMER0 OVF Timer/Counter0 Overflow

Address Source Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset

8 $007 SPI, STC Serial Transfer Complete

9 $008 UART, RX UART, Rx Complete

10 $009 UART, UDRE UART Data Register Empty

11 $00A UART, TX UART, Tx Complete

12 $00B ADC ADC Conversion Complete

13 $00C EE_RDY EEPROM Ready

14 $00D ANA_COMP Analog Comparator

AT90S/LS4433

1042G–AVR–09/02

AT90S/LS4433

The most typical program setup for the Reset and Interrupt Vector addresses are:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp EXT_INT1 ; IRQ1 Handler

$003 rjmp TIM1_CAPT ; Timer1 Capture Handler

$004 rjmp TIM1_COMP ; Timer1 compare Handler

$005 rjmp TIM1_OVF ; Timer1 Overflow Handler

$006 rjmp TIM0_OVF ; Timer0 Overflow Handler

$007 rjmp SPI_STC; ; SPI Transfer Complete Handler

$008 rjmp UART_RXC ; UART RX Complete Handler

$009 rjmp UART_DRE ; UDR Empty Handler

$00a rjmp UART_TXC ; UART TX Complete Handler

$00b rjmp ADC ; ADC Conversion Complete Interrupt Handler

$00c rjmp EE_RDY ; EEPROM Ready Handler

$00d rjmp ANA_COMP ; Analog Comparator Handler

;

$00e MAIN: ldi r16,low(RAMEND); Main program start

$00f out SP,r16;

$010 <instr> xxx ;

…… ……

Reset Sources The AT90S4433 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

POT

• External Reset. The MCU is reset when a low level is present on the RESET more than 50 ns.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage (V certain voltage.

During Reset, all I/O Registers are then set to their Initial Values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the Reset Logic. Table 4 and Table 5 define the timing and electrical parameters of the reset circuitry.

) falls below a

pin for

1042G–AVR–09/02

Figure 24. Reset Logic

Power-on Reset

Circuit

DATA BU S

MCU Status

BORF

PORF

WDRF

EXTRF

BODEN

BODLEVEL

RESET

Brown-out

Reset Circuit

Watchdog

Timer

On-chip

RC Oscillator

CKSEL[2:0]

Delay Counters

Counter Reset

Full

Table 4. Reset Characteristics (VCC=5.0V)

Symbol Parameter Min Typ Max Units

Power-on Reset Threshold Voltage, rising

(1)

POT

Power-on Reset Threshold Voltage, falling

1.0 1.4 1.8 V

0.4 0.6 0.8 V

Internal Reset

Note: 1. The Power-on Reset will not work unless the supply voltage has been below V

AT90S/LS4433

RESET Pin

RST

Threshold

0.6 V

Voltage

Brown-out Reset

BOT

Threshold Voltage

(BODLEVEL=1)

3.5

(BODLEVEL=0)

2.2

2.7

(BODLEVEL=1)

4.0

(BODLEVEL=0)

3.0

(BODLEVEL=1)

4.5

(BODLEVEL=0)

POT

(falling).

1042G–AVR–09/02

Table 5. Reset Delay Selections

AT90S/LS4433

CKSEL

[2:0]

000 16 ms + 6 CK 4 ms + 6 CK External Clock, slowly rising power

001 6 CK 6 CK External Clock, BOD enabled

010 256 ms + 16K CK 64 ms + 16K CK Crystal Oscillator

011 16 ms + 16K CK 4 ms + 16K CK Crystal Oscillator, fast rising power

100 16K CK 16K CK Crystal Oscillator, BOD enabled

101 256 ms + 1K CK 64 ms + 1K CK Ceramic Resonator

110 16 ms + 1K CK 4 ms + 1K CK Ceramic Resonator, fast rising power

111 1K CK 1K CK Ceramic Resonator, BOD enabled

Note: 1. Or external Power-on Reset.

Start-up Time,

at VCC=2.7V

TOUT

Start-up Time,

at VCC= 5.0V Recommended Usage

TOUT

(1)

This table shows the Start-up times from Reset. From sleep, only the clock counting part of the Start-up time is used. The Watchdog Oscillator is used for timing the Real Time part of the Start-up time. The number WDT Oscillator cycles used for each time-out is shown in Table 6.

Table 6. Number of Watchdog Oscillator Cycles

Time-out Number of Cycles

4.0 ms (at V

64 ms (at V

=5.0V) 4K

=5.0V) 64K

The frequency of the Watchdog Oscillator is voltage dependent, as shown in the Electrical Characteristics section.

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-

tion level is nominally 2.2V. The POR is activated whenever V

is below the detection

level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a failure in supply voltage.

The Power-on Reset (POR) circuit ensures that the device is Reset from Power-on. Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V

rise. The Time-out

period of the delay counter is a combination of Internal RC Oscillator cycles and External Oscillator cycles, and it can be defined by the user through the CKSEL Fuses. The eight different selections for the delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the V

decreases to below detection

level.

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Figure 25. MCU Start-up, RESET Tied to V

VCC

RESET

TIME-OUT

INTERNAL

RESET

POT

RST

TOUT

Figure 26. MCU Start-up, RESET Controlled Externally

VCC

RESET

TIME-OUT

INTERNAL

RESET

POT

RST

TOUT

External Reset An External Reset is generated by a low level on the RESET

than 50 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage (V period (t

) on its positive edge, the delay timer starts the MCU after the Time-out

RST

) has expired.

TOUT

Figure 27. External Reset during Operation

pin. Reset pulses longer

AT90S/LS4433

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AT90S/LS4433

Brown-out Detection AT90S4433 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V

level during the operation. The power supply must be decoupled with a 47 nF to 100 nF capacitor if the BOD function is used. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V

decreases to a

value below the trigger level, the Brown-out Reset is immediately activated. When V increases above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal (see Table 5). The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike-free Brown-out Detection.

The BOD circuit will only detect a drop in V

if the voltage stays below the trigger level

for longer than 3 µs for trigger level 4.0V, 7 µs for trigger level 2.7V (typical values).

Figure 28. Brown-out Reset during Operation

VCC

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle

duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period (t

). See page 43 for details on operation of the Watchdog.

TOUT

Figure 29. Watchdog Reset during Operation

1042G–AVR–09/02

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit 76543210

$34 ($54) ––––WDRF BORF EXTRF PORF MCUSR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-On Reset, or by writing a logical “0” to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is cleared by a Power-on Reset, or by writing a logical “0” to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset, or by writing a logical “0” to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical “0” to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then clear the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

Interrupt Handling The AT90S4433 has two 8-bit Interrupt Mask Control Registers; GIMSK (General Inter-

rupt Mask) Register and TIMSK (Timer/Counter Interrupt Mask) Register.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.

If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active.

AT90S/LS4433

1042G–AVR–09/02

General Interrupt Mask Register – GIMSK

AT90S/LS4433

Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software.

Bit 7 6 5 4 3 2 1 0

$3B ($5B) INT1 INT0 –– ––––GIMSK

Read/Write R/W R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR) defines whether the External Interrupt is activated on rising or falling edge of the INT1 pin or is level sensed. Please note that INTF1 Flag is not set when the level-sensitive interrupt condition is met. However, INT1 interrupt is generated, provided that INT1 mask bit is set in GIMSK Register. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.

General Interrupt Flag Register – GIFR

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) defines whether the External Interrupt is activated on rising or falling edge of the INT0 pin or is level sensed. Please note that INTF0 Flag is not set when the level-sensitive interrupt condition is met. However, INT0 interrupt is generated, provided that INT0 mask bit is set in GIMSK Register. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts”.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

Bit 7 6 5 4 3 2 1 0

$3A ($5A) INTF1 INTF0 –– ––––GIFR

Read/Write R/W R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – INTF1: External Interrupt Flag1

When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 in GIMSK, is set (one), the MCU will jump to the Interrupt Vector. The flag is always cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured as level interrupt.

1042G–AVR–09/02

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding Interrupt Flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 in GIMSK is set (one), the MCU will jump to the Interrupt Vector. The flag is always cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured as level interrupt.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

Bit 7 6 5 4 3 2 1 0

$39 ($59) TOIE1 OCIE1 ––TICIE1 – TOIE 0 – TIMSK

Read/Write R/W R/W R R R/W R R/W R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 6 – OCIE1: Timer/Counter1 Output Compare Match Interrupt Enable

When the OCIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a compare match in Timer/Counter1 occurs, i.e., when the OCF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 14, PB0 (ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S4433 and always reads as zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S4433 and always reads as zero.

AT90S/LS4433

1042G–AVR–09/02

Timer/Counter Interrupt Flag Register – TIFR

AT90S/LS4433

Bit 7 6 5 4 3 2 1 0

$38 ($58) TO V1 OCF 1 ––ICF1 – TOV0 – TIFR

Read/Write R/W R/W R R R/W R R/W R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1 (Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.

• Bit 6 – OCF1: Output Compare Flag 1

The OCF1 bit is set (one) when a Compare Match occurs between the Timer/Counter1 and the data in Output Compare Register 1 (OCR1). OCF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1 (Timer/Counter1 Compare Match Interrupt A Enable) and the OCF1 are set (one), the Timer/Counter1 Compare Match Interrupt is executed.

• Bits 5, 4 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 3 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an Input Capture Event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S4433 and always reads as zero.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed.

• Bit 0 – Res: Reserved Bit

1042G–AVR–09/02

This bit is a reserved bit in the AT90S4433 and always reads as zero.

External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, if

enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR). When the External Interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low.

The External Interrupts are set up as described in the specification for the MCU Control Register (MCUCR).

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. Four clock cycles after the Interrupt Flag has been set, the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter (two bytes) is pushed onto the Stack, and the Stack Pointer is decremented by two. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two and the I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

MCU Control Register – MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit 76543210

$35 ($55) ––SE SM ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R R R/W R/W R/W R/W R/W R/W

InitialValue00000000

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and always read as zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid having the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended that the Sleep Enable SE bit be set just before the execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle mode is selected as sleep mode. When SM is set (one), Power-down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes” below.

AT90S/LS4433

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