Rainbow Electronics AT90LS2343 User Manual

Features

• Utilizes the AVR

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz

• Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles – 128 Bytes Internal RAM – 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming

• Special Microcontroller Features

– Low-power Idle and Power-down Modes – External and Internal Interrupt Sources – Power-on Reset Circuit – Selectable On-chip RC Oscillator

• Specifications

– Low-power, High-speed CMOS Process Technology – Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.4 mA – Idle Mode: 0.5 mA – Power-down Mode: <1 µA

• I/O and Packages

– Three Programmable I/O Lines for AT90S/LS2323 – Five Programmable I/O Lines for AT90S/LS2343 – 8-pin PDIP and SOIC

• Operating Voltages

– 4.0 - 6.0V for AT90S2323/AT90S2343 – 2.7 - 6.0V for AT90LS2323/AT90LS2343

• Speed Grades

– 0 - 10 MHz for AT90S2323/AT90S2343-10 – 0 - 4 MHz for AT90LS2323/AT90LS2343-4 – 0 - 1 MHz for AT90LS2343-1

RISC Architecture

8-bit Microcontroller with 2K Bytes of In-System Programmable Flash

AT90S2323 AT90LS2323 AT90S2343 AT90LS2343

Pin Configuration

RESET

(CLOCK) PB3

GND

1 2 3

PB4

AT90S/LS2343

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

PDIP/SOIC

RESET

XTAL1 XTAL2

GND

AT90S/LS2323

1 2 3 4

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

Rev. 1004D–09/01

Description The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers

based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram Figure 1. The AT90S/LS2343 Block Diagram

VCC

8-BIT DATA BUS

INTERNAL

OSCILLATOR

GND

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

SPI

DATA REGISTER

PORTB

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTER

INTERRUPT

UNIT

EEPROM

DATA DIR.

REG. PORTB

TIMING AND

CONTROL

RESET

PORTB DRIVERS

PB0 - PB4

AT90S/LS2323/2343

1004D–09/01

Figure 2. The AT90S/LS2323 Block Diagram

VCC

8-BIT DATA BUS

GND

AT90S/LS2323/2343

INTERNAL

OSCILLATOR

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

Y Z

ALU

STATUS

SPI

DATA REGISTER

PORTB

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTER

INTERRUPT

UNIT

EEPROM

DATA DIR.

REG. PORTB

TIMING AND

CONTROL

OSCILLATOR

RESET

1004D–09/01

PORTB DRIVERS

PB0 - PB2

The AT90S2323/2343 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 3 (AT90S/LS2323)/5 (AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers, an 8bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two softwareselectable power-saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP Flash on a monolithic

chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.

The AT90S2323/2343 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.

Comparison between AT90S/LS2323 and AT90S/LS2343

The AT90S/LS2323 is intended for use with external quartz crystal or ceramic resonator as the clock source. The start-up time is fuse-selectable as either 1 ms (suitable for ceramic resonator) or 16 ms (suitable for crystal). The device has three I/O pins.

The AT90S/LS2343 is intended for use with either an external clock source or the internal RC oscillator as clock source. The device has five I/O pins.

Table 1 summarizes the differences in features of the two devices.

Table 1. Feature Difference Summary

Part AT90S/LS2323 AT90S/LS2343

On-chip Oscillator Amplifier yes no

Internal RC Clock no yes

PB3 available as I/O pin never internal clock mode

PB4 available as I/O pin never always

Start-up time 1 ms/16 ms 16 µs fixed

Pin Descriptions AT90S/LS2323

VCC Supply voltage pin.

GND Ground pin.

Port B (PB2..PB0) Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition becomes active.

RESET

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

AT90S/LS2323/2343

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

1004D–09/01

AT90S/LS2323/2343

Pin Descriptions AT90S/LS2343

VCC Supply voltage pin.

GND Ground pin.

Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition becomes active.

RESET

CLOCK Clock signal input in external clock mode.

Clock Options

Crystal Oscillator The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an

On-chip oscillator, as shown in Figure 3. XTAL1 and XTAL2 are input and output respectively. Either a quartz crystal or a ceramic resonator may be used. It is recommended that the AT90S/LS2343 be used if an external clock source is used, since this gives an extra I/O pin.

Figure 3. Oscillator Connection

External Clock The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or

by the On-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1 MHz

= 5V). A fuse bit (RCEN) in the Flash memory selects the On-chip RC oscillator as

the clock source when programmed (“0”). The AT90S/LS2343 is shipped with this bit programmed. The AT90S/LS2343 is recommended if an external clock source is used, because this gives an extra I/O pin.

The AT90S/LS2323 can be clocked by an external clock as well, as shown in Figure 4. No fuse bit selects the clock source for AT90S/LS2323.

1004D–09/01

Figure 4. External Clock Drive Configuration

AT90S/LS2323AT90S/LS2343

XTAL2

EXTERNAL OSCILATOR SIGNAL

PB3

GND

EXTERNAL OSCILATOR SIGNAL

XTAL1

GND

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed and the result is stored back in the register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register.

Figure 5. The AT90S2323/2343 AVR RISC Architecture

Data Bus 8-bit

1K x 16

Program

Flash

Instruction

Decoder

Control Lines

Program

Counter

Status

and Test

32 x 8

General

Purpose

Registers

ALU

Control

Registers

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

1004D–09/01

Indirect Addressing

Direct Addressing

128 x 8

Data

SRAM

I/O Lines

128 x 8

EEPROM

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S2323/2343 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F.

The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer (SP) is read/write-accessible in the I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 6. Memory Maps

EEPROM Data Memory

$000

EEPROM

(128 x 8)

$07F

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

General-purpose Register File

Figure 7 shows the structure of the 32 general-purpose registers in the CPU.

Figure 7. AVR

CPU General-purpose Working Registers

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire register file.

As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although the register file is not physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file.

1004D–09/01

X-register, Y-register and Zregister

The registers R26..R31 have some added functions to their general-purpose usage. These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z, are defined in Figure 8.

Figure 8. The X-, Y-, and Z-registers

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories: arithmetic, logic and bit functions.

In-System Programmable Flash Program Memory

The AT90S2323/2343 contains 2K bytes On-chip, In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles.

The AT90S2323/2343 Program Counter (PC) is 10 bits wide, hence addressing the 1024 program memory addresses. See page 42 for a detailed description on Flash data programming.

Constant tables must be allocated within the address 0 - 2K (see the LPM – Load Program Memory instruction description on page 60).

See page 12 for the different addressing modes.

EEPROM Data Memory The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as

a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 32, specifying the EEPROM address register, the EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 42 for a detailed description.

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized.

Figure 9. SRAM Organization

R0 $00

R1 $01

R2 $02

……

R29 $1D

R30 $1E

R31 $1F

I/O Registers

$00 $20

$01 $21

$02 $22

……

$3D $5D

$3E $5E

$3F $5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

The 224 data memory locations address the Register file, I/O memory and the data SRAM. The first 96 locations address the Register file + I/O memory, and the next 128 locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- and Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are used and decremented and incremented.

The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the AT90S2323/2343 are all directly accessible through all these addressing modes.

1004D–09/01

Program and Data Addressing Modes

The AT90S2323/2343 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single Register Rd

Register Direct, Two Registers Rd and Rr

Figure 10. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 11. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

AT90S/LS2323/2343

1004D–09/01

I/O Direct Figure 12. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or source register address.

Data Direct Figure 13. Direct Data Addressing

AT90S/LS2323/2343

Data Indirect with Displacement

1004D–09/01

A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register.

Figure 14. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.

Data Indirect Figure 15. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register.

Data Indirect with Predecrement

Data Indirect with Postincrement

Figure 16. Data Indirect Addressing with Pre-decrement

The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register.

Figure 17. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing.

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Constant Addressing Using the LPM Instruction

Indirect Program Addressing, IJMP and ICALL

Figure 18. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

Figure 19. Indirect Program Memory Addressing

Relative Program Addressing, RJMP and RCALL

1004D–09/01

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

Figure 20. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

Memory Access and Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external clock signal applied to the CLOCK pin. No internal clock division is used.

Figure 21. shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 22. shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register.

Figure 22. Single Cycle ALU Operation

T1 T2 T3 T4

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 23..

AT90S/LS2323/2343

1004D–09/01

Figure 23. On-chip Data SRAM Access Cycles

T1 T2 T3 T4

System Clock Ø

AT90S/LS2323/2343

Address

Prev. Address

Address

Data

I/O Memory The I/O space definition of the AT90S2323/2343 is shown in Table 2.

Table 2. AT90S2323/2343 I/O Space

Address Hex Name Function

$3F ($5F) SREG Status REGister

$3D ($5D) SPL Stack Pointer Low

$3B ($5B) GIMSK General Interrupt MaSK register

$3A ($5A) GIFR General Interrupt Flag Register

$39 ($59) TIMSK Timer/Counter Interrupt MaSK register

$38 ($58) TIFR Timer/Counter Interrupt Flag register

Write

Read

$35 ($55) MCUCR MCU Control Register

$34 ($54) MCUSR MCU Status Register

$33 ($53) TCCR0 Timer/Counter0 Control Register

$32 ($52) TCNT0 Timer/Counter0 (8-bit)

$21 ($41) WDTCR Watchdog Timer Control Register

$1E ($3E) EEAR EEPROM Address Register

$1D ($3D) EEDR EEPROM Data Register

$1C ($3C) EECR EEPROM Control Register

$18 ($38) PORTB Data Register, Port B

$17 ($37) DDRB Data Direction Register, Port B

$16 ($36) PINB Input Pins, Port B

Note: Reserved and unused locations are not shown in the table.

All AT90S2323/2343 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 generalpurpose working registers and the I/O space. I/O registers within the address range $00

- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O-specific commands IN

1004D–09/01

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to these addresses. All I/O register addresses throughout this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit 76543210

$3F ($5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Stack Pointer – SPL An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the

AT90S2323/2343. Eight bits are used to address the 128 bytes of SRAM in locations $60 - $DF.

Bit 76543210

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when data is pushed onto the Stack with the PUSH instruction and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI.

Reset and Interrupt Handling

The AT90S2323/2343 provides two interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. Both interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list also determines the priority levels of the interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc.

Table 3. Reset and Interrupt Vectors

Vector No. Program Address Source Interrupt Definition

1 $000 RESET

2 $001 INT0 External Interrupt Request 0

3 $002 TIMER0, OVF0 Timer/Counter0 Overflow

Hardware Pin, Power-on Reset and Watchdog Reset

1004D–09/01

The most typical program setup for the Reset and Interrupt vector addresses are:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp TIM_OVF0 ; Timer0 Overflow

$003 MAIN: ldi r16, low(RAMEND) ; Main program start

out SPL, r16

<instr> xxx

... ... ... ...

Reset Sources The AT90S2323/2343 provides three sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

POT

• External Reset. The MCU is reset when a low level is present on the RESET more than 50 ns.

• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are set to their initial values and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the reset logic. Table 4 defines the timing and electrical parameters of the reset circuitry.

; Handler;

pin for

Figure 24. Reset Logic

VCC

RESET

Power-On Reset

Circuit

100 - 500K

Reset Circuit

Watchdog

Timer

On-Chip

RC-Oscillator

POR

14-Stage Ripple Counter

Q0 Q13Q3

COUNTER RESET

INTERNAL

The AT90S/LS2323 has a programmable start-up time. A fuse bit (FSTRT) in the Flash memory selects the shortest start-up time when programmed (“0”). The AT90S/LS2323 is shipped with this bit unprogrammed.

The AT90S/LS2343 has a fixed start-up time.

RESET

AT90S/LS2323/2343

1004D–09/01

+ 44 hidden pages