Rainbow Electronics AT90LS2343 User Manual

Features

• Utilizes the AVR

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz

• Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles – 128 Bytes Internal RAM – 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming

• Special Microcontroller Features

– Low-power Idle and Power-down Modes – External and Internal Interrupt Sources – Power-on Reset Circuit – Selectable On-chip RC Oscillator

• Specifications

– Low-power, High-speed CMOS Process Technology – Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.4 mA – Idle Mode: 0.5 mA – Power-down Mode: <1 µA

• I/O and Packages

– Three Programmable I/O Lines for AT90S/LS2323 – Five Programmable I/O Lines for AT90S/LS2343 – 8-pin PDIP and SOIC

• Operating Voltages

– 4.0 - 6.0V for AT90S2323/AT90S2343 – 2.7 - 6.0V for AT90LS2323/AT90LS2343

• Speed Grades

– 0 - 10 MHz for AT90S2323/AT90S2343-10 – 0 - 4 MHz for AT90LS2323/AT90LS2343-4 – 0 - 1 MHz for AT90LS2343-1

RISC Architecture

8-bit Microcontroller with 2K Bytes of In-System Programmable Flash

AT90S2323 AT90LS2323 AT90S2343 AT90LS2343

Pin Configuration

RESET

(CLOCK) PB3

GND

1 2 3

PB4

AT90S/LS2343

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

PDIP/SOIC

RESET

XTAL1 XTAL2

GND

AT90S/LS2323

1 2 3 4

VCC

PB2 (SCK/T0)

PB1 (MISO/INT0)

PB0 (MOSI)

Rev. 1004D–09/01

Description The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers

based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2323/2343 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

Block Diagram Figure 1. The AT90S/LS2343 Block Diagram

VCC

8-BIT DATA BUS

INTERNAL

OSCILLATOR

GND

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

SPI

DATA REGISTER

PORTB

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTER

INTERRUPT

UNIT

EEPROM

DATA DIR.

REG. PORTB

TIMING AND

CONTROL

RESET

PORTB DRIVERS

PB0 - PB4

AT90S/LS2323/2343

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Figure 2. The AT90S/LS2323 Block Diagram

VCC

8-BIT DATA BUS

GND

AT90S/LS2323/2343

INTERNAL

OSCILLATOR

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

Y Z

ALU

STATUS

SPI

DATA REGISTER

PORTB

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTER

INTERRUPT

UNIT

EEPROM

DATA DIR.

REG. PORTB

TIMING AND

CONTROL

OSCILLATOR

RESET

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PORTB DRIVERS

PB0 - PB2

The AT90S2323/2343 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 3 (AT90S/LS2323)/5 (AT90S/LS2343) general-purpose I/O lines, 32 general-purpose working registers, an 8bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two softwareselectable power-saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP Flash on a monolithic

chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.

The AT90S2323/2343 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.

Comparison between AT90S/LS2323 and AT90S/LS2343

The AT90S/LS2323 is intended for use with external quartz crystal or ceramic resonator as the clock source. The start-up time is fuse-selectable as either 1 ms (suitable for ceramic resonator) or 16 ms (suitable for crystal). The device has three I/O pins.

The AT90S/LS2343 is intended for use with either an external clock source or the internal RC oscillator as clock source. The device has five I/O pins.

Table 1 summarizes the differences in features of the two devices.

Table 1. Feature Difference Summary

Part AT90S/LS2323 AT90S/LS2343

On-chip Oscillator Amplifier yes no

Internal RC Clock no yes

PB3 available as I/O pin never internal clock mode

PB4 available as I/O pin never always

Start-up time 1 ms/16 ms 16 µs fixed

Pin Descriptions AT90S/LS2323

VCC Supply voltage pin.

GND Ground pin.

Port B (PB2..PB0) Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition becomes active.

RESET

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

AT90S/LS2323/2343

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

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AT90S/LS2323/2343

Pin Descriptions AT90S/LS2343

VCC Supply voltage pin.

GND Ground pin.

Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port pins can provide internal pull-up resistors (selected for each bit). The Port B pins are tri-stated when a reset condition becomes active.

RESET

CLOCK Clock signal input in external clock mode.

Clock Options

Crystal Oscillator The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an

On-chip oscillator, as shown in Figure 3. XTAL1 and XTAL2 are input and output respectively. Either a quartz crystal or a ceramic resonator may be used. It is recommended that the AT90S/LS2343 be used if an external clock source is used, since this gives an extra I/O pin.

Figure 3. Oscillator Connection

External Clock The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or

by the On-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1 MHz

= 5V). A fuse bit (RCEN) in the Flash memory selects the On-chip RC oscillator as

the clock source when programmed (“0”). The AT90S/LS2343 is shipped with this bit programmed. The AT90S/LS2343 is recommended if an external clock source is used, because this gives an extra I/O pin.

The AT90S/LS2323 can be clocked by an external clock as well, as shown in Figure 4. No fuse bit selects the clock source for AT90S/LS2323.

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Figure 4. External Clock Drive Configuration

AT90S/LS2323AT90S/LS2343

XTAL2

EXTERNAL OSCILATOR SIGNAL

PB3

GND

EXTERNAL OSCILATOR SIGNAL

XTAL1

GND

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AT90S/LS2323/2343

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed and the result is stored back in the register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing, enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register.

Figure 5. The AT90S2323/2343 AVR RISC Architecture

Data Bus 8-bit

1K x 16

Program

Flash

Instruction

Decoder

Control Lines

Program

Counter

Status

and Test

32 x 8

General

Purpose

Registers

ALU

Control

Registers

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

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Indirect Addressing

Direct Addressing

128 x 8

Data

SRAM

I/O Lines

128 x 8

EEPROM

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5 shows the AT90S2323/2343 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the register file, $20 - $5F.

The AVR has Harvard architecture – with separate memories and buses for program and data. The program memory is accessed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer (SP) is read/write-accessible in the I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 6. Memory Maps

EEPROM Data Memory

$000

EEPROM

(128 x 8)

$07F

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.

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AT90S/LS2323/2343

General-purpose Register File

Figure 7 shows the structure of the 32 general-purpose registers in the CPU.

Figure 7. AVR

CPU General-purpose Working Registers

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire register file.

As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although the register file is not physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file.

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X-register, Y-register and Zregister

The registers R26..R31 have some added functions to their general-purpose usage. These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z, are defined in Figure 8.

Figure 8. The X-, Y-, and Z-registers

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories: arithmetic, logic and bit functions.

In-System Programmable Flash Program Memory

The AT90S2323/2343 contains 2K bytes On-chip, In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles.

The AT90S2323/2343 Program Counter (PC) is 10 bits wide, hence addressing the 1024 program memory addresses. See page 42 for a detailed description on Flash data programming.

Constant tables must be allocated within the address 0 - 2K (see the LPM – Load Program Memory instruction description on page 60).

See page 12 for the different addressing modes.

EEPROM Data Memory The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as

a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 32, specifying the EEPROM address register, the EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 42 for a detailed description.

AT90S/LS2323/2343

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AT90S/LS2323/2343

SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized.

Figure 9. SRAM Organization

R0 $00

R1 $01

R2 $02

……

R29 $1D

R30 $1E

R31 $1F

I/O Registers

$00 $20

$01 $21

$02 $22

……

$3D $5D

$3E $5E

$3F $5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

The 224 data memory locations address the Register file, I/O memory and the data SRAM. The first 96 locations address the Register file + I/O memory, and the next 128 locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- and Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are used and decremented and incremented.

The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the AT90S2323/2343 are all directly accessible through all these addressing modes.

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Program and Data Addressing Modes

The AT90S2323/2343 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single Register Rd

Register Direct, Two Registers Rd and Rr

Figure 10. Direct Single Register Addressing

The operand is contained in register d (Rd).

Figure 11. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

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I/O Direct Figure 12. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or source register address.

Data Direct Figure 13. Direct Data Addressing

AT90S/LS2323/2343

Data Indirect with Displacement

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A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register.

Figure 14. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.

Data Indirect Figure 15. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register.

Data Indirect with Predecrement

Data Indirect with Postincrement

Figure 16. Data Indirect Addressing with Pre-decrement

The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register.

Figure 17. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing.

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AT90S/LS2323/2343

Constant Addressing Using the LPM Instruction

Indirect Program Addressing, IJMP and ICALL

Figure 18. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

Figure 19. Indirect Program Memory Addressing

Relative Program Addressing, RJMP and RCALL

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Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

Figure 20. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

Memory Access and Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external clock signal applied to the CLOCK pin. No internal clock division is used.

Figure 21. shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 22. shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register.

Figure 22. Single Cycle ALU Operation

T1 T2 T3 T4

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 23..

AT90S/LS2323/2343

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Figure 23. On-chip Data SRAM Access Cycles

T1 T2 T3 T4

System Clock Ø

AT90S/LS2323/2343

Address

Prev. Address

Address

Data

I/O Memory The I/O space definition of the AT90S2323/2343 is shown in Table 2.

Table 2. AT90S2323/2343 I/O Space

Address Hex Name Function

$3F ($5F) SREG Status REGister

$3D ($5D) SPL Stack Pointer Low

$3B ($5B) GIMSK General Interrupt MaSK register

$3A ($5A) GIFR General Interrupt Flag Register

$39 ($59) TIMSK Timer/Counter Interrupt MaSK register

$38 ($58) TIFR Timer/Counter Interrupt Flag register

Write

Read

$35 ($55) MCUCR MCU Control Register

$34 ($54) MCUSR MCU Status Register

$33 ($53) TCCR0 Timer/Counter0 Control Register

$32 ($52) TCNT0 Timer/Counter0 (8-bit)

$21 ($41) WDTCR Watchdog Timer Control Register

$1E ($3E) EEAR EEPROM Address Register

$1D ($3D) EEDR EEPROM Data Register

$1C ($3C) EECR EEPROM Control Register

$18 ($38) PORTB Data Register, Port B

$17 ($37) DDRB Data Direction Register, Port B

$16 ($36) PINB Input Pins, Port B

Note: Reserved and unused locations are not shown in the table.

All AT90S2323/2343 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 generalpurpose working registers and the I/O space. I/O registers within the address range $00

- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O-specific commands IN

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and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to these addresses. All I/O register addresses throughout this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and peripherals control registers are explained in the following sections.

Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit 76543210

$3F ($5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set description for detailed information.

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AT90S/LS2323/2343

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Stack Pointer – SPL An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the

AT90S2323/2343. Eight bits are used to address the 128 bytes of SRAM in locations $60 - $DF.

Bit 76543210

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when data is pushed onto the Stack with the PUSH instruction and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI.

Reset and Interrupt Handling

The AT90S2323/2343 provides two interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. Both interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list also determines the priority levels of the interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc.

Table 3. Reset and Interrupt Vectors

Vector No. Program Address Source Interrupt Definition

1 $000 RESET

2 $001 INT0 External Interrupt Request 0

3 $002 TIMER0, OVF0 Timer/Counter0 Overflow

Hardware Pin, Power-on Reset and Watchdog Reset

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The most typical program setup for the Reset and Interrupt vector addresses are:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp TIM_OVF0 ; Timer0 Overflow

$003 MAIN: ldi r16, low(RAMEND) ; Main program start

out SPL, r16

<instr> xxx

... ... ... ...

Reset Sources The AT90S2323/2343 provides three sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

POT

• External Reset. The MCU is reset when a low level is present on the RESET more than 50 ns.

• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are set to their initial values and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the reset logic. Table 4 defines the timing and electrical parameters of the reset circuitry.

; Handler;

pin for

Figure 24. Reset Logic

VCC

RESET

Power-On Reset

Circuit

100 - 500K

Reset Circuit

Watchdog

Timer

On-Chip

RC-Oscillator

POR

14-Stage Ripple Counter

Q0 Q13Q3

COUNTER RESET

INTERNAL

The AT90S/LS2323 has a programmable start-up time. A fuse bit (FSTRT) in the Flash memory selects the shortest start-up time when programmed (“0”). The AT90S/LS2323 is shipped with this bit unprogrammed.

The AT90S/LS2343 has a fixed start-up time.

RESET

AT90S/LS2323/2343

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AT90S/LS2323/2343

Table 4. Reset Characteristics (V

= 5.0V)

Symbol Parameter Min Typ Max Units

Power-on Reset Threshold Voltage, rising 1.0 1.4 1.8 V

(1)

TOUT

POT

RST

Power-on Reset Threshold Voltage, falling 0.4 0.6 0.8 V

RESET Pin Threshold Voltage 0.6 V

Reset Delay Time-out Period AT90S/LS2323 FSTRT Programmed

Reset Delay Time-out Period AT90S/LS2323 FSTRT Unprogrammed

1.0 1.1 1.2 ms

11.0 16.0 21.0 ms

Reset Delay Time-out Period AT90S/LS2343 11.0 16.0 21.0 µs

Note: 1. The Power-on Reset will not work unless the supply voltage has been below V

(falling).

Table 5. Reset Characteristics (VCC = 3.0V)

Symbol Parameter Min Typ Max Units

Power-on Reset Threshold Voltage, rising 1.0 1.4 1.8 V

(1)

TOUT

POT

RST

Power-on Reset Threshold Voltage, falling 0.4 0.6 0.8 V

RESET Pin Threshold Voltage 0.6 V

Reset Delay Time-out Period AT90S/LS2323 FSTRT Programmed

Reset Delay Time-out Period AT90S/LS2323 FSTRT Unprogrammed

2.0 2.2 2.4 ms

22.0 32.0 42.0 ms

POT

TOUT

Note: 1. The Power-on Reset will not work unless the supply voltage has been below V

Reset Delay Time-out Period AT90S/LS2343 22.0 32.0 42.0 µs

POT

(falling).

Power-on Reset The AT90S2323/2343 is designed for use in systems where it can operate from the

internal RC oscillator (AT90S/LS2343), on-chip oscillator (AT90S/LS2323), or in applications where a clock signal is provided by an external clock source. After V reached V

, the device will start after the time t

POT

(see Figure 25). If the clock signal

TOUT

is provided by an external clock source, the clock must not be applied until V

has

reached the minimum voltage defined for the applied frequency.

For AT90S2323, the user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for each time-out is shown in Table 6. For AT90S2343, the start-up time is one Watchdog cycle only. The frequency of the Watchdog oscillator is voltage-dependent as shown in “Typical Characteristics” on page 49.

Table 6. Number of Watchdog Oscillator Cycles

FSTRT Time-out at VCC = 5V Number of WDT Cycles

Programmed 1.1 ms 1K

Unprogrammed 16.0 ms 16K

1004D–09/01

Figure 25. MCU Start-up, RESET Tied to VCC.

VCC

RESET

TIME-OUT

INTERNAL

RESET

POT

RST

TOUT

Figure 26. MCU Start-up, RESET

VCC

RESET

TIME-OUT

INTERNAL

RESET

POT

Controlled Externally

RST

TOUT

External Reset An external reset is generated by a low level on the RESET

than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (V period t

) on its positive edge, the delay timer starts the MCU after the Time-out

RST

has expired.

TOUT

Figure 27. External Reset during Operation

pin. Reset pulses longer

AT90S/LS2323/2343

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AT90S/LS2323/2343

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle

duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

Figure 28. Watchdog Reset during Operation

. Refer to page 30 for details on operation of the Watchdog.

TOUT

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210

$34 ($54) ––––––EXTRF PORF MCUSR

Read/WriteRRRRRRR/WR/W

Initial Value000000See Bit Description

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bit 1 – EXTRF: External Reset Flag

After a Power-on Reset, this bit is undefined (X). It will be set by an External Reset. A Watchdog Reset will leave this bit unchanged.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave this bit unchanged.

To summarize, Table 7 shows the value of these two bits after the three modes of reset.

Table 7. PORF and EXTRF Values after Reset

Reset Source PORF EXTRF

Power-on Reset 1 Undefined

External Reset Unchanged 1

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Watchdog Reset Unchanged Unchanged

To make use of these bits to identify a reset condition, the user software should clear both the PORF and EXTRF bits as early as possible in the program. Checking the PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before an External or Watchdog Reset occurs, the source of reset can be found by using the following truth table, Table 8.

Table 8. Reset Source Identification

PORF EXTRF Reset Source

0 0 Watchdog Reset

0 1 External Reset

1 0 Power-on Reset

1 1 Power-on Reset

Interrupt Handling The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (General

Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one) and will be executed by order of priority.

General Interrupt Mask Register – GIMSK

Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Bit 7 6 5 4 3 2 1 0

$3B ($5B) – INT0 –– ––––GIMSK

Read/Write R R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.”

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

AT90S/LS2323/2343

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General Interrupt Flag Register – GIFR

Timer/Counter Interrupt Mask Register – TIMSK

AT90S/LS2323/2343

Bit 7 6 5 4 3 2 1 0

$3A ($5A) – INTF0 –– ––––GIFR

Read/Write R R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 in GIMSK, is set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured as level interrupt.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

Bit 7 6 5 4 3 2 1 0

$39 ($59) –––– – –TOIE0 – TIMSK

Read/Write R R R R R R R/W R

Initial Value 0 0 0 0 0 0 0 0

Timer/Counter Interrupt FLAG Register – TIFR

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the Overflow Flag (Timer/Counter0) is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.

Bit 7 6 5 4 3 2 1 0

$38 ($58) –– ––––TOV0 – TIFR

Read/Write R R R R R R R/W R

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed.

1004D–09/01

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and always reads zero.

External Interrupt The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt

will trigger even if the INT0 pin is configured as an output. This feature provides a way of generating a software interrupt. The external interrupt can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register (MCUCR). When the external interrupt is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is held low.

The external interrupt is set up as described in the specification for the MCU Control Register (MCUCR).

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During these four clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in SREG is set. The vector is a relative jump to the interrupt routine and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the stack and the Stack Pointer is incremented by 2. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

MCU Control Register – MCUCR

The MCU Control Register contains control bits for general MCU functions.

Bit 76543210

$35 ($55) ––SE SM ––ISC01 ISC00 MCUCR

Read/Write R R R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep mode, unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle mode is selected as Sleep mode. When SM is set (one), Power-down mode is selected as sleep mode. For details, refer to the section “Sleep Modes”.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read as zero.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that

AT90S/LS2323/2343

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AT90S/LS2323/2343

activate the interrupt are defined in Table 9. The value on the INT01 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 9. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

01Reserved

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during Sleep mode, the MCU wakes up and executes from the Reset vector.

Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset.

Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

down mode. In this mode, the external oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog reset (if enabled), or an external level interrupt on INT0 can wake up the MCU.

Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog oscillator clock and if the input has the required level during this time, the MCU will wake up. The period of the Watchdog oscillator is 1 µs (nominal) at 5.0V and 25 the Watchdog oscillator is voltage-dependent as shown in section “Typical Characteristics” on page 49.

When waking up from Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is equal to the clock reset period, as shown in Table 4 and Table 5 on page 21.

If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be executed.

°C. The frequency of

1004D–09/01

Timer/Counter The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter –

Timer/Counter0. The Timer/Counter has prescaling selection from the 10-bit prescaling timer. The Timer/Counter can be used either as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting.

Timer/Counter Prescaler Figure 29 shows the Timer/Counter prescaler.

Figure 29. Timer/Counter0 Prescaler

CS00 CS01 CS02

10-BIT T/C PRESCALER

CK/8

TIMER/COUNTER0 CLOCK SOURCE

TCK0

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where CK is the oscillator clock. CK, external source and stop can also be selected as clock sources.

8-bit Timer/Counter0 Figure 30 shows the block diagram for Timer/Counter0.

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).

CK/64

CK/256

CK/1024

When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To ensure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.

AT90S/LS2323/2343

1004D–09/01

Figure 30. Timer/Counter 0 Block Diagram

AT90S/LS2323/2343

Timer/Counter0 Control Register – TCCR0

Bit 7 6 5 4 3 210

$33 ($53) –– – – –CS02 CS01 CS00 TCCR0

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and always read zero.

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0

The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.

Table 10. Clock 0 Prescale Select

CS02 CS01 CS00 Description

0 0 0 Stop, the Timer/Counter0 is stopped.

001CK

010CK/8

011CK/64

1 0 0 CK/256

1 0 1 CK/1024

1 1 0 External Pin T0, falling edge

1004D–09/01

1 1 1 External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting.

Timer/Counter0 – TCNT0

Bit 76543210

$32 ($52) MSB LSB TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 11. See characterization data for typical values at other V (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2323/2343 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 23.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.

levels. The WDR

Figure 31. Watchdog Timer

Oscillator

1 MHz at V

350 kHz at V

= 5V

= 3V

AT90S/LS2323/2343

1004D–09/01

Watchdog Timer Control Register – WDTCR

AT90S/LS2323/2343

Bit 7654 3210

$21 ($41) –––WDTOE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to “1” before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 11.

Table 11. Watchdog Timer Prescale Select

Number of WDT

WDP2 WDP1 WDP0

0 0 0 16K cycles 47 ms 15 ms

0 0 1 32K cycles 94 ms 30 ms

0 1 0 64K cycles 0.19 s 60 ms

0 1 1 128K cycles 0.38 s 0.12 s

1 0 0 256K cycles 0.75 s 0.24 s

1 0 1 512K cycles 1.5 s 0.49 s

1 1 0 1,024K cycles 3.0 s 0.97 s

1 1 1 2,048K cycles 6.0 s 1.9 s

Note: The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical

Characteristics section. The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero. To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select.

Oscillator Cycles

Typical Time-out at VCC = 3.0V

Typical Time-out at VCC = 5.0V

1004D–09/01

EEPROM Read/Write Access

EEPROM Address Register – EEAR

The EEPROM access registers are accessible in the I/O space.

The write access time is in the range of 2.5 - 4 ms, depending on the V

voltages. A

self-timing function, however, lets the user software detect when the next byte can be written.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

Bit 76543210

$1E ($3E) – EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – Res: Reserved Bit

This bit is a reserved bit in the AT90S2323/2343 and will always read as zero.

• Bit 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127.

EEPROM Data Register – EEDR

Bit 76543210

$1D ($3D) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

AT90S/LS2323/2343

1004D–09/01

EEPROM Control Register – EECR

AT90S/LS2323/2343

Bit 765432 10

$1C ($3C) –––––EEMWE EEWE EERE EECR

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90S2323/2343 and will always read as zero.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEAR (optional).

3. Write new EEPROM data to EEDR (optional).

4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to the EEMWE bit, the EEWE bit must be written to “0” in the same cycle).

5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR registers will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the four last steps to avoid these problems.

When the write access time (typically 2.5 ms at V

= 5V or 4 ms at VCC = 2.7V) has

elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined.

1004D–09/01

Prevent EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low V referred to as a Brown-out Detector (BOD). Please refer to application note AVR 180 for design considerations regarding power-on reset and low-voltage detection.

2. Keep the AVR core in Power-down Sleep mode during periods of low V will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption.

Reset Protection circuit, often

. This

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O

ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).

For the AT90S/LS2323, Port B is an 3-bit bi-directional I/O port. For the AT90S/LS2343, Port B is a 5-bit bi-directional I/O port.

Please note: Bits 3 and 4 in the description of PORTB, DDRB and PINB do not apply to the AT90S/LS2323. They are read only with a value of 0.

Three I/O memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18 ($38), Data Direction Register – DDRB, $17($37) and the Port B Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB4 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.

The Port B pins with alternate functions are shown in Table 12.

Port B Data Register – PORTB

Port B Data Direction Register – DDRB

Table 12. Port B Pin Alternate Functions

Port Pin Alternate Functions

PB0 MOSI (Data input line for memory downloading)

PB1

PB2

PB3 CLOCK (Clock input, AT90S/LS2343 only)

MISO (Data output line for memory uploading) INT0 (External Interrupt0 Input)

SCK (Serial clock input for serial programming) TO (Timer/Counter0 counter clock input)

When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate function description.

Bit 76543210

$18 ($38)

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

$17 ($37) –––DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

–––PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

1004D–09/01

Port B Input Pins Address – PINB

Bit 76543210

$16 ($36) –––PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial Value 0 0 0 N/A N/A N/A N/A N/A

The Port B Input Pins address (PINB) is not a register and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read and when reading PINB, the logical values present on the pins are read.

Port B as General Digital I/O

All pins in port B have equal functionality when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Table 13. DDBn Effects on Port B Pins

DDBn PORTBn I/O Pull-up Comment

0 0 Input No Tri-state (high-Z)

0 1 Input Yes PBn will source current if ext. pulled low

1 0 Output No Push-pull Zero Output

1 1 Output No Push-pull One Output

Alternate Functions of Port B The alternate pin functions of Port B are as follows:

• CLOCK – Port B, Bit 3

Clock input: AT90S/LS2343 only. When the RCEN fuse is programmed and the device runs from the internal RC oscillator, this pin is a general I/O pin. When the RCEN fuse is unprogrammed, an external clock source must be connected to CLOCK.

• SCK/T0 – Port B, Bit 2

In Serial Programming mode, this bit serves as the serial clock input, SCK.

During normal operation, this pin can serve as the external counter clock input. See the timer/counter description for further details. If external timer/counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output.

• MISO/INT0 – Port B, Bit 1

In Serial Programming mode, this bit serves as the serial data output, MISO.

During normal operation, this pin can serve as the external interrupt0 input. See the interrupt description for details on how to enable this interrupt. Note that activity on this pin will trigger the interrupt even if the pin is configured as an output.

• MOSI – Port B, Bit 0

In Serial Programming mode, this pin serves as the serial data input, MOSI.

AT90S/LS2323/2343

1004D–09/01

Memory Programming

AT90S/LS2323/2343

Program and Data Memory Lock Bits

Fuse Bits in AT90S/LS2323

The AT90S2323/2343 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 14. The Lock bits can only be erased with the Chip Erase operation.

Table 14. Lock Bit Protection Modes

Memory Lock Bits

Protection TypeMode LB1 LB2

1 1 1 No memory lock features enabled.

2 0 1 Further programming of the Flash and EEPROM is disabled.

3 0 0 Same as mode 2, and verify is also disabled.

Note: 1. In the high-voltage Serial Programming mode, further programming of the Fuse bits

are also disabled. Program the Fuse bits before programming the Lock bits.

The AT90S/LS2323 has two Fuse bits, SPIEN and FSTRT.

• When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading are enabled. Default value is programmed (“0”). This bit is not accessible in the lowvoltage Serial Programming mode.

• When the FSTRT Fuse is programmed (“0”), the shortest start-up time is selected as indicated in Table 6 on page 21. Default value is programmed (“0”). Changing the FSTRT Fuse does not take effect until the next Power-on Reset. In AT90S/LS2343 the start-up time is fixed.

(1)

The status of the Fuse bits is not affected by Chip Erase.

Fuse Bits in AT90S/LS2343

The AT90S/LS2343 has two Fuse bits, SPIEN and RCEN.

• When the RCEN Fuse is programmed (“0”), the internal RC oscillator is selected as the MCU clock source. Default value is programmed ("0") in AT90LS2343-1. Default value is un-programmed ("1") in AT90LS2343-4 and AT90S2343-10. Changing the RCEN Fuse does not take effect until the next Power-on Reset. AT90S/LS2323 cannot select the internal RC oscillator as the MCU source.

The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes All Atmel microcontrollers have a three-byte signature code that identifies the device.

The three bytes reside in a separate address space.

(Note:)

For the AT90S/LS2323

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2K bytes Flash memory)

3. $002: $02 (indicates AT90S/LS2323 when signature byte $001 is $91)

For AT90S/LS2343

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2K bytes Flash memory)

(Note:)

, they are:

1004D–09/01

3. $002: $03 (indicates AT90S/LS2343 when signature byte $001 is $91)

Note: When both Lock bits are programmed (Lock mode 3), the signature bytes cannot be read

in the low-voltage Serial mode. Reading the signature bytes will return: $00, $01 and $02.

Programming the Flash and EEPROM

Atmel’s AT90S2323/2343 offers 2K bytes of In-System Programmable Flash program memory and 128 bytes of EEPROM data memory.

The AT90S2323/2343 is shipped with the On-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed.

The device supports a high-voltage (12V) Serial Programming mode and a low-voltage Serial Programming mode. The +12V is used for programming enable only and no current of significance is drawn by this pin. The low-voltage Serial Programming mode provides a convenient way to download program and data into the device inside the user’s system.

The program and EEPROM memory arrays in the AT90S2323/2343 are programmed byte-by-byte in either programming modes. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the low-voltage Serial Programming mode.

During programming, the supply voltage must be in accordance with Table 15.

Table 15. Supply Voltage during Programming

Part Low-voltage Serial Programming High-voltage Serial Programming

AT90S2323 4.0 - 6.0V 4.5 - 5.5V

AT90LS2323 2.7 - 6.0V 4.5 - 5.5V

AT90S2323 4.0 - 6.0V 4.5 - 5.5V

AT90LS2323 2.7 - 6.0V 4.5 - 5.5V

High-voltage Serial Programming

AT90S/LS2323/2343

This section describes how to program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S2323/2343.

Figure 32. High-voltage Serial Programming

11.5 - 12.5V 4.5 - 5.5V

SERIAL CLOCK INPUT

AT90S/LS2323,

AT90S/LS2343

RESET

XTAL1/PB3

GND

VCC

PB2

PB1

PB0

SERIAL DATA OUTPUT

SERIAL INSTR. INPUT

SERIAL DATA INPUT

1004D–09/01

AT90S/LS2323/2343

High-voltage Serial Programming Algorithm

To program and verify the AT90S/LS2323 and AT90S/LS234 in the high-voltage Serial Programming mode, the following sequence is recommended (see instruction formats in Table 16):

1. Power-up sequence: Apply 4.5 - 5.5V between V

and GND. Set RESET and

PB0 to “0” and wait at least 100 ns. Then, if the RCEN Fuse is not programmed, toggle XTAL1/PB3 at least four times with minimum 100 ns pulse width. Set PB3 to “0”. Wait at least 100 ns. Or, if the RCEN Fuse is programmed, set PB3 to “0”. Wait for least 4 µs. In both cases, apply 12V to RESET

and wait at least 100 ns

before changing PB0. Wait 8 µs before giving any instructions.

2. The Flash array is programmed one byte at a time by supplying first the address, then the low and high data bytes. The write instruction is self-timed; wait until the PB2 (RDY/BSY

) pin goes high.

3. The EEPROM array is programmed one byte at a time by supplying first the address, then the data byte. The write instruction is self-timed; wait until the PB2 (RDY/BSY

) pin goes high.

4. Any memory location can be verified by using the Read instruction, which returns the contents at the selected address at serial output PB2.

5. Power-off sequence:Set PB3 to “0”. Set RESET Tu r n V

to “0”.

power off.

When writing or reading serial data to the device, data is clocked on the rising edge of the serial clock. See Figure 33, Figure 34 and Table 17 for details.

Figure 33. High-voltage Serial Programming Waveforms

SERIAL DATA INPUT

PB0

SERIAL INSTR. INPUT

PB1

SERIAL DATA OUTPUT

PB2

SERIAL CLOCK INPUT

XTAL1/PB3

MSB

012345678910

LSB

1004D–09/01

Table 16. High-voltage Serial Programming Instruction Set

Instruction Format

Instruction

Chip Erase

Write Flash High and Low Address

Write Flash Low Byte

Write Flash High Byte

Read Flash High and Low Address

Read Flash Low Byte

Read Flash High Byte

Write EEPROM Low Address

Write EEPROM Byte

Read EEPROM Low Address

Read EEPROM Byte

Write Fuse Bits (AT90S/ LS2323)

Write Fuse Bits (AT90S/ LS2343)

Write Lock Bits

PB0 PB1 PB2

PB0 PB1P

PB0 PB1 PB2

0_1000_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0001_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_ i i i i_i i i i _00 0_0010_1100_00

x_xxxx_xxxx_xx

0_ i i i i_i i i i _00 0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0010_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1000_00

x_xxxx_xxxx_xx

0_0001_0001_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_ i i i i_i i i i _00 0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0011_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1000_00

x_xxxx_xxxx_xx

0_0100_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0100_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0010_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_00aa_00 0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_0100_00

x_xxxx_xxxx_xx

0_0000_00aa_00 0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

o_oooo_ooox_xx

0_0000_0000_00 0_0111_1100_00

o_oooo_ooox_xx

0_0bbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0bbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

o_oooo_ooox_xx

0_11S1_111F_00 0_0010_1100_00

x_xxxx_xxxx_xx

0_11S1_111R_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_1111_1211_00 0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

x_xxxx_xxxx_xx

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00 0_0000_0000_00

0_0000_0000_00 0_0111_1100_00 0_0000_0000_00

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00 0_0000_0000_00

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00 0_0000_0000_00

Operation RemarksInstr.1 Instr.2 Instr.3 Instr.4

Wait t the Chip Erase cycle to finish.

Repeat Instr.2 for a new 256-byte page. Repeat Instr.3 for each new address.

Wait after Instr.3 until PB2 goes high. Repeat Instr.1, Instr. 2 and Instr.3 for each new address.

Repeat Instr.2 and Instr.3 for each new address.

Repeat Instr.1 and Instr.2 for each new address.

Repeat Instr.2 for each new address.

Wait after Instr.3 until PB2 goes high

Repeat Instr.2 for each new address.

Repeat Instr.2 for each new address

Wait t the Write Fuse bits cycle to finish. Set S,F = “0” to program, “1” to unprogram.

Wait t the Write Fuse bits cycle to finish. Set S,R = “0” to program, “1” to unprogram.

Wait after Instr.4 until PB2 goes high. Write 2, 1 = “0” to program the Lock bit.

WLWH_CE

WLWH_PFB

after Instr.3 for

AT90S/LS2323/2343

1004D–09/01

Table 16. High-voltage Serial Programming Instruction Set (Continued)

Instruction Format

AT90S/LS2323/2343

Instruction

Read Fuse and Lock Bits (AT90S/ LS2323)

Read Fuse and Lock Bits (AT90S/ LS2343)

Read Signature Bytes

PB0 PB1 PB2

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_1000_00 0_0100_1100_00

x_xxxx_xxxx_xx

Note: a = address high bits

b = address low bits i = data in o = data out

x = don’t care

1 = Lock Bit1 2 = Lock Bit2

F = FSTRT Fuse R = RCEN Fuse S = SPIEN Fuse

0_0000_0000_00 0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_00bb_00 0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1100_00

1_2Sxx_xxRx_xx

0_0000_0000_00 0_0111_1100_00

1_2Sxx_xxRx_xx

0_0000_0000_00 0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1100_00

o_oooo_ooox_xx

Operation RemarksInstr.1 Instr.2 Instr.3 Instr.4

Reading 1, 2, S, R = “0” means the Fuse/Lock bit is programmed.

Repeat Instr.2 - Instr.4 for each signature byte address.

1004D–09/01

High-voltage Serial Programming Characteristics

Figure 34. High-voltage Serial Programming Timing

SDI (PB0), SII (PB1)

IVSH

SHIX

SLSH

Low-voltage Serial Downloading

SCI (XTAL1/PB3)

SHSL

SDO (PB2)

SHOV

Table 17. High-voltage Serial Programming Characteristics, T

= 25°C ± 10%, VCC =

5.0V ± 10% (unless otherwise noted)

Symbol Parameter Min Typ Max Units

SHSL

SLSH

IVSH

SHIX

SHOV

WLWH_CE

WLWH_PFB

SCI (XTAL1/PB3) Pulse Width High 100.0 ns

SCI (XTAL1/PB3) Pulse Width Low 100.0 ns

SDI (PB0), SII (PB1) Valid to SCI (XTAL1/PB3) High

SDI (PB0), SII (PB1) Hold after SCI (XTAL1/PB3) High

SCI (XTAL1/PB3) High to SDO (PB2) Valid 10.0 16.0 32.0 ns

Wait after Instr.3 for Chip Erase 5.0 10.0 15.0 ms

Wait after Instr.3 for Write Fuse Bits 1.0 1.5 1.8 ms

50.0 ns

Both the program and data memory arrays can be programmed using the serial SPI bus while RESET and MISO (output) (see Figure 35). After RESET

is pulled to GND. The serial interface consists of pins SCK, MOSI (input)

is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed.

Figure 35. Low-voltage Serial Programming and Verify

AT90S/LS2323/2343

GND

AT90S/LS2323,

AT90S/LS2343

RESET

GND

VCC

PB2

PB1

PB0

2.7 - 6.0V

SCK

MISO

MOSI

1004D–09/01

AT90S/LS2323/2343

For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into $FF.

The program and EEPROM memory arrays have separate address spaces: $0000 to $03FF for Flash program memory and $000 to $07F for EEPROM data memory.

Either an external clock is applied to the XTAL1/PB3 pin or the device must be clocked from the internal RC oscillator (AT90S/LS2343 only). The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 2 MCU clock cycles High: > 2 MCU clock cycles

Low-voltage Serial Programming Algorithm

When writing serial data to the AT90S2323/2343, data is clocked on the rising edge of SCK.

When reading data from the AT90S2323/2343, data is clocked on the falling edge of SCK. See Figure 36, Figure 37 and Table 20 for timing details.

To program and verify the AT90S2323/2343 in the low-voltage Serial Programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 19):

1. Power-up sequence:

Apply power between V

and GND while RESET and SCK are set to “0”. (If the

programmer cannot guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to “0”.) If the device is programmed for external clocking, apply a 0 - 8 MHz clock to the XTAL1/PB3 pin. If the internal RC oscillator is selected as the clock source, no external clock source needs to be applied (AT90S/LS2343 only).

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section for minimum low and high periods for the serial clock input, SCK.

3. The serial programming instructions will not work if the communication is out of

synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected.

4. If a Chip Erase is performed (must be done to erase the Flash), wait t

after the instruction, give RESET Table 21 on page 46 for t

WD_ERASE

a positive pulse and start over from step 2. See

value.

WD_ERASE

5. The Flash or EEPROM array is programmed one byte at a time by supplying the

address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait t See Table 22 on page 46 for t

WD_PROG

before transmitting the next instruction.

value. In an erased device, no $FFs in the

data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction, which returns

the content at the selected address at the serial output MISO (PB1) pin.

1004D–09/01

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set CLOCK/XTAL1 to “0”. Set RESET Turn V

to “1”.

power off.

Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location

being programmed will give the value P1 until the auto-erase is finished, and then the value P2 will be given. See Table 18 for P1 and P2 values.

At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time t for t

WD_PROG

value. As a chip-erased device contains $FF in all locations, programming

WD_PROG

before programming the next byte. See Table 22

of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device.

Table 18. Read Back Value during EEPROM Polling

Part P1 P2

AT90S2323 $00 $FF

AT90S2343 $00 $FF

Data Polling Flash When a byte is being programmed into the Flash, reading the address location being

programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least t

WD_PROG

before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped.

Figure 36. Low-voltage Serial Downloading Waveforms

SERIAL DATA INPUT

PB0(MOSI)

SERIAL DATA OUTPUT

PB1(MISO)

SERIAL CLOCK INPUT

PB2(SCK)

MSB

LSB

AT90S/LS2323/2343

1004D–09/01

Table 19. Low-voltage Serial Programming Instruction Set AT90S2323/2343

Instruction Format

AT90S/LS2323/2343

Instruction

Programming Enable

Chip Erase

Read Program Memory

Write Program Memory

Read EEPROM Memory

Write EEPROM Memory

Read Lock and Fuse Bits (AT90S/LS2323)

Read Lock and Fuse Bits (AT90S/LS2343)

Write Lock Bits

OperationByte 1 Byte 2 Byte 3 Byte 4

1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial programming while

is low.

RESET

1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase both Flash and

EEPROM memory arrays.

0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from

program memory at word address a:b.

0100 H000 0000 00aa bbbb bbbb iiii iiii Write H (high or low) data i to

program memory at word address a:b.

1010 0000 0000 0000 xbbb bbbb oooo oooo Read data o from EEPROM

memory at address b.

1100 0000 0000 0000 xbbb bbbb iiii iiii Write data i to EEPROM memory at

address b.

0101 1000 xxxx xxxx xxxx xxxx 12Sx xxxF Read Lock and Fuse bits.

“0” = programmed, “1” = unprogrammed

0101 1000 xxxx xxxx xxxx xxxx 12Sx xxxR Read Lock and Fuse bits.

“0” = programmed, “1” = unprogrammed

1010 1100 1111 1211 xxxx xxxx xxxx xxxx Write Lock bits. Set bits 1,2 = “0” to

program Lock bits.

Write FSTRT Bit (AT90S/LS2323)

Write RCEN Bit (AT90S/LS2343)

Read Signature Bytes

Notes: 1. a = address high bits

b = address low bits H = 0 – Low byte, 1 – High byte o = data out i = data in

x = don’t care

1 = lock bit 1 2 = lock bit 2

F = FSTRT Fuse R = RCEN Fuse S = SPIEN Fuse

2. When the state of the RCEN/FSTRT bit is changed, the device must be power cycled for the changes to have any effect.

3. The signature bytes are not readable in Lock mode 3, i.e., both Lock bits programmed.

1010 1100 1011 111F xxxx xxxx xxxx xxxx Write FSTRT fuse. Set bit F = “0” to

1010 1100 1011 111R xxxx xxxx xxxx xxxx Write RCEN Fuse. Set bit R = ‘0’ to

0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read signature byte o from

program, “1” to unprogram.

program, ‘1’ to unprogram.

address b.

(3)

(2)

1004D–09/01

Low-voltage Serial Programming Characteristics

Figure 37. Low-voltage Serial Programming Timing

MOSI

OVSH

SHOX

SLSH

SCK

SHSL

MISO

SLIV

Table 20. Low-voltage Serial Programming Characteristics, T

2.7 - 6.0V (unless otherwise noted)

Symbol Parameter Min Typ Max Units

1/t

CLCL

1/t

CLCL

SHSL

SLSH

OVSH

SHOX

SLIV

CLCL

Oscillator Frequency (VCC = 2.7 - 4.0V) 0 4.0 MHz

Oscillator Period (VCC = 2.7 - 4.0V) 250.0 ns

Oscillator Frequency (VCC = 4.0 - 6.0V) 0 8.0 MHz

Oscillator Period (VCC = 4.0 - 6.0V) 125.0 ns

SCK Pulse Width High 2.0 t

SCK Pulse Width Low 2.0 t

MOSI Setup to SCK High t

MOSI Hold after SCK High 2.0 t

SCK Low to MISO Valid 10.0 16.0 32.0 ns

= -40°C to 85°C, VCC =

CLCL

Table 21. Minimum Wait Delay after the Chip Erase Instruction

Symbol 3.2V 3.6V 4.0V 5.0V

WD_ERASE

Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location

Symbol 3.2V 3.6V 4.0V 5.0V

WD_PROG

AT90S/LS2323/2343

18 ms 14 ms 12 ms 8 ms

9 ms 7 ms 6 ms 4 ms

1004D–09/01

Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin except RESET

with respect to Ground ..............................-1.0V to VCC + 0.5V

Voltage on RESET

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

with Respect to Ground ....-1.0V to +13.0V

AT90S/LS2323/2343

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Current

and GND Pins................................ 200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)

Symbol Parameter Condition Min Typ Max Units

IL1

IH1

IH2

Input Low Voltage (Except XTAL) -0.5 0.3 V

Input Low Voltage XTAL -0.5 0.1

4.2

2.4

(2)

Input High Voltage (Except XTAL, RESET)0.6 V

Input High Voltage XTAL 0.7 V

Input High Voltage RESET 0.85 V

= 20 mA, VCC = 5V

Output Low Voltage Ports B

Output High Voltage Ports B

Input Leakage Current I/O Pin

= 10 mA, VCC = 3V

= -3 mA, VCC = 5V

= -1.5 mA, VCC = 3V

VCC = 6V, Pin Low (absolute value)

VCC = 6V, Pin High (absolute value)

RRST Reset Pull-up 100.0 500.0 kΩ

I/O

I/O Pin Pull-up 30.0 150.0 kΩ

Power Supply Current AT90S2343

Power Supply Current AT90S2323

Active 4 MHz, V

Idle 4 MHz, V

Power-down 4 MHz

= 3V WDT Enabled

Power-down 4 MHz V

= 3V WDT Disabled

Active 4 MHz, V

Idle 4 MHz, V

Power-down

= 3V WDT Enabled

Power-down

= 3V WDT Disabled

= 3V 3.0 mA

= 3V 1.1 mA

(3)

= 3V 4.0 mA

= 3V 1.0 1.2 mA

(3)

9.0 15.0

<1.0 2.0 µA

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Minimum V

for Power-down is 2V.

(1)

VCC + 0.5 V

0.5

0.4

8.0

25.0

20.0

V V

µA

1004D–09/01

External Clock Drive Waveforms

Figure 38. Waveforms

External Clock Drive

TA = -40°C to 85°C

Symbol Parameter

1/t

CLCL

CHCX

CLCX

CLCH

CHCL

VIH1

VIL1

: 2.7V to 4.0V VCC: 4.0V to 6.0V

Oscillator Frequency 0 4.0 0 10.0 MHz

Clock Period 250.0 100.0 ns

High Time 100.0 40.0 ns

Low Time 100.0 40.0 ns

Rise Time 1.6 0.5 µs

Fall Time 1.6 0.5 µs

UnitsMin Max Min Max

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C

•f where CL = load capacitance, VCC = operating voltage and f = average switch-

L•VCC

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Figure 39. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

20.00

18.00

16.00

14.00

12.00

10.00

(mA)

8.00

6.00

4.00

2.00

0.00

0 1 2 3 4 5 6 7 8 9 1011 12131415

T = 25˚C

Frequency (MHz)

= 2.7V

= 3.0V

= 3.6V

= 3.3V

= 6V

= 5.5V

= 5V

= 4.5V

= 4V

1004D–09/01

Figure 40. Active Supply Current vs. V

ACTIVE SUPPLY CURRENT vs. V

FREQUENCY = 4 MHz

(mA)

2 2.5 3 3.5 4 4.5 5 5.5 6

Figure 41. Active Supply Current vs. V

ACTIVE SUPPLY CURRENT vs. V

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

T = 25˚C

T = 85˚C

(V)

T = 25˚C

(mA)

2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

T = 85˚C

AT90S/LS2323/2343

1004D–09/01

Figure 42. Idle Supply Current vs. Frequency

AT90S/LS2323/2343

IDLE SUPPLY CURRENT vs. FREQUENCY

4.5

3.5

2.5

(mA)

1.5

0.5

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Figure 43. Idle Supply Current vs. V

IDLE SUPPLY CURRENT vs. V

FREQUENCY = 4 MHz

2.5

T = 25˚C

Frequency (MHz)

= 2.7V

= 6V

= 5.5V

= 5V

= 4.5V

= 4V

= 3.6V

= 3.3V

= 3.0V

T = 25˚C

1.5

(mA)

0.5

2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

T = 85˚C

1004D–09/01

Figure 44. Idle Supply Current vs. V

IDLE SUPPLY CURRENT vs. V

DEVICE CLOCKED BY INTERNAL RC OSCILLATOR

0.8

0.7

0.6

0.5

0.4

(mA)

0.3

0.2

0.1

2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

Figure 45. Power-down Supply Current vs. V

POWER DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED

T = 25˚C

T = 85˚C

(µΑ)

2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

T = 70˚C

T = 45˚C

T = 25˚C

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 46. Power-down Supply Current vs. V

POWER DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

180

160

140

120

100

(µΑ)

2 2.5 3 3.5 4 4.5 5 5.5 6

(V)

Figure 47. Watchdog Oscillator Frequency vs. V

T = 85˚C

T = 25˚C

WATCHDOG OSCILLATOR FREQUENCY vs. V

1600

T = 25˚C

1400

1200

1000

800

F (KHz)

600

400

200

2 2.5 3 3.5 4 4.5 5 5.5 6

V (V)

T = 85˚C

1004D–09/01

Note: Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 48. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

120

100

I (µA)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

T = 25˚C

T = 85˚C

V = 5V

V (V)

Figure 49. Pull-up Resistor Current vs. Input Voltage

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

T = 25˚C

T = 85˚C

V = 2.7V

I (µA)

0 0.5 1 1.5 2 2.5 3

AT90S/LS2323/2343

V (V)

1004D–09/01

AT90S/LS2323/2343

Figure 50. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V = 5V

T = 25˚C

I (mA)

0 0.5 1 1.5 2 2.5 3

V (V)

Figure 51. I/O PIn Source Current vs. Output Voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

I (mA)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

T = 25˚C

T = 85˚C

V = 5V

V (V)

T = 85˚C

1004D–09/01

Figure 52. I/O Pin Sink Current vs. Output Voltage

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V = 2.7V

T = 25˚C

T = 85˚C

I (mA)

0 0.5 1 1.5 2

V (V)

Figure 53. I/O Pin Source Current vs. Output voltage

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

T = 25˚C

V = 2.7V

T = 85˚C

I (mA)

0 0.5 1 1.5 2 2.5 3

V (V)

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Figure 54. I/O Pin Input Threshold Voltage vs. V

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

2.5

1.5

Threshold Voltage (V)

0.5

2.7 4.0 5.0

Figure 55. I/O Pin Input Hysteresis vs. V

T = 25˚C

I/O PIN INPUT HYSTERESIS vs. V

0.18

0.16

0.14

0.12

0.1

0.08

Input hysteresis (V)

0.06

0.04

0.02

2.7 4.0 5.0

T = 25˚C

1004D–09/01

AT90S2323/2343 Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

$3F ($5F) SREG I T H S V N Z C page 18

$3E ($5E) Reserved

$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 19

$3C ($5C) Reserved

$3B ($5B) GIMSK -INT0 - - - - - - page 24

$3A ($5A) GIFR -INTF0 page 25

$39 ($59) TIMSK - - - - - -TOIE0- page 25

$38 ($58) TIFR

$37 ($57) Reserved

$36 ($56) Reserved

$35 ($55) MCUCR - -SESM- - ISC01 ISC00 page 26

$34 ($54) MCUSR - - - - - - EXTRF PORF page 23

$33 ($53) TCCR0 - - - - - CS02 CS01 CS00 page 29

$32 ($52) TCNT0 Timer/Counter0 (8 Bits) page 30

$31 ($51) Reserved

$30 ($50) Reserved

$2F ($4F) Reserved

$2E ($4E) Reserved

$2D ($4D) Reserved

$2C ($4C) Reserved

$2B ($4B) Reserved

$2A ($4A) Reserved

$29 ($49) Reserved

$28 ($48) Reserved

$27 ($47) Reserved

$26 ($46) Reserved

$25 ($45) Reserved

$24 ($44) Reserved

$23 ($43) Reserved

$22 ($42) Reserved

$21 ($41) WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 page 31

$20 ($40) Reserved

$1F ($3F) Reserved

$1E ($3E) EEAR - EEPROM Address Register page 32

$1D ($3D) EEDR EEPROM Data Register page 32

$1C ($3C) EECR - - - - - EEMWE EEWE EERE page 33

$1B ($3B) Reserved

$1A ($3A) Reserved

$19 ($39) Reserved

$18 ($38) PORTB - - - PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 35

$17 ($37) DDRB

$16 ($36) PINB - - - PINB4 PINB3 PINB2 PINB1 PINB0 page 36

$15 ($35) Reserved

… Reserved

$00 ($20) Reserved

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

- - - - - -TOV0- page 25

- - - DDB4 DDB3 DDB2 DDB1 DDB0 page 35

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Instruction Set Summary

Mnemonic Operands Description Operation Flags # Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract Two Registers Rd ← Rd − Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd − K Z,C,N,V,H 1

SBIW Rdl, K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl − K Z,C,N,V,S 2

SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd − Rr − C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd − K − C Z,C,N,V,H 1

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1

SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd, K Clear Bit(s) in Register Rd ← Rd • ($FF − K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus R d ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← Z None 3

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd, Rr Compare Rd − Rr Z,N,V,C,H 1

CPC Rd, Rr Compare with Carry Rd − Rr − C Z,N,V,C,H 1

CPI Rd, K Compare Register with Immediate Rd − K Z,N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (R(b) = 1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←=PC + k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←=PC + k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch i f Not Equal i f (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2

1004D–09/01

Instruction Set Summary (Continued)

Mnemonic Operands Description Operation Flags # Clocks

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move between Registers Rd ← Rr None 1

LDI Rd, K Load Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-inc. Rd ← (X), X ← X + 1 None 2

LD Rd, -X Load Indirect and Pre-dec. X ← X − 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, -Y Load Indirect and Pre-dec. Y ← Y − 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-inc. Rd ← (Z), Z ← Z + 1 None 2

LD Rd, -Z Load Indirect and Pre-dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-inc. (X) ← Rr, X ← X + 1 None 2

ST -X, Rr Store Indirect and Pre-dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-inc. (Y) ← Rr, Y ← Y + 1 None 2

ST -Y, Rr Store Indirect and Pre-dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

IN Rd, P In Port Rd ← P None 1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P, b Set Bit in I/O Register I/O(P,b) ← 1 None 2

CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left through Carry Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7) Z,C,N,V 1

ROR Rd Rotate Right through Carry Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit Load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0C1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0N1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0Z1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0I1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0S1

SEV Set Two’s Complement Overflow V ← 1V1

CLV Clear Two’s Complement Overflow V ← 0V1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0T1

SEH Set Half-carry Flag in SREG H ← 1H1

CLH Clear Half-carry Flag in SREG H ← 0H1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

AT90S/LS2323/2343

1004D–09/01

AT90S/LS2323/2343

Ordering Information

Power Supply Speed (MHz) Ordering Code Package Operation Range

2.7 - 6.0V 4 AT90LS2323-4PC AT90LS2323-4SC

AT90LS2323-4PI AT90LS2323-4SI

4.0 - 6.0V 10 AT90S2323-10PC AT90S2323-10SC

AT90S2323-10PI AT90S2323-10SI

2.7 - 6.0V 1 AT90LS2343-1PC AT90LS2343-1SC

AT90LS2343-1PI AT90LS2343-1SI

2.7 - 6.0V 4 AT90LS2343-4PC AT90LS2343-4SC

AT90LS2343-4PI AT90LS2343-4SI

4.0 - 6.0V 10 AT90S2343-10PC AT90S2343-10SC

AT90S2343-10PI AT90S2343-10SI

Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil-

lator has the same nominal clock frequency for all speed grades.

2. In AT90LS2343-1xx, the internal RC oscillator is selected as default MCU clock source (RCEN fuse is programmed) when the device is shipped from Atmel. In AT90LS2343-4xx and AT90S2343-10xx, the default MCU clock source is the clock input pin (RCEN fuse is unprogrammed). The fuse settings can be changed by high voltage serial programming.

8P3 8S2

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

1004D–09/01

Packaging Information

8P3

8P3, 8-lead, Plastic Dual Inline Package (PDIP), 0.300" Wide. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-001 BA

.300 (7.62) REF

10.16(0.400)

9.017(0.355)

7.11(0.280)

6.10(0.240)

5.33(0.210) MAX

Seating Plane

3.81(0.150)

2.92(0.115)

0.356(0.014)

0.203(0.008)

1.78(0.070)

1.14(0.045)

254(0.100) BSC

0.381(0.015)MIN

0.559(0.022)

0.356(0.014)

8.26(0.325)

7.62(0.300)

1.524(0.060)

0.000(0.000)

10.90(0.430) MAX

4.95(0.195)

2.92(0.115)

*Controlling dimension: Inches

REV. A 04/11/2001

AT90S/LS2323/2343

1004D–09/01

8S2

AT90S/LS2323/2343

.020 (.508) .012 (.305)

PIN 1

.050 (1.27) BSC

.212 (5.38) .203 (5.16)

.013 (.330)

.213 (5.41) .205 (5.21)

.080 (2.03) .070 (1.78)

.330 (8.38) .300 (7.62)

1004D–09/01

REF

.035 (.889) .020 (.508)

.004 (.102)

.010 (.254) .007 (.178)

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1004D–09/01/xM

Rainbow Electronics AT90LS2343 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Pin Configuration

Description The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollers

Block Diagram Figure 1. The AT90S/LS2343 Block Diagram

Comparison between AT90S/LS2323 and AT90S/LS2343

Pin Descriptions AT90S/LS2323

Port B (PB2..PB0) Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output

RESET

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

Pin Descriptions AT90S/LS2343

Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output

RESET

CLOCK Clock signal input in external clock mode.

Clock Options

Crystal Oscillator The AT90S/LS2323 contains an inverting amplifier that can be configured for use as an

External Clock The AT90S/LS2343 can be clocked by an external clock signal, as shown in Figure 4, or

Architectural Overview

General-purpose Register File

ALU – Arithmetic Logic Unit

In-System Programmable Flash Program Memory

EEPROM Data Memory The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as

SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized.

Program and Data Addressing Modes

Register Direct, Single Register Rd

Register Direct, Two Registers Rd and Rr

I/O Direct Figure 12. I/O Direct Addressing

Data Direct Figure 13. Direct Data Addressing

Data Indirect with Displacement

Data Indirect Figure 15. Data Indirect Addressing

Constant Addressing Using the LPM Instruction

Indirect Program Addressing, IJMP and ICALL

Relative Program Addressing, RJMP and RCALL

Memory Access and Instruction Execution Timing

I/O Memory The I/O space definition of the AT90S2323/2343 is shown in Table 2.

Reset and Interrupt Handling

Reset Sources The AT90S2323/2343 provides three sources of reset:

Power-on Reset The AT90S2323/2343 is designed for use in systems where it can operate from the

External Reset An external reset is generated by a low level on the RESET

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle

MCU Status Register – MCUSR

Interrupt Handling The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (General

General Interrupt Mask Register – GIMSK

General Interrupt Flag Register – GIFR

Timer/Counter Interrupt Mask Register – TIMSK

Timer/Counter Interrupt FLAG Register – TIFR

External Interrupt The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

MCU Control Register – MCUCR

Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-

Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

Timer/Counter The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter –

Timer/Counter Prescaler Figure 29 shows the Timer/Counter prescaler.

8-bit Timer/Counter0 Figure 30 shows the block diagram for Timer/Counter0.

Timer/Counter0 Control Register – TCCR0

Timer/Counter0 – TCNT0

Figure 31. Watchdog Timer

Watchdog Timer Control Register – WDTCR

EEPROM Read/Write Access

EEPROM Address Register – EEAR

EEPROM Data Register – EEDR

EEPROM Control Register – EECR

Prevent EEPROM Corruption

I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O

Port B Data Register – PORTB

Port B Data Direction Register – DDRB

Port B Input Pins Address – PINB

Port B as General Digital I/O

Alternate Functions of Port B The alternate pin functions of Port B are as follows:

Memory Programming

Program and Data Memory Lock Bits

Fuse Bits in AT90S/LS2323

Fuse Bits in AT90S/LS2343

Signature Bytes All Atmel microcontrollers have a three-byte signature code that identifies the device.

Programming the Flash and EEPROM