Rainbow Electronics AT89S53 User Manual

Features

• Compatible with MCS-51

• 12K Bytes of In-System Reprogrammable Downloadable Flash Memory

– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles

• 4V to 6V Operating Range

• Fully Static Operation: 0 Hz to 24 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Nine Interrupt Sources

• Programmable UART Serial Channel

• SPI Serial Interface

• Low-power Idle and Power-down Modes

• Interrupt Recovery From Power-down

• Programmable Watchdog Timer

• Dual Data Pointer

• Power-off Flag

™

Products

8-bit
Microcontroller
with 12K Bytes
Flash

Description

The AT89S53 is a low-power, high-performance CMOS 8-bit microcomputer with 12K
bytes of downloadable Flash programmable and erasable read only memory. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 instruction set and pinout. The on­chip downloadable Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the
Atmel AT89S53 is a powerful microcomputer which provides a highly-flexible and
cost-effective solution to many embedded control applications.

The AT89S53 provides the following standard features: 12K bytes of downloadable
Flash, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Point­ers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S53 is
designed with static logic for operation down to zero frequency and supports two soft­ware selectable power saving modes. The Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port, and interrupt system to continue functioning. The
Power-down mode saves the RAM contents but freezes the oscillator, disabling all
other chip functions until the next interrupt or hardware reset.

The downloadable Flash can change a single byte at a time and is accessible through
the SPI serial interface. Holding RESET active forces the SPI bus into a serial pro­gramming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.

AT89S53

Rev. 0787D–06/00

1

Pin Configurations

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

(T2) P1.0

(T2 EX) P1.1

P1.2
P1.3

(SS) P1.4
(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2
XTAL1

GND

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

PDIP

TQFP

P1.4 (SS)

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

4443424140393837363534

RST

(T0) P3.4
(T1) P3.5

1
2
3
4
5
6

NC

7
8
9
10
11

1213141516171819202122

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

PLCC

P1.4 (SS)

P1.3

P1.2

P1.1 (T2 EX)

65432

7
8
9
10
11
12

NC

13
14
15
16
17

1819202122232425262728

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P1.0 (T2)NCVCC

1

4443424140

NC

GND

(A8) P2.0

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

(A9) P2.1

(A10) P2.2

(A11) P2.3

P0.3 (AD3)

39

P0.4 (AD4)

38

P0.5 (AD5)

37

P0.6 (AD6)

36

P0.7 (AD7)

35

EA/VPP

34

NC

33

ALE/PROG

32

PSEN

31

P2.7 (A15)

30

P2.6 (A14)

29

P2.5 (A13)

(A12) P2.4

GND

GND

XTAL2

XTAL1

(A8) P2.0

(RD) P3.7

(WR) P3.6

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

AT89S53

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

2

Port 0 can also be configured to be the multiplexed low­order address/data bus during accesses to external
program and data memory. In this mode, P0 has internal
pullups.

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes during program
verification. External pullups are required during program
verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Block Diagram

AT89S53

V

CC

GND

B

REGISTER

RAM ADDR.

REGISTER

P0.0 - P0.7

PORT 0 DRIVERS

RAM

ACC

TMP2 TMP1

PORT 0

LATCH

P2.0 - P2.7

PORT 2 DRIVERS

PORT 2

LATCH

STACK

POINTER

FLASH

PROGRAM
ADDRESS
REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

WATCH

DOG

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

SPI

PORT

INCREMENTER

PROGRAM
COUNTER

DPTR

PROGRAM

LOGIC

3

Some Port 1 pins provide additional functions. P1.0 and
P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively.

Pin Description

Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serves the functions of various special features
of the AT89S53, as shown in the following table.

Port 3 also receives some control signals for Flash pro­gramming and verification.

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift
clock input/output pins as shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

and direction control)

P1.4 SS

P1.5 MOSI (Master data output, slave data input pin

P1.6 MISO (Master data input, slave data output pin

P1.7 SCK (Master clock output, slave clock input pin

(Slave port select input)

for SPI channel)

for SPI channel)

for SPI channel)

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8 bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

P3.3 INT1

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

P3.7 RD

(external interrupt 0)

(external interrupt 1)

(external data memory write strobe)

(external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem­ory. This pin is also the program pulse input (PROG

) during

Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89S53 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

4

AT89S53

AT89S53

/VPP

EA

External Access Enable. EA must be strapped to GND in

enable voltage (V
volt programming is selected.

) during Flash programming when 12-

PP

order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions. This pin also receives the 12-volt programming

XTAL1

Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT89S53 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

T2MOD

XXXXXX00

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

SPCR

000001XX

TH2

00000000

0F7H

0E7H

0D7H

0CFH

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

SPSR

00XXXXXX

TL0

00000000

DP0L

00000000

TL1

00000000

DP0H

00000000

TH0

00000000

DP1L

00000000

TH1

00000000

DP1H

00000000

WCON

00000010

SPDR

XXXXXXXX

PCON

0XXX0000

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

5

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate
effect.

User software should not write 1s to these unlisted loca-

Timer 2 Registers Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap­ture mode or 16-bit auto-reload mode.

Watchdog Control Register The WCON register contains
control bits for the Watchdog Timer (shown in Table 3). The

DPS bit selects one of two DPTR registers available.
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of the
new bits will always be 0.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

Bit

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK =

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

76543210

1 or TCLK = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

CP/RL2

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).

causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

6

AT89S53

AT89S53

Table 3. WCON—Watchdog Control Register

WCON Address = 96H Reset Value = 0000 0010B

PS2 PS1 PS0 reserved reserved DPS WDTRST WDTEN

Bit

Symbol Function

PS2
PS1
PS0

DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the

WDTRST Watchdog Timer Reset. Each time this bit is set to “1” by user software, a pulse is generated to reset the watchdog

WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.

SPI Registers Control and status bits for the Serial Periph­eral Interface are contained in registers SPCR (shown in
Table 4) and SPSR (shown in Table 5). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff­ered for writing and the values in SPDR are not changed by
Reset.

Interrupt Registers The global interrupt enable bit and the
individual interrupt enable bits are in the IE register. In
addition, the individual interrupt enable bit for the SPI is in

76543210

Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16
ms. When all three bits are set to “1”, the nominal period is 2048 ms.

second bank, DP1

timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only.

Dual Data Pointer Registers To facilitate accessing exter-

nal data memory, two banks of 16-bit Data Pointer

Registers are provided: DP0 at SFR address locations

82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON

selects DP0 and DPS = 1 selects DP1. The user should

always initalize the DPS bit to the appropriate value before

accessing the respective Data Pointer register.

Power Off Flag The Power Off Flag (POF) is located at

bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during

power up. It can be set and reset under software control

and is not affected by RESET.
the SPCR register. Two priorities can be set for each of the
six interrupt sources in the IP register.

7

Table 4. SPCR—SPI Control Register

SPCR Address = D5H Reset Value = 0000 01XXB

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0

Bit

Symbol Function

SPIE SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES

SPE SPI Enable. SPI = 1 enables the SPI channel and connects SS

DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

MSTR Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.

CPOL Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

CPHA Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

SPR0
SPR1

76543210

= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.

, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and

P1.7. SPI = 0 disables the SPI channel.

transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.

slave. Please refer to figure on SPI Clock Phase and Polarity Control.

SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the oscillator frequency, F

SPR1SPR0SCK = F

004
0116
1064
1 1 128

divided by

OSC.

, is as follows:

OSC.

Table 5. SPSR—SPI Status Register Data Memory - RAM

SPSR Address = AAH Reset Value = 00XX XXXXB

SPIF WCOL ––––––

Bit

Symbol Function

SPIF SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and

WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer,

76543210

ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing
the SPI data register.

the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF
bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.

Table 6. SPDR—SPI Data Register

SPDR Address = 86H Reset Value = unchanged

SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

Bit

76543210

8

AT89S53

AT89S53

Data Memory - RAM

The AT89S53 implements 256 bytes of RAM. The upper
128 bytes of RAM occupy a parallel space to the Special
Function Registers. That means the upper 128 bytes have
the same addresses as the SFR space but are physically
separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail­able as stack space.

Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) operates from
an independent oscillator. The prescaler bits, PS0, PS1
and PS2 in SFR WCON are used to set the period of the
Watchdog Timer from 16 ms to 2048 ms. The available
timer periods are shown in the following table and the
actual timer periods (at V
nominal.

The WDT is disabled by Power-on Reset and during
Power-down. It is enabled by setting the WDTEN bit in SFR
WCON (address = 96H). The WDT is reset by setting the
WDTRST bit in WCON. When the WDT times out without
being reset or disabled, an internal RST pulse is generated
to reset the CPU.

Table 7. Watchdog Timer Period Selection

= 5V) are within ±30% of the

CC

Table 7. Watchdog Timer Period Selection

1 0 0 256 ms

1 0 1 512 ms

1 1 0 1024 ms

1 1 1 2048 ms

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S53 operate the same way

as Timer 0 and Timer 1 in the AT89C51, AT89C52 and

AT89C55. For further information, see the October 1995

Microcontroller Data Book, page 2-45, section titled,

“Timer/Counters.”

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either

a timer or an event counter. The type of operation is

selected by bit C/T2

Timer 2 has three operating modes: capture, auto-reload

(up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table 8.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every

machine cycle. Since a machine cycle consists of 12 oscil-

lator periods, the count rate is 1/12 of the oscillator

frequency.

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding external

input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples

show a high in one cycle and a low in the next cycle, the

count is incremented. The new count value appears in the

register during S3P1 of the cycle following the one in which

the transition was detected. Since two machine cycles (24

oscillator periods) are required to recognize a 1-to-0 transi-

tion, the maximum count rate is 1/24 of the oscillator

frequency. To ensure that a given level is sampled at least

once before it changes, the level should be held for at least

one full machine cycle.

in the SFR T2CON (shown in Table 2).

WDT Prescaler Bits

Period (nominal)PS2 PS1 PS0

000 16 ms

001 32 ms

010 64 ms

0 1 1 128 ms

Table 8. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-Reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

XX0(Off)

9

Capture Mode

In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a l­to-0 transition at external input T2EX also causes the

Figure 1. Timer 2 in Capture Mode

OSC

T2 PIN

T2EX PIN

÷12

TRANSITION

DETECTOR

C/T2 = 0

C/T2 = 1

TR2

CAPTURE

CONTROL

EXEN2

current value in TH2 and TL2 to be captured into RCAP2H

and RCAP2L, respectively. In addition, the transition at

T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,

like TF2, can generate an interrupt. The capture mode is

illustrated in Figure 1.

TH2 TL2

CONTROL

RCAP2LRCAP2H

EXF2

TF2

OVERFLOW

TIMER 2

INTERRUPT

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 9). Upon reset, the DCEN bit
is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The
overflow also causes the timer registers to be reloaded with
the 16-bit value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If EXEN2 =
1, a 16-bit reload can be triggered either by an overflow or

by a 1-to-0 transition at external input T2EX. This transition

also sets the EXF2 bit. Both the TF2 and EXF2 bits can

generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,

as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer 2

count up. The timer will overflow at 0FFFFH and set the

TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal the values stored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or

underflows and can be used as a 17th bit of resolution. In

this operating mode, EXF2 does not flag an interrupt.

10

AT89S53

Figure 2. Timer 2 in Auto Reload Mode (DCEN = 0)

AT89S53

Table 9. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

––––––T2OE DCEN

Bit

Symbol Function

– Not implemented, reserved for future use.

T2OE Timer 2 Output Enable bit.

DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

76543210

11

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

Figure 4. Timer 2 in Baud Rate Generator Mode

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

OSC

T2 PIN

T2EX PIN

2

÷

TRANSITION

DETECTOR

C/T2 = 0

TR2

C/T2 = 1

CONTROL

TH2 TL2

RCAP2LRCAP2H

EXF2

TIMER 1 OVERFLOW

2

÷

"1"

"1"

TIMER 2

INTERRUPT

"0"

"0"

"0"

"1"

SMOD1

RCLK

16

÷

TCLK

16

÷

Rx

CLOCK

Tx

CLOCK

12

CONTROL

EXEN2

AT89S53

Baud Rate Generator

AT89S53

Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the
baud rates for transmit and receive can be different if Timer
2 is used for the receiver or transmitter and Timer 1 is used
for the other function. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in Fig­ure 4.

The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.

The baud rates in Modes 1 and 3 are determined by Timer
2’s overflow rate according to the following equation.

Modes 1 and 3 Baud Rates

The Timer can be configured for either timer or counter
operation. In most applications, it is configured for timer
operation (CP/T2
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator fre­quency). The baud rate formula is given below.

= 0). The timer operation is different for

Timer 2 Overflow Rate

----------------------------------------------------------- -=

16

2 is in use as a baud rate generator, T2EX can be used as

an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in

the baud rate generator mode, TH2 or TL2 should not be

read from or written to. Under these conditions, the Timer is

incremented every state time, and the results of a read or

write may not be accurate. The RCAP2 registers may be

read but should not be written to, because a write might

overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing the

Timer 2 or RCAP2 registers.

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on

P1.0, as shown in Figure 5. This pin, besides being a regu-

lar I/0 pin, has two alternate functions. It can be

programmed to input the external clock for Timer/Counter 2

or to output a 50% duty cycle clock ranging from 61 Hz to 4

MHz at a 16 MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit

(T2CON.1) must be cleared and bit T2OE (T2MOD.1)

C/T2

must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

Modes 1 and 3

-------------------------------------- -

Baud Rate

where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener­ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer

----------------------------------------------------------------------------------------------=

32 65536 RCAP2H,RCAP2L

Oscillator Frequency

()–[]×

Clock-Out Frequency

In the clock-out mode, Timer 2 rollovers will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer 2

as a baud-rate generator and a clock generator simulta-

neously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from one

another since they both use RCAP2H and RCAP2L.

------------------------------------------------------------------------------------------ -=

4 65536 RCAP2H,RCAP2L

Oscillator Frequency

()–[]×

13

Figure 5. Timer 2 in Clock-Out Mode

Figure 6. SPI Block Diagram

OSCILLATOR

DIVIDER

÷4÷16÷64÷128

SELECT

WCOL

SPIF

SPI STATUS REGISTER

SPI CLOCK (MASTER)

SPR1

SPR0

SPI CONTROL

MSB

8/16-BIT SHIFT REGISTER

READ DATA BUFFER

MSTR
SPE

8

SPIE

SPE

SPI CONTROL REGISTER

8

8

DORD

CLOCK

LOGIC

MSTR

LSB

CLOCK

CPOL

CPHA

SPR1

SPR0

S

M
M

S

S

M

MSTR

PIN CONTROL LOGIC

SPE

DORD

MISO

P1.6

MOSI

P1.5

SCK

1.7

SS

P1.4

14

SPI INTERRUPT

REQUEST

AT89S53

INTERNAL

DATA BU S

AT89S53

UART

The UART in the AT89S53 operates the same way as the
UART in the AT89C51, AT89C52 and AT89C55. For fur­ther information, see the October 1995 Microcontroller
Data Book, page 2-49, section titled, “Serial Interface.”

Serial Peripheral Interface

The serial peripheral interface (SPI) allows high-speed syn­chronous data transfer between the AT89S53 and
peripheral devices or between several AT89S53 devices.
The AT89S53 SPI features include the following:

• Full-duplex, 3-wire Synchronous Data Transfer

• Master or Slave Operation

• 1.5 MHz Bit Frequency (max.)

• LSB First or MSB First Data Transfer

• Four Programmable Bit Rates

• End of Transmission Interrupt Flag

Figure 7. SPI Master-slave Interconnection

MSB LSB

8-BIT SHIFT REGISTER

MASTER

• Write Collision Flag Protection

• Wakeup from Idle Mode (Slave Mode Only)

The interconnection between master and slave CPUs with

SPI is shown in the following figure. The SCK pin is the

clock output in the master mode but is the clock input in the

slave mode. Writing to the SPI data register of the master

CPU starts the SPI clock generator, and the data written

shifts out of the MOSI pin and into the MOSI pin of the

slave CPU. After shifting one byte, the SPI clock generator

stops, setting the end of transmission flag (SPIF). If both

the SPI interrupt enable bit (SPIE) and the serial port inter-

rupt enable bit (ES) are set, an interrupt is requested.

The Slave Select input, SS

individual SPI device as a slave. When SS

the SPI port is deactivated and the MOSI/P1.5 pin can be

used as an input.

There are four combinations of SCK phase and polarity

with respect to serial data, which are determined by control

bits CPHA and CPOL. The SPI data transfer formats are

shown in Figure 8 and Figure 9.

MISO

MISO

MSB LSB

8-BIT SHIFT REGISTER

/P1.4, is set low to select an

/P1.4 is set high,

SLAVE

SPI

CLOCK GENERATOR

Figure 8. SPI transfer Format with CPHA = 0

MOSI MOSI

SCK

SS SS

SCK

V

CC

*Not defined but normally MSB of character just received

15

Figure 9. SPI Transfer Format with CPHA = 1

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL=0)

SCK (CPOL=1)

1 2 3 4 5 6 7 8

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

MSB 6 5 4 3 2

MSB

*

65432

*Not defined but normally LSB of previously transmitted character

Interrupts

The AT89S53 has a total of six interrupt vectors: two exter­nal interrupts (INT0
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.

Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.

Note that Table 10 shows that bit position IE.6 is unimple­mented. In the AT89C51, bit position IE.5 is also
unimplemented. User software should not write 1s to these
bit positions, since they may be used in future AT89
products.

and INT1), three timer interrupts

Figure 10. Interrupt Sources

1 LSB

1 LSB

ET0 IE.1 Timer 0 interrupt enable bit.

EX0 IE.0 External interrupt 0 enable bit.

User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.

Table 10. Interrupt Enable (IE) Register

(MSB)(LSB)

EA

– ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0, no interrupt

– IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit.

ES IE.4 SPI and UART interrupt enable bit.

ET1 IE.3 Timer 1 interrupt enable bit.

EX1 IE.2 External interrupt 1 enable bit.

16

is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.

AT89S53

AT89S53

Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 11. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 12.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi­mum voltage high and low time specifications must be
observed.

Figure 11. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 12. External Clock Drive Configuration

17

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on­chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe­cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution

from where it left off, up to two machine cycles before the

internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that

invokes idle mode should not write to a port pin or to exter-

nal memory.

Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

Power-down Mode

In the power-down mode, the oscillator is stopped and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function Regis­ters retain their values until the power-down mode is
terminated. Exit from power-down can be initiated either by
a hardware reset or by an enabled external interrupt. Reset
redefines the SFRs but does not change the on-chip RAM.
The reset should not be activated before V
its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.

To exit power-down via an interrupt, the external interrupt
must be enabled as level sensitive before entering power­down. The interrupt service routine starts at 16 ms (nomi­nal) after the enabled interrupt pin is activated.

is restored to

CC

Program Memory Lock Bits

The AT89S53 has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the

additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value and holds that value until reset is activated. The

latched value of EA

at that pin in order for the device to function properly.

Once programmed, the lock bits can only be unpro-

grammed with the Chip Erase operations in either the

parallel or serial modes.

must agree with the current logic level

pin

Lock Bit Protection Modes

Program Lock Bits

Protection TypeLB1 LB2 LB3

1 U U U No internal memory lock feature.

2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes

from internal memory. EA
memory (parallel or serial mode) is disabled.

3 P P U Same as Mode 2, but parallel or serial verify are also disabled.

4 P P P Same as Mode 3, but external execution is also disabled.

Notes: 1. U = Unprogrammed

2. P = Programmed

18

AT89S53

(1)(2)

is sampled and latched on reset and further programming of the Flash

AT89S53

Programming the Flash

Atmel’s AT89S53 Flash Microcontroller offers 12K bytes of
in-system reprogrammable Flash Code memory.

The AT89S53 is normally shipped with the on-chip Flash
Code memory array in the erased state (i.e. contents =
FFH) and ready to be programmed. This device supports a
High-Voltage (12V) Parallel programming mode and a Low­Voltage (5V) Serial programming mode. The serial pro­gramming mode provides a convenient way to download
the AT89S53 inside the user’s system. The parallel pro­gramming mode is compatible with conventional third party
Flash or EPROM programmers.

The Code memory array occupies one contiguous address
space from 0000H to 2FFFH.

The Code array on the AT89S53 is programmed byte-by­byte in either programming mode. An auto-erase cycle is
provided with the self-timed programming operation in the
serial programming mode. There is no need to perform the
Chip Erase operation to reprogram any memory location in
the serial programming mode unless any of the lock bits
have been programmed.

In the parallel programming mode, there is no auto-erase
cycle. To reprogram any non-blank byte, the user needs to
use the Chip Erase operation first to erase the entire Code
memory array.

Parallel Programming Algorithm: To program and verify
the AT89S53 in the parallel programming mode, the follow­ing sequence is recommended:

1. Power-up sequence:

Apply power between V

Set RST pin to “H”.

Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait
for at least 10 milliseconds.

2. Set PSEN

ALE pin to “H”

EA pin to “H” and all other pins to “H”.

3. Apply the appropriate combination of “H” or “L” logic

levels to pins P2.6, P2.7, P3.6, P3.7 to select one of
the programming operations shown in the Flash
Programming Modes table.

4. Apply the desired byte address to pins P1.0 to P1.7

and P2.0 to P2.5.

Apply data to pins P0.0 to P0.7 for Write Code
operation.

5. Raise EA

erase or verification.

6. Pulse ALE/PROG

Code memory array, or the lock bits. The byte-write
cycle is self-timed and typically takes 1.5 ms.

pin to “L”

/VPP to 12V to enable Flash programming,

once to program a byte in the

and GND pins.

CC

7. To verify the byte just programmed, bring pin P2.7
to “L” and read the programmed data at pins P0.0 to
P0.7.

8. Repeat steps 3 through 7 changing the address and
data for the entire 12K-byte array or until the end of
the object file is reached.

9. Power-off sequence:

Set XTAL1 to “L”.

Set RST and EA

Turn V

Data Polling: The AT89S53 features DATA Polling to indi­cate the end of a write cycle. During a write cycle in the
parallel or serial programming mode, an attempted read of
the last byte written will result in the complement of the writ­ten datum on P0.7 (parallel mode), and on the MSB of the
serial output byte on MISO (serial mode). Once the write
cycle has been completed, true data are valid on all out­puts, and the next cycle may begin. DATA
begin any time after a write cycle has been initiated.

Ready/Busy

parallel programming mode can also be monitored by the
RDY/BSY
goes High during programming to indicate BUSY
pulled High again when programming is done to indicate
READY.

Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed Code can be read back via
the address and data lines for verification. The state of the
lock bits can also be verified directly in the parallel pro­gramming mode. In the serial programming mode, the state
of the lock bits can only be verified indirectly by observing
that the lock bit features are enabled.

Chip Erase: In the parallel programming mode, chip erase
is initiated by using the proper combination of control sig­nals and by holding ALE/PROG
array is written with all “1”s in the Chip Erase operation.

In the serial programming mode, a chip erase operation is
initiated by issuing the Chip Erase instruction. In this mode,
chip erase is self-timed and takes about 16 ms.

During chip erase, a serial read from any address location
will return 00H at the data outputs.

Serial Programming Fuse: A programmable fuse is avail­able to disable Serial Programming if the user needs
maximum system security. The Serial Programming Fuse
can only be programmed or erased in the Parallel Program­ming Mode.

The AT89S53 is shipped with the Serial Programming
Mode enabled.

power off.

CC

: The progress of byte programming in the

output signal. Pin P3.4 is pulled Low after ALE

pins to “L”.

Polling may

. P3.4 is

low for 10 ms. The Code

19

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of
locations 030H and 031H, except that P3.6 and P3.7 must
be pulled to a logic low. The values returned are as follows:

(030H) = 1EH indicates manufactured by Atmel
(031H) = 53H indicates 89S53

Programming Interface

Every code byte in the Flash array can be written, and the
entire array can be erased, by using the appropriate combi­nation of control signals. The write operation cycle is self­timed and once initiated, will automatically time itself to
completion.

All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.

Serial Downloading

The Code memory array can be programmed using the
serial SPI bus while RST is pulled to V
face consists of pins SCK, MOSI (input) and MISO (output).
After RST is set high, the Programming Enable instruction
needs to be executed first before program/erase operations
can be executed.

An auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need
to first execute the Chip Erase instruction unless any of the
lock bits have been programmed. The Chip Erase opera­tion turns the content of every memory location in the Code
array into FFH.

The Code memory array has an address space of 0000H to
2FFFH.

. The serial inter-

CC

be less than 1/40 of the crystal frequency. With a 24 MHz
oscillator clock, the maximum SCK frequency is 600 kHz.

Serial Programming Algorithm

To program and verify the AT89S53 in the serial program­ming mode, the following sequence is recommended:

1. Power-up sequence:

Apply power between VCC and GND pins.

Set RST pin to “H”.

If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.

2. Enable serial programming by sending the Pro­gramming Enable serial instruction to pin
MOSI/P1.5. The frequency of the shift clock sup­plied at pin SCK/P1.7 needs to be less than the
CPU clock at XTAL1 divided by 40.

3. The Code array is programmed one byte at a time
by supplying the address and data together with the
appropriate Write instruction. The selected memory
location is first automatically erased before new
data is written. The write cycle is self-timed and typ­ically takes less than 2.5 ms at 5V.

4. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be
set low to commence normal operation.

Power-off sequence (if needed):

Set XTAL1 to “L” (if a crystal is not used).

Set RST to “L”.

Turn V

power off.

CC

Either an external system clock is supplied at pin XTAL1 or
a crystal needs to be connected across pins XTAL1 and
XTAL2. The maximum serial clock (SCK) frequency should

20

AT89S53

Serial Programming Instruction

The Instruction Set for Serial Programming follows a 3 byte
protocol and is shown in the following table.

(2)

(2)

Instruction Set

AT89S53

Input Format

Instruction

OperationByte 1 Byte 2 Byte 3

Programming Enable 1010 1100 0101 0011 xxxx xxxx Enable serial programming interface after RST goes

high.

Chip Erase 1010 1100 xxxx x100 xxxx xxxx Chip erase the 12K memory array.

Read Code Memory low addr xxxx xxxx Read data from Code memory array at the selected

A12

A11

01

A9

A8

A10

A13

address. The 6 MSBs of the first byte are the high order
address bits. The low order address bits are in the
second byte. Data are available at pin MISO during the
third byte.

Write Code Memory low addr data in Write data to Code memory location at selected

A12

A11

A10

A9

A8

10

A13

address. The address bits are the 6 MSBs of the first
byte together with the second byte.

Write Lock Bits 1010 1100 xxxx xxxx Write lock bits.

Notes: 1. DATA polling is used to indicate the end of a write cycle which typically takes less than 10 ms at 2.7V.

2. “x” = don’t care.

.

LB1

x x111

LB2

LB3

Set LB1, LB2 or LB3 = “0” to program lock bits.

Flash Parallel Programming Modes

Mode RST PSEN ALE/PROG EA/V

Serial Prog. Modes H h

Chip Erase H L 12V H L L L X X

(1)

(1)

h

P2.6 P2.7 P3.6 P3.7

PP

x

Data I/O

P0.7:0

Address

P2.5:0 P1.7:0

Write (12K bytes) Memory H L 12V L H H H DIN ADDR

Read (12K bytes) Memory H L H 12V L L H H DOUT ADDR

Write Lock Bits: H L 12V H L H L DIN X

Bit - 1 P0.7 = 0 X

Bit - 2 P0.6 = 0 X

Bit - 3 P0.5 = 0 X

Read Lock Bits: H L H 12V H H L L DOUT X

Bit - 1 @P0.2 X

Bit - 2 @P0.1 X

Bit - 3 @P0.0 X

Read Atmel Code H L H 12V L L L L DOUT 30H

Read Device Code H L H 12V L L L L DOUT 31H

Serial Prog. Enable H L 12V L H L H P0.0 = 0 X

Serial Prog. Disable H L 12V L H L H P0.0 = 1 X

Read Serial Prog. Fuse H L H 12V H H L H @P0.0 X

(2)

Notes: 1. “h” = weakly pulled “High” internally.

2. Chip Erase and Serial Programming Fuse require a 10 ms PROG

pulse. Chip Erase needs to be performed first before

reprogramming any byte with a content other than FFH.

3. P3.4 is pulled Low during programming to indicate RDY/BSY.

4. “X” = don’t care

21

Figure 13. Programming the Flash Memory

Figure 15. Flash Serial Downloading

AT89S53

ADDR.

0000H/2FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-24 Mhz

A0 - A7

A8 - A13

P1

P2.0 - P2.5

P2.6

P2.7

P3.6

P3.7

XTAL2 EA

XTAL1

GND

Figure 14. Verifying the Flash Memory

V

P0

ALE

RST

PSEN

+5V

+4.0V to 6.0V

AT89S53

CC

PGM
DATA

PROG

V

PP

INSTRUCTION

INPUT

DATA OUTPUT

CLOCK IN

P1.5/MOSI

P1.6/MISO

P1.7/SCK

XTAL2

3-24 Mhz

V

I H

GND

V

CC

RSTXTAL1

V

I H

ADDR.

0000H/2FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

3-24 Mhz

A0-A7

A8 - A13

AT89S53

P1

P2.0 - P2.5

P2.6
P2.7

P3.6
P3.7

XTAL2 EA

XTAL1

GND

V

P0

ALE

RST

PSEN

CC

+5V

P GM D ATA
(USE 10K
PULLUPS)

V

I H

V

PP

V

I H

22

AT89S53

AT89S53

Flash Programming and Verification Characteristics – Parallel Mode

TA = 0°C to 70°C, VCC = 5.0V ± 10%

Symbol Parameter Min Max Units

V

PP

I

PP

1/t

t

AVGL

t

GHAX

t

DVGL

t

GHDX

t

EHSH

t

SHGL

t

GLGH

t

AVQ V

t

ELQV

t

EHQZ

t

GHBL

t

WC

CLCL

Programming Enable Voltage 11.5 12.5 V

Programming Enable Current 1.0 mA

Oscillator Frequency 3 24 MHz

Address Setup to PROG Low 48t

Address Hold after PROG 48t

Data Setup to PROG Low 48t

Data Hold after PROG 48t

P2.7 (ENABLE) High to V

PP

48t

CLCL

CLCL

CLCL

CLCL

CLCL

VPP Setup to PROG Low 10 µs

PROG Width 1 110 µs

Address to Data Valid 48t

ENABLE Low to Data Valid 48t

Data Float after ENABLE 048t

CLCL

CLCL

CLCL

PROG High to BUSY Low 1.0 µs

Byte Write Cycle Time 2.0 ms

23

Flash Programming and Verification Waveforms – Parallel Mode

Serial Downloading Waveforms

SERIAL CLOCK INPUT

SCK/P1.7

SERIAL DATA INPUT

MOSI/P1.5

SERIAL DATA OUTPUT

MISO/P1.6

7

MSB

MSB

4

6

5

3

2

1

0

LSB

LSB

24

AT89S53

AT89S53

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage ............................................ 6.6V

DC Output Current...................................................... 15.0 mA

DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 6.0V, unless otherwise noted

Symbol Parameter Condition Min Max Units

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

V

IL

V

IL1

V

IH

V

IH1

V

OL

V

OL1

V

OH

Input Low-voltage (Except EA)-0.50.2 V

Input Low-voltage (EA)-0.50.2 V

- 0.1 V

CC

- 0.3 V

CC

Input Hight-voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

Input Hight-voltage (XTAL1, RST) 0.7 V

Output Low-voltage
(Ports 1,2,3)

Output Low-voltage
(Port 0, ALE, PSEN)

Output Hight-voltage
(Ports 1,2,3, ALE, PSEN

(1)

(1)

)

= 1.6 mA 0.5 V

I

OL

= 3.2 mA 0.5 V

I

OL

I

= -60 µA, VCC = 5V ± 10% 2.4 V

OH

I

= -25 µA0.75 VCCV

OH

CC

VCC + 0.5 V

IOH = -10 µA0.9 VCCV

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

V

OH1

Output Hight-voltage
(Port 0 in External Bus Mode)

I

= -300 µA0.75 VCCV

OH

IOH = -80 µA0.9 VCCV

I

IL

I

TL

I

LI

Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA

Input Leakage Current
(Port 0, EA)

0.45 < V

IN

< V

CC

±10 µA

RRST Reset Pull-down Resistor 50 300 KΩ

C

IO

Pin Capacitance Test Freq. = 1 MHz, TA = 25°C10pF

Power Supply Current

I

CC

Power-down Mode

(2)

Notes: 1. Under steady state (non-transient) conditions, IOL

must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum I

per 8-bit port:

OL

Port 0: 26 mA
Ports 1,2, 3: 15 mA

Active Mode, 12 MHz 25 mA

Idle Mode, 12 MHz 6.5 mA

VCC = 6V 100 µA

VCC = 3V 40 µA

Maximum total I
If I

exceeds the test condition, V

OL

for all output pins: 71 mA

OL

may exceed the

OL

related specification. Pins are not guaranteed to sink
current greater than the listed test conditions.

2. Minimum V

for Power-down is 2V.

CC

25

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.

External Program and Data Memory Characteristics

12MHz Oscillator Variable Oscillator

Symbol Parameter

1/t

t

LHLL

t

AVL L

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVI V

t

PLAZ

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVW L

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

t

WHLH

CLCL

Oscillator Frequency 0 24 MHz

ALE Pulse Width 127 2t

Address Valid to ALE Low 43 t

Address Hold after ALE Low 48 t

ALE Low to Valid Instruction In 233 4t

ALE Low to PSEN Low 43 t

PSEN Pulse Width 205 3t

PSEN Low to Valid Instruction In 145 3t

Input Instruction Hold after PSEN 00 ns

Input Instruction Float after PSEN 59 t

PSEN to Address Valid 75 t

Address to Valid Instruction In 312 5t

PSEN Low to Address Float 10 10 ns

RD Pulse Width 400 6t

WR Pulse Width 400 6t

RD Low to Valid Data In 252 5t

Data Hold after RD 00 ns

Data Float after RD 97 2t

ALE Low to Valid Data In 517 8t

Address to Valid Data In 585 9t

ALE Low to RD or WR Low 200 300 3t

Address to RD or WR Low 203 4t

Data Valid to WR Transition 23 t

Data Valid to WR High 433 7t

Data Hold after WR 33 t

RD Low to Address Float 0 0 ns

RD or WR High to ALE High 43 123 t

- 40 ns

CLCL

- 13 ns

CLCL

- 20 ns

CLCL

- 65 ns

CLCL

- 13 ns

CLCL

- 20 ns

CLCL

- 45 ns

CLCL

- 10 ns

CLCL

- 8 ns

CLCL

- 55 ns

CLCL

- 100 ns

CLCL

- 100 ns

CLCL

- 90 ns

CLCL

- 28 ns

CLCL

- 150 ns

CLCL

- 165 ns

CLCL

- 50 3t

CLCL

- 75 ns

CLCL

- 20 ns

CLCL

- 120 ns

CLCL

- 20 ns

CLCL

- 20 t

CLCL

+ 50 ns

CLCL

+ 25 ns

CLCL

UnitsMin Max Min Max

26

AT89S53

External Program Memory Read Cycle

AT89S53

External Data Memory Read Cycle

27

External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol Parameter VCC = 4.0V to 6.0V

Min Max Units

28

1/t

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

CLCL

Oscillator Frequency 0 24 MHz

Clock Period 41.6 ns

High Time 15 ns

Low Time 15 ns

Rise Time 20 ns

Fall Time 20 ns

AT89S53

AT89S53

.

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF

Symbol Parameter 12 MHz Oscillator Variable Oscillator Units

Min Max Min Max

t

XLXL

t

QVXH

t

XHQX

Serial Port Clock Cycle Time 1.0 12t

Output Data Setup to Clock Rising

700 10t

CLCL

Edge

Output Data Hold after Clock Rising

50 2t

CLCL

Edge

CLCL

- 133 ns

- 117 ns

µs

t

XHDX

Input Data Hold after Clock Rising

00ns

Edge

t

XHDV

Clock Rising Edge to Input Data
Val i d

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms

(1)

700 10t

Float Waveforms

(1)

- 133 ns

CLCL

Notes: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measure­ments are made at VIH min. for a logic 1 and VIL max.
for a logic 0.

Notes: 1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V

OH/VOL

level occurs.

29

Notes: 1. XTAL1 tied to GND for ICC (power-down)

2. Lock bits programmed

30

AT89S53

Ordering Information

Speed

(MHz)

24 4.0V to 6.0V AT89S53-24AC

33 4.5V to 5.5V AT89S53-33AC

Power

Supply

4.0V to 6.0V AT89S53-24AI

Ordering Code Package Operation Range

AT89S53-24JC
AT89S53-24PC

AT89S53-24JI
AT89S53-24PI

AT89S53-33JC
AT89S53-33PC

44A
44J
40P6

44A
44J
40P6

44A
44J
40P6

AT89S53

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

= Preliminary Information

Package Type

44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

31

Packaging Information

1.20(0.047) MAX

10.10(0.394)

9.90(0.386)

SQ

12.21(0.478)

11.75(0.458)

SQ

0.75(0.030)

0.45(0.018)

0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0
7

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flatpack (TQFP)
Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AC

.045(1.14) X 30° - 45°

.656(16.7)

SQ

.650(16.5)

.695(17.7)
.685(17.4)

.500(12.7) REF SQ

.022(.559) X 45° MAX (3X)

SQ

.012(.305)
.008(.203)

.630(16.0)
.590(15.0)

.021(.533)
.013(.330)

.043(1.09)
.020(.508)

.120(3.05)

.090(2.29)
.180(4.57)
.165(4.19)

.032(.813)
.026(.660)

.050(1.27) TYP

.045(1.14) X 45°

PIN NO. 1
IDENTIFY

Controlling dimension: millimeters

40P6, 40-lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)

2.07(52.6)

.220(5.59)

SEATING

PLANE

MAX

.161(4.09)
.125(3.18)

.110(2.79)
.090(2.29)

.012(.305)
.008(.203)

2.04(51.8)

1.900(48.26) REF

.065(1.65)

.041(1.04)

.630(16.0)
.590(15.0)

.690(17.5)
.610(15.5)

PIN

1

.566(14.4)
.530(13.5)

.090(2.29)

.005(.127)

.065(1.65)
.015(.381)

.022(.559)
.014(.356)

0

REF

15

MAX

MIN

32

AT89S53

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International:
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e-mail

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http://www.atmel.com

BBS

1-[phone]

© Atmel Corporation 2000.

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0787D–06/00/xM