Rainbow Electronics AT89S52 User Manual

Features

• Compatible with MCS-51

• 8K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

®

Products

8-bit
Microcontroller
with 8K Bytes
In-System

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus­try-standar d 80C51 instru ctio n set an d pino ut. The o n-chip Flash allow s the pro gram
memory to be reprogramme d in -s yste m or by a con ve nti ona l non vo lat il e mem or y pro ­grammer. By combin ing a versat ile 8-bit CPU wi th in-system program mable Flas h on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to co ntinue f unctio ning. T he Po wer-down mode s aves t he RAM con ­tents but freezes the oscillator, disabling all other chip functions until the next interrupt
or hardware reset.

Programmable
Flash

AT89S52

Rev. 1919A-07/01

1

Pin Configurations

PDIP

PLCC

(T2) P1.0

(T2 EX) P1.1

P1.2
P1.3

P1.4
(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2
XTAL1

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

TQFP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

P0.0 (AD0)

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

(RD) P3.7

(WR) P3.6

XTAL2

XTAL1

GND

1

NC

4443424140

(A8) P2.0

(A9) P2.1

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

39
38
37
36
35
34
33
32
31
30
29

(A10) P2.2

(A11) P2.3

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

GND

GND

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

P0.0 (AD0)

P0.1 (AD1)

(A8) P2.0

(A9) P2.1

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

33
32
31
30
29
28
27
26
25
24
23

(A11) P2.3

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

2

AT89S52

Block Diagram

AT89S52

V

CC

GND

B

REGISTER

RAM ADDR.

REGISTER

P0.0 - P0.7

PORT 0 DRIVERS

RAM

ACC

TMP2 TMP1

PORT 0

LATCH

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

WATCH

DOG

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

ISP

PORT

INCREMENTER

PROGRAM

COUNTER

DUAL DPTR

PROGRAM

LOGIC

3

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, e ach pin can sink eight T TL inputs . When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be conf igured to be the multiple xed low­order address/data bus during accesses to external
program and data memory. In this mode, P0 has internal
pullups.

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes during program ve rifica­tion. External pullups are required during program
verification.

Port 1

Port 1 is an 8 -bit bid irect iona l I/O port wi th inte rnal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

P1.5 MOSI (used for In-System Progr amm ing )
P1.6 MISO (used for In-System Progr amm ing )
P1.7 SCK (used for In-System Programming)

Port 2

Port 2 is an 8 -bit bid irect iona l I/O port wi th inte rnal pullu ps.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to

) because of the internal pullups.

IL

clock-out

and direction control)

) because of the internal pullups.

IL

external data memor y th at u se 16-bi t ad dr es se s (MO V X @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-b it bi directi onal I/O po rt with i ntern al pull ups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serv es t he fun ctions of variou s spec ial features
of the AT89S52, as shown in the following table.

Port 3 also receives some control signals for Flash pro­gramming and verification.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 0)
(external interrupt 1)

(external data memory write strobe)

(external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device. This pin drives
High for 96 oscillator pe riods a fter the W atc hdo g ti mes ou t.
The DISRTO bit in SFR AUXR (addre ss 8EH) ca n be used
to disable this feature. In the default state of bit DISRTO,
the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Ena ble ( ALE) is an out put p ulse for latc hing
the low byte of the address du ring accesse s to externa l
memory. This pin is also the program pulse input (PROG
during Flash programmin g.

In normal operation, ALE is emitted at a constant rate of
1/6 the oscil lator frequen cy and may be used for externa l
timing or cloc king purposes. N ote, however, th at one
ALE pulse is skipped during each acces s to external data
memory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is

)

4

AT89S52

AT89S52

weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to exter­nal program memory.

When the AT89S52 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped durin g

each access to external data memory.

EA

/VPP

External Access Enable. EA

must be strapped to GND in

Note, howev er, tha t if lo ck bit 1 is pro gramm ed, EA
internally latched on reset.

EA

should be strapped to VCC for internal program execu-

tions.
This pin also receives the 12-volt programming enable volt-

age (V

) during Flash programming.

PP

XTAL1

Input to the inverting os cillator amp lifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscill ator amplifier.

order to enable the device to fetch cod e from exter nal pro­gram memory locations starting at 0000H up to FFFFH.

Table 1. AT89S52 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

B

00000000

ACC

00000000

will be

0F7H

0E7H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111SP00000111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

RCAP2L

00000000

AUXR1

XXXXXXX0

TL0

00000000

DP0L

00000000

RCAP2H

00000000

TL1

00000000

DP0H

00000000

TL2

00000000

TH0

00000000

DP1L

00000000

TH2

00000000

TH1

00000000

DP1H

00000000

WDTRST

XXXXXXXX

AUXR

XXX00XX0

PCON

0XXX0000

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

5

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke

Table 2. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

76543210

Symbol Function

TF2 Timer 2 overflow flag set b y a Time r 2 overflow and mus t be cle ared b y softw ar e. TF2 will not be se t when eith er RCLK = 1

or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

new features. In th at case, the res et or inactiv e values of
the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 3) for Timer 2. The register pai r (RCAP 2H, RCAP 2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap­ture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

CP/RL2

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enab le . Wh en set, allo ws a captu re o r reload to occur as a resul t of a ne gativ e trans ition on T2 EX if T imer

2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
CP/RL2

Timer or counter select for Timer 2. C/T2 = 0 f or time r fun cti on. C/T2 = 1 for external event counter (falling edge triggered).

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

causes automatic re loa ds to oc c ur w he n Ti me r 2 o verflows or nega tive transitio ns o ccur a t T2EX when EXEN2 = 1. When

either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

6

AT89S52

AT89S52

Table 3a. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00XX0B

Not Bit Addressable

– – – WDIDLE DISRTO – – DISALE

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion
DISALE Disable/Enable ALE

DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is act ive only during a MOVX or MOVC instruction

DISRTO Disable/Enable Reset out

DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only

WDIDLE Disable/Enab le WDT in IDLE mode

WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitat e acces sing bot h
internal and external data memory, two banks o f 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP 1 at 84H-85H. Bit DPS = 0
in SFR AUXR 1 selects DP0 and DPS = 1 selects DP1.
The user should always initial ize the DPS bit to the

appropriate value before accessing the respective Data
Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.

Table 3b. AUXR1: Auxiliar y Regi ste r 1

AUXR1 Address = A2H Reset Value = XXXXXXX0B

Not Bit Addressable

–––– – – –DPS

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion
DPS Data Pointer Register Select

DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H

7

Memory Organization

MCS-51 devices have a separate address space for Pro­gram and Data Memory. Up to 64K bytes each of external
Program and Data Memory can be addressed.

Program Memory

If the EA pin is connec ted to GND, all pr ogram f etches ar e
directed to external memory.

On the AT89S52, if EA
fetches to addresses 0000H through 1FFFH are directed to
internal memory and fetches to addresses 2000H through
FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The
upper 128 byte s occupy a para llel addr ess space to the
Special Function Reg is ter s. T hi s m ean s that the upp er 12 8
bytes have th e s ame addre sse s a s the SF R spac e b ut a re
physically separate from SFR space.

is connected to VCC, program

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU acces ses the upp er 128 bytes
of RAM or th e SFR sp ace. Ins tructions w hich us e direct
addressing access of the SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instru ct ion , wher e R0 co ntai ns 0A0 H, ac ce ss es
the data byte at a ddress 0A0H, rath er than P2 (whos e
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so th e uppe r 128 bytes o f data RAM a re av ail­able as stack space.

8

AT89S52

AT89S52

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 13-bit c ounter an d the Wat chdog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT i s enabled, it will
increment every machine cycle whi le the o scillator i s run­ning. The WDT timeout period is dependent on the external
clock frequenc y. There is no way to disab le the WDT
except through reset (either hardware reset or WDT over­flow reset). When WDT overflows, it will drive an output
RESET HIGH pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to W DTRST to av oid a WDT over­flow. The 13-bit counter overflows when it reach es 8191
(1FFFH), and this wi ll reset the device. When the W DT is
enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the
WDT at least ev ery 8191 ma chine cycles . To reset th e
WDT the user must write 01EH and 0E1H to WDTRST.
WDTRST is a writ e-on ly r egi st er. T he W DT co unt er c anno t
be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST pin. The RESET pulse
duration is 96xTO SC, whe re TOSC= 1/FOS C. To ma ke the
best use of the WDT, it should be serviced in those sec­tions of code that will periodically be executed within the
time required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down mode the osci llato r s top s, whi c h mea ns th e
WDT also stops. While in Power-down mode, the user
does not need to service the WDT. There are tw o methods
of exiting Power-down mode: by a hardware reset or via a
level-activated exter nal inte rrupt whic h is enabl ed prior t o
entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it
normally does whe never the AT89S5 2 is reset. Exitin g
Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabi­lize. When the interrupt is brought high, the interrupt is
serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started
until the interrupt is pulled high. It is suggested that the
WDT be reset during the interrupt service for the interrupt
used to exit Power-down mode.

To ensure that the WDT does not overflow within a few
states of exiting Power-down, it is best to reset the WDT
just before entering Power-down mode.

Before going into the IDLE mode , the WDIDLE bi t in SFR
AUXR is used to d eter mine w het her th e WD T c onti nues t o
count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the de fault s tate. To pr event the WDT
from resetting the AT89S52 while in IDLE m ode, the u ser
should always set up a timer that will periodically exit IDLE,
service the WDT, and reenter IDLE mode.

With WDIDLE bit ena bled, the WDT will stop to count in
IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT89S52 operates the same way as the
UART in the AT89C51 and AT89C52. For further informa­tion on the UART operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Prod­ucts’, then ‘805 1-Archite cture Flash M icrocontr oller’, then
‘Product Overview ’.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way
as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For
further information on the timers’ operation, refer to the
ATMEL Web site (http://www.atmel.com). From the hom e
page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8- bi t regis te rs, T H2 a nd TL2. In the
Timer function, th e TL2 register is incremented e very
machine cycl e. S ince a ma chine cy cle cons ists o f 1 2 os cil­lator periods, the count rate is 1/12 of the oscillator
frequency.

Table 3. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload
0 1 1 16-bi t Capture
1 X 1 Baud Rate Generator
X X 0 (Off)

in the SFR T2CON (shown in Table 2).

9