Rainbow Electronics AT89LV51 User Manual

Features

•

Compatible with MCS-51™ Products

•

4K Bytes of Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

•

2.7V to 6V Operating Range

•

Fully Static Operation: 0 Hz to 12 MHz

•

Three-Level Program Memory Lock

•

128 x 8-Bit Internal RAM

•

32 Programmable I/O Lines

•

Two 16-Bit Timer/Counters

•

Six Interrupt Sources

•

Programmable Serial Channel

•

Low Power Idle and Power Down Modes

Description

The AT89LV51 is a low-voltage, high-performan ce CMOS 8-bit microcomputer with
4K bytes of Flash Programmable and Erasable Read Only Memory. The device is
manufactured us ing Atmel ’s high dens ity nonv olatil e memory te chnolo gy and is com ­patible with the industry standard MCS-51™ instruction set and p inout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven­tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89LV51 is a powerful microcomputer which pro­vides a highly flexible and cost effective solution to many embedded control applica­tions. The AT89LV51 operates at 2.7 volts up to 6.0 volts.

PDIP

(continued)

Pin Configurations

INDEX
CORNER

P1.5
P1.6
P1.7

RST

(RXD) P3.0

(TXD) P3.1
()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

NC

P1.0

1

P1.1

2

P1.2

3

P1.3

4

P1.4

5

P1.5

6
7

TQFP

P1.3

P1.2

424340

41

15

14

XTAL2

()P3.7RD

P1.0

P1.1

16

GND

XTAL1

39

17

NC

38

18

GND

VCC

37

19

(A8) P2.0

P0.1 (AD1)

P0.0 (AD0)

36

35

21

20

(A9) P2.1

(A10) P2.2

P0.2 (AD2)

P0.3 (AD3)

34

33
32

31
30
29
28
27
26
25
24
23

22

(A11) P2.3

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP

NC

ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

INDEX
CORNER

(RXD) P3.0

(TXD) P3.1
()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

P1.4

44

1
2
3
4
5
6
7
8
9
10
11

13

12

()P3.6WR

P1.6
P1.7

8

RST
(RXD) P3.0
(TXD) P3.1

()P3.2INT0
()P3.3INT1

(T0) P3.4
(T1) P3.5

()P3.6WR

()P3.7RD P2.3 (A11)

XTAL2 P2.2 (A10)
XTAL1 P2.1 (A9)

9
10
11
12
13
14
15
16
17
18
19

GND P2.0 (A8)

20

PLCC

NC

P1.0

P1.1

P1.2

P1.4

P1.3

65444

2

1

P1.5
P1.6
P1.7

RST

NC

3

7
8
9
10
11
12
13
14
15
16
17 29

181920 24

()P3.6WR

()P3.7RD

21

XTAL2

22

XTAL1

23

GND

NC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

VCC

P0.0 (AD0)

424340

252827

26

(A9) P2.1

(A8) P2.0

V
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP
ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)

P0.2 (AD2)

P0.1 (AD1)

P0.3 (AD3)

41

39

38
37

36
35
34
33
32
31
30

(A10) P2.2

(A12) P2.4

(A11) P2.3

CC

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

EA/VPP

NC

ALE/PROG
PSEN

P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

8-Bit
Microcontroller
with 4K Bytes
Flash

AT89LV51

0303D-D–12/97

4-45

Block Diagram

4-46

AT89LV51

AT89LV51

The AT89LV51 provides the following standard features:
4K bytes of Flash, 128 b ytes of RAM , 32 I/O lines, two 16­bit timer/coun ters, a fiv e ve ctor two- leve l in terrupt arc hitec ­ture, a full duplex serial port, on-chip oscillator and clock
circuitry. In addition, the AT89LV51 is designed with static
logic for operation down to zero frequency an d supports
two software select able power saving mo des. The Idle
Mode stops the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue
functioning. The Power Down Mode saves the RAM con­tents but freezes the os cillato r dis ablin g all othe r chip func ­tions until the next hardware reset.

Pin Description

V

CC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 may also be configured to be the multiplexed low­order address/data bus during accesses to ex ternal pro­gram and data memory . In this m ode P0 ha s int ernal pul­lups.

Port 0 also rece ives th e code by tes dur ing Fla sh prog ram­ming, and outputs the code bytes during program verifica­tion. External pu llups are requ ired dur ing pro gram ver ifica­tion.

Port 1

Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2

Port 2 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs ,
Port 2 pins that are externally being pulled low will source
current (I

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addre sses ( MOVX @
DPTR). In this ap plication it uses strong internal pull ups

) because of the internal pullups.

IL

) because of the internal pullups.

IL

when emitting 1s. During accesses to external data mem­ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89LV51 as listed below:

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

Port 3 also receives some control signals for Flash pro­gramming and verification.

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG

) during Flash

programming.
In normal operation ALE is emitted at a constant rate of 1/6

the oscillator fr equen cy, and ma y be us ed for ext ernal tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external Data Mem­ory.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89LV51 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

4-47

EA

/V

PP

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA

will be

internally latched on reset.

should be strapped to VCC for internal program execu-

EA
tions.

This pin also receives the 12-volt programming enable volt­age (V

) during Flash programming, when 12-volt pro-

PP

gramming is selected.

XTAL1

Input to the inverting os cillator ampl ifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addre sses are occupi ed, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke
new features. In th at case, th e reset or inac tive valu es of
the new bits will always be 0.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89LV51 operate the same
way as Timer 0 and Timer 1 in the AT89C51.

Table 1.

AT89LV51 SFR Map and Reset Values

0F8H 0FFH

0F0H B

00000000

0E8H 0EFH

0E0H ACC

0D8H 0DFH

0D0H PSW

0C8H T2CON

0C0H 0C7H

0B8H IP

0B0H P3

0A8H IE

0A0H P2

98H SCON

90H P1

88H TCON

80H P0

00000000

00000000

00000000

XX000000

11111111

0X000000

11111111

00000000

11111111

00000000

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

TH0

00000000

TH2

00000000

TH1

00000000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4-48

AT89LV51

AT89LV51

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, resp ectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi­mum voltage high and low time specifications must be
observed

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on­chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe­cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any en abled
interrupt or by a hardware reset.

It should be noted t hat when id le is termi nated by a hard­ware reset, the devi ce normally r esumes prog ram execu­tion, from where it le ft off, up t o tw o machi ne c ycles befo re
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one t hat writes to a port pin or to external
memory.

Figure 1.

Note: C1, C2 = 30 pF ± 10 pF for Crystals

Figure 2.

Oscillator Connections

C2

C1

= 40 pF ± 10 pF for Ceramic Resonators

XTAL2

XTAL1

GND

External Clock Drive Configuration

NC

EXTERNAL

OSCILLATOR

SIGNAL

XTAL2

XTAL1

GND

Power Do wn Mode

In the power down mode the oscillator is stopped, and the
instruction t hat invo kes po wer down is th e last instru ction
executed. The on-chip RAM and Special Function Regis­ters retain their values until the power d own m ode is ter mi­nated. The only exit fr om power do wn is a hard ware reset .
Reset redefines the SFRs but does not change the on-c hip
RAM. The reset should not be activated before V

CC

is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta­bilize.

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Po w er Down Internal 0 0 Data Data Data Data
Po w er Down External 0 0 Float Data Data Data

4-49