Rainbow Electronics AT89LP214 User Manual
Features
• 8-bit Microcontroller Compatible with MCS
• Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
• Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Data Retention: Minimum 10 Years
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
• Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs (AT89LP213 only)
– Enhanced UART with Automatic Address Recognition and Framing Error
Detection (AT89LP214 only)
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
• Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
• I/O and Packages
– Up to 12 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 14-lead TSSOP or PDIP
• Operating Conditions
– 2.4V to 5.5V V
–-40° C to 85°C Temperature Range
Voltage Rang e
CC
®
51 Products
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP213
AT89LP214
Preliminary
1. Description
The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller
with 2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel's high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions
need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they
3538A–MICRO–7/06
have bytes to execute, and most of the remaining instructions require only one additional clock.
The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can
deliver only 4 MIPS at the same current consumption. Conversely, at the same throughput as
the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces
power consumption.
The AT89LP213/214 provides the following standard features: 2K bytes of In-System Programmable Flash memory, 128 bytes of RAM, up to 12 I/O lines, two 16-bit timer/counters, two PWM
outputs (AT89LP213 only), a programmable watchdog timer, a full duplex serial port
(AT89LP214 only), a serial peripheral interface, an internal RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system.
The two timer/counters in the AT89LP213/214 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters on the AT89LP213 may independently
drive a pulse width modulation output.
The I/O ports of the AT89LP213/214 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the
ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt
using the general-purpose interrupt interface. The I/O pins of the AT89LP213/214 tolerate voltages higher than the device’s own power supply, up to 5.5V. When the device is supplied at
2.4V and all I/O ports receive 5.5V, the total back flowing current an all I/Os is less than 100 µA.
2. Pin Configuration
2.1 AT89LP213: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
(INT0/XTAL1) P3.2
2.2 AT89LP214: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
(INT0/XTAL1) P3.2
GND
(GPI2) P1.2
(T0) P3.4
GND
(GPI2) P1.2
(RxD) P3.0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
14
P1.6 (MISO/GPI6)
13
P1.4 (SS/GPI4)
12
P1.1 (AIN1/GPI1)
11
P1.0 (AIN0/GPI0)
10
VCC
9
P3.5 (T1)
8
P3.3 (XTAL2/CLKOUT/INT1)
14
P1.6 (MISO/GPI6)
13
P1.4 (SS/GPI4)
12
P1.1 (AIN1/GPI1)
11
P1.0 (AIN0/GPI0)
10
VCC
9
P3.1 (TxD)
8
P3.3 (XTAL2/CLKOUT/INT1)
2
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
3. Pin Description
Table 3-1. AT89LP213 Pin Description
Pin Symbol Type Description
I/O
1P1.5
2P1.7
3P1.3
4GND IGround
5P1.2
I/O
I/O
I/O
I/O
I/OIP1.2: User-configurable I/O Port 1 bit 2.
P1.5: User-configurable I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as
slave, this pin is an input.
I
GPI5: General-purpose Interrupt input 5.
P1.7: User-configurable I/O Port 1 bit 7.
SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is
an input.
I
GPI7: General-purpose Interrupt input 7.
P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled).
I
I
I
: External Active-Low Reset input (if Reset Fuse is enabled. See “External Reset” on page 15).
RST
GPI3: General-purpose Interrupt input 3.
DCL: Serial Clock input for On-chip Debug Interface when OCD is enabled.
GPI2: General-purpose Interrupt input 2.
AT89LP213/214 [Preliminary]
6P3.4
7P3.2
8P3.3
9P3.5
10 VDD I Supply Voltage
11 P1.0
12 P1.1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3.4: User-configurable I/O Port 3 bit 4.
T0: Timer/Counter 0 External Input or PWM Output.
P3.2: User-configurable I/O Port 3 bit 2.
I
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as
a port pin if the internal RC oscillator is selected as the clock source.
DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC
oscillator is selected as the clock source.
P3.3: User-configurable I/O Port 3 bit 3.
O
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal
RC oscillator is selected as the clock source.
O
CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the
internal clock divided by 2.
DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external
clock is selected as the clock source.
P3.5: User-configurable I/O Port 3 bit 5.
T1: Timer/Counter 1 External input or PWM output.
P1.0: User-configurable I/O Port 1 bit 0.
I
AIN0: Analog Comparator Positive input.
I
GPI0: General-purpose Interrupt input 0.
P1.1: User-configurable I/O Port 1 bit 1.
I
AIN1: Analog Comparator Negative input.
I
GPI1: General-purpose Interrupt input 1
13 P1.4
14 P1.6
3538A–MICRO–7/06
I/O
I/O
I/O
P1.4: User-configurable I/O Port 1 bit 4.
I
SS
: SPI slave select input.
I
GPI4: General-purpose Interrupt input 4.
P1.6: User-configurable I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured
as slave, this pin is an output.
I
GPI6: General-purpose Interrupt input 6.
3
Table 3-2. AT89LP214 Pin Description
Pin Symbol Type Description
1P1.5
2P1.7
I/O
I/O
I/O
I/O
P1.5: User-configurable I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as
slave, this pin is an input.
I
GPI5: General-purpose Interrupt input 5.
P1.7: User-configurable I/O Port 1 bit 7.
SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is
an input.
I
GPI7: General-purpose Interrupt input 7.
I/O
3P1.3
4GND IGround
5P1.2
6P3.0
7P3.2
8P3.3
9P3.1
10 VDD I Supply Voltage
I/OIP1.2: User-configurable I/O Port 1 bit 2.
I/OIP3.0: User-configurable I/O Port 3 bit 0.
I/O
I/O
I/O
I/O
I/O
P1.3: User-configurable I/O Port 1 bit 3 (if Reset Fuse is disabled).
I
I
I
I
O
O
O
: External Active-Low Reset input (if Reset Fuse is enabled. See “External Reset” on page 15).
RST
GPI3: General-purpose Interrupt input 3.
DCL: Serial Clock input for On-chip Debug Interface.
GPI2: General-purpose Interrupt input 2.
RXD: Serial Port Receiver input.
P3.2: User-configurable I/O Port 3 bit 2.
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits. It may be used as
a port pin if the internal RC oscillator is selected as the clock source.
DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the internal RC
oscillator is selected as the clock source.
P3.3: User-configurable I/O Port 3 bit 3.
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the internal
RC oscillator is selected as the clock source.
CLKOUT: When the internal RC oscillator is selected as the clock source, may be used to output the
internal clock divided by 2.
DDA: Serial Data input/output for On-chip Debug Interface when OCD is enabled and the external clock
is selected as the clock source.\
P3.1: User-configurable I/O Port 3 bit 1.
TXD: Serial Port Transmitter output.
11 P1.0
12 P1.1
13 P1.4
14 P1.6
4
I/O
I/O
I/O
I/O
I/O
P1.0: User-configurable I/O Port 1 bit 0.
I
AIN0: Analog Comparator Positive input.
I
GPI0: General-purpose Interrupt input 0.
P1.1: User-configurable I/O Port 1 bit 1.
I
AIN1: Analog Comparator Negative input.
I
GPI1: General-purpose Interrupt input 1
P1.4: User-configurable I/O Port 1 bit 4.
I
I
I
: SPI slave select input.
SS
GPI4: General-purpose Interrupt input 4.
P1.6: User-configurable I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When configured
as slave, this pin is an output.
GPI6: General-purpose Interrupt input 6.
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
4. Block Diagram
AT89LP213/214 [Preliminary]
Figure 4-1. AT89LP213 Block Diagram
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Por t 3
Configurable I/O
Por t 1
Configurable I/O
General-purpose
Interrupt
CPU Clock
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
Configurable
Oscillator
Crystal or
Resonator
Figure 4-2. AT89LP214 Block Diagram
Single Cycle
8051 CPU
2KB Flash
128 Bytes
RAM
Por t 3
Configurable I/O
Por t 1
Configurable I/O
General-purpose
Interrupt
CPU Clock
UART
SPI
Timer 0
Timer 1
Analog
Comparator
Watchdog
Timer
On-Chip
RC Oscillator
Configurable
Oscillator
Crystal or
Resonator
3538A–MICRO–7/06
5
5. Comparison to Standard 8051
The AT89LP213/214 is part of a family of devices with enhanced features that are fully binary
compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments,
and pin alternate functions are identical to Atmel's existing standard 8051 products. However,
due to the high performance nature of the device, some system behaviors are different from
those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from
the standard 8051 are outlined in the following paragraphs.
5.1 System Clock
The CPU clock frequency equals the external XTAL1 frequency. The oscillator is no longer
divided by 2 to provide the internal clock, and x2 mode is not supported.
5.2 Instruction Execution with Single-cycle Fetch
The CPU fetches one code byte from memory every clock cycle instead of every six clock
cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer
executes instructions in 12 to 48 clock cycles. Each instruction executes in only 1 to 4 clock
cycles. See “Instruction Set Summary” on page 59 for more details.
5.3 Interrupt Handling
The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In
order for an interrupt to be serviced at the end of an instruction, its flag needs to have been
latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of
the previous instruction if the current instruction executes in only a single clock cycle.
5.4 Timer/Counters
5.5 Serial Port
The external interrupt pins, INT0
every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response,
this leads to a higher maximum rate of incidence for the external interrupts.
By default the Timer/Counters is incremented at a rate of once per clock cycle. This compares to
once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the increment rate. The TPS bits in the CLKREG SFR control the
prescaler (Table 9-2 on page 13). Setting TPS = 1011B will cause the timers to count once every
12 clocks.
The external Timer/Counter pins, T0 and T1, are sampled at every clock cycle instead of once
every 12 clock cycles. This increases the maximum rate at which the Counter modules may
function.
The baud rate of the UART in Mode 0 is 1/2 the clock frequency, compared to 1/12 the clock frequency in the standard 8051; and output data is only stable around the rising edge of the serial
clock. In should also be noted that when using Timer 1 to generate the baud rate in Mode 1 or
Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain
the same baud rate in the AT89LP214 while running at the same frequency as a standard 8051,
the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to
facilitate longer time-out periods for generating low baud rates.
and INT1, are sampled at every clock cycle instead of once
6
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
5.6 Watchdog Timer
The Watchdog Timer in AT89LP213/214 counts at a rate of once per clock cycle. This compares
to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time
base for all timers and reduce the counting rate.
5.7 I/O Ports
The I/O ports of the AT89LP213/214 may be configured in four different modes. By default all
the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all
ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must
be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs. The user can also
configure the ports to start in quasi-bidirectional mode by disabling the Tristate-Port User Fuse.
When this fuse is disabled, P1M0 and P3M0 will reset to 00h instead of FFh and the ports will be
weakly pulled high.
5.8 Reset
The RST pin of the AT89LP213/214 is active-low as compared with the active high reset in the
standard 8051. In addition, the RST
minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.
AT89LP213/214 [Preliminary]
pin is sampled every clock cycle and must be held low for a
6. Memory Organization
The AT89LP213/214 uses a Harvard Architecture with separate address spaces for program
and data memory. The program memory has a regular linear address space with support for up
to 64K bytes of directly addressable application code. The data memory has 128 bytes of internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP213/214 does not
support external data memory or external program memory.
6.1 Program Memory
The AT89LP213/214 contains 2K bytes of on-chip In-System Programmable Flash memory for
program storage. The Flash memory has an endurance of at least 10,000 write/erase cycles and
a minimum data retention time of 10 years. The reset and interrupt vectors are located within the
first 59 bytes of program memory (refer to Table 12-1 on page 19). Constant tables can be allocated within the entire 2K program memory address space for access by the MOVC instruction.
The AT89LP213/214 does not support external program memory.
Figure 6-1. Program Memory Map
007F
User Signature Array
0040
001F
Atmel Signature Array
0000
07FF
3538A–MICRO–7/06
Program Memory
0000
7
A map of the AT89LP213/214 program memory is shown in Figure 6-1. In addition to the 2K
code space from 0000h to 07FFh, the AT89LP213/214 also supports a 64-byte User Signature
Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fashion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While
SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array
is mapped to addresses 0040h to 007Fh and the Atmel Signature Array is mapped to addresses
0000h to 001Fh. SIGEN must be cleared before using MOVC to access the code memory.
The Atmel Signature Array is initialized with the Device ID in the factory. The User Signature
Array is available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array; however, reads are
always allowed.
6.2 Data Memory
Table 6-1.
AUXR1 = A2H Reset Value = XXXX 0XXXB
Not Bit Addressable
Bit76543210
The AT89LP213/214 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O
memory mapped into a single 8-bit address space. The 128 bytes of data memory may be
accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128
bytes of I/O memory reside in the upper 128 byte address space (Figure 6-2). The I/O memory
can only be accessed through direct addressing and contains the Special Function Registers
(SFRs). Indirect accesses to the upper 128 byte addresses will return invalid data. The lowest
32 bytes of data memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits
(PSW.3 and PSW.4) select which register bank is in use. Instructions using register addressing
will only access the currently specified bank. The AT89LP213/214 does not support external
data memory.
Figure 6-2. Data Memory Map
FFH
AUXR1 – Auxiliary Register 1
––––SIGEN–––
Accessible
UPPER
128
80H
7F H
LOWER
128
0
8
AT89LP213/214 [Preliminary]
By Direct
Addressing
Only
Accessible
By Direct
and Indirect
Addressing
Only
Special Function
Registers
Ports
Status and Control Bits
Timers
Registers
Stack Pointer
Accumulator
(Etc.)
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
7. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 7-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
Table 7-1. AT89LP213/214 SFR Map and Reset Values
89ABCDEF
0F8H 0FFH
0F0H
0E8H
0E0H
0D8H 0DFH
0D0H
0C8H
0C0H P1M0
0B8H
0B0H
0A8H
0A0H AUXR1
98H
90H
88H
80H
Notes: 1. All SFRs in the left-most column are bit-addressable.
B
0000 0000
SPSR
000x x000
ACC
0000 0000
PSW
0000 0000
IP
x000 0000
P3
xx11 1111
IE
0000 0000
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
01234567
2. Reset value is xx11 1111B when Tristate-Port Fuse is enabled and xx00 0000B when disabled.
SPCR
0000 0000
SADEN
0000 0000
SADDR
0000 0000
SBUF
xxxx xxxx
TCONB
0010 0100
TMOD
0000 0000
SP
0000 0111
SPDR
xxxx xxxx
(2)
xxxx 0xxx
GPMOD
0000 0000
RL0
0000 0000
TL0
0000 0000
DPL
0000 0000
P1M1
xx00 0000
GPLS
0000 0000
RL1
0000 0000
TL1
0000 0000
DPH
0000 0000
GPIEN
0000 0000
RH0
0000 0000
TH0
0000 0000
GPIF
0000 0000
RH1
0000 0000
TH1
0000 0000
(2)
P3M0
WDTRST
(write-only)
P3M1
xx00 0000
IPH
x000 0000
WDTCON
0000 x000
ACSR
xx00 0000
CLKREG
0000 x000
PCON
0000 0000
0F7H
0EFH
0E7H
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
3538A–MICRO–7/06
9
8. Enhanced CPU
The AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance
is due to two factors. First, the CPU fetches one instruction byte from the code memory every
clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions
in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A simple example is shown in Figure 8-1.
The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it
has bytes to execute. The majority of instructions in the AT89LP213/214 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See “Instruction Set Summary” on
page 59 for more detailed information on individual instructions. Figures 8-2 and 8-3 show
examples of 1- and 2-byte instructions.
Figure 8-1. Parallel Instruction Fetches and Executions
T
n
T
System Clock
th
Instruction
(n+1)
n
th
Instruction
Fetch Execute
Fetch Execute
(n+2)th Instruction
Figure 8-2. Single-cycle ALU Operation (Example: INC R0)
T
1
System Clock
Total Execution Time
Register Operand Fetch
n+1
T
T
n+2
Fetch
2
T
3
10
ALU Operation Execute
Result Write Back
Fetch Next Instruction
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data)
System Clock
Total Execution Time
Fetch Immediate Operand
ALU Operation Execute
Result Write Back
Fetch Next Instruction
8.1 Restrictions on Certain Instructions
The AT89LP213/214 is an economical and cost-effective member of Atmel's growing family of
microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the
MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However,
there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such
that the destination address falls within the physical program memory space of the device, which
is 2K for the AT89LP213/214. This should be the responsibility of the software programmer. For
example, LJMP 7E0H would be a valid instruction, whereas LJMP 900H would not.
T
1
T
2
T
3
8.1.1 Branching Instructions
The LCALL, LJMP, ACALL, AJMP, SJMP, and JMP @A+DPTR unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (locations 000H to 7FFH for the AT89LP213/214). Violating the physical space limits may cause
unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ
conditional branching instructions, the same previous rule applies. Again, violating the memory
boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 8051 family architecture have been preserved.
8.1.2 MOVX-related Instructions, Data Memory
The AT89LP213/214 contains 128 bytes of internal data memory. RAM accesses to addresses
above 7FH will return invalid data. Furthermore, the stack depth is limited to 128 bytes, the
amount of available RAM. The Stack Pointer should not be allowed to point to locations above
7FH. External DATA memory access is not supported in this device, nor is external PROGRAM
memory execution. Therefore, no MOVX [...] instructions should be included in the program.
A typical 8051 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the user to know the physical features
and limitations of the device being used and to adjust the instructions used accordingly.
3538A–MICRO–7/06
11
9. System Clock
The system clock is generated directly from one of three selectable clock sources. The three
sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The
clock source is selected by the Clock Source User Fuses as shown in Table 9-1. No internal
clock division is used to generate the CPU clock from the system clock. See “User Configuration
Fuses” on page 71.
Table 9-1. Clock Source Settings
Clock Source
Fuse 1
9.1 Crystal Oscillator
When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and
XTAL2 for connection to an external quartz crystal or ceramic resonator. When using the crystal
oscillator, P3.2 and P3.3 will have their inputs and outputs disabled. When using the crystal
oscillator, XTAL2 should not be used to drive a board-level clock without a buffer.
9.2 External Clock Source
The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly
by the clock source. XTAL2 may be left unconnected, used as P3.3 I/O, or configured to output
a divided version of the system clock.
9.3 Internal RC Oscillator
The AT89LP213/214 has an internal RC oscillator tuned to 8.0 MHz ±2.5%. When enabled as
the clock source, XTAL1 and XTAL2 may be used as P3.2 and P3.3 respectively. XTAL2 may
also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted by changing the RC Adjust Fuses. (See “User Configuration Fuses” on
page 71).
Clock Source
Fuse 0 Selected Clock Source
0 0 Crystal Oscillator
01Reserved
1 0 External Clock on XTAL1
1 1 Internal 8 MHz RC Oscillator
9.4 System Clock Out
When the AT89LP213/214 is configured to use either an external clock or the internal RC oscillator, a divided version of the system clock may be output on XTAL2 (P3.3). The Clock Out
feature is enabled by setting the COE bit in CLKREG. The two CDV bits determine the clock
divide ratio. For example, setting COE = “1” and CDIV = “00” when using the internal oscillator
will result in a 3.950 MHz (±5%) clock output on P3.3. P3.3 must be configured as an output in
order to use the clock out feature.
12
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
Table 9-2.
CLKREG = 8FH Reset Value = 0000 0000B
Not Bit Addressable
Bit76543210
Symbol Function
TPS3
TPS2
TPS1
TPS0
CDV1
CDV0
COE
CLKREG – Clock Control Register
TPS3 TPS2 TPS1 TPS0 – CDV1 CDV0 COE
Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The prescaler
is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value stored in the
TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycles (TPS = 0000B). To
configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to 1011B.
Clock Out Division. Determines the frequency of the clock output relative to the system clock.
CDIV1
00f/2
01f/4
10f/8
11f/16
Clock Out Enable. Set COE to output a divided version of the system clock on XTAL2 (P3.3). The internal RC oscillator
or external clock source must be selected in order to use this feature.
CDIV0 Clock Out Frequency
10. Reset
During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the
program starts execution from the Reset Vector, 0000H. The AT89LP213/214 has five sources
of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset.
10.1 Power-on Reset
A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level is
nominally 1.4V. The POR is activated whenever V
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A
power-on sequence is shown in Figure 10-1 on page 14. When V
Reset threshold voltage V
ization sequence completes, the start-up timer determines how long the device is kept in POR
after V
POR threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The
internally generated reset can be extended beyond the power-on period by holding the RST
low longer than the time-out.
is below the detection level. The POR cir-
CC
reaches the Power-on
CC
, an initialization sequence lasting t
POR
rise. The POR signal is activated again, without any delay, when VCC falls below the
CC
is started. When the initial-
POR
pin
3538A–MICRO–7/06
13
Figure 10-1. Power-on Reset Sequence (BOD Disabled)
V
CC
V
POR
t
POR
+ t
SUT
V
POR
TIME-OUT
RST
(RST Tied to VCC)
INTERNAL
RESET
RST
INTERNAL
RESET
(RST Controlled Externally)
t
RHD
V
RH
If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until
after V
reaches the BOD threshold voltage V
CC
as shown in Figure 10-2. However, if this
BOD
event occurs prior to the end of the initialization sequence, the timer must first wait for that
sequence to complete before counting.
Figure 10-2. Power-on Reset Sequence (BOD Enabled)
V
BOD
t
SUT
V
CC
TIME-OUT
t
POR
V
POR
RST
(RST Tied to VCC)
INTERNAL
RESET
V
RH
t
RHD
INTERNAL
RESET
Note: t
RST
is approximately 92 µs ± 5%.
POR
(RST Controlled Externally)
The start-up timer delay is user configurable with the Start-up Time User Fuses and depends on
the clock source (Table 10-1). The start-up delay should be selected to provide enough settling
time for V
and the selected clock source. The Start-Up Time fuses also control the length of
CC
the start-up time after a Brown-out Reset or when waking up from Power-down during internally
timed mode.
14
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
Table 10-1. Start-up Timer Settings
AT89LP213/214 [Preliminary]
10.2 Brown-out Reset
The AT89LP213/214 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is
nominally 2.2V. The purpose of the BOD is to ensure that if V
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. A BOD sequence is shown in Figure 10-3. When V
trigger level V
trigger level, the start-up timer releases the internal reset after the specified time-out period has
expired (Table 10-1). The Brown-out Detector must be enabled by setting the BOD Enable Fuse.
(See “User Configuration Fuses” on page 71).
SUT Fuse 1 SUT Fuse 0 Clock Source t
00
01
10
11
, the internal reset is immediately activated. When VCC increases above the
BOD
Internal RC/External Clock 16 µs
Crystal Oscillator 1024 µs
Internal RC/External Clock 512 µs
Crystal Oscillator 2048 µs
Internal RC/External Clock 1024 µs
Crystal Oscillator 4096 µs
Internal RC/External Clock 4096 µs
Crystal Oscillator 16384 µs
fails or dips while executing at
CC
decreases to a value below the
CC
SUT (±
5%)
CC
10.3 External Reset
Figure 10-3. Brown-out Detector Reset
V
V
CC
V
POR
BOD
t
SUT
TIME-OUT
INTERNAL
RESET
The P1.3/RST pin can function as either an active-LOW reset input or as a digital general purpose I/O, P1.3. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input
function on P1.3. (See “User Configuration Fuses” on page 71). When cleared, P1.3 may be
used as an input or output pin. When configured as a reset input, the pin must be held low for at
least two clock cycles to trigger the internal reset.
Note: During a power-up sequence, the fuse selection is always overridden and therefore the pin will
always function as a reset input. An external circuit connected to this pin should not hold this
pin LOW during a power-on sequence as this will keep the device in reset until the pin transitions high. After the power-up delay, this input will function either as an external reset input or
as a digital input as defined by the fuse bit. Only a power-up reset will temporarily override the
selection defined by the reset fuse bit. Other sources of reset will not override the reset fuse bit.
P1.3/RST
external reset pin is held low. When the reset pin is disabled by the fuse, ISP may only be entered
by pulling P1.3 low during power-up.
also serves as the In-System Programming (ISP) enable. ISP is enabled when the
3538A–MICRO–7/06
15
10.4 Watchdog Reset
When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.
Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the
watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times
out. See “Programmable Watchdog Timer” on page 57 for details on the operation of the
Watchdog.
10.5 Software Reset
The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset
sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTCON. See “Software Reset” on page 58 for more information on software reset.
11. Power Saving Modes
The AT89LP213/214 supports two different power-reducing modes: Idle and Power-down.
These modes are accessed through the PCON register.
11.1 Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The timers, UART, SPI, and GPI blocks continue to function during Idle. The comparator and watchdog may be selectively enabled or disabled during
Idle. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode
with an interrupt, the interrupt will immediately be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle.
11.2 Power-down Mode
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator and powers down the Flash memory in order to minimize power consumption. Only
the power-on circuitry will continue to draw power during Power-down. During Power-down, the
power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be
retained, but the SFR contents are not guaranteed once V
may be exited by external reset, power-on reset, or certain interrupts.
11.2.1 Interrupt Recovery from Power-down
Three external interrupts may be configured to terminate Power-down mode. XTAL1 or XTAL2,
when not used for the crystal oscillator or external clock, may be used to exit Power-down
through external interrupts INT0
or INT1, that interrupt must be enabled and configured for level-sensitive operation. General
purpose interrupt 3 (GPI3) can also wake up the device when the RST
must be enabled and configured for low level detection in order to terminate Power-down.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 11-1.
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
has been reduced. Power-down
CC
(P3.2) and INT1 (P3.3). To wake up by external interrupt INT0
pin is disabled. GPI3
16
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page
15). The interrupt pin need not remain low for the entire time-out period.
Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0)
PWD
XTAL1
t
SUT
INT1
INTERNAL
CLOCK
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure
11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1)
PWD
XTAL1
INT1
INTERNAL
CLOCK
11.2.2 Reset Recovery from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST
an internal timer begins counting as shown in Figure 11-3. The internal clock will not be allowed
to propagate to the CPU until after the timer has timed out. The time-out period is controlled by
the Start-up Timer Fuses. (See Table 10-1 on page 15). If RST
a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the
device will remain in reset until RST
, Power-down is exited, the oscillator is restarted, and
returns high before the time-out,
is brought high.
3538A–MICRO–7/06
17
Figure 11-3. Reset Recovery from Power-down.
PWD
XTAL1
RST
INTERNAL
CLOCK
INTERNAL
RESET
t
SUT
Table 11-1.
PCON = 87H Reset Value = 000X 0000B
Not Bit Addressable
Bit76543210
Symbol Function
SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
PWDEX Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake
POF Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
GF1, GF0 General-purpose Flags
PD Power-down bit. Setting this bit activates power-down operation.
IDL Idle Mode bit. Setting this bit activates Idle mode operation
PCON – Power Control Register
SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL
a frame error regardless of the state of SMOD0.
up from Power-down is internally timed.
affected by RST or BOD (i.e. warm resets).
12. Interrupts
The AT89LP213/214 provides 7 interrupt sources: two external interrupts, two timer interrupts, a
serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These
interrupts and the system reset each have a separate program vector at the start of the program
memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA,
which disables all interrupts.
18
Each interrupt source (except the analog comparator) can be individually programmed to one of
four priority levels by setting or clearing bits in the interrupt priority registers IP and IPH. The
analog comparator is fixed at the lowest priority level. An interrupt service routine in progress
can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower
priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two
requests of different priority levels are pending at the end of an instruction, the request of higher
priority level is serviced. If requests of the same priority level are pending at the end of an
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
instruction, an internal polling sequence determines which request is serviced. The polling
sequence is based on the vector address; an interrupt with a lower vector address has higher
priority than an interrupt with a higher vector address. Note that the polling sequence is only
used to resolve pending requests of the same priority level.
The External Interrupts INT0
and INT1 can each be either level-activated or edge-activated,
depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears
the flag that generated an external interrupt only if the interrupt was edge-activated. If the interrupt was level activated, then the external requesting source (rather than the on-chip hardware)
controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON plus SPIF in SPSR.
None of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine normally must determine whether RI, TI, or SPIF generated the interrupt, and the
bit must be cleared by software.
A logic OR of all eight flags in the GPIF register causes the general-purpose interrupt. None of
these flags is cleared by hardware when the service routine is vectored to. The service routine
must determine which bit generated the interrupt, and the bit must be cleared in software. If the
interrupt was level activated, then the external requesting source must de-assert the interrupt
before the flag may be cleared by software.
The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware
when the service routine is vectored to and must be cleared by software.
Most of the bits that generate interrupts can be set or cleared by software, with the same result
as though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software. The two exceptions are the SPI interrupt flag
SPIF and the general-purpose interrupt flags in GPIF. These flags are only set by hardware and
may only be cleared by software.
Table 12-1. Interrupt Vector Addresses
Interrupt Source Vector Address
System Reset RST or POR or BOD 0000H
External Interrupt 0 IE0 0003H
Timer 0 Overflow TF0 000BH
External Interrupt 1 IE1 0013H
Timer 1 Overflow TF1 001BH
Serial Port RI or TI or SPIF 0023H
General-purpose Interrupt GPIF 002BH
Analog Comparator CF 0033H
3538A–MICRO–7/06
19
12.1 Interrupt Response Time
n
The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls
the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine as the next instruction, provided that the interrupt is not blocked
by any of the following conditions: an interrupt of equal or higher priority level is already in
progress; the instruction in progress is RETI or any write to the IE, IP, or IPH registers. Either of
these conditions will block the generation of the LCALL to the interrupt service routine. The second condition ensures that if the instruction in progress is RETI or any access to IE, IP or IPH,
then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated at the last cycle of each instruction, and the values polled are the values
that were present at the previous clock cycle. If an active interrupt flag is not being serviced
because of one of the above conditions and is no longer active when the blocking condition is
removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered. Every polling cycle is new.
If a request is active and conditions are met for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction executed. The call itself takes
four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an
interrupt request and the beginning of execution of the first instruction of the service routine. A
longer response time results if the request is blocked by one of the previously listed conditions. If
an interrupt of equal or higher priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If the instruction in progress is not
in its final clock cycle, the additional wait time cannot be more than 3 cycles, since the longest
are only 4 cycles long. If the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 7 cycles (a maximum of three more cycles to complete the
instruction in progress, plus a maximum of 4 cycles to complete the next instruction). Thus, in a
single-interrupt system, the response time is always more than 5 clock cycles and less than 13
clock cycles. See Figure 12-1 and Figure 12-2.
20
Figure 12-1. Minimum Interrupt Response Time
Clock Cycles
INT0
IE0
Instruction LCALL 1st ISR Instr.Cur. Instr.
15
Ack.
Figure 12-2. Maximum Interrupt Response Time
Clock Cycles
INT0
IE0
Instruction RETI 4 Cyc. Instr. LCALL 1st ISR I
113
AT89LP213/214 [Preliminary]
Ack.
3538A–MICRO–7/06
AT89LP213/214 [Preliminary]
Table 12-2. IE – Interrupt Enable Register
IE = A8H Reset Value = 0000 0000B
Bit Addressable
EA EC EGP ES ET1 EX1 ET0 EX0
Bit76543210
Symbol Function
EA Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled
by setting /clearing its own enable bit.
EC Comparator Interrupt Enable
EGP General-purpose Interrupt Enable
ES Serial Port Interrupt Enable
ET1 Timer 1 Interrupt Enable
EX1 External Interrupt 1 Enable
ET0 Timer 0 Interrupt Enable
EX0 External Interrupt 0 Enable
.
Table 12-3. IP – Interrupt Priority Register
IP = B8H Reset Value = X000 0000B
Bit Addressable
–
Bit76543210
Symbol Function
PGP General-purpose Interrupt Priority Low
PS Serial Port Interrupt Priority Low
PT1 Timer 1 Interrupt Priority Low
PX1 External Interrupt 1 Priority Low
PT0 Timer 0 Interrupt Priority Low
PX0 External Interrupt 0 Priority Low
–
PGP PS PT1 PX1 PT0 PX0
3538A–MICRO–7/06
21
Table 12-4.
IPH = B7H Reset Value = X000 0000B
Not Bit Addressable
IPH – Interrupt Priority High Register
–
Bit76543210
Symbol Function
PGH General-purpose Interrupt Priority High
PSH Serial Port Interrupt Priority High
PT1H Timer 1 Interrupt Priority High
PX1H External Interrupt 1 Priority High
PT0H Timer 0 Interrupt Priority High
PX0H External Interrupt 0 Priority High
–
PGH PSH PT1H PX1H PT0H PX0H
13. I/O Ports
The AT89LP213/214 can be configured for between 9 and 12 I/O pins. The exact number of I/O
pins available depends on the clock and reset options as shown in Table 13-1. All port pins are
5V tolerant, that is they can be pulled up or driven to 5.5V even when operating at a lower V
such as 3V.
Table 13-1. I/O Pin Configurations
Clock Source Reset Option Number of I/O Pins
External Crystal or Resonator
External RST
No external reset 10
External RST
External Clock
No external reset 11
External RST
Internal RC Oscillator
No external reset 12
Pin 9
Pin 10
Pin 11
CC
13.1 Port Configuration
All port pins on the AT89LP213/214 may be configured to one of four modes: quasi-bidirectional
(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may
be assigned in software on a pin-by-pin basis as shown in Table 13-2. The Tristate-Port User
Fuse determines the default state of the port pins. When the fuse is enabled, all port pins default
to input-only mode after reset. When the fuse is disabled, all port pins, with the exception of P1.0
and P1.1, default to quasi-bidirectional mode after reset and are weakly pulled high. Each port
pin also has a Schmitt-triggered input for improved input noise rejection. During Power-down all
the Schmitt-triggered inputs are disabled with the exception of P1.3, P3.2 and P3.3, which may
be used to wake up the device. Therefore P1.3, P3.2 and P3.3 should not be left floating during
Power-down
22
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
.
Table 13-2. Configuration Modes for Port x, Bit y
PxM0.y PxM1.y Port Mode
0 0 Quasi-bidirectional
0 1 Push-pull Output
1 0 Input Only (High Impedance)
1 1 Open-drain Output
13.1.1 Quasi-bidirectional Output
Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasibidirectional port can be used both as an input and output without the need to reconfigure the
port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin is driven low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the
pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin
high if it is left floating.
AT89LP213/214 [Preliminary]
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains
a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source
current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external
device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the
pin low under these conditions, the external device has to sink enough current to overpower the
weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-tohigh transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a
logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the
port pin high. The quasi-bidirectional port configuration is shown in Figure 13-1. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3).
Figure 13-1. Quasi-bidirectional Output
1 Clock Delay
(D Flip-Flop)
V
CC
Strong
V
CC
Ver y
Weak
V
CC
Weak
Por t
Pin
3538A–MICRO–7/06
From Port
Register
Input
Data
PWD
23
13.1.2 Input-only Mode
The input only port configuration is shown in Figure 13-2. The output drivers are tristated. The
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3). Input pins can be
safely driven to 5.5V even when operating at lower V
the Schmitt trigger will be set by the V
level and must be taken into consideration.
CC
levels; however, the input threshold of
CC
Figure 13-2. Input Only
Figure 13-3. Input Only for P1.3, P3.2 and P3.3
13.1.3 Open-drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configuration is shown in Figure 13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during
Power-down (see Figure 13-3). Open-drain pins can be safely pulled high to 5.5V even when
operating at lower V
the V
Figure 13-4. Open-drain Output
Input
Data
PWD
Input
Data
levels; however, the input threshold of the Schmitt trigger will be set by
CC
level and must be taken into consideration.
CC
Por t
Pin
Por t
Pin
. The pull-
CC
13.1.4 Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. The push-pull port configuration is shown in Figure 13-5. The input circuitry of
P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-3).
24
AT89LP213/214 [Preliminary]
From Port
Register
Input
Data
PWD
Por t
Pin
3538A–MICRO–7/06
Figure 13-5. Push-pull Output
From Port
Register
13.2 Port 1 Analog Functions
The AT89LP213/214 incorporates an analog comparator. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must
have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting
the port pins into the input-only mode as described in “Port Configuration” on page 22. Digital
inputs on P1.0 and P1.1 are disabled whenever the Analog Comparator is enabled by setting the
CEN bit in ACSR. CEN forces the PWD
Schmitt trigger circuitry. P1.0 and P1.1 will always default to input-only mode after reset regardless of the state of the Tristate-Port Fuse.
AT89LP213/214 [Preliminary]
V
CC
Por t
Pin
Input
Data
PWD
input on P1.0 and P1.1 low, thereby disabling the
13.3 Port Read-modify-write
A read from a port will read either the state of the pins or the state of the port register depending
on which instruction is used. Simple read instructions will always access the port pins directly.
Read-modify-write instructions, which read a value, possibly modify it, and then write it back, will
always access the port register. This includes bit write instructions such as CLR or SETB as they
actually read the entire port, modify a single bit, then write the data back to the entire port. See
Table 13-3 for a complete list of Read-modify-write instruction which may access the ports.
Table 13-3. Port Read-modify-write Instructions
Mnemonic Instruction Example
ANL Logical AND ANL P1, A
ORL Logical OR ORL P1, A
XRL Logical EX-OR XRL P1, A
JBC Jump if bit set and clear bit JBC P3.0, LABEL
CPL Complement bit CPL P3.1
INC Increment INC P1
DEC Decrement DEC P3
DJNZ Decrement and jump if not zero DJNZ P3, LABEL
MOV PX.Y, C Move carry to bit Y of Port X MOV P1.0, C
CLR PX.Y Clear bit Y of Port X CLR P1.1
SETB PX.Y Set bit Y of Port X SETB P3.2
3538A–MICRO–7/06
25
13.4 Port Alternate Functions
Most general-purpose digital I/O pins of the AT89LP213/214 share functionality with the various
I/Os needed for the peripheral units. Table 13-5 lists the alternate functions of the port pins.
Alternate functions are connected to the pins in a logic AND fashion. In order to enable the
alternate function on a port pin, that pin must have a “1” in its corresponding port register bit,
otherwise the input/output will always be “0”. Furthermore, each pin must be configured
for the correct input/output mode as required by its peripheral before it may be used as such.
Table 13-4 shows how to configure a generic pin for use with an alternate function.
Table 13-4. Alternate Function Configurations for Pin y of Port x
PxM0.y PxM1.y Px.y I/O Mode
0 0 1 bidirectional (internal pull-up)
0 1 1 output
1 0 X input
1 1 1 bidirectional (external pull-up)
Table 13-5. Port Pin Alternate Functions
Configuration Bits
Port Pin
P1.0 P1M0.0 P1M1.0
P1.1 P1M0.1 P1M1.1
P1.2 P1M0.2 P1M1.2 GPI2
P1.3 P1M0.3 P1M1.3 GPI3 RST
P1.4 P1M0.4 P1M1.4
P1.5 P1M0.5 P1M1.5
P1.6 P1M0.6 P1M1.6
P1.7 P1M0.7 P1M1.7
P3.0 P3M0.0 P3M1.0 RXD
P3.1 P3M0.1 P3M1.1 TXD
P3.2 P3M0.2 P3M1.2 INT0 Internal RC Oscillator Only
P3.3 P3M0.3 P3M1.3
P3.4 P3M0.4 P3M1.4 T0
P3.5 P3M0.5 P3M1.5 T1
P3.6 not configurable CMPOUT Pin is tied to comparator output
Alternate
Function NotesPxM0.y PxM1.y
AIN0 input-only
GPI0
AIN1 input-only
GPI1
SS
GPI4
MOSI
GPI5
MISO
GPI6
SCK
GPI7
AT89LP214 Only
INT1
CLKOUT
Internal RC Oscillator or
External Clock Source Only
AT89LP213 Only
must be disabled
26
AT89LP213/214 [Preliminary]
3538A–MICRO–7/06
14. Enhanced Timer/Counters
The AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Timer,
the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a
clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency.
The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see
Table 9-2 on page 13). Both Timers share the same prescaler.
As a Counter, the register is incremented in response to a l-to-0 transition at its corresponding
input pin, T0 or T1. The external input is sampled every clock cycle. When the samples show a
high in one cycle and a low in the next cycle, the count is incremented. The new count value
appears in the register during the cycle following the one in which the transition was detected.
Since 2 clock cycles are required to recognize a l-to-0 transition, the maximum count rate is 1/2
of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it
should be held for at least one full clock cycle to ensure that a given level is sampled at least
once before it changes. In the AT89LP214, the T0 and T1 inputs are not available at the pins.
However, the inputs may be exercised in software by toggling the P3.4 and P3.5 bits in the
Port 3 register.
Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:
variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control
bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit
pairs (M1, M0) in TMOD select the operating modes.
AT89LP213/214 [Preliminary]
14.1 Mode 0 – Variable Width Timer/Counter
Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from
1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.
By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.
Figure 14-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count
rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled
to the Timer when TR1 = 1 and either GATE = 0 or INT1
to be controlled by external input INT1
bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register consists of all
8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should
be ignored. Setting the run flag (TR1) does not clear the registers.
Mode 0: Time-out Period
Note: RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage
registers.
= 1. Setting GATE = 1 allows the Timer
, to facilitate pulse width measurements. TR1 is a control
PSC
256 2
------------------------------------------------------ -
Oscillator Frequency
×
01+
TPS
1+()×=
3538A–MICRO–7/06
27
Loading...