Rainbow Electronics AT89C51RC User Manual

Features

• Compatible with MCS-51

• 32K Bytes of Reprogrammable Flash Memory

• Endurance: 1000 Write/Erase Cycles

• 4V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 512 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Programmable Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Hardware Watchdog Timer

• Dual Data Pointer

• Power-off Flag

™

Products

Description

The AT89C51RC is a low-power, high-performance CMOS 8-bit microcomputer with
32K bytes of Flash programmable read only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry-standard 80C51 and 80C52 instruction set and

(continued)

8-bit
Microcontroller
with 32K Bytes
Flash

AT89C51RC

Pin Configurations

TQFP

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

P0.0 (AD0)

4443424140393837363534

1

P1.5

2

P1.6

3

P1.7

4

RST

(T0) P3.4
(T1) P3.5

5
6

NC

7
8
9
10
11

1213141516171819202122

GND

GND

XTAL2

XTAL1

(A8) P2.0

(RD) P3.7

(WR) P3.6

(A9) P2.1

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

(A10) P2.2

(A11) P2.3

(A12) P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

P1.5
P1.6
P1.7
RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

1

(T2) P1.0

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST

(T0) P3.4
(T1) P3.5

(RD) P3.7

XTAL2
XTAL1

GND

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

(T2EX) P1.1

(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(WR) P3.6

PLCC

P1.4

P1.3

P1.2

P1.1 (T2 EX)

65432
7
8
9
10
11
12

NC

13
14
15
16
17

1819202122232425262728

XTAL2

XTAL1

(RD) P3.7

(WR) P3.6

PDIP

P1.0 (T2)NCVCC

1

NC

GND

40

VCC

39

P0.0 (AD0)

38

P0.1 (AD1)

37

P0.2 (AD2)

36

P0.3 (AD3)

35

P0.4 (AD4)

34

P0.5 (AD5)

33

P0.6 (AD6)

32

P0.7 (AD7)

31

EA/VPP

30

ALE/PROG

29

PSEN

28

P2.7 (A15)

27

P2.6 (A14)

26

P2.5 (A13)

25

P2.4 (A12)

24

P2.3 (A11)

23

P2.2 (A10)

22

P2.1 (A9)

21

P2.0 (A8)

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

4443424140

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

P0.3 (AD3)

39

P0.4 (AD4)

38

P0.5 (AD5)

37

P0.6 (AD6)

36

P0.7 (AD7)

35

EA/VPP

34

NC

33

ALE/PROG

32

PSEN

31

P2.7 (A15)

30

P2.6 (A14)

29

P2.5 (A13)

(A12) P2.4

Rev. 1920A–08/00

1

pinout. The on-chip Flash allows the program memory to
be user programmed by a conventional nonvolatile memory
programmer. A total of 512 bytes of internal RAM are avail­able in the AT89C51RC. The 256-byte expanded internal
RAM is accessed via MOVX instructions after clearing bit 1
in the SFR located at address 8EH. The other 256-byte

Block Diagram

P0.0 - P0.7

V

CC

PORT 0 DRIVERS

GND

RAM segment is accessed the same way as the Atmel
AT89-series and other 8052-compatible products. By com­bining a versatile 8-bit CPU with Flash on a monolithic chip,
the Atmel AT89C51RC is a powerful microcomputer which
provides a highly-flexible and cost-effective solution to
many embedded control applications.

P2.0 - P2.7

PORT 2 DRIVERS

PSEN

ALE/PROG

EA / V

RST

RAM ADDR.

REGISTER

B

REGISTER

TIMING

AND

PP

CONTROL

ACC

INSTRUCTION

REGISTER

RAM

TMP2

PSW

ALU

PORT 0

LATCH

TMP1

PORT 2

LATCH

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

QUICK
FLASH

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM
COUNTER

DUAL
DPTR

PORT 1

WATCH

DOG

OSC

2

AT89C51RC

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

AT89C51RC

The AT89C51RC provides the following standard features:
32K bytes of Flash, 512 bytes of RAM, 32 I/O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi­tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89C51RC is designed
with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM con­tents but freezes the oscillator, disabling all other chip func­tions until the next external interrupt or hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be configured to be the multiplexed low­order address/data bus during accesses to external
program and data memory. In this mode, P0 has internal
pull-ups.

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes during program verifica­tion. External pull-ups are required during program
verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

) because of the internal pull-ups.

IL

clock-out

and direction control)

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pull-ups.

IL

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull­ups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pull-ups.

IL

Port 3 also serves the functions of various special features
of the AT89C51RC, as shown in the following table.

Port 3 also receives some control signals for Flash pro­gramming and verification.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device. This pin drives
High for 96 oscillator periods after the Watchdog times out.
The DISRTO bit in SFR AUXR (address 8EH) can be used
to disable this feature. In the default state of bit DISTRO,
the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external

3

memory. This pin is also the program pulse input (PROG
during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external
timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data
memory.

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89C51RC is executing code from external
program memory, PSEN

is activated twice each machine

)

cycle, except that two PSEN
each access to external data memory.

EA

/VPP

External Access Enable. EA
order to enable the device to fetch code from external pro­gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA
internally latched on reset.

should be strapped to VCC for internal program

EA
executions.

This pin also receives the 12-volt programming enable volt­age (V

) during Flash programming.

PP

XTAL1

Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

activations are skipped during

must be strapped to GND in

Table 1. AT89C51RC SFR Map and Reset Values

0F8H 0FFH

will be

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111SP00000111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

RCAP2L

00000000

AUXR1

XXXXXXX0

TL0

00000000

DP0L

00000000

RCAP2H

00000000

TL1

00000000

DP0H

00000000

TL2

00000000

TH0

00000000

DP1L

00000000

TH2

00000000

TH1

00000000

DP1H

00000000

WDTRST

XXXXXXXX

AUXR

XXX00000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4

AT89C51RC

AT89C51RC

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke

Table 2. T2CON – Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

76543210

Symbol Function

new features. In that case, the reset or inactive values of
the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap­ture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.

CP/RL2

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1

or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When

Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared
by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer

2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

CP/RL2

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

5

Table 3a. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00X00B

Not Bit Addressable

–––WDIDLE DISRTO – EXTRAM DISALE

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DISALE Disable/Enable ALE

DISALE Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency

1 ALE is active only during a MOVX or MOVC instruction

EXTRAM Internal External RAM (00H-FFH) access using MOVX @ Ri/DPTR

EXTRAM Operating Mode

0 Internal ERAM (00H-FFH) access using MOVX @ Ri/DPTR

1 External data memory access

DISTRO Disable/Enable Reset out

DISRTO

0 Reset pin is driven High after WDT times out

1 Reset pin is input only

WDIDLE Disable/Enable WDT in IDLE mode

WDIDLE

0 WDT continues to count in IDLE mode

1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both
internal and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in
SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The
user should always initialize the DPS bit to the appropriate

value before accessing the respective Data Pointer
Register.

Power Off Flag: The Power Off Flag (POF) is located at bit
4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and rest under software control and
is not affected by reset.

Table 3b. AUXR1: Auxiliary Register 1

AUXR1 Address = A2H Reset Value = XXXXXXX0B

Not Bit Addressable

––– – – – –DPS

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DPS Data Pointer Register Select

DPS

0 Selects DPTR Registers DP0L, DP0H

1 Selects DPTR Registers DP1L, DP1H

6

AT89C51RC

Memory Organization

MCS-51 devices have a separate address space for Pro­gram and Data Memory. Up to 64K bytes each of external
Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are
directed to external memory.

On the AT89C51RC, if EA
fetches to addresses 0000H through 7FFFH are directed to
internal memory and fetches to addresses 8000H through
FFFFH are to external memory.

Data Memory

The AT89C51RC has internal data memory that is mapped
into four separate segments: the lower 128 bytes of RAM,
upper 128 bytes of RAM, 128 bytes special function regis­ter (SFR) and 256 bytes expanded RAM (ERAM).

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to
7FH) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to
FFH) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses
80H to FFH) are directly addressable only.

4. The 256-byte expanded RAM (ERAM, 00H-FFH) is
indirectly accessed by MOVX instructions, and with
the EXTRAM bit cleared.

The Lower 128 bytes can be accessed by either direct or
indirect addressing. The Upper 128 bytes can be accessed
by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. This means they
have the same address, but are physically separate from
the SFR space.

When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to the
upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction. Instructions that
use direct addressing access SFR space. For example:

MOV 0A0H, # data

accesses the SFR at location 0S0H (which is P2). Instruc­tions that use indirect addressing access the Upper 128
bytes of data RAM. For example:

MOV@R0, # data

where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).

is connected to VCC, program

AT89C51RC

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail­able as stack space.

The 256 bytes of ERAM can be accessed by indirect
addressing, with EXTRAM bit cleared and MOVX instruc­tions. This part of memory is physically located on-chip,
logically occupying the first 256 bytes of external data
memory.

Figure 1. Internal and External Data Memory Address

(with EXTRAM = 0)

FF

ERAM
256 BYTES

00

FF

80

00

UPPER
128 BYTES
INTERNAL
RAM

LOWER
128 BYTES
INTERNAL
RAM

FF

SPECIAL
FUNCTION
REGISTER

80

With EXTRAM = 0, the ERAM is indirectly addressed,
using the MOVX instruction in combination with any of the
registers R0, R1 of the selected bank or DPTR. An access
to ERAM will not affect ports P0, P2, P3.6 (WR

). For example, with EXTRAM = 0,

(RD

MOVX@R0, # data

where R0 contains 0A0H, accesses the ERAM at address
0A0H rather than external memory. An access to external
data memory locations higher than FFH (i.e. 0100H to
FFFFH) will be performed with the MOVX DPTR instruc­tions in the same way as in the standard MCS-51, i.e., with
P0 and P2 as data/address bus, and P3.6 and P3.7 as
write and read timing signals. Refer to Figure 1.

With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be
similar to the standard MCS-51. MOVX@Ri will provide an
8-bit address multiplexed with data on Port 0 and any out­put port pins can be used to output higher-order address
bits. This is to provide the external paging capability.
MOVX@DPTR will generate a 16-bit address. Port 2 out­puts the high-order 8 address bits (the contents of DP0H),
while Port 0 multiplexes the low-order 8 address bits (the
contents of DP0L) with data. MOVX@Ri and
MOVX@DPTR will generate either read or write signals on
P3.6 (WR

) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256
bytes RAM (lower and upper RAM) internal data memory.
The stack may not be located in the ERAM.

FF

0100
0000

), and P3.7

EXTERNAL
DATA
MEMORY

7

Hardware Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, it will
increment every machine cycle while the oscillator is run­ning. There is no way to disable the WDT except through
reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse
at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT over­flow. The 14-bit counter overflows when it reaches 16383
(3FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the
WDT at least every 16383 machine cycles. To reset the
WDT the user must write 01EH and 0E1H to WDTRST.
WDTRST is a write-only register. The WDT counter cannot
be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sec­tions of code that will periodically be executed within the
time required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the
WDT also stops. While in Power-down mode, the user
does not need to service the WDT. There are two methods
of exiting Power-down mode: by a hardware reset or via a
level-activated external interrupt which is enabled prior to
entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it
normally does whenever the AT89C51RC is reset. Exiting
Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabi­lize. When the interrupt is brought high, the interrupt is ser­viced. To prevent the WDT from resetting the device while
the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be
reset during the interrupt service for the interrupt used to
exit Power-down mode.

To ensure that the WDT does not overflow within a few
states of exiting Power-down, it is best to reset the WDT
just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR
AUXR is used to determine whether the WDT continues to
count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT
from resetting the AT89C51RC while in IDLE mode, the
user should always set up a timer that will periodically exit
IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in
IDLE mode and resumes the count upon exit from IDLE.

UART

The UART in the AT89C51RC operates the same way as
the UART in the AT89C51 and AT89C52. For further infor­mation, see the December 1997 Microcontroller Data Book,
page 2-48, section titled, “Serial Interface”.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89C51RC operate the same
way as Timer 0 and Timer 1 in the AT89C51 and AT89C52.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 4.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator
frequency.

Table 4. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

X X 0 (Off)

In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which

in the SFR T2CON (shown in Table 2).

8

AT89C51RC