Rainbow Electronics AT89C2051 User Manual

Using the AT89C2051 Microcontroller

as a Virtual Machine

It is often cited that what differentiates an
embedded microcontroller from other
general purpose computing devices is its
integration into a larger electrical or elec­tro-mechanical system. While this is
generally true , the f act rema ins tha t pro­cessors of widely differing capabi lity and
architecture are employed in this regard.

Unfortunately, this broad explanation
defines nothing; we are still left to con­tend with everything from full-blown
embedded PCs to the smallest self-con­tained single-chip microcontrollers.
Within this expansi ve realm, conve n­tional wisdom may lead to the conclu­sion that the smallest microcontrollers
are only appropr iate for drivi ng small­scale applications with very limited pro­cessing requireme nts. While this is
unquestionably the case in many
instances, a class of app lication s exists
that mandates a relatively high level of
program complexity within severely con­strained space limitations. Faced with
such a seeming paradox, engineers
often feel they have no choice but to
adopt a less than opti mal design stra t­egy using a larger mi crocontroller than
originally intend ed.

The problem, of cours e, i s one of limited
resources. Functio nal complexity implies
a non-trivial program, and the greater
the functional complexity the larger the
program. Even as the capability of small
single-chip microcontrollers contin u­ously inches upward s, application
requirements seem to grow at a com­mensurate rate. Tr ying to hit such a
moving target is difficult at best.

The economy of using a microcontr oller
with just enough processing power for a
given application is a potent incentive to
find just the right fit. Of course, this only

works when the system requirements
are thoroughly understood and clearly
defined. Since such a design normally
has little reserve capacity, it is usually
hard pressed to handle featu re s be yo nd
those originally specified. Should addi­tional capabilities eventually b ecome a
necessity, the result could be a system
that runs out of steam and an engineer
that runs out of options. Such are the
perils of designing on the edge.

Atmel’s AT89C2051 offers capabilities
that far exceed those of competing
devices of similar size. This op ens up
potential design opportu nities that wer e
simply unattainable with previously avail­able parts. Housed in a 20-pin package,
Atmel’s miniature microcontroller retains
all the major features of the 8 051 archi­tecture. Furtherm ore, the AT89 C2051
includes all of the 8051’s “special” pins
including the external interrupts, UART
transmit and receive lines, and the exter­nal timer controls. Even though the
AT89C2051 significantly ups the pro­cessing ante, it would seem that there
are limits to what you can accomplish
with any single-chip microcontroller.

This dilemma is nothing new. The tradi­tional way of dealing with such limita­tions has been to operate the microcon­troller in external memory mode. Com­mon sense would in dicat e the hope less­ness of applying such an appr oach to
the AT89C2051. After all, the
AT89C2051 is truly a single-chip design
that does not even possess an externa l
bus structure. It turns out that the situa­tion is not hopeless at all.

AT89C2051
Flash
Microcontroller

Application
Note

w

5-47

Processor Simulation

The concept of microprocessor simulation is widely used
and well understood. Simulation is often used for develop­ment

purposes where a P C program mo dels a sp ecific proc es­sor’s architecture and interprets and executes its binary
instruction set. Using this technique enables one to
develop, test, and debug algorithms that will ul timately be
combined into a l arger p ro gr am. Su ch a p ro gr am wil l e ve n­tually run on a standalone microprocessor or microcontrol­ler. Using simulation early in the design cycle i s attractive
because it allows you to start developing code long before
the actual target hardware is available.

Processor simulation has also been applied to simulate
entire computi ng syst ems. In t his conte xt, exis ting ap plica­tion programs, in their nativ e binary format, have been
coerced to run on various compute rs powered by com­pletely different processors. For obvious reasons, the per­formance resulting from such an approach often proves to
be disappointi ng. This does no t necess arily hav e to be the
case if the implementation is designed for a specific pur­pose. Factors effecting performance efficiency include the
host processor’s strengths and limitations, the specific
types of operations that are to be simulated, and, to an
extent, the language the original program is written in.

Virtual Processor Simulation

Many developmental simul ators have be en produced tha t
emulate the functions of popula r proces sors and microcon­trollers using st andard des ktop co mputer s. The same pr in­ciples can be utilized at the other end of the spect rum;
there are cases where runn ing a simulation on a small
microcontroller can be put to an advantage. In this case,
however, the benefit is not derived from simulating a known
processor, but on e that offer s inhe rent adva ntages tail ored
to solving the specific problem at hand. The implication, of
course, points to the design of a virtual processor. The idea
is based on the pr em is e of u si ng a re al proc es s or to imple­ment a virtual device specifically designed to suit the spe­cial needs of a particular application. In other words,
designing the tool set for a particular job.

The fact is that adopting such a methodology can ultimately
result in an archit ect ur e tha t c an be pr essed to serve as an
efficient vehicle for a number of special ized tasks. Detai ls
including the fundamental architecture, instruction set, and
memory model can be app roached with tota l freed om. But ,
can such an approach provide the level of performance
demanded by embedded applicati ons ?

Efficiency and Overhead

To illustrate that efficiency is a subjective matter, consider
what happens when a ty pical C pr og ram is c om pil ed to r un
on an 8051 processor. It’s inconceivab le that, on such an
architecture, any C statement will effectively compile down
to any correspondi ng 8051 instruct ion. A single C state ­ment invariably results in the execution of multiple instruc­tion steps. It follows that, gi ven an efficient simulated
instruction set, the simulation overhead might account for a
very small percentage of the overall execution time.

The key behind making this premise work is to devise an
instruction set and processor architecture that’s conducive
to performing the types of operations that a C compiler nat­urally generates. In such an implementation, the contrived
instruction set essentially amounts to an intermediate lan­guage. The op codes mere ly serve as a vehicle for suc­cinctly conveying the compiler’s directives to the target pro­cessor for execution.

The target processor, while performing the functions of a
simulator, interprets the intermediate instructions to per­form the functions specified in the original high level lan­guage source sta tements. Th e resul ting eff iciency c an be
quite tolerable sin ce the bulk of the i nstr uctio ns wou ld exe ­cute regardless of whether they were emitted directly by
the compiler or invoked by the simulation kernel.

It turns out the performance penalty of such an approach
is, to a great exten t, dependent on the way the program
memory itself is impleme nted. Sin ce the AT89 C2051 has
no external bus structure it makes sense to use a serial bus
to access the progra m memory . Using I
provides the required fle xibility along with reason able
throughput.

2

Selecting I
choosing from a wide variety of EEPROM memory devices.
The most favorable configuration is Atmel’s AT24C64 that
offers 8K byte s of st orage in an 8-pi n packag e. Utiliz ing
extended 16-bit ad dressing , the AT 24C64 p rovides li near
access to the entire intern al memory array. A nd altho ugh a
lot of functional ity can b e cr am med i nto a si ng le ch ip , a ddi ­tional devices can easily be added in 8K increments to han­dle very complex applications. Up to eight AT24C64s can
simultaneously reside on the I
storage while using just two wires.

Of course, serial memory access does come at a cost. In
this case the expense comes in the form of access time. To
an extent, this is moderated by the fact that the AT24C64
can operate at a 400 kHz cloc k rate (s tandard I
fied at a maximum of 100 kH z). Remember however , that

2

C can exact a significan t performa nce penalty because a

I
substantial percentage of its bandwidth can be consumed
for control functions.

C as a memory bus presents the potential of

2

C bus providing a full 64K of

2

C for this purpose

2

C is speci-

5-48

Microcontroller

2

The greatest overhead burden that I
the transfer of addressing information. For every random
read or write, a 16-bit address must be transmitted along
with the extra overhead necessary to coordinate bus con­trol for both the addressing phase and the data manipula­tion phase. Under such conditions, actual data movement
could be swamped by the requisite overhead resulting in
unacceptable performance degradation. Fortunately, I
provides a means of eliminating much of this wasteful activ­ity.

2

The AT24C64, like all other I
an internal auto-increment address generator. Using this
feature, once addressability is established, data can be
continually streamed in a sequential fashion. As each byte
is read and ac knowle dged the internal addre ss generat or
increments in preparation for the n ext byte transfer. The
AT24C64 sets the maximum speed limit at 400 kHz but I
does not impose a lower limit. Effectively, the minimum fre­quency can drop all the way to DC. As a result, it’s accep t­able to suspend a s equ ential tr an sfe r fo r as l ong a s neces ­sary.

Utilizing these features, communications can be sped up
considerably. The rami fications are particu larly sign ificant
when the memory is use d to store an executab le prog ram.
For example, once an address is written into the AT24C64,
data can be fetched in a continual stream until the program
branches or, if multiple AT24C64’s are used, until it
becomes necessary to cross into the next chip. At these
points it’s necessary to explicitly reload the internal address
generator. Normally, how ev er, the majority of the accesses
will be sequential, resulting in greatly reduced overhead.

C memory devices, contains

C imposes involves

2

2

Processor Simulators and Language
Interpreters

It’s important to note the distinction between language spe­cific interpreters that implement a defined language such
as BASIC, and a processor simulator that interprets a low
level binary instruction set. A tokenized BASIC interpreter,
while quite effi cient in e xecuting the command s that are
explicitly implemented as part of the language, is strictly
confined to what the language supports. The inherent effi­ciency of an interpret ed langu age come s at the expen se of
flexibility.

In contrast, a processor s imulator, that deal s with a true
binary instruction set, enjo ys total freedom in combining
these basic op codes into larger functional entities in
almost limitless permutations. Just like a real processor, a
simulated processor can ut ilize its instruc tion set for st an­dard and custom C l ibra ry f unc tio ns , fl oat ing po in t li br ari es ,
device drivers, etc.

Microcontroller

The Virtual Machine — An Imaginary
Processor

The processor to be described is imaginary in the sense
that its architecture and instruction set a re original and
unique. Realize, however, that this is not just a toy or an
intellectual diversion—from an implementation standpoint it
is quite real. The fundamental concept has been success-

C

fully ported to a variety of processor architectures. A ver­sion exists that runs on a personal computer that is suitable
for demonstration and development purposes. T he most
promising sm all-sy stem p ort ha s be en to t he AT 89C2051
due to the microcontroller’s standard processing core and
integrated peripheral set. The basic 8K Virtual Machine is
schematically depicte d in Fig ure 1. The c ircuit’s simplicity
reveals that this is primarily a software implementation—
the definitive soft machine.

C

This imaginary processor, the product of Dunfield Develop­ment Systems, has served in various applications providing
reliable solutions to real world problems where a standard
configuration was not necessary, optimal, or practical. That
this Virtual Machine al so goes by the name “C-FLEA”
affirms its optimization for efficiently rendering the output of
a C language code generator.

The prime currency of a proc essor is time. V iewed in this
context, the expense of complexity can prove unacceptably
burdensome. Taking this into consideration, the Virtual
Machine, based on a simple 16-bit architecture that incor­porates only four registers, is the epitome of simplicity. This
register set comprises an accumulator, index register,
stack pointer, an d program coun ter. Appendi x A provid es
detailed infor mati on abou t the Vi rtual Mac hin e arc hite cture
and instruction set. R efer to Ta bl e 1 fo r a des c ripti on o f the
fundamental resource set.

Although the Virtual Machi ne pe rfo r ms all operati on s to 16 ­bit precision, the needs of many embe dded systems
resolve to 8 bits. To facilitate working with this common
denominator, the Virtual Machine stores data in little endian
format (low byte first) which facilitates the use of a given
variable’s base address to refer to either an 8-bit or 16-bit
quantity. Interesti ngly, the ar chitecture provides n o user
accessible flags. When invoking a compare instruction,
internal flags persist only long enough to accommodate the
ensuing branch instruction or the intervening compare
modifiers (which are described later).

This spartan register set is made workable by the inclusion
of a variety of add ress ing mo des tha t exc el at the ty pes of
stack manipulations tha t are central to the canonical C
implementation. The Vir tual Machine’s memory access
instructions, detailed in Table 2, include the following
addressing modes: immediate (8 or 16 bit), direct, indirect
through index register (with or without offset), indirect
through stack with offset, top of st ack, and in direct thro ugh
top of stack (remove or leave value on stack).

5-49

The bulk of the virtual instruction set is presented in Table

3. These instructions include memory access instructions,
arithmetic instruction, and logical instructions. In keeping
with the previously established proposition, most can return
either bytes or words.

Since the compare in struc tions are de signed to only deter ­mine equality, the instruction set is augmented by a set of
special compa re modifiers . Using these , nuances of rela­tive (signed and unsigned) magnitude can be coerc ed from
the basic com pare instruction s. These modifier s are
described in Table 4.

Program branching is supported using the relatively con­ventional set of cond ition al and u ncon ditio nal j ump i nstr uc­tions shown in Table 5. Versions are provided for both near
and far destinati on targets to e nhance code efficiency.
Note the inclusion of the SWITC H ins tructio n whic h pr oves
especially useful since the “normal” compare instructions
destroy the contents of the accumulator when returning the
result of the compare operation.

Table 6 presents the stack manipulation set. Inc luded are
common functio ns such as CALL, RETur n, and PUSH .
Conspicuously absent is an explicit POP instruction. The
corresponding functionality is provided by the various
addressing modes that, by default, manipulate the top of
the stack. For instanc e, PO P A is s y non ym ous wi th LD S +.
Additional instruc tions ar e inc luded to facil itate stac k frame
creation and des tructi on tha t is a nece ssar y func tion of the
C language implementation.

Finally, the virtual instruction set is rounded with a number
of miscellaneous instructions shown in Table 7. For the
most part, these pe rform s tanda rd fu nction s tha t shou ld be
self explanatory. The input/output instructions are special in
that they offer an implementation specific avenue for estab­lishing certain peripheral functions as instructions. Remem­ber that, even though, the vi rtual instruc tion set offers the
programmer to tal f reedom t o cons truct an y kind o f comp u­tational sequence, all I/O operations are dependent on the
support coded into the Virtual Machine kernel. Essentially,
the simulation kernel is the software embodiment of a
microprocess or archite cture. Nat urally, th e goal is to pr o­vide a general purpose en gin e capable of serving in a wide
variety of real embedded systems.

A significant numbe r of op codes re main unassi gned and
are available for future use.

Initial Program Loader

While not actually p art of the Vi rtual Machi ne, the sim ula­tion kernel contains a built-in program loader utility. This
operates serially and is invoked following a system reset by
a sequence of special commands from a utility program
running on the host computer. In addition to transferring the
load image to the Virtual Process or, the PC program pro­vides a number of features which include a simulator (that
can hook into the target’s logical and physical I/O sub­system) and a console wind ow for per forming user I/O to
the target system. Since the Virtual Machine’s co de gener­ator emits a standard Intel HEX file format, the use of the
PC utili ty program is optional.

In principle, there is no r ea so n why a n AT24C64 cannot be
programmed externally us ing a standard device prog ram­mer just as you would program an EPROM for a use in a
typical embedded computer. Although workable, this
approach would, at the least, prove cumbersome through­out the development cyc le. The difficul ty of this approa ch
would be exacerbated in a system using mu ltiple memory
chips. Obviously, it would be completely unworkable in the
event a Virtual Machine computer was rendered as a sur­face mount assembly.

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Microcontroller