Rainbow Electronics AT86RF401 User Manual
Features
• RF Frequency Range of 264–456 MHz
• 6 dBm RF Output into Matched Antenna
• RF Output Power Adjustable over 36 dB with 1 dB Resolution
• Phase-locked Loop (PLL) Based Frequency Synthesizer
• Supports OOK Modulation
• Data Bandwidth of Up to 10 Kbps Manchester
• 2-volt Operation
• 8-bit AVR
• Minimal External Components
• Space-saving 20-lead TSSOP
• 2 KB (1K x 16) of Flash Program Memory
• 128 Bytes of EEPROM
• 128 Bytes of SRAM
• In-system Programmable Data and Program Memory
• Six I/Os (Serial I/F, LED Drive Outputs, Button Input Interrupts)
• Low Battery Detect and Brown-out Protection
• Software Fine-tuning of VCO Tank Circuit
â
RISC Microcontroller Core
Smart RF
™
Wireless Data
Microtransmitter
Applications
• Remote Keyless Entry (RKE) Transmitters
• Wireless Security Systems
• Home Appliance Control (Lighting Control, Ceiling Fans)
• Radio Remote Control (Hobby, Toys)
• Garage Door Openers
• Wireless PC Peripherals (Keyboard, Mouse)
• Telemetry (Tire Pressure, Utility Meter, Asset Tracking)
Description
The Atmel AT86RF401 Smart RF™Microtransmitter is a highly integrated, low-cost RF
transmitter, combined with an AVR
single LiMnO
coin cell (CR2032 or similar), three capacitors, an inductor and a tuned-
2
loop antenna to implement a complete on-off keyed (OOK) wireless RF data
transmitter.
Figure 1. Block Diagram
XTAL/CLK
XTALB
OSCILLATOR
PHASE
DETECTOR
RISC microcontroller. It requires only a crystal, a
L1
VCO
L2
ANT
RF
AMP
ANTB
CFIL
LOOP FIL
LOOP
FILTER
PRESCALER
÷
24
B+
AT86RF401
Preliminary
AVDD
AGND
POWER
SUPPLY
SUPERVISOR
CLOCK
RESET
WATCHDOG
LOW-VOLTAGE DETECT
BROWN-OUT PROTECT
DVDD
DGND
DATA
AVR RISC µC
2 KB Flash Program Memory
128 Bytes EEPROM Data Memory
IO5
IO4
IO3
SDI/IO0
SCK/IO2
SDO/IO1
GAIN
TRIM
RESETB
1424D–RKE–09/02
1
In-system programmable, nonvolatile Flash program memory and EEPROM data storage make possible rapid time-to-market and lower inventory costs.
Static current consumption is kept to a minimum with an ultra-low current shutdown
mode. Normal operation resumes when a button is pressed. This activates the crystal
oscillator circuit that serves as the clock for the AVR microcontroller.
The RF carrier is synthesized utilizing an on-board Voltage Controlled Oscillator (VCO).
Optimal tuning of the VCO is maintained over component tolerance through the use of a
software-controlled switched capacitor array. Its accuracy is maintained with a PLL
detector that compares the crystal oscillator to a frequency-scaled version (divided by
24) of the RF carrier. The resulting error signal adjusts the VCO to produce a very stable
RF carrier.
An interrupt-based bit-timer structure, integral to the AVR microcontroller, simplifies the
implementation of user-specific, data-bit encoding routines, such as PWM or Manchester, for modulating the RF carrier. Thirty-six dB of RF power output control is available to
the user in 1 dB steps and is addressable in software. The RF signal output is placed
differentially on a tuned-loop antenna, which may be realized as a counterspread copper trace on a PCB.
The AT86RF401 is fabricated in Atmel’s 0.6 µm Mixed Signal CMOS + EEPROM process, enabling true system-level integration (SLI).
Figure 2. 20-lead TSSOP
ANTB
LOOPFIL
RESETB
N/C
I/O0 (SDI)
I/O1 (SDO)
I/O2 (SCK)
XTAL/CLK
L1
L2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ANT
CFIL
AVDD
DVDD
AGND
DGND
I/O5
I/O4
I/O3
XTALB
2
AT86RF401
1424D–RKE–09/02
Figure 3. Sample Circuit
EXTERNAL LOOP FILTER (OPTIONAL)
AT86RF401
V+
R1
C4
L1
RESET SDO
SDI
SCLK
SPI Programming Interface
S1
C3
U1
Y1
C2
ANT
CFIL
AVDD
DVDD
AGND
DGND
IO5
IO4
IO3
XTALB
20
19
18
17
16
15
14
13
12
11
C5
1
ANTB
2
LOOPFIL
3
L1
4
L2
5
RESETB
6
NC
7
IO0/SDI
8
IO1/SDO
9
IO2/SCLK
10
XTAL/CLK
S2 S
V+
C1 B1
3
Table 1. Recommended Parts List
Value
Part Number
B1 3.6V CR2032, Li Battery
C1 0.01 µF 0603, X7R, ± 10%
C2 100 pF 0603, COG, ± 5%
C3 Antenna Dependent Antenna Dependent Antenna Dependent 0603, COG, ± 0.1 pF
C4 Not req’d Not req’d Frequency Dependent 0603, COG, ± 5%
C5 Not req’d Not req’d Frequency Dependent 0603, COG, ± 0.25 pF
L1 82 nH 39 nH Frequency Dependent 1608, ± 5%
R1 Not req’d Not req’d Frequency Dependent 0603, ± 5%
S1 Switch SPST
S2 Switch SPST
S3 Switch SPST
U1 AT86RF401 20-lead TSSOP
Y1 13.125 MHz 18.08 MHz Frequency Dependent
(Common)
Value
(315 MHz)
Value
(433.92 MHz)
Value
(Ext. Loop Filter) Specification
13.125 MHz:
Crystek
™
P/N 016757
18.080 MHz:
Crystek P/N 016758
1424D–RKE–09/02
3
Table 2. Pin Descriptions – 20-lead TSSOP
Symbol Pin Description
120
ANTB 1 Differential Antenna Output
10 mA
LOOPFIL 2
L1 3
V
VCO
V
DD
2
V
DD
External VCO Loop-filter Connection.
V
is the VCO control voltage.
3
V
VCO
V
DD
4
2
V
DD
VCO
External VCO Inductor Connection.
V
is the VCO control voltage.
3
V
VDD
V
DD
4
2
V
DD
VCO
L2 4
4
AT86RF401
External VCO Inductor Connection.
V
is the VCO control voltage.
3
4
VCO
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Table 2. Pin Descriptions – 20-lead TSSOP (Continued)
V
DD
AT86RF401
SPI Reset Input: A “low” on this pin resets the device and puts
the part into SPI mode. A logic-high on this pin causes the
device to execute its program if the V
RESETB 5
35 k Ω
5
out voltage level.
To AV R
NC 6 No Connect. Float Pin.
V
DDVDD
I/O0 (SDI) 7
I/O1 (SDO)
Data
nable−
Data
Enable
V
DD
Data
Enable−
8
Data
Enable
35 k Ω
7
SPI Data In/Input/Output 0: General-purpose I/O and button
input. In SPI mode, this pin serves as SDI (Serial Data Input).
To AV R
V
DD
35 k Ω
SPI Data Out/Input/Output 1: General-purpose I/O and button
8
input. In SPI mode, this pin serves as SDO (Serial Data
Output).
To AV R
is above the brown-
DD
I/O2 (SCK)
XTAL/CLK 10
1424D–RKE–09/02
V
V
DD
DD
Data
Enable−
9
Data
Enable
10
40 pF
35 k Ω
9
To AV R
SPI Clock/Input/Output 2: General-purpose I/O and button
input. In SPI mode, this pin serves as SCK (SPI Clock Input).
Crystal/Clock Input: Input to the inverting oscillator amplifier
and input to the internal clock operating circuit. This pin may
be driven externally for test purposes.
11
40 pF
5
Table 2. Pin Descriptions – 20-lead TSSOP (Continued)
10
40 pF
XTALB 11 Crystal Output: Output from the inverting oscillator amplifier
11
40 pF
V
V
DD
DD
Data
IO3 12 Input/Output 3: General-purpose I/O and button input
IO4 13 Input/Output 4: General-purpose I/O and button input
Enable
Data
Enable
Data
Enable
Data
Enable
V
DD
35 k Ω
V
DD
35 k Ω
12
To AV R
13
To AV R
V
V
DD
DD
Data
IO5 14 Input/Output 5: General-purpose I/O and button input
Enable
Data
Enable
35 k Ω
14
To AV R
DGND 15 Digital Ground
AGND 16 Analog Ground
DVDD 17 Digital Voltage Supply
6
AT86RF401
1424D–RKE–09/02
Table 2. Pin Descriptions – 20-lead TSSOP (Continued)
AVDD 18 Analog Voltage Supply
19
CFIL 19 External Data Rate Filter
420 KΩ
120
ANT 20 Differential Antenna Output
1.06 pF
10 mA
AT86RF401
1424D–RKE–09/02
7
Absolute Maximum Ratings*
Antenna Voltage (Pins 1, 20)...................................... −1V to 10V
Operating Temperature ........................................−40°Cto+85°C
Storage Temperature (without bias) ................−55°Cto+125°C
Voltage on V
Voltage on Pins 2–19 (TSSOP 20) ................ −0.1 to V
with respect to ground ............................. 6.0V
DD
DD
+0.3V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Characteristics
VDD=3.3V;f
Symbol Parameter Conditions Min Typ Max Unit
Supply
V
DD
I
DD
= 13.125 MHz; f
XTAL
AVR=fXTAL
÷ 16; TA=25°C unless otherwise specified.
Supply Voltage 2.0 3.3 5.0 V
=3.3V
V
Standby Current (off)
DD
= 25°C
T
A
– 0.1 0.5 µA
AVR Active – 3.4 – mA
Frequency Synthesizer + AVR Active – 14.3 – mA
Transmit (FS, AVR and Power Amp active) CW modulation – 23.2 – mA
Digital Inputs (SDI, SCK, RESETB, IOx)
V
IH
V
IL
I
IH
I
IL
High-level Input Voltage 0.8* V
Low-level Input Voltage 0 – 0.2* V
High-level Input Current VIH=V
Low-level Input Current VIL=0V, VDD=5.0V −140 ––µA
Digital Outputs (SDO, IOx)
V
OH
V
OL
High-level Output Voltage IOH= −500 µA VDD−0.4 ––V
Low-level Output Voltage IOL=2mA ––0.4 V
Microcontroller/System
t
TX
f
AVR
EE
EE
LIFE
CYCLES
Time from Button Wake-up to RF Outputs Active – 0.5 1.0 ms
AVR Clock Frequency ––1.25 MHz
EEPROM Retention
EEPROM Write/Erase Endurance
, V
DD
=5.0V ––1µA
DD
Initial programming
conditions:
V
=3.3V±10%
DD
Te mp = 25 °C±10%
2.0V ≤ V
DD
≤ 5.0V
−40°C ≤ Te m p ≤
85°C
DD
– V
DD
DD
V
V
––10 years
––100,000 cycles
8
AT86RF401
1424D–RKE–09/02
Analog/RF Specs
AT86RF401
VDD=3.3V;f
Symbol Parameter Conditions Min Typ Max Unit
RF Amplifier
I
PA
P
CTLRANGE
P
CTLRES
Crystal Oscillator
f
OSC
Frequency Synthesizer/PLL
F
OUT
1
P
HARM
f
MOD
Note: 1. Characterized but not guaranteed by test due to dependency on PCB trace antenna
Functional
= 13.125 MHz; f
XTAL
Power Amp Output Current Transmitting (RF “ON”), 0 dB Attenuation – 8.6 – mA
Power Control Range – 36 – dB
Power Control Resolution – 1 – dB
Oscillation Frequency Range 11 – 19 MHz
Output Frequency Range 264 – 456 MHz
Harmonics
OOK Modulation Data Rate Using Manchester Data Bit Encoding ––10 Kbps
AVR=fXTAL
÷ 16; TA=25°C unless otherwise specified.
I/O Pins Static during RF Transmission
Using PCB Trace Antenna
– −60 – dBc
The complete circuit consists of the following functional blocks.
Description
Transmitter
Crystal Oscillator The crystal oscillator circuit is designed to work with crystals with fundamental frequen-
cies between 11 and 19 MHz. Forty pF of internal capacitance is connected between
each of the crystal input pins and (chip) ground. Alternatively, an external clock can be
used for these functions.
This circuit provides the master clock for the entire chip. A programmable divider is used
to provide the AVR system clock.
Radio Frequency Power Amplifier
Frequency Synthesizer The frequency synthesizer utilizes a PLL, which consists of a phase detector, a ÷24
Lock Detector The lock detection block provides an indication of the state of the phase lock loop (PLL).
The RF power amplifier generates a differential output suitable for driving an off-chip
tuned-loop antenna from the PLL output. The PLL output signal is gated using on-off
keyed (OOK) modulation before transmission. It is used as the RF carrier frequency for
the transmitted data stream. The amplifier can be configured via software to reduce the
power output by 36 dB (with 1 dB resolution).
prescaler, an on-chip loop filter and an integrated VCO. The VCO output is buffered
prior to the output amplifier. The output frequency is 24 times the crystal frequency. To
offset component tolerance, a switched capacitor array is connected between pins 3
and 4 of the VCO. Thirty-two discrete steps of capacitance are available to tune the
VCO control voltage. An internal window comparator monitors the magnitude of the tuning voltage and is used by the AVR core to determine the optimal tuning configuration.
Lock condition is determined by counting the number of cycle slips in a given time
1424D–RKE–09/02
9
period. A number of registers are available to adjust the performance of the lock detector. These include lock delay and unlock delay timers as well as a cycle slip counter.
Bandgap Reference The device uses a 1.2V (nominal) bandgap reference generator to provide consistent
performance over a wide range of input supply voltages. This reference voltage is used
throughout the device.
Brown-out Protection/Low Battery Detection
Brown-out Protection
Low Battery Detection
The brown-out protection and low battery detection functions consist of a voltage reference, a sampling block and an autozero comparator. The circuit’s primary operating
mode is brown-out protection.
The brown-out protection circuit detects when the level of VDDdrops below the minimum
voltage that guarantees proper operation. The brown-out voltage for this device is typically 1.8 volts.
If a brown-out occurs, the device enters a reset state. It stays in this state until either of
the following occurs:
• The level of VDDincreases ~0.1–0.2 volts above the brown-out voltage. This causes
the device to enter a warm reboot state.
• The level of V
drops to ~0 volts, then increases above the POR level. This places
DD
thedeviceintothe“cold start” mode of operation, identical to battery insertion.
The low battery detection feature allows the programmer to select a value for VDDat
which a warning is issued to the user. This warning may be utilized to activate an I/O
port, for example.
If low battery detection occurs, Bit 7 of register BL_CONFIG is set. Bit 6 of register
BL_CONFIG is used to indicate that Bit 7 is valid. It is left to the programmer to poll both
bits to ensure the potential warning is valid.
Bits 5–0 of register BL_CONFIG are used to program the low battery detect level. This
warning level is programmable between ~1.5–2.7 volts.
Note: The warning level can be set below the brown-out voltage level.
The formula for calculating the low battery detection threshold is located in Table 3.
Table 3. Low Battery Detection Threshold Formulas (V
VDDFalling
VDD
-----------------------------------------------------------=
1
3.887 V
0.887
---------------
BL[5:0] 71 3.887
10
AT86RF401
63
×
REF
× BL[5:0]+
V
REF
-------------
V
1–××=
DD
bo_hyst = 1 (large hysteresis) bo_hyst = 0 (small hysteresis)
VDD
BL[5:0] 71 4.05
is approximately 0.7 volts)
REF
4.05 V
×
× BL[5:0]+
REF
V
REF
-------------
V
DD
-----------------------------------------------------------=
0.887
---------------
1
63
1–××=
V
Rising
DD
VDD
BL[5:0] 71 4.22
-----------------------------------------------------------=
1
4.22 V
×
0.887
---------------
63
REF
× BL[5:0]+
V
REF
-------------
V
DD
1424D–RKE–09/02
1–××=
AT86RF401
Bit Timer A hardware assist has been included in the AT 86 R F4 01 to make transmission of data
easier. Keying of the transmitter is timed by this logic, and interrupts are generated
when data is needed by the timer or when transmission is complete. The timer also supports code that uses polling instead of interrupts. Using polling instead of interrupts may
facilitate higher bit rates. Additionally, this timer may be used to time pulses arriving at
the I/O3 pin. This enables the AT86RF401 to be used to decode the signal detected by
an external receiver chip.
Transmit Mode Bit Coding and Timing
Interrupts There are two interrupts associated with transmit mode:
Bit Timer in Receive Mode When put into receive mode, the bit timer times pulses arriving at the I/O3 pin. When
Bit coding is done by the AVR before data is sent to the bit timer. Bit timing is controlled
by the count value in the Bit Timer Count (BTCNT) register and the two most significant
bits in the Bit Timer Control Register (BTCR). Generally the time of each bit is:
P
P countval 1+()×=
xx
where
P
istheperiodofeachtimeslotand
and BTCR registers.
countval
1. Transmit Buffer Empty Interrupt: This vectors to address 0x04. Flag 0 is set, and,
2. TXDONE Interrupt: This vectors to address 0x02. Flag 2 is set, and, if enabled,
enabled, the counter counts up from zero and places that value in the BTCNT register
when an edge occurs. If the edge is rising, the DATA bit in the BTCR is set. If the edge
is falling, the DATA bit in the BTCR is reset. This mode may be used to decode signals
from a receiver chip easily.
xx
= {BTCR[7:6], BTCNT[7:0]}.
if enabled, this interrupt is generated when the timer removes the value from the
DATA bit in the BTCR. This interrupt service routine should load the next bit into
the DATA bit in the BTCR.
an interrupt is generated when the counter has counted down to zero and the
buffer is empty. This indicates that the transmission is complete. This interrupt
service routine should turn off the transmitter and turn off the bit timer using the
mode bits.
P
is the AVR clock period that is set in the PWR_CTL register.
countval
is the counter value in the BTCNT
Bit Timer Operation as a Generic Timer/Counter
1424D–RKE–09/02
The Bit Timer may be used as a generic timer by not allowing it to key off the transmitter.
An interrupt is generated after the amount of time dictated by the count value.
11
Watchdog Timer When enabling the watchdog timer, the status of the watchdog time is unknown. The
user is advised to execute a WDR instruction before enabling the watchdog. Otherwise,
the device might get reset before the first WDR after enabling is reached. To prevent the
unintentional disabling of the watchdog, a special turn-off procedure must be followed
when the watchdog is disabled. Refer to the description of the Watchdog Timer Control
Register on page 38 for details (see Register $22 in I/O Memory). The watchdog timer
prescaler determines the number of system clocks that occur before the watchdog reset
is asserted. The system clock is determined by Bits[7:5] of the AVR_CONFIG register.
Reset and Interrupt Handling
The AT86RF401 Reset and Interrupt vectors are defined in Table 4. The I-bit in the status register must be set to enable the interrupts.
Table 4. Reset and Interrupt Vectors
Vector
Number
1 $000 RESETB, Watchdog, Buttons Hardware Pin or Watchdog or
2 $002 Transmission Done (TXDONE) Bit Timer Flag 2 Interrupt
4 $004 Transmit Buffer Empty Bit Timer Flag 0 Interrupt
Program
Address Source Interrupt Definition
The most typical and general program setup for the Reset and Interrupt Vector
Addresses are:
Address Labels Code Comments
$000 jmp RESET ; Reset handler
$002 jmp BT_F2_ISR ; Bit timer flag 2 interrupt service routine
$004 jmp BT_F0_ISR ; Bit timer flag 0 interrupt service routine
$006 MAIN: <instr> xxx ; Main program start
…… ……
Reset Sources The AT86RF401 has several sources of reset:
• Power-on Reset: The device is reset when the supply voltage is applied between the
VDD and GND pins. There are 10
occurring and the part becoming active. This is to ensure that the power is stable.
• External Reset: The device is reset when a logic low level is present on the RESETB
pin. This resets all I/O Registers and puts the part into SPI mode. The I/O Registers
may be read and written by the SPI interface after two AVR System Clocks.
• Watchdog Reset: This is similar to power-on reset but is caused by the watchdog
timer and does not have a 10
• Brown-out Reset: This is caused by the battery voltage dropping below the Brownout Threshold voltage trip point.
• Button Reset (software reset): The part is placed into a special reset state by
software. The part is released from reset when a properly configured button is
activated, and the part is not in external reset or brown-out reset. In the button reset
state, most I/O registers are not reset.
6
cycles of delay between Power-on Reset
6
cycle delay prior to becoming active.
Button Reset
12
AT86RF401
1424D–RKE–09/02
AT86RF401
During power-on reset and watchdog reset, all I/O registers are set to their initial values,
and the program starts execution from address $000.
Note: The instruction placed in address $000 must be an RJMP (relative jump) instruction or a
JMP (absolute jump) to the reset handling routine. If an RJMP or JMP instruction is not
present at address $000, the part is placed into a “no program” resetstate.Thisistopro-
tect the part from fetching instructions when no program is present.
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is a minimum of four
clock cycles. After the four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program
Counter is pushed onto the stack. The vector is a jump to the interrupt routine, and this
jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter is popped back from the stack. When AVR exits from
an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note: The Status Register (SREG) is not saved by the AVR hardware. This must be performed
by user software when required.
Memory Programming
Program Memory Lock Bits
In-system Flash and EEPROM
SPI Interface Both the program and data memory arrays can be programmed using the serial SPI bus
The AT86RF401 microtransmitter provides two lock bits that can be left unprogrammed
(“1”) or can be programmed (“0”) to obtain the additional features listed in Table 5.
Table 5. Lock Bit Protection Modes
Program Lock Bits
ModeLB1 LB2
Protection Type
1 1 1 No program lock features
201
3 0 0 Same as mode 2, but Verify is also disabled
Note: The lock bits can only be erased with the Chip Erase operation.
The AT86RF401 offers 2 Kbytes (1K x 16) of in-system reprogrammable Flash program
memory and 128 bytes of EEPROM data memory. This memory can be programmed
serially via the SPI interface.
while RESETB is pulled to GND. The serial interface consists of pins SCK, SDI (input)
and SDO (output).
Further programming of the EEPROM is disabled (both program and
data memory).
1424D–RKE–09/02
When programming, an auto-erase cycle is built into the self-timed programming operation, and there is no need to first execute the Chip Erase instruction. The Chip Erase
operation sets every memory location in the EEPROM array to $FF.
Either an external system clock is supplied at pin XTAL/CLK or a crystal needs to be
connected across pins XTAL/CLK and XTALB. The minimum low and high periods for
the serial clock (SCK) input are defined as follows:
Low:
4 XTAL Clock Cycles
High:
16 XTAL Clock Cycles
13
Serial Programming Algorithm
Refer to Figure 4 (page 15), Figure 5 (page 16) and Figure 6 (page 17). To program and
verify the AT86RF401 in the serial programming mode, the following sequence is
recommended.
Power-up Sequence:
1. Apply power between VDD and GND while RESETB and SCK are set to “0”.Ifa
crystal is not connected across pins XTAL and XTALB, apply a clock signal to the
XTAL pin. If the programmer can not guarantee that SCK is held low during
power-up, RESETB must be given a positive pulse after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable instruction to pin SDI. This must occur prior to any program/erase
operations.
3. If a chip erase is performed, wait 4 ms, give RESETB a positive pulse and start
over again from Step 2.
4. The array is programmed one byte at a time by supplying the address and data
together with the appropriate Write instruction. The memory location is first automatically erased before new data is written. The next byte can be written after
4ms.
5. Any memory location can be verified by using the Read instruction, which
returns the content at the selected address at serial output SDO.
6. At the end of the programming session, RESETB must be set high to commence
normal operation.
14
AT86RF401
1424D–RKE–09/02
Data EEPROM Access from the AVR
Table 6. AT86RF401 Serial Programming Instruction Set
Instruction Format
AT86RF401
Instruction
Programming
Enable
Chip Erase
Read Program
Memory
Write Program
Memory
1010 1100 0101 0011 xxxx xxxx xxxx xxxx
1010 1100 100x xxxx xxxx xxxx xxxx xxxx
0010 H000 0000 00aa bbbb bbbb oooo oooo
0100 H000 0000 00aa bbbb bbbb iiii iiii
Read
EEPROM
1010 0000 0000 0000 xbbb bbbb oooo oooo
Memory
Write
EEPROM
1100 0000 0000 0000 xbbb bbbb iiii iiii
Memory
Write Lock Bits
I/O Read
I/O Write
1010 1100 111x x21x xxxx xxxx xxxx xxxx
10110000 0000 0000 00bbbbbb oooo oooo
11010000 0000 0000 00bbbbbb iiii iiii
Note: a = address high bits
b = address low bits
H =0:Lowbyte,1:Highbyte
o = data out
i = data in
x = don’tcare
1=lockbit1
2=lockbit2
OperationByte 1 Byte 2 Byte 3 Byte 4
Enable Serial Programming after
RESETB goes low.
Chip erase EEPROM
Read H (high or low) data o from Program
memory at word address a:b
Write H (highorlow)datai to Program
memory at word address a:b
Read data o from EEPROM memory at
address b
Write data i to EEPROM memory at
address b
Write lock bits. Set bits 21 = “0” to
program lock bits.
Read data 0 from I/O memory address b
Write data i to I/O memory address b
1424D–RKE–09/02
Figure 4. Serial Programming and Verify
AT86RF401
RESETB
GND
6 to 20 MHz
Notes: 1. When
2. When
explanation.
XTALB
XTAL
writing
,dataisclockedonthe
reading
, data is clocked on the
BAT
SCK
SDO
SDI
rising
falling
2.0–3.5V
CLOCK IN
DATA OUT
INSTR. IN, DATA IN
edge of CLK.
edge of CLK. See Figure 5 for an
15
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