Rainbow Electronics AT86RF231 User Manual

Features

• High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4

• Industry Leading Link Budget (104 dB)

• Ultra-Low Current Consumption:

• Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator

• Optimized for Low BoM Cost and Ease of Production:

• Easy to Use Interface:

• Radio Transceiver Features:

• Special IEEE 802.15.4-2006 Hardware Support:

• MAC Hardware Accelerator:

• Extended Feature Set Hardware Support:

• Industrial Temperature Range:

• I/O and Packages:

• Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003

• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210

™

ZigBee

and ISM Applications

– Receiver Sensitivity -101 dBm – Programmable Output Power from -17 dBm up to +3 dBm

–

SLEEP

–

TRX_OFF

–

RX_ON

–

BUSY_TX

– Few External Components Necessary (Crystal, Capacitors and Antenna) – Excellent ESD Robustness

– Registers, Frame Buffer and AES Accessible through Fast SPI – Only Two Microcontroller GPIO Lines Necessary – One Interrupt Pin from Radio Transceiver – Clock Output with Prescaler from Radio Transceiver

– 128-byte FIFO (SRAM) for Data Buffering – Programmable Clock Output, to Clock the Host Microcontroller or as Timer

Reference – Integrated RX/TX Switch – Fully Integrated, Fast Settling PLL to support Frequency Hopping – Battery Monitor – Fast Wake-Up Time < 0.25 msec

– FCS Computation and Clear Channel Assessment – RSSI Measurement, Energy Detection and Link Quality Indication

– Automated Acknowledgement, CSMA-CA and Retransmission – Automatic Address Filtering – Automated FCS Check

– AES 128bit Hardware Accelerator – RX/TX Indication (external RF Front-End Control) – RX Antenna Diversity – Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s – True Random Number Generation for Security Application

– -40° C to +85° C

– 32-pin Low-Profile QFN Package 5 x 5 x 0.9 mm³ – RoHS/Fully Green

0.02 µA

0.4 mA

13.2 mA

14.3 mA (at max. Transmit Power of +3 dBm)

™

Low power

2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, and ISM Applications

AT86RF231

Preliminary

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1. Pin-out Diagram

Figure 1-1. AT86RF231 Pin-out Diagram

DIG3

DIG4

AVSS

RFP

RFN

AVSS

DVSS

/R S T

AVSS

EVDD

AVDD

AVSS

31 30 29 28 27 26 25

AVSS

AT86RF

9 10111213141516

DIG1

DIG2

exposed paddl e

231

DVSS

DVD D

SLP_TR

XTAL2

XTAL1

IR Q

/SEL

MOSI

DVSS

MISO

SCLK

DVSS

CLKM

DVSS

DEVDD

Note: The exposed paddle is electrically connected to the die inside the package. It shall be soldered to

the board to ensure electrical and thermal contact and good mechanical stability.

AT86RF231

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1.1 Pin Descriptions

Table 1-1. Pin Description AT86RF231

Pins Name Type Description

AT86RF231

1 DIG3 Digital output (Ground)

2 DIG4 Digital output (Ground)

3 AVSS Ground Ground for RF signals

4 RFP RF I/O Differential RF signal

5 RFN RF I/O Differential RF signal

6 AVSS Ground Ground for RF signals

7 DVSS Ground Digital ground

8 /RST Digital input Chip reset; active low

9 DIG1 Digital output (Ground)

10 DIG2 Digital output (Ground)

11 SLP_TR Digital input Controls sleep, transmit start, receive states; active high, see Section 6.5

12 DVSS Ground Digital ground

13 DVDD Supply Regulated 1.8V voltage regulator; digital domain, see Section 9.4

14 DVDD Supply Regulated 1.8V voltage regulator; digital domain, see Section 9.4

15 DEVDD Supply External supply voltage; digital domain

16 DVSS Ground Digital ground

1. RX/TX Indicator, see Section 11.5

If disabled, pull-down enabled (AVSS)

1. RX/TX indicator (DIG3 inverted), see Section 11.5

2. If disabled, pull-down enabled (AVSS)

1. Antenna Diversity RF switch control, see Section 11.4

2. If disabled, pull-down enabled (DVSS)

1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.4

2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.6

3. If functions disabled, pull-down enabled (DVSS)

17 CLKM Digital output Master clock signal output; low if disabled, see Section 9.6

18 DVSS Ground Digital ground

19 SCLK Digital input SPI clock

20 MISO Digital output SPI data output (Master Input Slave Output)

21 DVSS Ground Digital ground

22 MOSI Digital input SPI data input (Master Output Slave Input)

23 /SEL Digital input SPI select, active low

24 IRQ Digital output

25 XTAL2 Analog input Crystal pin, see Section 9.6

26 XTAL1 Analog input Crystal pin or external clock supply, see Section 9.6

27 AVSS Ground Analog ground

28 EVDD Supply External supply voltage, analog domain

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1. Interrupt request signal; active high or active low; configurable

2. Frame Buffer Empty Indicator; active high, see Section 11.7

Table 1-1. Pin Description AT86RF231 (Continued)

Pins Name Type Description

29 AVDD Supply Regulated 1.8V voltage regulator; analog domain, see Section 9.4

30 AVSS Ground Analog ground

31 AVSS Ground Analog ground

32 AVSS Ground Analog ground

Paddle AVSS Ground Analog ground; Exposed paddle of QFN package

AT86RF231

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1.2 Analog and RF Pins

1.2.1 Supply and Ground Pins EVDD, DEVDD

EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver.

AVDD, DVDD

AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated dependent on the current radio transceiver state. The voltage regulators can be configured for external supply.

For details, refer to Section 9.4 “Voltage Regulators (AVREG, DVREG)” on page 110.

AVSS, DVSS

AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB.

AT86RF231

1.2.2 RF Pins RFN, RFP

A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital ICs such as a microcontroller.

The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed. Therefore, when connecting an RF-load providing a DC path to the power supply or ground, AC-coupling is required as indicated in Table

1-2 on page 6.

A simplified schematic of the RF front end is shown in Figure 1-2 on page 5.

Figure 1-2. Simplified RF Front-end Schematic

AT86RF231PCB

LNA

RFP RFN

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0.9V

CM Feedback

RXTX

The RF port DC values depend on the operating state, refer to Section 7. “Operating Modes” on

page 33.

In TRX_OFF state, when the analog front-end is disabled (see Section 7.1.2.3 “TRX_OFF -

Clock State” on page 35), the RF pins are pulled to ground, preventing a floating voltage.

In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30 pF to ensure the stability of this common-mode feedback loop.

In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see

Figure 1-2 on page 5, pulls the inductor center tap to ground. A DC voltage drop of 20 mV

across the on-chip inductor can be measured at the RF pins.

1.2.3 Crystal Oscillator Pins XTAL1, XTAL2

The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6 “Crystal Oscillator (XOSC)” on page 116.

When using an external clock reference signal, XTAL1 shall be used as input pin.

For further details, refer to Section 9.6.3 “External Reference Frequency Setup” on page 117.

1.2.4 Analog Pin Summary

Table 1-2. Analog Pin Behavior - DC values

Pin Values and Conditions Comments

DC level at pins RFP/RFN for various transceiver states AC coupling is required if an antenna with a DC path to ground is used.

Serial capacitance and capacitance of each pin to ground must be < 30 pF.

DC level at pins XTAL1/XTAL2 for various transceiver states Parasitic capacitance (C

load capacitance to the crystal.

DC level at pin DVDD for various transceiver states Supply pins (voltage regulator output) for the digital 1.8V voltage domain,

recommended bypass capacitor 1 µF.

DC level at pin AVDD for various transceiver states Supply pin (voltage regulator output) for the analog 1.8V voltage domain,

recommended bypass capacitor 1 µF.

RFP/RFN

XTAL1/ XTAL2

DVD D

AVD D

VDC = 0.9V (BUSY_TX) VDC = 20 mV (receive states)

= 0 mV (otherwise)

= 0.9V at both pins

= 3 pF

PA R

= 1.8V (all states, except SLEEP)

= 0 mV (otherwise)

VDC = 1.8V (all states, except P_ON, SLEEP, RESET, and TRX_OFF)

= 0 mV (otherwise)

) of the pins must be considered as additional

PA R

AT86RF231

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AT86RF231

1.3 Digital Pins

The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Section 6. “Microcontroller

Interface” on page 16.

Additional digital output signals DIG1...DIG4 are provided to control external blocks, i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see Section 11.4 “Antenna Diver-

sity” on page 142 and Section 11.5 “RX/TX Indicator” on page 147. After reset, these pins are

pulled-down to digital ground (DIG1/DIG2) or analog ground (DIG3/DIG4).

1.3.1 Driver Strength Settings

The driver strength of all digital output pins (MISO, IRQ, DIG1, DIG2, DIG3, DIG4) and CLKM pin can be configured using register 0x03 (TRX_CTRL_0), see Table 1-3 on page 7.

Table 1-3. Digital Output Driver Configuration

Pins Default Driver Strength Recommendation/Comment

MISO, IRQ, DIG1,....., DIG4 2 mA Adjustable to 2 mA, 4 mA, 6 mA and 8 mA

CLKM 4 mA Adjustable to 2 mA, 4 mA, 6 mA and 8 mA

The capacitive load should be as small as possible as, not larger than 50 pF when using the 2 mA minimum driver strength setting. Generally, the output driver strength should be adjusted to the lowest possible value in order to keep the current consumption and the emission of digital signal harmonics low.

1.3.2 Pull-Up and Pull-Down Configuration

Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON, see Section 7.1.2.1 “P_ON - Power-On after VDD” on page 34. Table 1-4 on page 7 summarizes the pull-up and pull-down configuration.

Table 1-4. Pull-Up / Pull-Down Configuration of Digital Input Pins in P_ON State

Pins H pull-up, L pull-down

/RST H

/SEL H

SCLK L

MOSI L

SLP_TR L

In all other states, there are no pull-up or pull-down resistors connected to any of the digital input pins. In RESET state, the pull-up or pull-down resistors are not enabled.

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1.3.3 Register Description Register 0x03 (TRX_CTRL_0):

The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate.

Bit 7 6 5 4 3 2 1 0

PAD_IO PAD_IO_CLKM CLKM_SHA_SEL CLKM_CTRL TRX_CTRL_0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 1 1 0 0 1

• Bit [7:6] - PAD_IO

The register bits set the output driver current of all digital output pads, except CLKM.

Table 1-5. Digital Output Driver Strength

PA D_ I O 0

Note: 1. Reset values of register bits are underlined characterized in the document.

(1)

14 mA

26 mA

38 mA

2 mA

• Bit [5:6] - PAD_IO_CLKM

The register bits set the output driver current of pin CLKM. Refer also to Section 9.6 “Crystal

Oscillator (XOSC)” on page 116.

Table 1-6. CLKM Driver Strength

PAD_IO_CLKM 0 2 mA

1 4 mA

26 mA

38 mA

• Bit 3 - CLKM_SHA_SEL

Refer to Section 9.6 “Crystal Oscillator (XOSC)” on page 116.

• Bit [2:0] - CLKM_CTRL

Refer to Section 9.6 “Crystal Oscillator (XOSC)” on page 116.

AT86RF231

8111A–AVR–05/08

2. Disclaimer

3. Overview

AT86RF231

Typical values contained in this datasheet are based on simulations and testing. Min and Max values are available when the radio transceiver has been fully characterized.

The AT86RF231 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4 and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF231 is particularly suitable for applications like:

• 2.4 GHz IEEE 802.15.4 and ZigBee systems

• Wireless sensor networks

• Industrial Control

• Residential and commercial automation

• Health care

• Consumer electronics

• PC peripherals

The AT86RF231 can be operated by using an external microcontroller like Atmel's AVR microcontrollers. A comprehensive software programming description can be found in reference [6], AT86RF231 Software Programming Model.

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4. General Circuit Description

This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed.

The AT86RF231 block diagram is shown in Figure 4-1 on page 10.

Figure 4-1. AT86RF231 Block Diagram

DIG3/4

RFP

RFN

DIG1/2

XTAL1

ext. PA and Power

Control

PLL PA

LNA

Analog Domain Digital Domain

PPF BPF Limiter ADC

Antenna Diversity

XOSC

XTAL2

AVREG

TX Data

FTN, BATMON

AGC

Configuration Register s

TX BBP

Frame

Buffer

RX BBP

RSSI

Control Logic

The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP).

DVREG

AES

SPI

(Slave)

/SEL MISO MOSI SCLK

IRQ CLKM DIG2 /RST SLP_TR

The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32length block coding (spreading) according to [1] and [2]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA).

A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.

Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V supply.

AT86RF231

8111A–AVR–05/08

AT86RF231

An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data.

The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines.

The AT86RF231 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP state.

For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio transceiver also supports alternative data rates up to 2 Mb/s.

For long-range applications or to improve the reliability of an RF connection the RF performance can further be improved by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF231 with dedicated control pins without the interaction of the microcontroller.

Additional features of the Extended Feature Set, see Section 11. “AT86RF231 Extended Fea-

ture Set” on page 128, are provided to simplify the interaction between radio transceiver and

microcontroller.

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5. Application Circuits

5.1 Basic Application Schematic

A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in

Figure 5-1 on page 12. The 50Ω single-ended RF input is transformed to the 100Ω differential

RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, capacitor C4 improve matching.

Figure 5-1. Basic Application Schematic

1 2 3 4 5 6 7 8

DIG3 DIG4

AVSS RFP RFN AVSS DVSS /RST

AVSS

DIG1

AVSS

DIG2

10 11

CB2

CB1

AVSS

AVDD

AT86RF231

SLP_TR

DVSS

CX1 CX2

EVDD

DVDD

13 14

CB3 CB4

AVSS

DVDD

15 16

XTAL1

DEVDD

XTAL

2526272829303132

XTAL2

/SEL

MOSI

DVSS

MISO SCLK

DVSS CLKM

DVSS

IRQ

24 23 22 21 20 19 18 17

Digital Interface

The power supply decoupling capacitors (CB2, CB4) are connected to the external analog supply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All decoupling and bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance.

The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of

AT86RF231

8111A–AVR–05/08

AT86RF231

the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes, refer to Section 11.3 “High Data Rate Modes” on page 137.

Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the CLKM pin is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization.

The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds.

Table 5-1. Example Bill of Materials (BoM) for Basic Application Schematic

Designator Description Value Manufacture Part Number Comment

B1 SMD balun 2.4 GHz Wuerth 748421245

CB1 CB3

CB2 CB4

CX1, CX2 Crystal load capacitor 12 pF

C4 RF matching 0.47 pF Johnstech

XTAL Crystal

LDO VREG bypass capacitor

Power Supply decoupling

CLKM low-pass filter capacitor

CLKM low-pass filter resistor

1 µF

2.2 pF

680Ω Designed for f

CX-4025 16 MHz SX-4025 16 MHz

AVX Murata

Epcos Epcos AVX

AVX Murata

ACAL Taitjen Siward

0603YD105KAT2A GRM188R61C105KA12D

06035A120JA GRP1886C1H120JA01

B37930 B37920 06035A220JAT2A

06035A229DA GRP1886C1H2R0DA01

XWBBPL-F-1 A207-011

X5R (0603)

COG (0603)

COG 5%

(0402 or 0603)

COG (0603)

Designed for f

10% 16V

50VC1, C2 RF coupling capacitor 22 pF

±0.5 pF

=1 MHz

CLKM

=1 MHz

CLKM

8111A–AVR–05/08

5.2 Extended Feature Set Application Schematic

The AT86RF231 supports additional features like:

•

Security Module (AES) see Section 11.1

•

High Data Rate Mode see Section 11.3

•

Antenna Diversity uses pins DIG1/2 see Section 11.4

•

RX/TX indicator uses pins DIG3/4 see Section 11.5

•

RX Frame Time Stamp uses pin DIG2 see Section 11.6

An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see Section 11. “AT86RF231 Extended Feature Set” on page 128, is shown in Fig-

ure 5-2 on page 14. Although this example shows all additional hardware features combined, it

is possible to use all features separately or in various combinations.

Figure 5-2. Extended Feature Application Schematic

CX1 CX2

CB2

CB1

XTAL

ANT0

ANT1

SW2

2526

2728

AVSS

XTAL2

XTAL1

DVDD

DEVDD

IRQ

/SEL

MOSI

DVSS

MISO SCLK

DVSS CLKM

DVSS

24 23 22 21 20 19 18

Digital Interface

RF-

2930

3132

AVSS

1 2

LNA

Switch

RF-

Balun

Switch

B1SW1

3 4 5 6 7 8

AVSS

DIG3 DIG4

AVSS RFP RFN AVSS DVSS /RST

DIG1

9 10111213141516

AT86RF231

DIG2

SLP_TR

AVDD

DVSS

EVDD

DVDD

CB3 CB4

In this example, a balun (B1) transforms the differential RF signal at the radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to

Figure 5-1 on page 12. The RF-Switches (SW1, SW2) separate between receive and transmit

path in an external RF front-end.

These switches are controlled by the RX/TX Indicator, represented by the differential pin pair DIG3/DIG4, refer to Section 11.5 “RX/TX Indicator” on page 147.

During receive the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch

AT86RF231

8111A–AVR–05/08

AT86RF231

control pins DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1).

During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and fed to the antennas via an RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity controlled by the differential pin pair DIG1/DIG2.

The security engine (AES) and High Data Rate Modes do not require specific circuitry to operate. The security engine (AES) has to be configured in advance, for details refer to Section 11.1

“Security Module (AES)” on page 128. The High Data Rate Modes are enabled by register bits

OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2), for details refer to Section 11.3 “High

Data Rate Modes” on page 137.

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6. Microcontroller Interface

This section describes the AT86RF231 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 6-1 on page 16. The SPI timing and protocol are described below.

Figure 6-1. Microcontroller to AT86RF231 Interface

Microcontroller AT86RF231

/SEL /SEL

MOSI MISO

SPI - Master

SCLK

GPIO1/CLK

GPIO2/IRQ

GPIO3 GPIO4

SPI

/SEL MOSI MISO SCLK

CLKM

IRQ

SLP_TR

/RST

MOSI MISO SCLK

CLKM IRQ

SLP_TR /RST

SPI - Slave

DIG2GPIO5 DIG2

Microcontrollers with a master SPI such as Atmel's AVR family interface directly to the AT86RF231. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller.

Table 6-1 on page 16 introduces the radio transceiver I/O signals and their functionality.

Table 6-1. Signal Description of Microcontroller Interface

Signal Description

/SEL SPI select signal, active low

MOSI SPI data (master output slave input) signal

MISO SPI data (master input slave output) signal

SCLK SPI clock signal

CLKM Clock output, refer to Section 9.6.4 usable as:

-microcontroller clock source

-high precision timing reference

-MAC timer reference

IRQ Interrupt request signal, further used as:

-Frame Buffer Empty Indicator, refer to Section 11.7

AT86RF231

8111A–AVR–05/08

Table 6-1. Signal Description of Microcontroller Interface (Continued)

SLP_TR Multipurpose control signal (functionality is state dependent, see Section 6.5):

/RST AT86RF231 reset signal, active low

DIG2 Optional, IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.6

6.1 SPI Timing Description

Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode.

In synchronous mode, the maximum SCLK frequency is 8 MHz.

In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal at pin CLKM is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions.

AT86RF231

-Sleep/Wakeup enable/disable SLEEP state

-TX start BUSY_TX_(ARET) state

-disable/enable CLKM RX_(AACK)_ON state

Figure 6-2 on page 17 and Figure 6-3 on page 17 illustrate the SPI timing and introduces its

parameters. The corresponding timing parameter definitions t

“Digital Interface Timing Characteristics” on page 157.

Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t

/SEL

SCLK

MOSI

MISO

Figure 6-3. SPI Timing, Detailed Drawing of Timing Parameter t1 to t

/SEL

67 5 4 3 2 1 0 67 5 4 3 2 1 0

Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0Bit 4 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0Bit 4Bit 7

Bit 7

, t6, t8 and t

- t9 are defined in Section 12.4

SCLK

MOSI

MISO

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t4t

Bit 7 Bit 6 Bit 5

Bit 7 Bit 6

Bit 5

The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H.

An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.2 “SPI Protocol” on page 19.

/SEL = L enables the MISO output driver of the AT86RF231. The MSB of MISO is valid after t1 (see Section 12.4 “Digital Interface Timing Characteristics” on page 157 parameter 12.4.3) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up resistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output driver is also enabled.

Referring to Figure 6-2 on page 17 and Figure 6-3 on page 17 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t

“Digital Interface Timing Characteristics” on page 157 parameters 12.4.5 and 12.4.6.

This SPI operational mode is commonly known as "SPI mode 0".

and t4, refer to Section 12.4

AT86RF231

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AT86RF231

6.2 SPI Protocol

Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see

Table 6-2 on page 19) with MSB first. This command byte defines the SPI access mode and

additional mode-dependent information.

Table 6-2. SPI Command Byte definition

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Mode Access Type

1 0 Register address [5:0]

1 1 Register address [5:0] Write access

Read access

001 Reserved

Frame Buffer access

0 1 1 Reserved Write access

000 Reserved

SRAM access

0 1 0 Reserved Write access

Read access

Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte (see value "PHY_STATUS" in Figure 6-4 on page 19 to Figure 6-14 on page 23) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1 “Register Description - SPI Control” on page

24.

In Figure 6-4 on page 19 to Figure 6-14 on page 23 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller.

The different access modes are described within the following sections.

6.2.1 Register Access Mode

A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select bit (bit 6), and a 6-bit register address.

On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 6-4 on page 19).

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Figure 6-4. Packet Structure - Register Read Access

byte 1 (command byte) byte 2 (data byte)

1 ADDRESS[5:0]0 XXMOSI

PHY_STATUS

Note: 1. Each SPI access can be configured to return radio controller status information

(PHY_STATUS) on MISO, for details refer to Section 6.3 “Radio Transceiver Status informa-

tion” on page 24.

(1)

READ DATA[7:0]MISO

On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 6-6 on page 20).

Figure 6-5. Packet Structure - Register Write Access

byte 1 (command byte) byte 2 (data byte)

1 ADDRESS[5:0]1 WRITE DATA[7:0]MOSI

PHY_STATUS XXMISO

Each register access must be terminated by setting /SEL = H.

Figure 6-6 on page 20 illustrates a typical SPI sequence for a register access sequence for write

and read respectively.

Figure 6-6. Example SPI Sequence - Register Access Mode

/SEL

SCLK

MOSI

MISO

WRITE COMMAND WRITE DATA READ COMMAND XX

PHY_STATUS XX PHY_STATUS READ DATA

6.2.2 Frame Buffer Access Mode

The 128 byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3 “Frame Buffer” on page 107. An introduction to the IEEE 802.15.4 frame format can be found in Section 8.1 “Introduction - IEEE 802.15.4 -

2006 Frame Format” on page 79.

Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR[7:0] indicates the frame length followed by the PSDU data, see Figure 6-7 on page 20 and

Figure 6-8 on page 21.

On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, one more byte is transferred containing the link quality indication (LQI) value of the received frame, for details refer to Section 8.6 “Link Quality

Indication (LQI)” on page 99. Figure 6-7 on page 20 illustrates the packet structure of a Frame

Buffer read access.

Figure 6-7. Packet Structure - Frame Read Access

byte 1 (command byte)

0 reserved[5:0]0MOSI

1 XX

PHY_STATUSMISO

AT86RF231

byte 2 (data byte)

PHR[7:0]

byte 3 (data byte)

PSDU[7:0]

byte n-1 (data byte)

PSDU[7:0]

byte n (data byte)

LQI[7:0]

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Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the PHR byte only.

On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8 on page 21.

Figure 6-8. Packet Structure - Frame Write Access

AT86RF231

byte 1 (command byte)

0 reserved[5:0]1MOSI

1 PHR[7:0]

PHY_STATUSMISO

The number of bytes n for one frame access is calculated as follows:

• Read Access:

• Write Access:

The maximum value of frame_length is 127 bytes. That means that n ≤ 130 for Frame Buffer read and n ≤ 129 for Frame Buffer write accesses.

Each read or write of a data byte increments automatically the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access may be terminated (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field.

The content of the Frame Buffer is only overwritten by a new received frame or a Frame Buffer write access.

byte 2 (data byte)

byte 3 (data byte)

PSDU[7:0]

byte n-1 (data byte)

PSDU[7:0]

n = 3 + frame_length

[PHY_STATUS, PHR byte, PSDU data, and LQI byte]

n = 2 + frame_length

[command byte, PHR byte, and PSDU data]

byte n (data byte)

PSDU[7:0]

Figure 6-9 on page 21 and Figure 6-10 on page 22 illustrate an example SPI sequence of a

Frame Buffer access to read and write a frame with 4-byte PSDU respectively.

Figure 6-9. Example SPI Sequence - Frame Buffer Read of a Frame with 4-byte PSDU

/SEL

SCLK

MOSI

MISO

8111A–AVR–05/08

COMMAND XX XX XX XX XX

PHY_STATUS PHR PSDU 2PSDU 1 PSDU 4PSDU 3

LQI

Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU

/SEL

SCLK

MOSI

MISO

COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4

PHY_STATUS XX XXXX XXXX

Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to Section 9.3 “Frame Buffer” on page 107.

Notes

• The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile.

• To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to

Section 11.8 “Dynamic Frame Buffer Protection” on page 154.

• It is not possible to retransmit received frames without a Frame Buffer read and write access cycle.

• For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to Section 7.2.4 “TX_ARET_ON - Transmit with Automatic Retry and

CSMA-CA Retry” on page 64.

6.2.3 SRAM Access Mode

The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may reduce the SPI traffic.

The SRAM access mode is useful, for instance, if a transmit frame is already stored in the Frame Buffer and dedicated bytes (e.g. sequence number, address field) need to be replaced before retransmitting the frame. Furthermore, it can be used to access only the LQI value after frame reception. A detailed description of the user accessible frame content can be found in Section

9.3 “Frame Buffer” on page 107.

Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 6-2 on

page 19. The following byte indicates the start address of the write or read access. The address

space is 0x00 to 0x7F for radio transceiver receive or transmit operations.

On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 6-11 on page 22).

Figure 6-11. Packet Structure - SRAM Read Access

byte 1 (command byte)

0 reserved[5:0]0MOSI

0 ADDRESS[7:0]

PHY_STATUSMISO

AT86RF231

byte 2 (address)

byte 3 (data byte)

DATA[7:0]

byte n-1 (data byte)

DATA[7:0]

byte n (data byte)

DATA[7:0]

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On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 6-12 on page 23).

On SRAM read or write accesses do not attempt to read or write bytes beyond the SRAM buffer size.

Figure 6-12. Packet Structure - SRAM Write Access

AT86RF231

byte 1 (command byte)

0 reserved[5:0]1MOSI

0 ADDRESS[7:0]

PHY_STATUSMISO

byte 2 (address)

byte 3 (data byte)

DATA[7:0]

byte n-1 (data byte)

DATA[7:0]

As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.

Figure 6-13 on page 23 and Figure 6-14 on page 23 illustrate an example SPI sequence of a

SRAM access to read and write a data package of 5-byte length respectively.

Figure 6-13. Example SPI Sequence - SRAM Read Access of a 5 byte Data Package

/SEL

SCLK

MOSI

MISO

COMMAND ADDRESS XX XX XX XX

PHY_STATUS XX DATA 2DATA 1 DATA 4DATA 3

Figure 6-14. Example SPI Sequence - SRAM Write Access of a 5 byte Data Package

byte n (data byte)

DATA[7:0]

DATA 5

/SEL

SCLK

MOSI

MISO

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COMMAND ADDRESS DATA 1 DATA 2 DATA 3 DATA 4

PHY_STATUS XX XXXX XXXX

Notes

• The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see Section 6.2.2 “Frame Buffer Access Mode” on page 20).

• If the SRAM access mode is used to read PSDU data, the Frame Buffer contains all PSDU data except the frame length byte (PHR). The frame length information can be accessed only using Frame Buffer access.

• Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to Section 9.3.3 “Interrupt Handling” on page

109.

DATA 5

6.3 Radio Transceiver Status information

Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO.

The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to 0x00.

6.3.1 Register Description - SPI Control Register 0x04 (TRX_CTRL_1):

The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver.

Bit 7 6 5 4 3 2 1 0

+0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE IRQ_MASK_MODE IRQ_POLARITY TRX_CTRL_1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

• Bit 7 - PA_EXT_EN

Refer to Section 11.5 “RX/TX Indicator” on page 147.

• Bit 6 - IRQ_2_EXT_EN

Refer to Section 11.6 “RX Frame Time Stamping” on page 150.

• Bit 5 - TX_AUTO_CRC_ON

Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85.

• Bit 4 - RX_BL_CTRL

Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152.

• Bit [3:2] - SPI_CMD_MODE

Each SPI transfer returns bytes back to the SPI master. The content of the first byte can be configured using register bits SPI_CMD_MODE. The transfer of the following status information can be configured as follows:

Table 6-3. Radio Transceiver Status Information - PHY_STATUS

SPI_CMD_MODE 0

1 monitor TRX_STATUS register; see Section 7.1.5

2 monitor PHY_RSSI register; see Section 8.3

3 monitor IRQ_STATUS register; see Section 6.6

default (empty, all bits 0x00)

• Bit 1 - IRQ_MASK_MODE

Refer to Section 6.6 “Interrupt Logic” on page 29.

• Bit 0 - IRQ_POLARITY

Refer to Section 6.6 “Interrupt Logic” on page 29.

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6.4 Radio Transceiver Identification

The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID.

6.4.1 Register Description - AT86RF231 Identification

Bit 76543210

+0x1C PART_NUM[7:0] PART_NUM

Read/WriteRRRRRRRR

Reset Value00000011

• Bit [7:0] - PART_NUM

This register contains the radio transceiver part number.

Table 6-4. Radio Transceiver Part Number

AT86RF231

PA RT _ N UM 3

AT86RF231 part number

Bit 76543210

+0x1D VERSION_NUM[7:0] VERSION_NUM

Read/WriteRRRRRRRR

Reset Value00000010

• Bit [7:0] - VERSION_NUM

This register contains the radio transceiver version number.

Table 6-5. Radio Transceiver Version Number

VERSION_NUM 2

Revision A

Bit 76543210

+0x1E MAN_ID_0[7:0] MAN_ID_O

Read/WriteRRRRRRRR

Reset Value00011111

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• Bit [7:0] - MAN_ID_0

Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not stored in registers.

Table 6-6. JEDEC Manufacturer ID - Bits [7:0]

MAN_ID_0 0x1F

Atmel JEDEC manufacturer ID, Bits [7:0] of 32 bit manufacturer ID: 00 00 00 1F

Bit 76543210

+0x1F MAN_ID_1[7:0] MAN_ID_1

Read/WriteRRRRRRRR

Reset Value00000000

• Bit [7:0] - MAN_ID_1

Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers.

Table 6-7. JEDEC Manufacturer ID - Bits [15:8]

MAN_ID_1 0x00

Atmel JEDEC manufacturer ID, Bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F

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AT86RF231

6.5 Sleep/Wake-up and Transmit Signal (SLP_TR)

Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the AT86RF231 and is summarized in Table 6-8 on page 27. The radio transceiver states are explained in detail Section 7. “Operating Modes” on page 33.

Table 6-8. SLP_TR Multi-functional Pin

Transceiver Status Function Transition Description

PLL_ON TX start Starts frame transmission

TX_ARET_ON TX start Starts TX_ARET transaction

TRX_OFF Sleep Takes the radio transceiver into SLEEP state, CLKM disabled

SLEEP Wakeup Takes the radio transceiver back into TRX_OFF state, level sensitive

RX_ON Disable CLKM Takes the radio transceiver into RX_ON_NOCLK state and disables CLKM

RX_ON_NOCLK Enable CLKM Takes the radio transceiver into RX_ON state and enables CLKM

RX_AACK_ON Disable CLKM

RX_AACK_ON_NOCLK Enable CLKM Takes the radio transceiver into RX_AACK_ON state and enables CLKM

LH⇒

HL⇒

LH⇒

HL⇒

LH⇒

HL⇒

Takes the radio transceiver into RX_AACK_ON_NOCLK state and disables CLKM

In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a TX transaction. Here pin SLP_TR is sensitive on rising edge only.

After initiating a state change by a rising edge at pin SLP_TR in radio transceiver states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge.

SLEEP state

The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF231 can be powered down to reduce the overall power consumption.

A power-down scenario is shown in Figure 6-15 on page 28. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF231 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 clock cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF231 awakes when the microcontroller releases pin SLP_TR. This concept provides the lowest possible power consumption.

The CLKM clock frequency settings for 250 kHz and 62.5 kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state.

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Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer

SLP_TR

CLKM

TR2

35 CLKM clock cycles CLKM off

Note: Timing figure t

refer to section Table 7-1 on page 42.

TR2

async timer elapses

(microcontroller)

RX_ON and RX_AACK_ON states

For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF231 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON).

If an incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames.

This can be achieved by a rising edge on pin SLP_TR that turns off the CLKM. Then the radio transceiver state changes from RX_ON or RX_AACK_ON (Extended Operating Mode) to RX_ON_NOCLK or RX_AACK_ON_NOCLK respectively.

In case that a frame is received (e.g. indicated by an IRQ_2 (RX_START) interrupt) the clock output CLKM is automatically switched on again.

This scenario is shown in Figure 6-16 on page 28. In RX_ON state, the clock at pin 17 (CLKM) is switched off after 35 clock cycles when setting the pin SLP_TR = H.

In states RX_(AACK)_ON_NOCLK and RX_(AACK)_ON, the radio transceiver current consumptions are equivalent. However, the RX_(AACK)_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM).

Figure 6-16. Wake-Up Initiated by Radio Transceiver Interrupt

radio transceiver

IRQ

SLP_TR

CLKM

35 CLKM clock cycles CLKM off

AT86RF231

typ. 5 µs

IRQ issued

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AT86RF231

6.6 Interrupt Logic

6.6.1 Overview

The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too.

Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other.

The supported interrupts for the Basic Operating Mode are summarized in Table 6-9 on page

29.

Table 6-9. Interrupt Description in Basic Operating Mode

IRQ Name Description Section

IRQ_7 (BAT_LOW) Indicates a supply voltage below the programmed threshold. Section 9.5.4

IRQ_6 (TRX_UR) Indicates a Frame Buffer access violation. Section 9.3.3

IRQ_5 (AMI) Indicates address matching. Section 7.2.3.5

Multi-functional interrupt:

1. AWAKE_END:

IRQ_4 (CCA_ED_READY)

IRQ_3 (TRX_END)

IRQ_2 (RX_START)

IRQ_1 (PLL_UNLOCK)

IRQ_0 (PLL_LOCK) Indicates PLL lock. Section 9.7.5

• Indicates radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.

2. CCA_ED_READY:

• Indicates the end of a CCA or ED measurement.

RX: Indicates the completion of a frame reception. TX: Indicates the completion of a frame transmission.

Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the PHR is valid to read from Frame Buffer.

Indicates PLL unlock. If the radio transceiver is BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately.

Section 7.1.2.3

Section 8.4.4 Section 8.5.4

Section 7.1.3 Section 7.1.3

Section 7.1.3

Section 9.7.5

The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state, refer to register 0x01 (TRX_STATUS).

After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF.

The second meaning is only valid for receive states. If the microcontroller initiates an energydetect (ED) or clear-channel-assessment (CCA) measurement, the completion of the measurement is indicated by interrupt IRQ_4 (CCA_ED_READY), refer to Section 8.4.4 “Interrupt

Handling” on page 92 and Section 8.5.4 “Interrupt Handling” on page 95 for details.

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After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.

Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the microcontroller could modify the register.

The interrupt handling in Extended Operating Mode is described in Section 7.2.5 “Interrupt Han-

dling” on page 67.

If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided.

The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H issues an interrupt request.

If "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152 for details.

6.6.2 Register Description Register 0x0E (IRQ_MASK):

he IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after power up sequence (P_ON state) or reset (RESET state).

Bit 7 6 5 4 3 2 1 0

+0x0E MASK_BAT_LOW MASK_TRX_UR MASK_AMI MA SK_CCA_ED_READY MASK_TRX_ END

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Reset Value 0 0 0 0 0 0 0 0

MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK IRQ_MASK

If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

The IRQ_STATUS register contains the status of the pending interrupt requests.

Bit 7 6 5 4 3 2 1 0

+0x0F BAT_LOW TRX_UR AMI CCA_ED_READY TRX_END RX_START PLL_UNLOCK PLL_LOCK IRQ_STATUS

Read/Write R R R R R R R R

Initial Value 0 0 0 0 0 0 0 0

By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register.

If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no timing information for this interrupt is provided.

If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

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