• Data Rates up to 64 kbps with Data Clock and no Manchester Encoding Required
• High Output Power Allowing Very Low Cost Printed Antennas:
– +10 dBm in the 915 MHz Frequency Band
– +12 dBm in the 868 MHz Frequency Band
– +14 dBm in the 433 MHz Frequency Band
• FSK Modulation: Integrated Modulator and Demodulator
• Power Savings:
– Stand Alone "Sleep" Mode and "Wake-up" Procedures
– 8 Selectable Digital Levels for Output Power
– High Data Rate and Fast Settling Time of the PLL
– Oscillator Running Mode "Ready to Start"
– Analog FSK Discriminator Allowing Measurement and Correction of Frequency
Drifts
• 100% Digital Interface through R/W Registers Including:
– Digital RSSI
–V
Readout
CC
Description
FSK
Transceiver for
ISM Radio
Applications
AT86RF211
(aka: TRX01)
The AT86RF211 (aka: TRX01) is a single chip transceiver dedicated to low power
wireless applications, optimized for licence-free ISM band operations from 400 MHz to
950 MHz. Its flexibility and unique level of integration make it a natural choice for any
system related to telemetry, remote controls, alarms, radio modems, Automatic Meter
Reading, hand held ter m i na l s, high-tech toys, etc . The AT86RF2 11 makes bidir e ctional communications affordable for applications such as secured transmissions with
hand-shake procedures, new features and services, etc. The AT86RF211 can easily
be configured to provide the optimal solution for the user’s application: choice of external filters vs. technical requirements (bandwidth, selectivity, immunity, range, etc), and
software protocol (single channel, multiple channel, FHSS). The AT86RF211 is also
well adapted to battery operated systems, as it can be powered with only 2.4V. It also
offers a “Wake Up” receiver feature to save power by alerting the associated microcontrolleronly when a valid inquiry is detected.
Rev. 1942C–WIRE–06/02
1
General Overview
General Overview of
Functioning
The AT86RF211 is a microcontroller RF peripheral: all the user has to do is to write/read
registers to setup the chip (i.e. frequency selection) or have information about parameters such as RSSI level, Vbattery, PLL lock state. All these operations are carried out via
a three-wire serial interface.
Normal ModeThechipisset-upbythe microcontroller: frequency and mode (Rx or Tx). Then it acts
like a "pipe": any data entering DATAMSG is immediately radiated (Tx) or any wanted
signal collected by the aerial i s demodulated, transferred to the microcontroller by the
same pin DATAMSG (Rx) as reshaped bits. No data is stored or processed into the
chip. See Figure 1.
Note:In Rx mode, a clock recovery DATACLK is available on the digital interface to provide the
microcontroller with a synchronization signal.
Wake-up ModeThe chip is set up in a special Rx mode called sleep mode. The chip wakes up periodi-
cally thanks to its internal timer (stand alone procedure, the microcontroller is in powerdown mod e), waiting for an expected message previously defined. If no correct
sequence is received, the periodic scan continues.
If a correct message is detected, its data field is stored into the AT86RF211 (up to 32
bits) and an interrupt is generated on the WAKEUP pin.
See Figure 2 and Figure 3.
2
AT86RF211
1942C–WIRE–06/02
Figure 1. Reception and Transmit Mode
SLE, SCK, SDATA
AT86RF211
F = Frequency of
transmitted signal
AT86RF211 (TRX01)
(for set-up)
Transmit mode
3
Companion Microcontroller
SLE, SCK, SDATA
Companion Microcontroller
(for set-up)
3
DATAMSG
AT86RF211 acts like a "pipe"
(data is transmitted with NO
processing): automatic data
to frequency conversion.
- DATAMSG = 0: F = F0
- DATAMSG = 1: F = F1
F = Frequency of
received signal
AT86RF211 (TRX01)
Receive mode
AT86RF211 also acts like a "pipe":
data (collected by the antenna)
is available on pin DATAMSG:
1942C–WIRE–06/02
DATACLK
DATAMSG
DATAMSG
DATACLK
3
Figure 2. Wake-up Overview
Header + Address
Step 1: The chip is set up in sleep mode
using the 3-wire interface (SLE, SCK,
SDATA), then Microcontroller goes to sleep,
waiting for an interrupt on WAKEUP pin
Companion Microcontroller
Figure 3. Periodical Scan
Power
Consumption
Step 2: The chip wakes-up periodically,
waiting for an expected message
(stand-alone operation)
Data stored
3
WAKEUP pin
Data field
AT86RF211 (TRX01)
Wake-up mode
Step 3: If a correct header is received (mandatory)
and address matches (if any), the data field
is then stored into AT86RF211 and WAKEUP pin is
activated (to wake-up the Microcontroller).
The Microcontroller will then read the data into one
of its registers, and begin a relevant procedure.
Note: Data field is optional: the chip can be simply
woken-up with no dedicated data.
Oscillator settling
Sleep mode
Reception mode
Short reception window
Wake Up period
Timing
4
AT86RF211
1942C–WIRE–06/02
Block Diagram
Figure 4. AT86RF211 Block Diagram
AT86RF211
Optional
These are the only blocks that depend
on the selected ISM band (433, 868
or 915 MHz): dual band applications
can be done by only switching them.
Synthesizer, loop filter, IF filter(s),
power supply decoupling are identical.
AERIAL
MATCHING
CIRCUIT
TX/RX
PA
RPOWER
PWR
CTRL
RF
FILTER
TX
LNA
GAIN MIN/MAX
Rx
MIXER1
IF1
FILTER
OSC
10.245 MHz
or
20.945 MHz
10.7 MHz
or
21.4 MHz
IF1
MIXER2
AMP
SYNTHESIZER
FREQUENCY
IF2
FILTER
CTRL
CONTROL LOGIC
DATA
MSG
455 kHz
AMP
RSSI LEVEL
DATA
SLE
SCK
CLK
IF2
SDATA
FM DISCRIMINATOR
BANDWIDTH CTRL
DATA SLICER
WAKE-UP
WAKE-UP
OPTIONAL
FILTER
1942C–WIRE–06/02
5
Pin Description
Table 1. Pinout
PinNameCommentsPinNameComments
1RPOWERFull scale output power resistor25SKFILTThreshold for data slicer
2TXGND1GND26DSINData slicer input
3RFRF input/output27DISCOUTDiscriminator output
4TXGND2GND28IF2VCCVCC
5TXGND3GND29IF2GNDGND
6TXGND4GND30IF2INIF2 amplifier input
7TXVCCVCC31IF2DEC2.2 nF to ground
8TXGND5GND32DISCFILTDiscriminator bypass
9DIGNDGND33IF2OUTIF2 mixer output
10DIVCCVCC34IF1DEC4.7 nF to ground
11DATAMSGInput/output digital message35IF1INIF1amplifierinput
12SLESerial interface enable36IF1OUTIF1 mixer output
13SCKSerial interface clock37AGNDGND
14SDATASerial interface data38AVCCVCC
15WAKEUPWake-up output39CVCC2VCC
16DATACLKData clock recovery40CGND2GND
17–Test pin: do not connect41FILT1Synthesizer output
18EVCC1VCC42VCOINSynthesizer input (VCO)
19EGND1GND43EVCC2VCC
20–Test pin: do not connect44EGND2GND
21CGND1GND45RXINLNA input from SAW filter
22CVCC1VCC46RXVCCVCC
23XTAL1Crystal input47RXGNDGND
24XTAL2Crystal output48SWOUTSwitch output
Notes:1. All VCCpins must be connected in each functional mode (Tx, Rx, wake-up, PDN)
2. To be connected:
Rxmodeonly,allbut:1,3,17,20,48
Tx mode only, all but: 15 to 17, 20, 25 to 27, 30 to 36, 45, 48
3. Pin 20 must remain unconnected or connected to ground
6
AT86RF211
1942C–WIRE–06/02
AT86RF211
Detailed Description
Frequency Synthesis
Crystal Reference OscillatorThe reference cloc k i s based on a classical Colpitts architecture with three external
capacitors.
An XTAL with load capac itor in the range of 10 pF - 20 pF is recommended. The bias
circuitry of the oscillator is optimized to produce a low drive level for the XTAL. T his
reduces XTAL aging. Any standard, parallel mode 10.245 MHz or 20.945 MHz crystal
canbeused.
Note:The PLL is activated only when the o scillator is stabilized.
Figure 5. Crystal Oscillator Inputs
XTAL1
XTAL2
Figure 6. Typical Networks
(2)
XTAL2
C2 = 56 pF
CL = 20 pF
(1)
33 pF
XTAL1
C1 = 68 pF
6.5/30 pF
XTAL2
C2 = 68 pF
(2)
XTAL1
C1 = 82 pF
CL = 16 pF
Notes:1. Various load capacitance (CL) crystals can be used. In case CLdiffers of 16 pF or 20 pF, the surrounding network (C1, C2)
2. Thanks to the fine steps of the synthesizer (200 Hz), the trimmer capacitor can be replaced by a software adjustment.
(1)
15 pF
must be re-calculated.
6.5/30 pF
SynthesizerA high-speed, high-resolution multi-loop synthesizer is integrated. The synthesizer can
operate within two frequency bands: 400 MHz to 480 MHz and 800 MHz to 950 MHz. All
channels in these two bands can be selected through software programming (registers
F0 to F3). All circuitry is on-chip with the exception of the PLL loop filter. The phase
comparison is made thanks to a charge pump topology. Typical charge pump current is
225 µA.
1942C–WIRE–06/02
7
Figure 7. Synthesizer Loop Filter Schematic
P F D
&
C H P
Fref
VCO
FILT1
Note:The PLL loop filter can be designed to optimize the phase noise around the carrier.
Three configurations can be suggested, regarding the application and channel spacing:
- Narrow band: (14.7 kΩ + 2.2 nF) // 220 pF
-Typical:(3.3kΩ + 5.6 nF) // 560 pF
- High datarates: (10 kΩ + 1 nF) // 100 pF
VCOIN
8
AT86RF211
1942C–WIRE–06/02
Receiver Description
)
Figure 8. Typical Expected Currents in Rx Mode
32.00
AT86RF211
Supply Current - R x Mode
868 or
915 MHz
30.00
Isupply (mA)
28.00
26.00
2.252.502.753.003.253.503.754.004.25
Vsupply (V)
Detailed Current - Rx Mode
10.00
8.00
6.00
4.00
Suppl y Currents (mA
2.00
0.00
2.252.502.753.003.253.503.754.004.25
Vsupply (V)
433 MHz
EVCC2
EVCC1
RXVCC
CVCC2
CVCC1
AVCC
DIVCC
IF2VCC
TXVCC
1942C–WIRE–06/02
9
Overview and Choice of
Intermediate Frequencies
For selectivity and flexibility purpose, a classical and robust 2 IF superheterodyne architecture has been selected for the AT86RF211. In order to minimize the external
components cost, the most popular IF values have been chosen. The impedances of the
input/output o f the mixing s tages have been internally matched to the most usual
ceramic filter impedances.
Two typical IF values are suggested:
•10.7 MHz is the most popular option.
•21.4 MHz: the image frequency is far enough from the carrier frequency to enable
the use of a front-end ceramic filter instead of a SAW filter. It is also noticeable that
21.4 MHz quartz filters usually have more abrupt slopes than 10.7 MHz ceramic
filters.
Rx - Tx SwitchA S PST switch is integrated. In the transmission mode, it protects the LNA input from
the large voltage swings of the PA output (up to several volts peak-to-pea k) , which is
switched to a high impedance state. It is automatically turned ON or OFF by the RX/TX
control bit. The insertion loss is about 2 dB and the reverse isolation about 30 dB i n a
300Ω environment.
Image Rejection and RF FilterThe immunity of the AT86RF211 can be improved with an external band-pass filter.
For example, when using a SAW Filter, this device must be matched with the LNA input
and the switch output. The following scheme gives the typical implementation for an
868 MHz application with a 50Ω/50Ω SAW filter.
Figure 9. Typical 50Ω SAW Filter Implementation in the 868 MHz Band
These inductors can be printed
SWOUT (pin 48)
SPST Switch
SAW
50Ω
See Table 2 for precise matching information.
The SAW filter can be replaced by a TEM ceramic, helicoidal or a ceramic coax λ/4 res-
onator designed as a narrow band-pass filter. For instance, with an IF selected at
10.7 MHz, a -3 dB bandwidth of 5 MHz, with an insertion loss of 1 dB and an image
rejection of 12 dB can be achieved with the following:
12 nH2.2 nH
RXIN
(pin 45)
10
AT86RF211
1942C–WIRE–06/02
Figure 10. TEM Filter
AT86RF211
1
/4
TEM
pF
1 pF
Zc = 7Ω
l = 0.75
(19 mm)
Such a filter also p rovi des an out-of-band interference reje ction greater than 20dB,
40MHzawayfrom433MHz.
First LNA/MixerThe main characteristics of the LNA/Mixer are typically:
•Voltage gain: 17 dB for the LNA/Mixer; 11 dB if gain min. is selected
•Bandwidth: 1.2 GHz
•Noise figure of LNA alone: 3 dB at 900 MHz, best matching
•Noise figure of LNA + mixer:
8 dB at 900 MHz, with maximum gain and best matching
12 dB at 900 MHz, with minimum gain and best matching
•1 dB compression point: -20 dBm at the input of LNA
Notes:1. RXIN: impedance to be seen by LNA input for NF optimization purpose
2. SWOUT: output impedance of the RF switch
The gain is programmable through bit 25 of CTRL1 register (6dB attenuation when min
gain is selected). The choice for the matching between the SWITCH and the LNA
depends main ly on the chosen SAW filter. Usual ly in/out impedance o f SAW filters is
50Ω, but other ones can be implemented and the matching network recalculated thanks
to the previous impedance table.
The LNA is directly coupled to the first mixer. Input and output of the LNA/Mixer must be
connected through a capacitive link because of thei r internal DC coupling. A SAW or
ceramic filter provides such a link.
1942C–WIRE–06/02
11
Figure 11. Schematic Input of the LNA
Figure 12. Schematic Output of the Mixer
The first mixer translates the input RF signal down to 10.7 MHz or 21.4 MHz as chosen
by the user. The local oscillator is provided by the same synthesizer which will generate
a local frequency 10.7 MHz or 21.4 MHz away from the Tx carrier frequency.
The output impedance of the mixer is 330Ω with a 20% accuracy, so that low cost, standard 10.7 MHz ceramic filters can be directly driven. Other IFs may be chosen thanks to
the high bandwidth (50 MHz) of the mixer.
IF1 filteringA popular ceramic filter is used to reject the second image frequency and provide a first
level of filtering.
The IF1 filter can however be removed; it leads to a sensitivity reduction of about 3 dB
(the substitution coupling capacitor should be > 100 pF).
IF1 Gain and Second MixerThe input impedance of the IF1 amplifier is naturally 330Ω to match the input filter. The
voltage gain, i.e. gain at 10.7 MHz or 21.4 MHz added to the conversion gain at 455 kHz
is typically 14 dB when loaded by 1700Ω. The second mixer operates at a fixed LO frequency of 10.245 MHz or 20.945 MHz. Its output impedance is 1700Ω in parallel with 20
pF.
IF1OUT
12
AT86RF211
1942C–WIRE–06/02
Figure 13. IF1 Filtering
IF1
AT86RF211
Filter
IF1OUT
(pin 36)
330 Ω
C > 100 pF
Figure 14. Schematic Input of IF1 Amplifier
IF1IN
IF1DEC
330Ω
IF1IN
(pin 35)
"or"
330 Ω
20 kΩ
Figure 15. Schematic Output of the Second Mixer
1600 Ω
IF2OUT
IF2 Filtering and GainIF2 filtering achieves a narrow channel selection. In case it is not used, it should be
replaced by a > 1 nF coupling capacitor, thus the IF1 filter is the only part achieving the
channel selection. Available commercial filters with a 35 kHz BW allow data rates up to
19.6 kbps if crystal temperature drifts are very low.
For faste r communications and/or wider channelization, this ceramic filter can be
replaced by an LC band-pass filter as proposed hereafter.
1942C–WIRE–06/02
13
Figure 16. LC Band-pass Filter
10 nF
Filter
gain
F1
F2
~ F1
40 kHz or higher
~ F2
10 nF
global response
Frequency
•10 nF capacitors cut DC response forward and backward.
•The first network has the low cut-off frequency.
•The second network has the high cut-off frequency.
IF2 Amplifier ChainThe input impedance of the IF2 amplifier is 1700Ω. This value enables the use of popu-
lar filters with impedance between 1500Ω and 2000Ω. It is directly connected to the FSK
demodulator. The bandwidth is internally limited to 1 MHz to minimize the noise before
the discriminator. It acts like a band pass filter centered at 455 kHz with capacitive coupling between stages of amplifier and mixer. Total voltage gain is typically 86 dB.
Thanks to the capacitive coupling, no slow DC feedback loop is needed enabling a fast
turn on time. IF2DEC has to be decoupled with at least 2.2 nF.
Figure 17. Input of the IF2 Amplifier Schematic
IF2IN
1900 Ω
14
AT86RF211
IF2DEC
1942C–WIRE–06/02
AT86RF211
RSSI OutputThe RSSI value can be read as a 6 bits word in the STATUS register. Its value is linear
in dB as plotted below:
Figure 18. Typical RSSI output (board implementation, T = 25°C, V
CC
=3V)
RSSI Output
70
60
50
40
30
RSSI Code
20
10
0
-110-100-90-80-70-60-50-40-30
Note:Should the RSSI be required for accuratemeasurement purpose (precision better than 5 dB), then it is possible to measure one
value with a calibrated RF source and store it into the microcontroller, during the production testing.
Di spersi on: +/-5 dB
Dynamic Range: 50dB
Power Level at Antenna Input Port (dBm)
The RSSI dynamic range is 50 dB from -95 dBm to -45 dBm RF input signal power, over
temperature and power supply ranges. The RSSI LSB’s value weighs about 1.3 dB i n
the linear area. The RSSI value is measured from the IF2 chain.
The RSSI is periodically measured thanks to a successive approxi mati on ADC with a
12 µs clock. Thereafter, the time needed to complete the right code depends on the
power step: a 10 dB step on the aerial leads to a 10/1.3 = 8 clock cycles, i.e. 96 µs (full
range from code 0 to 63 = 756 µs). Its value can be compared with a user predefined
value (TRSSI), so that the demodulated data is enabled only if the RSSI value is above
this threshold. Some hysteresis effect may be added (see CTRL1 register’s content).
The AT86RF211 also has the possibility to measure another voltage. The ADC measuring the RSSI can be turned into voltage or discriminator output DC level measurement.
1942C–WIRE–06/02
15
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