Rainbow Electronics AT84AD004 User Manual

Features

• Dual ADC with 8-bit Resolution

• 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode

• Single or 1:2 Demultiplexed Output

• LVDS Output Format (100Ω)

• 500 mVpp Analog Input (Differential Only)

• Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

• Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)

• LQFP144 Package

• Temperature Range:

– 0°C < T
– -40°C < T

• 3-wire Serial Interface

– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:

– Internal Static or Dynamic Built-In Test (BIT)

< 70°C (Commercial Grade)

A

< 85°C (Industrial Grade)

A

Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel

Dual 8-bit
500 Msps ADC

AT84AD004
Smart ADC

Performance

• Low Power Consumption: 0.7W per Channel

• Power Consumption in Standby Mode: 120 mW

• 1 GHz Full Power Input Bandwidth (-3 dB)

• SNR = 43 dB Typ (7.0 ENOB), THD = -53 dBc, SFDR = -55 dBc at Fs = 500 Msps

Fin = 250 MHz

• 2-tone IMD3: -54 dBc (249 MHz, 251 MHz) at 500 Msps

• DNL = 0.25 LSB, INL = 0.5 LSB

• Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)

• Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)

• Low Bit Error Rate (10

-15

) at 500 Msps

Application

• Instrumentation

• Satellite Receivers

• Direct RF Down Conversion

• WLAN

5390A–BDC–06/04

1

Description The AT84AD004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W

power consumption and excellent digitizing accuracy. It integrates dual on-chip
track/holds that provide an enhanced dynamic performance with a sampling rate of up to
500 Msps and an input frequency bandwidth of 1 GHz. The dual concept, the integrated
demultiplexer and the easy interleaving mode make this device user-friendly for all dual
channel applications, such as direct RF conversion or data acquisition. The smart func­tion of the 3-wire serial interface eliminates the need for external components, which are
usually necessary for gain and offset tuning and setting of other parameters, leading to
space and power reduction as well as system flexibility.

Functional Description

The AT84AD004 is a dual 8-bit 500 Msps ADC based on advanced high-speed
BiCMOS technology.

Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H),
and an 8-bit flash-like architecture core analog-to-digital converter. The output data is
followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω).

Two over-range bits are provided for adjustment of the external gain control on each
channel.

A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several
adjustments:

• Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus
interface (steps of 0.18 dB)

• Analog input switch: both ADCs can convert the same analog input signal I or Q

• Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the
output frequency on the data ready output signal

• Partial or full standby on channel I or channel Q

• Clock selection:
– Two independent clocks: CLKI and CLKQ
– One master clock (CLKI) with the same phase for channel I and channel Q
– One master clock but with two phases (CLKI for channel I and CLKIB for

channel Q)

• ISA: Internal Settling Adjustment on channel I and channel Q

• FiSDA: Fine Sampling Delay Adjustment on channel Q

• Adjustable Data Ready Output Delay on both channels

• Test mode: decimation mode (by 16), Built-in Test

A calibration phase is provided to set the two DC offsets of channel I and channel Q
close to code 127.5 and calibrate the two gains to achieve a maximum difference of

0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial

interface.
The AT84AD004 operates in fully differential mode from the analog inputs up to the dig-

ital outputs. The AT84AD004 features a full-power input bandwidth of 1 GHz.

2

AT84AD004

5390A–BDC–06/04

Figure 1. Simplified Block Diagram

AT84AD004

VINI

VINIB

VINQ

VINQB

INPUT

MUX

CLKI

DDRB

Gain control I
Calibration
Gain/offset
ISA I

Gain control Q
Calibration
Gain/offset
ISA Q & FiSDA

+

S/H

-

Input switch

+

S/H

-

Clock Buffer

ADC

ADC

8bit

8bit

Q

Divider

2 to16

DoirI

I

8

BIT

DoirQ

8

DMUX

DMUX

DRDA

I

1:2

or

1:1

I

DMUX control

3-wire Serial Interface

3WSI

DMUX control

1:2

or

1:1

Q

LVDS

Clock
Buffer

LVDS
Buffer

I

LVDS
buffer

Q

16

16

16

16

2

CLKIO

DOAI
DOAIN

DOBI
DOBIN

2

DOIRI
DOIRIN

Data
Clock

Ldn

Mode

2

DOIRQ
DOIRQN

DOAQ
DOAQN

DOBQ
DOBQN

CLKQ

DDRB

Clock Buffer

Divider
2 to 16

DRDA

Q

LVDS
Clock
Buffer

2

CLKQO

5390A–BDC–06/04

3

Typical Applications

Figure 2. Satellite Receiver Application

Satellite

Dish

I

Control Functions:
Clock and Carrier

Recovery...

Q

Low Noise Converter

(Connected to the Dish)

Bandpass
Amplifier

11..12 GHz

Local Oscillator

Bandpass
Amplifier

I

Q

Demodulation

1..2 GHz

Low Pass

Filter

AT84AD004

Clock

Satellite Tuner

Tunable

Band Filter

Synthesizer

1.5 … 2.5 GHz

I

Local Oscillator

Q

Q

Band Filter

0

90

Quadrature

IF

AGC

4

AT84AD004

5390A–BDC–06/04

Figure 3. Dual Channel Digital Oscilloscope Application

DAC

Channel B

A

Channel A

A

Gain

ADC B

DAC

Offset

DAC

Offset

Analog Switch

DAC
Gain

ADC A

FISO
RAM

AT84AD004

Display

µP

Channel Mode

Selection

Clock
Selection

Timing

Circuit

DACs

Smart Dual

ADC

DACs

Absolute Maximum Ratings

Parameter Symbol Value Unit

Analog positive supply voltage V

Digital positive supply voltage V

Output supply voltage V

Maximum difference between V

Minimum V

CCO

Analog input voltage

CCA

and V

CCD

V

CCA

V

or V

V

INI

V

or V

INQ

Digital input voltage V

Clock input voltage V

Maximum difference between V

CLK

and V

CLKB

CLK

V

or VC

CLK

Maximum junction temperature T

Storage temperature T

Lead temperature (soldering 10s) T

CCA

CCD

CCO

to V

CCO

D

- V

J

stg

leads

CCD

INIB
INQB

LKB

CLKB

3.6 V

3.6 V

3.6 V

± 0.8 V

1.6 V

1/-1 V

-0.3 to V

-0.3 to V

+ 0.3 V

CCD

+ 0.3 V

CCD

-2 to 2 V

125 °C

-65 to 150 °C
300 °C

Note: Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are

within specified operating conditions. Long exposure to maximum ratings may affect device reliability.

5

5390A–BDC–06/04

Recommended Conditions of Use

Parameter Symbol Comments Recommended Value Unit

Analog supply voltage V

Digital supply voltage V

Output supply voltage V

Differential analog input voltage (full-scale)

CCA

CCD

CCO

V

-V

INQ

-V

IniB

or

INQB

INi

V

Differential clock input level Vinclk 600 mVpp

3.3 V

3.3 V

2.25 V

500 mVpp

Internal Settling Adjustment (ISA) with a 3-wire
serial interface for channel I and channel Q

Operating temperature range T

ISA -50 ps

Ambient

Commercial grade

Industrial grade

0 < T

-40 < T

< 70

A

< 85

A

Electrical Operating Characteristics

Unless otherwise specified:

•V

•V

• LVDS digital outputs (100Ω)

•T

• Full temperature range: 0°C < T

Table 1. Electrical Operating Characteristics in Nominal Conditions

Parameter Symbol Min Typ Max Unit

= 3.3V; V

CCA

- V

INI

INB

(typical) = 25°C

A

or V

CCD

INQ

(industrial grade)

= 3.3V; V

- V

INQB

= 2.25V

CCO

= 500 mVpp full-scale differential input

< 70°C (commercial grade) or -40°C < TA < 85°C

A

°C

Resolution 8Bits
Power Requirements

Positive supply voltage

- Analog

- Digital

Output digital (LVDS) and serial interface

V
V

V

CCA
CCD

CCO

3.15

3.15

2.0

3.3

3.3

2.25

3.45

3.45

2.5

V
V
V

Supply current (typical conditions)

- Analog

- Digital

- Output

I

CCA

I

CCD

I

CCO

150
230
100

180
275
120

mA
mA
mA

Supply current (1:2 DMUX mode)

- Analog

- Digital

- Output

6

AT84AD004

I

CCA

I

CCD

I

CCO

150
260
175

180
310
210

mA
mA

5390A–BDC–06/04

AT84AD004

Table 1. Electrical Operating Characteristics in Nominal Conditions (Continued)

Parameter Symbol Min Typ Max Unit

Supply current (2 input clocks, 1:2 DMUX mode)

- Analog

- Digital

- Output

Supply current
(1 channel only, 1:1 DMUX mode)

- Analog

- Digital

- Output

Supply current
(1 channel only, 1:2 DMUX mode)

- Analog

- Digital

- Output

I

CCA

I

CCD

I

CCO

I

CCA

I

CCD

I

CCO

I

CCA

I

CCD

I

CCO

150
290
180

80

160

55

80

170

90

180
350
215

95

190

65

95
205
110

mA

mA
mA

mA

mA
mA

mA

Supply current (full standby mode)

- Analog

- Digital

- Output

Nominal dissipation
(1 clock, 1:1 DMUX mode, 2 channels)

I

CCA

I

CCD

I

CCO

P

12
24

3

D

1.4 1.7 W

17

34

5

mA
mA
mA

Nominal dissipation (full standby mode) stbpd 120 mW

Analog Inputs

- V
or

- V

IniB

mV

450 500 550

INQB

IN

2pF

mV

V

INi

Full-scale differential analog input voltage

V

INQ

Analog input capacitance I and Q C

Full power input bandwidth (-3 dB) FPBW 1.0 GHz

Gain flatness (-0.5 dB) 400 MHz

Clock Input

Logic compatibility for clock inputs and DDRB
Reset (pins 124,125,126,127,128,129)

PECL/ECL/LVDS

PECL/LVDS clock inputs voltages
(V

CLKI/IN

or V

CLKQ/QN

)

- V

V

IL

IH

600 mV

Differential logical level

Clock input power level -9 0 6 dBm

Clock input capacitance 2 pF

Digital Outputs

Logic compatibility for digital outputs
(depending on the value of V

CCO

)

Differential output voltage swings
(assuming V

5390A–BDC–06/04

= 2.25V)

CCO

V

OD

LV DS

220 270 350 mV

7

Table 1. Electrical Operating Characteristics in Nominal Conditions (Continued)

Parameter Symbol Min Typ Max Unit

Output levels (assuming V
100Ω differentially terminated
Logic 0 voltage
Logic 1 voltage

Output offset voltage (assuming V
100Ω differentially terminated

Output impedance R

Output current (shorted output) 12 mA

Output current (grounded output) 30 mA

Output level drift with temperature 1.3 mV/°C

Digital Input (Serial Interface)

Maximum clock frequency (input clk) Fclk 50 MHz

Input logical level 0 (clk, mode, data, ldn) -0.4 0 0.4 V

= 2.25V)

CCO

= 2.25V)

CCO

V

OL

V

OH

V

OS

O

1.0

1.25

1125 1250 1325 mV

1.1

1.35

1.2

1.45

50 W

V
V

Input logical level 1 (clk, mode, data, ldn) V

- 0.4 V

CCO

- 0.4 V

CCO

+ 0.4 V

CCO

Output logical level 0 (cal) -0.4 0 0.4 V

Output logical level 1 (cal) V

- 0.4 V

CCO

CCO

V

+ 0.4 V

CCO

Maximum output load (cal) 15 pF

Note: The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off.

Table 2. Electrical Operating Characteristics

Parameter Symbol Min Typ Max Unit
DC Accuracy

No missing code Guaranteed over specified temperature range

Differential non-linearity DNL 0.25 0.6 LSB

Integral non-linearity INL 0.5 1 LSB

Gain error (single channel I or Q) with calibration -0.5 0 0.5 LSB

Input offset matching (single channel I or Q) with calibration -0.5 0 0.5 LSB
Gain error drift against temperature

Gain error drift against V

CCA

0.062

0.064

Mean output offset code with calibration 127 127.5 128 LSB

Transient Performance

Bit Error Rate
Fs = 1 Gsps

BER 10

-15

10

-12

Fin = 250 MHz

LSB/°C

LSB/mV

Error/

sample

ADC settling time channel I or Q
(between 10% - 90% of output response)

-V

Ini

= 500 mVpp

iniB

V

TS 170 ps

Note: The gain setting is 0 dB, two clock inputs, no standby mode [full power mode], 1:2 DMUX, calibration on.

8

AT84AD004

5390A–BDC–06/04

AT84AD004

Table 3. AC Performances

Parameter Symbol Min Typ Max Unit
AC Performance
Signal-to-noise Ratio

Fs = 500 Msps Fin = 20 MHz

Fs = 500 Msps Fin = 250 MHz 41 43 dBc

Fs = 500 Msps Fin = 500 MHz 42 dBc

Effective Number of Bits

Fs = 500 Msps Fin = 20 MHz

Fs = 500 Msps Fin = 250 MHz 6.7 7.0 Bits

Fs = 500 Msps Fin = 500 MHz 6.8 Bits

Total Harmonic Distortion (First 9 Harmonics)

Fs = 500 Msps Fin = 20 MHz

Fs = 500 Msps Fin = 250 MHz 47 53 dBc

Fs = 500 Msps Fin = 500 MHz 51 dBc

Spurious Free Dynamic Range

Fs = 500 Msps Fin = 20 MHz

Fs = 500 Msps Fin = 250 MHz 49 55 dBc

Fs = 500 Msps Fin = 500 MHz 54 dBc

Two-tone Inter-modulation Distortion (Single Channel)

= 249 MHz , F

F

IN1

Phase matching using auto-calibration and FiSDA
in interlace mode (channel I and Q)
Fin = 250 MHz
Fs = 500 Msps

= 251 MHz at Fs = 500 Msps IMD -54 dBc

IN2

SNR

ENOB

|THD|

|SFDR|

dϕ -0.7 0 0.7 °

42 44 dBc

77.2 Bits

48 54 dBc

50 56 dBc

Crosstalk channel I versus channel Q
Fin = 250 MHz, Fs = 500 Msps

Notes: 1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode,

1:1 DMUX, ISA = -50 ps.

2. Measured on the AT84AD004TD-EB Evaluation Board.

5390A–BDC–06/04

(2)

Cr -55 dB

9

Table 4. AC Performances in Interlace Mode

Parameter Symbol Min Typ Max Unit
Interlace Mode

Maximum equivalent clock frequency Fint = 2 x Fs
Where Fs = external clock frequency

Minimum clock frequency F

F

int

int

1Gsps

20 Msps

Differential non-linearity in interlace mode intDNL 0.25 LSB

Integral non-linearity in interlace mode intINL 0.5 LSB

Signal-to-noise Ratio in Interlace Mode

Fint = 1 Gsps Fin = 20 MHz

42 dBc

iSNR

Fint = 1 Gsps Fin = 250 MHz 40 dBc

Effective Number of Bits in Interlace Mode

Fint = 1 Gsps Fin = 20 MHz

7.1 Bits

iENOB

Fint = 1 Gsps Fin = 250 MHz 6.8 Bits

Total Harmonic Distortion in Interlace Mode

Fint = 1 Gsps Fin = 20 MHz

52 dBc

|iTHD|

Fint = 1 Gsps Fin = 250 MHz 49 dBc

Spurious Free Dynamic Range in Interlace Mode

Fint = 1 Gsps Fin = 20 MHz

|iSFDR|

54 dBc

Fint = 1 Gsps Fin = 250 MHz 52 dBc

Two-tone Inter-modulation Distortion (Single Channel) in Interlace Mode

= 249 MHz , F

F

IN1

= 251 MHz at F

IN2

= 1 Gsps iIMD -54 dBc

int

Note: One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration

phase is necessary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment.

10

AT84AD004

5390A–BDC–06/04

AT84AD004

Table 5. Switching Performances

Parameter Symbol Min Typ Max Unit
Switching Performance and Characteristics - See “Timing Diagrams” on page 12.

Maximum operating clock frequency F

Minimum clock frequency (no transparent mode)

Minimum clock frequency (with transparent mode) 1 Ksps

S

F

S

500 Msps

10 Msps

Minimum clock pulse width [high]
(No transparent mode)

Minimum clock pulse width [low]
(No transparent mode)

Aperture delay: nominal mode with ISA & FiSDA TA 1 ns

Aperture uncertainty Jitter 0.4 ps (rms)

Data output delay between input clock and data TDO 3.8 ns

Data Ready Output Delay TDR 3 ns

Data Ready Reset to Data Ready TRDR 2 ns

Data Output Delay with Data Ready TD2

Data Ready (CLKO) Delay Adjust (140 ps steps) Tdrda range -560 to 420 ps

Output skew 50 100 ps

Output rise/fall time for DATA (20% - 80%) TR/TF 300 350 500 ps

Output rise/fall time for DATA READY (20% - 80%) TR/TF 300 350 500 ps

Data pipeline delay (nominal mode)

Data pipeline delay (nominal mode) in S/H
transparent mode

DDRB recommended pulse width 1 ns

TC1 0.4 1 50 ns

TC2 0.4 1 50 ns

1/2 Fs

+Tdrda

3 (port B)

3.5 (port A, 1:1 DMUX mode)

TPD

4 (port A, 1:2 DMUX mode)

2.5 (port B)

3 (port A, 1:1 DMUX mode)

3.5 (port A, 1:2 DMUX mode)

Clock cycles

ps

5390A–BDC–06/04

11

Timing Diagrams

Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 1 X 0 0

TA

VIN

N + 1

N

N + 2

CLKI or CLKQ

Pipeline delay = 4 clock cycles

DOIA[0:7]

or DOQA[0:7]

DOIB[0:7]

or DOQB[0:7]

N - 4

Pipeline delay = 3 clock cycles

N - 3 N - 1 N +1

TD2

CLKOI or CLKOQ

(= CLKI/2)

CLKOI or CLKOQ

(= CLKI/4)

Figure 5. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 0 X 0 0

N + 3

N - 2

Programmable delay

TDO

N

TDO

12

TA

VIN

N

N + 1

CLKI or CLKQ

Pipeline delay = 3.5 clock cycles

DOIA[0:7]

or DOQA[0:7]

N - 3

CLKOI or CLKOQ

DOIB[0:7] and DOQB[0:7] are high impedance

AT84AD004

N + 2

N - 2

N + 3

N - 1

TDO

N

N + 1

5390A–BDC–06/04

Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 1 X 0 0

AT84AD004

TA

VIN

N

CLKI

DOIA[0:7]

DOIB[0:7]

DOQA[0:7]

DOQB[0:7]

CLKOI

(= CLKI/2)

CLKOI

(= CLKI/4)

CLKOQ is high impedance

N + 1

Pipeline delay = 4 clock cycles

NI - 4

Pipeline delay = 3 clock cycles

NI - 3 NI - 1 NI +1

NQ - 4 NQ - 2 NQ

NQ - 3 NQ - 1 NQ +1

N + 2

TD2

N + 3

NI - 2

TDO

NI

TDO

5390A–BDC–06/04

13

Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0

TA

VIN

N

N + 1

CLKI

Pipeline delay = 3.5 clock cycles

DOIA[0:7]

DOQA[0:7]

N - 3

N - 3

CLKOI

DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance

N + 2

N - 2

N - 2

N + 3

N - 1

N - 1

TDO

N

N

N + 1

N + 1

14

AT84AD004

5390A–BDC–06/04

Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 X 0 0

N + 4

N + 5

VIN

CLKI

CLKIN

TA

N + 2

N + 1

N

N + 3

AT84AD004

N + 6

DOQA[0:7]

DOQB[0:7]

DOIA[0:7]

DOIB[0:7]

CLKOI

(= CLKI/2)

CLKOI

(= CLKI/4)

CLKOQ is high impedance

Pipeline delay = 4 clock cycles

N - 8

Pipeline delay = 3 clock cycles

N - 6 N - 2 N + 2

Pipeline delay = 3.5 clock cycles

N - 7 N - 3 N + 1

N - 5 N - 1 N + 3

TD2

N - 4

TDO

N

TDO

TDO

5390A–BDC–06/04

15

Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q

Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 0 X 0 0

N + 4

N + 5

VIN

TA

N + 2

N + 1

N

N + 3

CLKI

CLKIN

N + 6

Pipeline delay = 3.5 clock cycles

DOQA[0:7]

DOIA[0:7]

N - 6

Pipeline delay = 3 clock cycles

N - 5

N - 4

N - 3

CLKOI

(= CLKI/2)

DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance

Figure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)

Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0

N + 16

VIN

N - 16

16 clock cycles

N

N - 2

N - 1

N + 32

TDO

TDO

N

N + 1

N + 2

N + 3

CLKI

DOIA[0:7]

DOQA[0:7]

N - 16

N - 16

N

N

CLKOI

DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance

Notes: 1. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16.

16

AT84AD004

N + 16 N + 32 N + 48

N + 16 N + 32 N + 48

5390A–BDC–06/04

Figure 11. Data Ready Reset

AT84AD004

500 ps

CLKI or

CLKQ

1 ns min

DDRB

Figure 12. Data Ready Reset 1:1 DMUX Mode

TA

VIN

Clock in

Reset

CLKI or

CLKQ

DOIA[0:7] or

DOQA[0:7]

N

ALLOWED

N + 1

500 ps

FORBIDDENFORBIDDEN

ALLOWED

Pipeline Delay + TDO

N

TDR

CLKOI or

CLKOQ

2 ns

TDR

DDRB

1 ns min

Note: The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset

occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then
only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes
the output clock return to normal mode (after TDR).

5390A–BDC–06/04

17

Figure 13. Data Ready Reset 1:2 DMUX Mode

TA

VIN

CLKI or

CLKQ

DOIA[0:7] or

DOQA[0:7]

Clock in

Reset

N

N + 1

Pipeline Delay + TDO

N

DOIB[0:7] or

DOQB[0:7]

CLKOI or CLKOQ

(= CLKI/2)

CLKOI or CLKOQ

(= CLKI/4)

DDRB

Notes: 1. In 1:2 DMUX, Fs/2 mode:

The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is low, it goes high only when its half cycle is complete; if the reset occurs when it is high, it remains
high) and then only, remains in reset state (frozen to a high level in 1:2 DMUX Fs/2 mode). The next rising edge of the input
clock after reset makes the output clock return to normal mode (after TDR).

2. In 1:2 DMUX, Fs/4 mode:

The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low)
and then only, remains in reset state (frozen to a low level in 1:2 DMUX Fs/4 mode). The next rising edge of the input clock
after reset makes the output clock return to normal mode (after TDR).

N + 1

TDR

TDR

TDR + 2 cycles

TDR + 2 cycles

2 ns

1 ns min

18

AT84AD004

5390A–BDC–06/04