– 80C51 core with 6 clocks per instruction
– 8 MHz On-Chip Oscillator
– PLL for generating 96 MHz clock to supply CPU core, USB and Smart Card Interfaces
– Programmable CPU clock from 500 kHz / X1 to 48 MHz / X1
• Reset Controller
– Power On Reset (POR) feature avoiding an external reset capacitor
– Power Fail Detector (PFD)
– Watch-Dog Timer
• Power Management
– Two power saving modes: Idle and Power Down
– Four Power Down Wake-up Sources: Smart Card Detection, Keyboard Interrupt, USB
Resume, External Interrupt
– Input Voltage Range: 4.5V - 5.5V
– Core’s Power Consumption (Without Smart Card and USB):
•30 mA Maximum Operating Current @ 48 MHz / X1
•200 µA Maximum Power-down Current @ 5.5V
• Interrupt Controller
– up to 7 interrupt sources
– up to 4 Level Priority
• Memory Controller
– Internal Program memory: up to 16 Kbytes of ROM
– Internal Data Memory : 768 bytes including 256 bytes of data and 512 bytes of XRAM
• Two 16-bit Timer/Counters
• USB 2.0 Full Speed Interface
– 48 MHz DPLL
– On-Chip 3.3V USB voltage regulator and transceivers
– Software detach feature
– 7 endpoints programmable with In or out directions and ISO, Bulk or Interrupt Transfers :
•Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers
•Endpoints 1,2,3: 8 bytes FIFO
•Endpoints 4,5: 64 Bytes FIFO
•Endpoint 6: 2*64 bytes FIFO with Pin-Pong feature
• ISO 7816 UART Interface Fully Compliant with EMV2000, GIE-CB and WHQL Standards
– Programmable ISO clock from 1 MHz to 4.8 MHz
– Card insertion/removal detection with automatic deactivation sequence
– Programmable Baud Rate Generator from 372 to 11.625 clock pulses
– Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention
– Automatic character repetition on parity errors
– 32 Bit Waiting Time Counter
– 16 Bit Guard Time Counter
– Internal Step Up/Down Converter with Programmable Voltage Output:
•1.8V-30mA, 3V-50mA and 5V-60mA
– Current overload protection
– 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface
• Alternate Smart Card Interface with CLK, IO and RST
• UART Interface with Integrated Baud Rate Generator (BRG)
• Four 12 I/O bit Ports
– Up to four LED outputs with 3 level programmable current source: 2, 4 and 10 mA
– Two General Purpose I/O programmable as external interrupts
• Packages
– VQFP32, QFN32, Die
C51
Microcontroller
with USB and
Smart Card
Reader
Interfaces
AT83C5127
Summary
For detailed functional description,
please refer to the AT8xC5122/23
datasheet.
7519A–SCR–04/05
1
Product descriptionAT83C5127 product is high-performance CMOS derivatives of the 80C51 8-bit micro-
controllers designed for USB smart card reader applications.
The AT83C5127 is a low pin count of the AT8xC5122 and is proposed in ROM version.
The ROM device is only factory programmable.
Block Diagram
VCC
VSS
XTA L 1
XTA L 2
RST
8 MHz
Osci llat or
PLLPLLF
WATCH-DOG
POR
PFD
RESET
3. 3 V
Regulat or
256 x8
RAM
80C51 8-BIT CORE
256 x 8
RAM
16K x 8
ROM
512 x 8
XR A M
TxD
RxD
UART
Interface
INTERNAL ADD RESS AND DATA BUS
3-BI T
PORT
16-BI T
TI MER S
P1[2,6-7]
T[0-1]
Par all el I/O Port s
8-BI T
PORT
P3[0-7]
I nterr upt
Cont roll er
1-BI T
PORT
LI
CVCC
DC/DC
Conv ert er
USB
Interface
D+
D-
CVSS
VREF
Interface
ISO 7816
3.3V
Regulat or
AVSS
AVCC
CPRES
CRST
CCLK
CIO
CC4
CC8
DVCC
IN T[ 0-1]
P5.0
LED's
CRST1
CCLK1
Alt ernat e
Card
LED[0-3]
CIO1
2
AT83C5127
7519A–SCR–04/05
Package Description
AT83C5127
Figure 1. VQFP32 Package Pinout
CIO
DVCC
P1.2/CPRES
CC8
CRST
CC4
CCLK
P5.0
VSS
1
2
3
4
5
6
7
8
CVCC
Figure 2. MLF32 Package Pinout
CIO
DVCC
P1.2/CPRES
CC8
CRST
CC4
CCLK
P5.0
VSS
1
2
3
4
5
6
7
8
CVCC
D-D+AVC C
P1.7/CCLK1
VREF
PLLF
28 27 26
VQFP32
1211109131415
LI
VCC
P1.7/CCLK1
CVSS
VREF
P3.7/LED3
D-D+AVC C
XTAL1
XTAL2
PLLF
28 27 26
MLF32
1211109131415
LI
VCC
CVSS
XTAL1
XTAL2
P3.7/LED3
AVS S
2529303132
P3.1/TxD
24
P1.6
23
P3.0/RxD
22
P3.5/T1/CRST1
21
P3.2/INT0/LED0/CIO1
20
P3.3/INT1
19
P3.4/T0/LED1
18
P3.6/LED2
17
16
RST
AVS S
2529303132
P3.1/TxD
24
P1.6
23
P3.0/RxD
22
P3.5/T1/CRST1
21
P3.2/INT0/LED0/CIO1
20
P3.3/INT1
19
P3.4/T0/LED1
18
P3.6/LED2
17
16
RST
7519A–SCR–04/05
3
Pin Description
Table 1. Pin Description
Port
LQFP32
Internal
Power
QFN32
Supply ESDI/O
Reset
LevelAlt
Reset
ConfigConf 1Conf 2Conf 3Led
CIO3232CVCC6KVI/O0CIOPort51
CC433CVCC6KVI/O0CC8Port51
P1.222VCC2KVI/O1CPRESPort51
CC455CVCC6KVI/O0CC4Port51
CCLK66CVCC6KVO0CCLKPush-pull
CRST44CVCC6KVO0CRSTPush-pull
P1.62323VCC2KVI/O1Port51
P1.73131VCC2KVI/O1CCLK1Port51
P3.02222VCC2KVI/O1RxDPort51Push-pull
P3.12424VCC2KVI/O1TxDPort51Push-pull
P3.22020VCC2KVI/O1INT0Port51LED0
P3.31919VCC2KVI/O1INT1Port51Push-pull
CVCC inactive at reset.
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
Weak & medium pull-up can be
disconnected
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
CVCC inactive at reset
ESD tested with a 10µF on CVCC
P3.41818VCC2KVI/O1T0Port51Push-pullLED1
P3.52121VCC2KVI/O1T1Port51
P3.61717VCC2KVI/O1Port51LED2
P3.71313VCC2KVI/O1Port51LED3
P5.077VCC2KVI/O1Port51Push-pull
Reset Input
The Port pins are driven to their reset conditions when a voltage lower
than V
is applied, whether or not the oscillator is running.
IL
RST
4
AT83C5127
1616VCCI/0
This pin has an internal 10K pull-up resistor which allows the device to
be reset by connecting a capacitor between this pin and VSS.
Asserting RST
returns the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal
reset occurs.
when the chip is in Idle mode or Power-Down mode
7519A–SCR–04/05
Table 1. Pin Description (Continued)
Internal
Power
Port
D+2929DVCCI/O
QFN32
LQFP32
Supply ESDI/O
Reset
LevelAlt
USB Positive Data Upstream Port
This pin requires an external serial resistor of 33Ω and a 1.5 K
up to
Reset
ConfigConf 1Conf 2Conf 3Led
VREF for full speed configuration.
AT83C5127
Ω
pull-
D-2828DVCCI/O
V
REF
XTAL11414VCCI
XTAL21515VCCO
PLLF2626AVCCO
AVC C272 7PW R
VCC1212PWR
LI1010PWR
3030AVCCO
USB Negative Data Upstream Port
This pin requires an external serial resistor of 33Ω
USB Voltage Reference: 3.0 <
V
can be connected to D+ through a 1.5 KΩ resistor. The V
REF
voltage is controlled by software.
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal or an external oscillator must be
connected to this pin.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal circuit must be connected to
this pin. If an external oscillator is used, leave XTAL2 unconnected.
PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter.
Analog Supply Voltage
AVCC is used to supply the internal 3.3V analog regulator which
supplies the internal USB driver
Supply Voltage
VCC is used to supply the internal 3.3V digital regulator which
supplies the PLL, CPU core and internal I/O’s
DC/DC Input
LI supplies the current for the charge pump of the DC/DC converter.
- LI tied directly to VCC : the DC/DC converter must be configured in
regulator mode.
- LI tied to VCC through an external 10µH coil : the DC/DC converter
can be configured either in regulator or in pump mode.
VREF < 3.6 V
REF
CVCC99PWR
DVCC11PWR
CV SS1111GN D
VSS88GND
AVSS2525GND
7519A–SCR–04/05
Card Supply Voltage
CVCC is the ouput of internal DC/DC converter which supplies the
Smart Card Interface. It must be connected to an external decoupling
capacitor of 10 µF with the lowest ESR as this parameter influences
on the CVCC noise
Digital Supply Voltage
DVCC is the output of the internal analog 3.3V regulator which
supplies the USB driver. This pin must be connected to an external
680nF decoupling capacitor if the USB interface is used.
DC/DC Ground
CVSS is used to sink high shunt currents from the external coil
Digital Ground
VSS is used to supply the PLL, buffer ring and the digital core
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