Rainbow Electronics AT83C26 User Manual

Features

• 5 Smart Card Interfaces

– Compliance with ISO 7816, EMV2000, GIE-CB and GSM Standards – Direct Connection to the Smart Cards

Logic Level Shifters Short Circuit Current Limitation 4kV+ ESD Protection (MIL/STD 883 Class 3)

– 1 or 2 Master Smart Card interfaces

Synchronous Card support (with C4 and C8 Contacts)

Card Detection and Automatic de-activation sequence on card extraction – 1 to 4 SAM/SIM cards (15 to 30mA each) – Programmable Voltage for each smart card

Class A: 5V ±0.4V at 60 mA (±0.25V at 65 mA with VCC= 5V±10%)

Class B: 3V ±0.2V at 60 mA

Class C: 1.8V ±0.14V at 40mA – Low Ripple Noise: < 200 mV – Programmable Activation Sequence – Automatic de-activation on card power-fail or over-current and system power-fail – Card Clock Stop High or Low for Card Power-down Modes

• Versatile Host Interface

– Two Wire Interface (TWI) Link at 400kbit/s

Programmable Address allow up to 4 AT83C26 on the bus – Programmable Interrupt Output

• Reset Output Includes

– Power-On Reset (POR) – Power-Fail Detector (PFD)

• Extended Voltage Operation: 3 to 5.5V

• Low Power Consumption

– 5 mA Maximum Operating Current (without Smart Card) – 150 mA Maximum In-rush Current (each DC/DC) –30 µA Typical Power-down Current (without Smart Card)

• 4 to 48 MHz Clock Input

• System clock derived from the external clock input

• Industrial Temperature Range: -40 to +85°C

• Packages: QFN48, VQFP48

Smart Card Reader Interface With Power Management

AT83C26

Description

The AT83C26 is a smart card reader interfac e IC for s mart c ard re ade r/ writer a pplic ations such as EFT/POS terminal s and set top boxes. It enable s the management of any type of smart card from any kind of host. Up to 4 AT83C26 can be connected in parallel thanks to the programmable TWI address.

Its high efficiency DC/DC con verters and low quiesce nt current i n stand-by mod e make it particularly suited to lo w power an d portable a pplicati ons. The red uced bil l of material allows to lower significantly the system size and cost. A sophisticated protection system guarantees timely and controlled shutdown upon error conditions.

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AT83C26

Acronyms

Block Diagram

TWI: Two Wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset

BYPASS

EVCC

RESET

INT

A2/CK, A1/RST

SCL

SDA

I/O1

I/O2

AUX1

AUX2

VCC

VSS

Voltage supervisor POR/PFD

TWI Controller

I/0 Selection

CVSSB

CVCCB

Main Control & Logic Unit

CVCCINB

LIB

DC/DC Converter B

Timer 16 bits

LDO LDO

LDO

CVSS1

LIA

DC/DC Converter A

smart card 1

smart card 2

Analog Drivers

SAM/SIM 1

CVCCIN1

CVCC1

CVCC2 CVCC3 CVCC4

CVCC5

CPRES1 CRST1 CIO1 CC41 CC81

CCLK1

CPRES2 CRST2 CIO2

CCLK2 CC42, see (1) CC82, see (1)

CRST3, see (1) CIO3, see (1) CCLK3

SC1

SC2

SC3

CLK

Clock Circuit CCLK

Clock Controller

SAM/SIM 2

SAM/SIM 3

CRST4 CIO4 CCLK4

CRST5 CIO5 CCLK5

SC4

SC5

Note: 1. CRST3/CC82 are on the same pin. CIO3/CC42 are on the same pin. If complete Smart card 2

interface is used, SAM/SIM3 isn’t available. Respectively, if SAM/SIM3 is used, complete Smart card 2 isn’t available.

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Pin Description

Pinout (Top View)

AT83C26

VQFP48 Pinout

CVCC3

CRST3/CC82

CCLK3

CIO3/CC42

CVCC4 CRST4

CCLK4

CIO4

CIO5

CCLK5

CRST5

CVCC5

QFN48 Pinout

CIO2

CRST2

CCLK2

4748

2 3 4

6 7 8 9

13 14 15 16 17

CIO1

CC81

CC41

CVCC2

CVCCINB

4445

VQFP 48

TOP VIEW

18 19 20

CCLK1

CRST1

ESET R

CPRES2

4243

CPRES1

CVCCIN1

CVCCB

21 22 23 24

CVCC1

EVCC

LIB

CVSSB

CLK

A2/CK A1/RST

AUX1

32 31

AUX2 IO1

IO2

SCL

SDA

27 26

BYPASS

VSS

LIA

VCC

CVSS1

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CVCC3

CRST3/CC82

CCLK3

CIO3/CC42

CVCC4 CRST4

CCLK4

CIO4

CIO5

CCLK5

CRST5

CVCC5

CIO2

CCLK2

4748

2 3 4

6 7 8 9

13 14 15 16 17

CIO1

CC81

CC41

CRST2

CCLK1

CVCCINB

CVCC2

4445

QFN 48

TOP VIEW

18 19 20

CRST1

CVCCIN1

CPRES2

4243

ESET R

CVCCB

21 22 23 24

CVCC1

CPRES1

CVCCB

CVCC1

EVCC

LIB

CVSSB

INT

CLK

A2/CK

A1/RST

AUX1

AUX2

IO1

IO2

SCL SDA

27 26

BYPASS

VSS

LIA

VCC

CVSS1

AT83C26

Signals

Table 1. Ports Description

VQFP48 or

QFN48

Pin number

1 CVCC3 4kV+ PWR VCC pin for SC3 interface.

Pad Name Pad Internal

Power Supply

ESD

Limits

Pad T y pe Description

2 CRST3/CC82 CVCC3 4kV+

3 CCLK3 CVCC3 4kV+ O CCLK pin for SC3 interface.

4 CIO3/CC42 CVCC3 4kV+

5 CVCC4 4kV+ PWR VCC pin for SC4 interface. 6 CRST4 CVCC4 4kV+ O RST pin for SC4 interface. 7 CCLK4 CVCC4 4kV+ O CCLK pin for SC4 interface.

8 CIO4 CVCC4 4kV+

9 CIO5 CVCC5 4kV+

10 CCLK5 CVCC5 4kV+ O CCLK pin for SC5 interface. 11 CRST5 CVCC5 4kV+ O RST pin for SC5 interface. 12 CVCC5 4kV+ PWR VCC pin for SC5 interface.

13 CC81 CVCC1 4kV+

I/O

pull up

I/O

pull up

I/O

pull up

I/O

pull up

I/O

pull up

See SC2_CFG1 register: If SC2_FULL bit = 0, CRST pin for SC3 interface. If SC2_FULL bit = 1, CC8 pin for SC2 interface.

See SC2_CFG1 register: If SC2_FULL bit = 0, CIO pin for SC3 interface. If SC2_FULL bit = 1, CC4 pin for SC2 interface.

CIO pin for SC4 interface.

CIO pin for SC5 interface.

CC8 pin for SC1 interface.

14 CC41 CVCC1 4kV+

15 CIO1 CVCC1 4kV+

16 CCLK1 CVCC1 4kV+ O CCLK pin for SC1 interface. 17 CRST1 CVCC1 4kV+ O RST pin for SC1 interface. 18 CVCCIN1 4kV+ PWR This pin must be connected to CVCC1 pins next to the package.

19 CPRES1 VCC 4kV+

20 CVCC1 4kV+ PWR

21 CVCC1 4kV+ PWR VCC pin for SC1 interface.

I/O

pull up

I/O

pull up

CC4 pin for SC1 interface.

CIO pin for SC1 interface.

Card presence for SC1 interface. An internal pull up to VCC can be activated in the pad if necessary using

PULLUP1 bit in SC1_CFG1 register (activated by default). VCC pin for SC1 interface.

The two CVCC1 pins are connected together near the package. Only one wire goes to the smart card connector. The reason of two CVCC1 pins is to reduce noise.

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Table 1. Ports Description (Continued)

VQFP48 or

QFN48

Pin number

22 LIA 2kV PWR

Pad Name Pad Internal

Power Supply

ESD

Limits Pad Type Description

AT83C26

DC/DCA input. LIA must be tied to VCC pin through an external coil (typically 10µH) and

provides the current for the charge pump of the DC/DCA converter. It may be directly connected to VCC if the step-up converter is not used

(see STEPREGA bit in SC1_CFG4 register and see minimum VCC values in T able 50.for class A and Table 51. for class B)

23 CVSS1 2kV GND

24 VCC 2kV PWR VCC is used to power the internal voltage regulators and I/O buffers. 25 VSS 2kV GND Ground.

26 BYPASS VCC 2kV I

27 SDA VCC 2kV

28 SCL VCC 2kV

29 IO2 EVCC 2kV

30 IO1 EVCC 2kV

31 AUX2 EVCC 2kV

32 AUX1 EVCC 2kV

33 A1/RST EVCC 2kV I

I/O

open drain

I/O

open drain

I/O

pull up

I/O

pull up

I/O

pull up

I/O

pull up

DC/DCA input. This pin must be directly connected to the VSS of power supply.

A high level on this pin activates a low power consumption mode with internal regulator bypassed.

Micro controller interface function: TWI serial data. An external pull up must be connected on SDA pin (4.7kOhms).

Micro controller interface function: TWI clock. An external pull up must be connected on SCL pin (4.7kOhms).

The behavior of this pin depends on IOSEL[3/0] bits values (see IO_SELECT register).

The TWI address depends on the value present on this pin at reset. If CRST transparent mode is selected, the A1/RST signal is connected to

CRST1 or CRST2 pins (see CRST_SEL1 and CRST_SEL2 bits respectively in SC1_CFG4 and SC2_CFG2 registers).

34 A2/CK EVCC 2kV I

35 CLK EVCC 2kV I Master clock.

36 INT VCC 2kV

37 EVCC PWR

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open drain

The TWI address depends on the value present on this pin at reset. If CCLKn transparent mode is selected, the A2/CK signal is connected to

CCLKn pins (with n=1 to 5). See CKSn[2:0] bits respectively in SC1_CFG1, SC2_CFG2, SC3_CFG2,

SC4_CFG2, SC5_CFG2 registers.

Interruption status. An internal pull up to VCC can be activated in the pin if necessary using

INT_PULLUP bit in SC1_CFG4 (deactivated by default). Extra supply voltage (Micro controller power supply).

EVCC is used to supply the internal level shifters of host interface pins. EVCC is connected to the host power supply. EVCC voltage can be directly connected to VCC if the host power supply

and the AT83C26 power supply is the same.

AT83C26

Table 1. Ports Description (Continued)

VQFP48 or

QFN48

Pin number

Pad Name Pad Internal

Power Supply

ESD

Limits Pad Type Description

38 CVSSB GND

39 LIB 2kV PWR

40 CVCCB 2kV PWR

41 CVCCB 2kV PWR DC/DCB output.

42 RESET VCC 2kV

43 CPRES2 VCC 4kV+

44 CVCCINB PWR This pin must be connected to CVCCB pins next to the package.

I/O

open drain

pull up

DC/DCB input. This pin must be directly connected to the VSS of power supply.

DC/DCB input. LIB must be tied to VCC pin through an external coil (typically 10µH) and

provides the current for the charge pump of the DC/DCB converter. It may be directly connected to VCC if the step-up converter is not used

(see STEPREGB bit in DCDCB register and see minimum VCC values in Table 53.for class A and Table 54. for class B)

DC/DCB output. The two CVCCB pins are connected together near the package. CVCCB

pin is only used for DC/DCB voltage measurements.The reason of two CVCCB pins is to reduce noise.

Micro controller interface function: reset signal.

• power on reset

• A low level on this pin keeps the AT83C26 under reset even if applied on power-on. It also resets the AT83C26 if applied when the AT83C26 is running.

• Asserting RESET

Card presence for SC2 interface.

An internal pull to VCC can be activated in the pad if necessary using PULLUP2 bit in SC2_CFG1 register (activated by default).

45 CVCC2 4kV+ PWR VCC pin for SC2 interface. 46 CRST2 CVCC2 4kV+ O CRST pin for SC2 interface. 47 CCLK2 CVCC2 4kV+ O CCLK pin for SC2 interface.

48 CIO2 CVCC2 4kV+

I/O

pull up

CIO pin for SC2 interface.

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Pad Type Description

To simplify the understanding of Figure 1. to F igure 8., a shortcut is possible by replacing the weak transistor by a 100k Ohms pull-up resistor, the medium transistor by a 10k Ohms pull-up resistor and the strong transistor by a 1k Ohms pull-up resistor.

Input/Output with Pull-up Configuration (IO1, IO2, AUX1, AUX2)

This output type can be used as both an inpu t and output withou t the need to r econfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the port outputs a logic low state, it is driven strongly and able to sink a fairly large current.

Figure 1. Input/Output with Pull-up Configuration

AT83C26

2 DCCLK CLOCK DELAY

Strong

Keep

PMOS

Port latch Data

NMOS

Input Data

Input/Output with Pull-up Configuration (CIOn with n = 1, 2, 3, 4, 5) and (CC4n, CC8n with n = 1,

Figure 2. Input/Output with Pull-up Configuration

PMOS

Strong

Medium

Slew control with CIOn_SLEW_CTRL bits (n= 1 to 5)

Port latch Data

2 DCCLK CLOCK DELAY

NMOS

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Input Data

AT83C26

Input/Output with Open Drain Configuration (SDA, SCL, RESET) Figure 3. Input/Output with Open Drain Configuration

Data

NPort latch

NMOS

Input Data

Output Configuration (CCLKn with n = 1, 2, 3, 4, 5) Figure 4. Output Configuration

Strong

PMOS

Port latch Data

NMOS

Slew control with CIOn_SLEW_CTRL bits

Output Configuration (CRSTn with n = 1, 2, 3, 4, 5) Figure 5. Output Configuration

Port latch Data

Strong

PMOS

NMOS

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Open drain Output with programmable pull-up Configuration (INT) Figure 6. Open Drain Output with programmable pull-up

AT83C26

Port latch Data

Input Configuration (A1, A2, CLK, BYPASS) Figure 7. Input

Input Data

INT_PULLUP bit

NMOS

Weak

Input with programmable pull-up Configuration (CPRES1, CPRES2) Figure 8. Input with programmable pull-up

INT_PULLUP bit

Input Data

Weak

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AT83C26

Operational Modes

TWI Bus Control The Atmel Two-wire Inter fac e (T WI ) interc onn ec ts c omp one nts on a un iqu e two-wi re bus, mad e

up of one clock line and one data line with s peeds of up to 400 K bits per se cond, based on a byte-oriented transfer format.

The TWI-bus interface can be used:

– To configure the AT83C26 – To select interface – To select the operating mode of the card: 1.8V, 3V or 5V – To configure the automatic activation sequence – To start or stop sessions (activation and de-activation sequences) – To initiate a warm reset – To control the clock to the card in active mode – To control the clock to the card in stand-by mode (stop LOW, stop HIGH or running) – To enter or leave the card stand-by or power-down modes – To select the interface (connection to the host I/O/C4/C8) – To request the status (card present or not, over-current and out of range supply

voltage occurrence) – To drive and monitor the card contacts by software – To accurately measure the ATR delay when automatic activation is used – Re-use the AT83C24 command set for the first DC/DC and smart card interface with

the following changes:

•CKS extended to CONFIG2[0:3], CKS=8 selects CLK/3 and CKS>8 is reserved

•The slave address byte for TWI write commands is 0100 A2A110 and 0100 A2A111 for TWI read commands

TWI Commands

Frame Structure The structure of the TWI bus data frames is made of one or a series of write and read com-

mands completed by STOP. Write commands to the AT83C26 have the structure:

ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)

Read commands to the AT83C26 have the structure:

ADDRESS BYTE + DATA BYTE(S)

The ADDRESS BYTE is sampled on A2/CK and A1/RST after each reset (hard/sof t/g en er a l call) but A2/CK, A1/RST can be used for transparent mode after the reset.

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Figure 1. Data transfer on TWI bus

SDA

Address byte

AT83C26

acknowledgement from slave

command and/or data

SCL

123456

start condition

stop condition

Address Byte The first byte to send to the device is the address byte. The device controls if the hardware

address (A2/CK, A1/RST pins on reset) corresponds to the address given in the address byte (A2, A1 bits).

If the level is not stable on A2/CK pin at reset, the user has to manage the possible address taken by the device.

Figure 2. Address Byte

b7 b6 b5 b4 b3 b2 b1 b0

0A2

R/W

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Slave Address on 7 Bits

1 for READ Command

0 for WRITE Command

Up to 4 devices can be connected on the same TWI bus. Each device is configured with a different combination on A2/CK, A1 /RST pins. The address by te of each device for read/wri te operations are listed below.

Table 2. Address Byte Values

(A2/CK pin)

0 0 0x43 0x42 0 1 0x47 0x46 1 0 0x4B 0x4A 1 1 0x4F 0x4E

(A1/RST pin)

Address Byte

for

Read

Command

Address Byte

for

Write

Command

AT83C26

RESET pin

The TWI ADDRESS BYTE is sampled on A2/CK and A1/RST after a rising edge on RESET pin. The delay between the rising edge and the sampling of A2/CK and A1/RST is t1.

The value for t1 is 22 CLK period. The minimum value for t2 is 40 CLK period. During the t2 time, the TWI bus is not ready to

receive a command. The CLK period depends on the frequency of the signal on CLK pin. The RESET pin is an I/O with Open Drain. The host IO pin connecte d to RESET must be an I/O

with open drain (with external pull-up) or an I/O with internal pull up (without external pull-up). Figure 3. Timings after reset

Sampling of TWI address

RESET

BYPASS pin

A high level on this pin activates a low power consumption mode. At reset, the level on this pin must be fixed (VSS or VCC). Before to set BYPASS pin, SHUTDOWNA and SHUTDOWNB bits must be set. If SHUTDOWNA bit is set, DCDCA is switched off. If SHUTDOWNB bit is set, DCDCB is switched off. If SHUTDOWNA and SHUTDOWNB bits are set, the regulator is switched off. If BYPASS pin is at a high level, the bandgaps are switched off.

Smart Card Interfaces

The AT83C2 6 enable s the ma nageme nt of up to 5 smart c ard inte rfaces . Due to s hared IOs between SC2 and SC3, the user should choose between a full SC2 interface (with CC4 and CC8) or SC3 interfa ce.

SDA

Address byte

The SC2_FULL bit in SC2_CFG1 register is used to select the SC2/S C3 interfaces configuration.

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Table 3. SC2 and SC3 shared IOs

AT83C26

Pin name

CPRES2 CRST2 CIO2 CCLK2 CRST3/CC82 CIO3/CC42 CCLK3

SC2_FULL = 1 SC3 interface not available

CPRES2 CRST2 CIO2 CCLK2 CC82 CC42 unused

DCDC Converters

SC2_FULL = 0 SC2 without CC4and CC8 + SC3 interface

CPRES2 CRST2 CIO2 CCLK2 CRST3 CIO3 CCLK3

The DC/DC A converter is used to provide smart card voltage for the SC1 interface (CVCC1). The DC/DC B converter i s used to provi de sm art car d volt age for the SCn int erfac es (n=2 , 3, 4,

5). DC/DC converters need a clock of 4MHz (see Section “Clock Controller”). Two internal oscilla-

tors (one for each converter) provide the DC/DC clocks. The DC/DCB output is connected on 4 LDO regulators (Low Drop Output) to generate CVCCn

voltage (n=2, 3, 4, 5).

Clock Controller

The clock controller outputs six clocks:

1. Five clocks for CCLK1, CCLK2, CCLK3, CCLK4 and CCLK5. Four different sources can be used: CLK pin, DCCLK signal, CARDCKn bit (n=1, 2, 3, 4, 5) or A2/CK.

2. A DCCLK clock used for pads and deactivation sequence.

Clock controller for SCn (n=1, 2, 3, 4, 5)

The transparent mode with A2/CK pin is available on SCn interface. The CKSn[2:0] register is used to select this transparent mode between A2/CK and CCLKn. The bi t CKSTOPn must be cleared to have CCLKn running according to CKSn[2:0].

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AT83C26

Figure 4. Clock Block Diagram with Software Activation

CRST controller

CRSTn for SCn interface (n=1, 2)

CLK

A2/CK

Internal oscillators

DCK[2:0]

CKSn[2:0]

DC/DCA and B

CARDCKn bit

CKSTOPn bit

DCCLK

CCLKn

The CRSTn output pin is driven by the CARDRSTn bit value or by A1/RST pin. Three modes are available:

• If the ARTn bit is reset, CRSTn pin is driven by CARDRSTn bit.

• If the ARTn bit is set, CRSTn pin is controlled and follows the “Automatic Reset Transition” (see Activation sequence page 25).

• A transparent mode with A1/RST pin.

Figure 5. CRSTn Block Diagram

A1/RST

CARDRSTn bit

tb delay

0 1

ARTn bit

0 1

CRST_SELn bit

CRSTn

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CRSTn for SCn interface (n= 3, 4, 5)

The CRSTn output pin is driven by the CARDRSTn bit value (see SCn_CFG2 register). Two modes are available:

• If the ARTn bit is reset, CRSTn pin is driven by CARDRSTn bit.

• If the ARTn bit is set, CRSTn pin is controlled and follows the “Automatic Reset Transition” (see Activation seque nce page 25).

Figure 6. CRSTn Block Diagram

AT83C26

CARDRSTn bit tb delay

If SC2_FULL=1, the SC3 interface is not available.

CIO, CC4, CC8 controller

CIO1, CC41, CC81 controller for SC1 interface

The CIO1, CC41, CC81 output pins are driven respectively by CARDIO1, CARDC41, CARDC81 bits values or by I/O1, I/O2, AUX1or AUX2 signals. This selection depends of the IODIS1 bit value (SC1_INTERFACE register) and of IOSEL[3:0] bits value (IO_SELECT register).

Figure 7. CIO1, CC41, CC81 Block Diagram

IO1

IO2

AUX1

AUX2

HiZ control

CARDRSTn bit

Multiplex

0 1

ARTn bit

CARDIO1 bit

CARDC41 bit

CRSTn

CIO1

CC4

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CARDC81 bit

IODIS1 bit

If IODIS1 is set, the CARDIO1 bit value is output on CIO1.The input selected by IOSEL for CIO1 is in High impedance state. CC41 and CC81 have the same behavior.

If IODIS1 is reset, data are bidirectional between the I/O1, I/O2, AUX1, AUX2 pins (see IO_SELECT register) and CIO1, CC41, CC81 pins.

IOSEL[3:0]

CC81

AT83C26

CIO2, CC42, CC82 controller for SC2 interface

Figure 8. CIO2, CC42, CC82 Block Diagram

IO1

IO2

AUX1 AUX2

The SC2_FULL bit must be set to use CC42 and CC82.

CIOn controller for SCn interface (n=3, 4, 5)

The CIOn output pin is driven by CARDIOn bit values or by I/O1, I/O2, AUX1 or AUX2 signals. This selection depends of the IODISn bit value. If IODISn is reset, data are bidirectional between the I/O1, I/O2, AUX1, AUX2 pins (see IO_SELECT register) and CIOn pins.

Figure 9. CIOn Block Diagram

HiZ control

IODIS2 bit

Multiplex

IOSEL[3:0]

CARDIO2 bit

CARDC42 bit

CARDC82 bit

CIO2

CC4

CC82

IO1

IO2

AUX1

AUX2

CIOn (n=1 to 5), CC41, CC81, CC42, CC82 transparent mode description

Two modes are available on CIOn, CC4n, CC8n signals:

• Bit control (a bit controls the output pin)

• Transparent mode (IO signal and CIO are linked after level shifter)

According to IO_SELECT register value and IODISn bits values, one of 4 input pins (IO1, IO2, AUX1 or AUX2) is linked to the selected output.

The idle state is the high level. Each signal is bidirectional.

HiZ control

IODISn bit

Multiplex

IOSEL[3:0]

CARDIOn bit

CIOn

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T ransparent mode arbitration system

The first between IO and CIO to force a low level becomes the master. The slave signal is grounded after t1 delay:

t1 max = 2* (CLK period).

Figure 10. Bidirectional mode

AT83C26

CIO

master

slave

master

The minimum delay for a puls e at 0 or 1 to b e detected is between 0.5 and 1.5 CLK peri od (depending on arrival time).

If IO and CIO are both grounded, CIO becomes the master.

The minimum delay to switch of master without electrical conflict is equal to:

t2 min = 4 * (CLK period) + 2 * (DCCLK period) * (CLK period).

If a master switch appears before this minimum delay, the electrical conflict delay is:

t2 = 2 * (DCCLK period) * (CLK period)

Figure 11. Electrical conflict

7511B–SCR–10/05

CIO

master

slave

CIO pad becomes output

slave

master

AT83C26

CCLKn and CIOn (n=1 to 5) slew rate control

Three registers SLEW_CTRL_1, SLEW_CTRL_2 and SLEW_CTRL_3 control the slew rate of the CIOn and CCLKn signals. Each signal has 2 control bits.

An automatic mode is proposed. The VCARDn[1:0] value is used to automatically adjust the slew rate.

For specific cases, like long wires between AT83C26 and smart card connector for example, the user can forced the slew rate.

The rising edge and the falling edge are modified with the slew rate control for CCLKn. Only the rising edge is modified on CIOn with the slew rate control. See Table 63. to Table 68. in Electrical Characteristics.

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Card Presence Detection

Card presence detection for SC1 interface

The card presence si gnal is conn ected on th e CPRES1 pin . The polari ty of card pres ence contact is selected with the CARDDET1 bit (see SC1_CFG1 register). A programmable filtering is controlled with the CDS1[2-0] bits.

The internal pull-up on the CPRES1 pin can be disconnected in order to reduce the consumption. An external pull-up mu st be con nected to V c c. The PULLUP1 bit (see SC1_CFG1 registe r) controls this feature.

AT83C26

Figure 12. SC1 presence Input

VCC

External Pull-up Resistor

VCC

Card Presence Contact

CPRES1

Card Presence Contact

VSS

External Pull-down Resistor

INT

VSS

If the card presence co ntact i s connec ted to Vc c, t he interna l pull -up mus t be dis connect ed an d an external pull-down must be connected to the CPRES1 pin.

An interrupt can be generated if a card is inserted or extracted (see Section “Interr upts”, page 30).

Card Presence Detection for SC2 interface

VCC

PULLUP1 Bit CARDDET1 Bit

= 1 Closed = 0 Open

VCC

= 1 Closed = 0 Open

INT_PULLUP Bit

Figure 13. SC2 presence Input

= 1 No Card if CPRES1 = 0 = 0 No Card if CPRES1 = 1

FILTERING

CDS1[2-0]

CARDIN1 bit

= 1 Card Inserted = 0 No Card

VCC

External Pull-up Resistor

Card Presence Contact

VSS

7511B–SCR–10/05

VSS

VCC

Card Presence Contact

External Pull-down Resistor

CPRES2

INT

VCC

INT_PULLUP Bit

= 1 Closed = 0 Open

PULLUP2 Bit

= 1 Closed = 0 Open

CARDDET2 Bit

= 0 Closed = 1 Open

ITDIS2 Bit

= 1 No Card if CPRES2 = 0 = 0 No Card if CPRES2 = 1

FILTERING

CDS2[2-0]

CARDIN2 bit

= 1 Card Inserted = 0 No Card

AT83C26

DC/DC converters

DC/DC A converter

The DC/DC A converter is c ontrolled by VCARD1 [1:0], SHUTDOWNA, ICCADJ A, STEPREGA , VCARD_OK1 and DEMBOOSTA[1:0 ] bits .

The DC/DC A converter cannot be switched on while the CPRES1 pin remains inactive. If CPRES1 pin becomes inactive while the DC/DC A converter is operating an automatic shut down sequence of the DC/DC A converter is initiated by the electronics.

A write operation in VCARD1[1:0] (0x01, 0x02, 0x03) starts the DC/DC. When the output voltage remains within the voltage range specified by VCARD1[1:0], the VCARD_OK1 bit is set.

After a deact ivation se quence (ca rd extractio n, DC/DC o utput voltag e out of r ange, SHUTDOWNA bit =1...) the DC/DC A converter is automatically stopped.

It is mandatory to switch off the DC/DC A converter before entering in Power-down mode. The DC/DC A Converter can work in two different modes which are selected by STEPREGA bit:

• Pump Mode (STEPREGA = 0): an external inductance of 10 µH must be connected between pins LIA and VCC. VCC can be higher or lower than CVCC1.

• Regulator mode (STEPREGA = 1): no external inductance is required but VCC must be always higher than CVCC+0.3V.

The current drawn from power suppl y by the DC/DC A conv erter is controll ed during the startup phase in order to avoid high transient cur rent mainly in Pump Mod e which could cause the power supply voltage to drop dramatically . This control is done by means of bits DEMBOOSTA[1:0], which increases progressively the startup current level.

The DC/DCA sensitivity to any overflow current can be modified (20%) by using the ICCADJA bit (SC1_CFG3 register).

Initialization Procedure for DC/DC A converter

The initialization procedure is described in flow chart:

• Select the CVCC1 level by means of bits VCARD1[1:0] in SC1_CFG0 register,

• Set bits DEMBOOST A[1:0] in SC1_CFG4 register following the current level control wanted.

• Monitor VCARD_OK1 bit in SC1_STATUS register in order to know when the DC/DC A Converter is ready (CVCC1 voltage has reached the expected level)

While VCC1 remains hi gher t han 3.6V an d star tup cur rent lowe r than 30 mA (dependi ng on th e load type), the DC/DC A converter should be ready without having to increment DEMBOOSTA[1:0] bits beyond [0:0] level. If at least one of th e two conditions ar e not met (VCC <

3.6V or startup current > 30 mA), it will be necessary to increment the DEMBOOSTA[1:0] bits

until the DC/DC converter is ready. Increment of DEMBOOSTA[1:0] bits increases at the same time the current overflow level in the

same proportion as the startup current. So once the DC/DC converter is ready it advised to decrement the DEMBOOSTA[1:0] bits to restore the overflow current to its normal or desired value.

7511B–SCR–10/05

Figure 9. DC/DC A Converter Initialization Procedure

DEMBOOSTA[1:0]=[0:0]

Set Time-out to 3 ms

VCARD_OK1=1

Time-out

Expired

Increment

DEMBOOSTA[1:0]

AT83C26

Decrement

DEMBOOSTA[1:0]

to adjust the

current overflow

END

DC/DC B converter

DEMBOOSTA[1:0]

is at Maximum?

DC/DC A Converter

Initialization Failure

END

The DC/DC B converter is controlled by DCDCB register. The DC/DC B converter can be switched on even if CPRES2 pin remains inactive. A write operation in VDCB[1:0] (0x01, 0x02, 0x03) starts the DC/DC. When the output voltage

remains within the voltage range specified by VDCB_OK[1:0], the VDCB_OK bit is set. The DC/DC B Converter can work in two different modes which are selected by STEPREGB:

• Pump Mode (STEPREGB = 0): an external inductance of 10 µH must be connected between pins LIB and VCC. VCC can be higher or lower than selected voltage.

• Regulator mode (STEPREGB = 1): no external inductance is required but VCC must be always higher than selected voltage+0.3V.

7511B–SCR–10/05

The current drawn from power suppl y by the DC/DC B conv erter is controll ed during the startup phase in order to avoid high transient cur rent mainly in Pump Mod e which could cause the power supply voltage to drop dramatically . This control is done by means of bits DEMBOOSTB[1:0], which increases progressively the startup current level.

AT83C26

The DC/DCB sensitivity to any overflow current can be modified (20%) by using the ICCADJB bit (DC/DCB register).

Initialization Procedure for DC/DC B converter

The initialization procedure is described in flow chart:

• Select the DC/DC B level by means of bits VDCB[1:0] in DCDCB register,

• Set bits DEMBOOSTB[1:0] in INTERFACEB register following the current level control wanted.

• Monitor VDCB_OK bit in DCDCB register in order to know when the DC/DC B Converter is ready

Figure 10. DC/DC B Converter Initialization Procedure

DEMBOOSTB[1:0]=[0:0]

Set Time-out to 3 ms

VDCB_OK=1

Decrement

DEMBOOSTB[1:0]

Time-out

Expired

Increment

DEMBOOSTB[1:0]

is at Maximum?

DC/DC B Converter Initialization Failure

END

to adjust the

current overflow

END

(ready to start LDO)

Increment of DEMBOOSTB[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. So once the DC/DC B con verter is ready it advise d to decrement the DEMBOO STB[1:0] bits to restore the overfl ow current to its nor mal or desire d value.

7511B–SCR–10/05

LDO initialization Procedure

AT83C26

When the DC/DC B voltage rises the selected voltage (VDCB_OK=1), the card voltage selection on CVCC2, CVCC3, CVCC4 or CVCC5 starts the corresponding LDO.

The CVCC2 card voltage must be st arted i n first (if nee ded). When the VC ARD_OK2 is set, the CVCC3,CVCC4, CVCC5 card voltage are started one after each other (if needed) with the same procedure.

The SC2_FULL bit must be set to use SC2 full interface:

CIO3/CC42 is CC42 and CRST3/CC82 is CC82.

As the power supply of CIO3/CC42 and of CRST3/CC8 2 is CVCC3, when SC2_FULL=1, CVCC3 = CVCC2. The SC3 interface is disable and LDO3 receives LDO2 command (VCARD3[1:0] = VCARD2[1:0]).

Figure 11. LDOn Initialization Procedure (n = 2, 3, 4, 5)

Init condition:

DCDCB started

(VDCB_OK = 1)

Start LDOn,

write VCARDn[1:0]

Set Timer 2ms

IPLUSn = 1

VCARD_OKn = 1

LDOn started

Time-out Expired

and IPLUSn=1

LDOn initialization

failure

The LDOn output voltage must be at 0V before to program 1.8V/3V/5V.

7511B–SCR–10/05

AT83C26

Activation Sequence Overview (n=1, 2, 3, 4, 5)

The activation sequence on SC1 is only available if a card is detected on CPRES1 (CARDIN1 bit = 1).

The activation sequence on SC2 is only available if a card is detected on CPRES2 (CARDIN2 bit = 1).

The activation seq uence on SC3 , SC4, S C5, is only av ailab le if DC/DC B is s tarte d (VDCB_ OK = 1).

The SCn interface starts the activation sequence after a TWI write command in VCARDn[1:0] bits to program the CVCCn voltage.

The SC3, SC4, SC5 interfaces (SIM/SAM interfaces) don’t have card presence detector. After the DC/DC start, the user ap plicati on will check the AT R to detect if a SIM/SAM is present

in the connector. The automatic reset transition mode (ART=1) controls the CRST pin and check if the first start

bit of the ATR respects ISO7816 timings. All status bits of an interface (see bits in registers with ”This bit is cleared by hardware when this

Software Activation for SCn interfaces (n=1, 2, 3, 4, 5) with ARTn bit = 0

The activation sequence is controlled by s oftware using TWI co mmands, depend ing on the cards to support. For ISO 7816 cards, the following sequence can be applied:

1. Card Voltage is set by software to the required value (VCARDn[1:0] bits). The TWI

writing command in VCARDn[1:0] starts the DC/DC (or LDO).

2. Wait of the end of the DC/DC (or LDO) init with a polling on VCARD_OKn bit or wait

for INT be set by software.

3. CKSTOPn, IODISn are programmed by software. CKSTOPn bit is reset to have the

clock running. IODISn (see IO_SELECT for SC2, SC3, SC4, SC5) is reset to enable the transparent mode on CIOn,CC4n, CC8n.

4. CRSTn pin is controlled by software using CARDRSTn bit.

to go Low. When VCARD_OKn bit is set (by hardware), CARDIOn bit should

7511B–SCR–10/05

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