Rainbow Electronics AT83C24NDS User Manual
Features
• Smart Card Interface
– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards
Card Clock Stop High or Low for Card Power-down Modes
Support Synchronous Cards with C4 and C8 Contacts
Card Detection and Automatic de-activation Sequence
Programmable Activation Sequence
– Direct Connection to the Smart Card
Logic Level Shifters
Short Circuit Current Limitation (see electrical characteristics)
8kV+ ESD Protection (MIL/STD 883 Class 3)
– Programmable Voltage
5V ±5% at 65 mA (Class A)
3V ±0.2V at 65 mA (Class B)
1.8V ±0.14V at 40 mA
– Low Ripple Noise: < 200 mV
• Versatile Host Interface
– ICAM (Conditional Access) Compatible
– Two Wire Interface (TWI) Link
Programmable Address Allow up to 8 Devices
– Programmable Interrupt Output
– Automatic Level Shifter (1.6V to VCC)
• Reset Output Includes
– Power-On Reset (POR)
– Power-Fail Detector (PFD)
• High-efficiency Step-up Converter: 80 to 98% Efficiency
• Extended Voltage Operation: 3V to 5.5V
• Low Power Consumption
– 180 mA Maximum In-rush Current
– 30 μA Typical Power-down Current (without Smart Card)
• 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24)
• 18 to 48MHz Clock input (for AT83C24NDS)
• Industrial Temperature Range: -40 to +85°C
• Packages: SO28 and QFN28
Smart Card
Reader
Interface with
Power
Management
AT83C24B
AT83C24NDS
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applications such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in
parallel using the programmable TWI address.
Its high efficiency DC/DC converter, low quiescent current in standby mode makes it
particularly suited to low power and portable applications. The reduced bill of material
allows reducing significantly the system cost. A sophisticated protection system guar
antees timely and controlled shutdown upon error conditions.
The AT83C24NDS is a dedicated version approved by NDS for use with NDS VideoGuard conditional access software in set-top boxes. All AT83C24 datasheet is
applicable to AT83C24NDS. The main differences between AT83C24 and
AT83C24NDS are listed below:
1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS,
CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24
2/ 18MHz minimum on input clock for AT83C24NDS
3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24,
3.3µF mandatory for AT83C24NDS
-
4234F–SCR–10/05
Acronyms TWI: Two-wire Interface
POR: Power On Reset
PFD: Power Fail Detect
ART: Automatic Reset Transition
ATR: Answer To Reset
MSB: Most Significant Bit
LSB: Least Significant bit
SCIB: Smart Card Interface Bus
Block Diagram
DVCC
EVCC
RESET
PRES/ INT
A2/CK, A1/RST, A0/3V, CMDVCC
SCL
SDA
CLK
I/O, C4, C8
VCC
Voltage
supervisor
POR/PFD
TWI
Controller
Clocks Controller
VSS
Main
Control
& Logic Unit
LI
DC/DC
Converter
Timer
16 Bits
Analog
Drivers
CVSS
CVCC
CVCCIN
CPRES
CRST
CIO, CC4, CC8
CCLK
2
AT83C24
4234F–SCR–10/05
Pin Description
Pinouts (Top View) 28-pin SOIC Pinout QFN28 pinout
AT83C24
Signals
Table 1. Ports Description
Pad Name Pad Internal
Power Supply
A2/CK-
A1/RST-
A0/3V
EVCC 3 kV I
C8
1
DVCC
VSS
VCC
CVSS
CVCC
CRST
CCLK
NC
CC4
2
3
4
5
6
7
8
LI
9
10
11
12
13
14
RESET
CMDVCC
CVCCin
Note: 1. NC = Not Connected
2. SOIC and QFN packages are available for AT83C24 and for AT83C24NDS
ESD
Limits
Pad
Type
Description
Microcontroller Interface Function:
TWI bus slave address selection input.
A2/CK and A1/RST pins are respectively connected to CCLK and CRST signals in
“transparent mode” (see
A0/3V is used for hardware activation to select CVCC voltage (3V or 5V).
The slave address of the device is based on the value present on A2, A1, A0 on the
rising edge of
CLK rising edge.
CLK
28
RESET
DVCC
C8
27
26
28
1
2
V
CC
3
4
LI
5
6
7
8
9
CRST
QFN 28
TOP VIEW
101112
NC
CCLK
CLK
25
CC4
C4
PRES/INT
24
23
13
CC8
CPRES
I/O
22
EVCC
21
20
A2
/CK
19
A1
/RST
18
/3V
A0
17
SCL
16
SDA
15
NC
14
CIO
19
17
15
27
26
25
24
23
22
21
20
18
16
PRES/INT
C4
I/O
EVCC
/CK
A2
/RST
A1
/3V
A0
SCL
SDA
NC
CIO
CC8
CPRES
CMDVCC
VSS
CVSS
CVCC
CVCCin
page 17 ).
RESET pin (see Table 2). In fact, the address is taken internally at the 11th
PRES/INT EVCC
RESET VCC
4234F–SCR–10/05
3 kV
3 kV
O
open-
drain
I/O
open-
drain
Microcontroller Interface Function:
Depending on IT_SEL value (see CONFIG4 register),
PRES/INT outputs card presence status or interruptions (page 9)
An internal Pull-up (typ 330kΩ,see Table 18)to EVCC can be activated in the pad if
necessary using INT_PULLUP bit (CONFIG4 register).
Remark: during power up and before registers configuration, the PRES/INT signal must
be ignored.
Microcontroller Interface Function:
• Power-on reset
• A low level on this pin keeps the AT83C24 under reset even if applied on power-on.
It also resets the AT83C24 if applied when the AT83C24 is running (see Power
monitoring §).
• Asserting RESET when the chip is in Shut-down mode returns the chip to normal
operation.
• AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on VCC or
DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or
interrupt other devices. After reset, AT83C24 needs to be reconfigured before
starting a new card session.
3
Table 1. Ports Description (Continued)
Pad Name Pad Internal
Power Supply
ESD
Limits
Pad
Type Description
SDA VCC
SCL VCC
I/O EVCC
C4 EVCC
C8 EVCC
CLK EVCC
CIO CVCC 8 kV+
CC4 CVCC 8 kV+
3 kV
3 kV
3 kV
3 kV I/O
3 kV I/O
3 kV
I/O
open-
drain
I/O
open-
drain
I/O
(pull-up)
(pull-up)
I
I/O
(pull-up)
I/O
(pull-up)
Microcontroller Interface Function
TWI serial data
Microcontroller Interface Function
TWI serial clock
Microcontroller Interface Function
Copy of CIO pin and high level reference for EVCC.
An external pull up to EVCC is needed on IO pin.
I/O is the reference level for EVCC if EVCC is connected to a capacitor.
This feature is unused if EVCC is connected to VCC.
Microcontroller Interface Function
Copy of Card CC4.
Microcontroller Interface Function
Copy of Card CC8.
Microcontroller Interface Function
Master Clock
Smart card interface function
Card I/O
Smart card interface function
Card C4
CC8 CVCC 8 kV+
CPRES VCC 8 kV+
CCLK CVCC 8 kV+ O
CRST CVCC 8 kV+ O
CMDVCC EVCC
VCC 3 kV+ PWR
LI 3 kV+ PWR
3 kV+
I/O
(pull-up)
I
(pull-up)
I
(pull-up)
Smart card interface function
Card C8
Smart card interface function
Card presence
An internal Pull-up to VCC can be activated in the pad if necessary using PULLUP bit
(CONFIG1 register).
Smart card interface function
Card clock
Smart card interface function
Card reset
Microcontroller Interface Function:
Activation/Shutdown of the smart card Interface.
Supply Voltage
VCC is used to power the internal voltage regulators and I/O buffers.
DC/DC Input
LI must be tied to VCC pin through an external coil (typically 4.7 μH) and provides the
current for the charge pump of the DC/DC converter.
It may be directly connected to VCC if the step-up converter is not used (see STEPREG
bit in CONFIG4 register and see minimum VCC values in
Table 21 (class B)).
Table 20 (class A) and
4
AT83C24
4234F–SCR–10/05
Table 1. Ports Description (Continued)
Pad Name Pad Internal
Power Supply
CVCC 8 kV+ PWR
ESD
Limits
AT83C24
Pad
Type Description
Card Supply Voltage
CVCC is the programmable voltage output for the Card interface.
It must be connected to external decoupling capacitors (see page 34 and page 36).
CVCCin 8 kV+ PWR
DVCC 3 kV+ PWR
EVCC 3 kV+ PWR
CVSS 8 kV+ GND
VSS GND Ground
Card Supply Voltage
This pin must be connected to CVCC.
Digital Supply Voltage
Is internally generated and used to supply the digital core.
This pin has to be connected to an external capacitor of 100 nF and should not be
connected to other devices.
Extra Supply Voltage (Microcontroller power supply)
EVCC is used to supply the internal level shifters of host interface pins.
EVCC voltage can be supplied from the external EVCC pin connected to the host power
supply.
If EVCC cannot be connected to the host power supply, it must be tied to an external
capacitor. EVCC voltage can be generated internally by an automatic follow up of the
logic high level on the I/O pin. In this configuration, connect a 100 nF + 100kOhms in
parallel between EVCC pin and VSS pin.
DC/DC Ground
CVSS is used to sink high shunt currents from the external coil.
Note: ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses generated
according to Mil/STD 883 Class3. Recommended capacitors soldered on CVCC and VCC pins.
4234F–SCR–10/05
5
Operational Modes
TWI Bus Control The Atmel Two-wire Interface (TWI) interconnects componen ts on a uniq ue two-wire bu s, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format.
The TWI-bus interface can be used:
– To configure the AT83C24
– To select the operating mode of the card: 1.8V, 3V or 5V
– To configure the automatic activation sequence
– To start or stop sessions (activation and de-activation sequences)
– To initiate a warm reset
– To control the clock to the card in active mode
– To control the clock to the card in stand-by mode (stop LOW, stop HIGH or running)
– To enter or leave the card stand-by or power-down modes
– To select the interface ( connection to the host I/O / C4/ C8)
– To request the status (card present or not, over-current and out of range supply
voltage occurrence)
– To drive and monitor the card contacts by software
– To accurately measure the ATR delay when automatic activation is used
TWI Commands
Frame Structure The structure of the TWI bus data frames is made of one or a series of write and read com-
mands completed by STOP.
Write commands to the AT83C24 have the structure:
ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)
Read commands to the AT83C24 have the structure:
ADDRESS BYTE + DATA BYTE(S)
The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset (hard/soft/general
call) but A2/CK, A1/RST, A0/3V can be used for transparent mode after the reset.
Figure 1. Data transfer on TWI bus
acknowledgement
SDA
SCL
Adresse byte
123456
from slave
78
command
and/or data
9
start condition
6
AT83C24
stop condition
4234F–SCR–10/05
AT83C24
Address Byte The first byte to send to the device is the address byte. The device controls if the hardware
address (A2/CK, A1/RST, A0/3V pins on reset) corresponds to the address given in the
address byte (A2, A1, A0 bits).
If the level is not stable on A2/CK pin (or A1/RST pin, or A0/3V pin) at reset, the user has to send
the commands to the possible address taken by the device.
If A2/CK to A0/3V are tied to the host microcontroller and their reset values are unknown, a general call on the TWI bus allows to reset all the AT83C24 devices and set their address after
A2/CK to A0/3V are fixed.
Figure 2. Address Byte
b7 b6 b5
1
0
Slave Address on 7 Bits
0
b4
b3 b2 b1
0
A2
A1
1 for READ Command
0 for WRITE Command
A0
b0
R/W
Up to 8 devices can be connected on the sam e TWI bus. Each device is configured with a differ ent combination on A2/CK, A1/RST, A0/3V pins. The corresponding address byte values for
read/write operations are listed below.
Table 2. Address Byte Values
A2
(A2/CK pin)
0 0 0 0x41 0x40
0 0 1 0x43 0x42
0 1 0 0x45 0x44
0 1 1 0x47 0x46
1 0 0 0x49 0x48
A1
(A1/RST pin)
A0
(A0/3V pin)
Address Byte
for
Read
Command
Address Byte
for
Write
Command
4234F–SCR–10/05
1 0 1 0x4B 0x4A
1 1 0 0x4D 0x4C
1 1 1 0x4F 0x4E
7
Write Commands The write commands are:
1. Reset:
Initializes all the logic and the TWI interface as after a power-up or power-fail reset. If a
smart card is active when RESET falls, a deactivation sequence is performed. This is a onebyte command.
2. Write Config:
Configures the device according to the last six bits in the CONFIG0 register and to the fol-
lowing four bytes in CONFIG1, CONFIG2, CONFIG3 then CONFIG4 registers. This is a
five bytes command.
Figure 3. Command byte format for Write CONFIG0 command
b7 b6 b5 b4 b3 b2 b1
0
1
X
X
CONFIG0 on 6 Bits
X
X
b0
X
X
3. Write Timer:
Program the 16-bit automatic reset transition timer with the following two bytes. This is a
three bytes command.
4. Write Interface:
Program the interface. This is a one-byte command. The MSB of the command byte is fixed
at 0.
5. General Call Reset:
A general call followed by the value 06h has the same effect as a Reset command.
Table 3. Write Commands Description
Address Byte
(See Table 2) Command Byte
Data Byte 1Data Byte 2Data Byte 3Data Byte
4
1. Reset 0100 A2A1A00 1111 1111
2. Write config
3. Write Timer 0100 A2A1A00 1111 1100 TIMER1 TIMER0
4. Write Interface
5. General Call
Reset
8
AT83C24
0100 A2A1A00
0100 A2A1A00
0000 0000 0000 0110
(10 + CONFIG0 6
bits)
(0+INTERFACE 7
bits)
CONFIG1 CONFIG2 CONFIG3 CONFIG4
4234F–SCR–10/05
AT83C24
Read Command After the slave address has been configured, the read command allows to read one or several
bytes in the following order:
• ST A TUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERF ACE, TIMER1, TIMER0,
CAPTURE1, CAPTURE0
• FFh is completing the transfer if the microcontroller attempts to read beyond the last byte.
Note: Flags are only reset after the corresponding byte read has been acknowledged by the master.
Table 4. Read Command Description
Byte Description Byte Value
Address byte 0100 A2A1A01
Data byte 1 STATUS
Data byte 2 CONFIG0
Data byte 3 CONFIG1
Data byte 4 CONFIG2
Data byte 5 CONFIG3
Data byte 6 CONFIG4
Data byte 7 INTERFACE
Data byte 8 TIMER 1 (MSB)
Data byte 9 TIMER 0 (LSB)
Data byte 10 CAPTURE 1 (MSB)
Data byte 11 CAPTURE 0 (LSB)
Data byte 12 0xFF
Interrupts The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).
• If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).
PRES/
INT is driven Low by any of the following event:
– INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by software )
– VCARD_INT bit set in STATUS register (the DC/DC output voltage has settled)
– over-current detection on CVCC
– VCARDERR bit set in CONFIG0 register (out of range vol t age on CVCC or bit set b y
software)
– ATRERR bit set in CONFIG0 register (no ATR before the card clock counter
overflows or bit set by software).This control of ATR timing is only available if ART bit
=1.
If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release
PRES/
INT pin to high level.
Several AT83C24 devices can share the same interrupt and the microcontroller can identify
the interrupt sources by polling the status of the AT83C24 devices using TWI commands.
4234F–SCR–10/05
• If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing
devices) the PRES/
INT output is High to indicate a card is present and none of the following
event has occured:
9
Card Presence Detection
The card presence is provided by the CPRES pin. The polarity of card presence contact is
selected with the CARDDET bit (see CONFIG1 register). A programmable filtering is controlled
with the CDS[2-0] bits (see CONFIG1 register).
An internal pull-up on the CPRES pin can be disconnected in order to reduce the consumption,
an external pull-up must then be connected to VCC. The PULLUP bit (see CONFIG1 register)
controls this feature.
The card presence switch is usually connected to Vss ( card present if CPRES=1). The CARDDET bit must be set. The internal pull up can be connected.
If the card presence contact is connected to Vcc (card present if CPRES=0), the internal pull-up
must be disconnected (see PULLUP bit) and an external pull-down must be connected to the
CPRES pin.
An interrupt can be generated if a card is inserted or extracted (see interrupts §).
Figure 4. Card Presence Input
VCC
– over-current detection on CVCC
– VCARDERR bit set in CONFIG0 register (out of range vol t age on CVCC or bit set b y
software)
VSS
VCC
VSS
External
Pull-up
Card
Contact
Presence
Card
Contact
Presence
External
Pull-down
CPRES
PRES/INT
VCC
(See Table 18)
Internal
Pull-up
EVCC
= 1 Closed
= 0 Open
INT_PULLUP Bit
PULLUP Bit CARDDET Bit
= 1 Closed
= 0 Open
IT_SEL Bit
IT Controller
= 1 No Card if CPRES = 0
= 0 No Card if CPRES = 1
FILTERING
CDS[2-0]
CARDIN bit
= 1 Card Inserted
= 0 No Card
10
AT83C24
4234F–SCR–10/05
CIO, CC4, CC8 Controller
The CIO, CC4, CC8 output pins are driven re spectively by CARDIO, CARDC4, CARDC8 bits
values or by I/O, C4, C8 signal pins. This selection depends of the IODIS bit value. If IODIS is
reset, data are bidirectional between respectively I/O, C4, C8 pins and CIO, CC4, CC8 pins.
Figure 5. CIO, CC4, CC8 Block Diagram
I/O
AT83C24
CVCC
0
CIO
EVCC
C4
EVCC
C8
IO and CIO pins are linked together thro ugh the on chip level shifters if IODIS bit=0 in INTERFACE register. This is done automatically during an hardware activation.
Their iddle level are 1. With IO high, CIO is pulled up.
The same behavior is applicable on C4/ CC4 and C8/ CC8 pins.
The maximum frequency on those lines depends on CLK frequency (3 clock rising edges to
transfer). With CLK=27MHz, the maximum fre q uen cy on this lin e is 1.5MHz.
Due to the minimum transfer delay allowed for NDS applications, the CLK minimum frequ ency is
18MHz.
CARDIO bit
CARDC4 bit
CARDC8 bit
1
CVCC
0
1
CVCC
0
1
IODIS bit
CC4
CC8
Clock Controller The clock controller generates two clocks (as shown in Figure 6 and Figure 7):
1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK signal,
CARDCK bit or A2/CK pin (in transparent mode).
2. a clock for DC/DC converter.
4234F–SCR–10/05
11
Figure 6. Clock Block Diagram with Software Activation (see page 14)
CLK
A2/CK
Figure 7. Clock Block Diagram with Hardware Activation (see page 14)
CLK
DCK[2:0]
CKS[2:0]
DCK[2:0]
DCCLK
CARDCK bit
DCCLK
DC/DC
0
1
CKSTOP bit
DC/DC
CCLK
A2/CK
CMDVCC
A1/RST
CRST_SEL bit
CKS[2:0]
CARDCK bit
Hardware
activation
CKSTOP bit
0
1
CCLK
CRST Controller The CRST output pin is driven by the A1 /RST pin signal pin or by the CARDRST bit value. This
selection depends of the CRST_SEL bit value (see CONFIG4 register).
If the CRST pin signal is driven by the CARDRST bit value, two modes are available:
• If the ART bit is reset, CRST pin is driven by CARDRST bit.
• If the ART bit is set, CRST pin is controlled and follows the “Automatic Reset Transition”
(
page 15).
12
AT83C24
4234F–SCR–10/05
Figure 8. CRST Block Diagram with soft activation
AT83C24
0
CARDRST bit
Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used)
CARDRST bit
A1/RST
tb delay
see Fig 12
1
ART bit
ART bit
0
1
CRST_SEL bit = 0
0
1
CRST
0
1
CRST
CMDVCC
CMDVCC
Hardware
activation
CRST_SEL bit = 1
deactivation
activation
4234F–SCR–10/05
13
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