Rainbow Electronics AT77C105A User Manual

Features

• Thermal Sensitive Layer Over a 0.35 µm CMOS Array

• Image Zone: 0.4 x 11.6 mm

• Image Array: 8 × 232 = 1856 Pixels

• Pixel Pitch: 50 × 50 µm = 500 dpi Resolution

• On-chip 8-bit Analog to Digital Converter

• Serial Peripheral Interface (SPI) - 2 Modes:

– Fast Mode at 16 Mbps Max for Imaging – Slow Mode at 200 kbps Max for Navigation and Control

• Die Size: 1.5 × 15 mm

• Operating Voltage: 2.3 to 3.6V

• I/O Voltage: 1.65 to 3.6V

• Operating Temperature Range: -40°C to 85°C

• Finger Sweeping Speed from 2 to 20 cm/Second

• Low Power: 4.5 mA (Image Acquisition), 1.5 mA (Navigation), <10 µA (Sleep Mode)

• Hard Protective Coating (>4 Million Sweeps)

• High Protection from Electrostatic Discharge

• Small Form Factor Packaging

FingerChip

Thermal Fingerprint Sweep Sensor,

Description

Atmel’s AT77C105A fingerprint sensor is dedicated to PDA, cellular and smartphone applications. Based on FingerChip thermal technology, the AT77C105A is a linear sensor that captures fingerprint images by sweeping the finger over the sensing area. This product embeds true hardware-based 8-way navigation and click functions as well, as enabling elimination of mechanical joystick devices.

Applications

• Scrolling, Menu and Item Selection for PDAs, Cellular or Smartphone Applications

• Cellular and Smartphones-based Security (Device Protection, Network and ISP Access, E-commerce)

• Personal Digital Agenda (PDA) Access

• User Authentication for Private and Confidential Data Access

• Portable Fingerprint Acquisition

Chip-on-board Package

Hardware Based Navigation and Click Functions, Extended I/O range (1.8-3.3V)

AT77C105A Preliminary

Sweep your finger to make life easier

Actual size of sensor

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Table 1. Pin Description for Chip-on-board Package: AT77C105A-CB08V

Pin Number Name Type Description

1 Not connected 2 Not connected 3 Not connected 4 Not connected 5GNDDGDigital ground supply 6GNDAGAnalog ground supply - connect to GNDD 7 VDDD P Digital power supply 8VDDAPAnalog power supply - connect to V 9SCKI Serial Port Interface (SPI) clock 10 TESTA IO Reserved for the analog test, not connected 11 MOSI I Master-out slave-in data 12 VDD_IO P Input/output power supply - connect IO voltage compatibility accordingly 13 MISO O Master-in slave-out data 14 SCANEN I Reserved for the scan test in factory, must be grounded 15 SSS I Slow SPI slave select (active low 16 IRQ O Interrupt line to host (active low). Digital test pin 17 FSS I Fast SPI slave select (active low)

18 RST I Reset and sleep mode control (active high) 19 FPL I Front plane, must be grounded

Note: The die attach is connected to pin 6 and must be grounded. The FPL pin must also be grounded.

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Figure 1. Typical Application

AT77C105A [Preliminary]

VDDD VDDD

10 kΩ

TESTA

VDD_IO

VDDD

IRQ VDD_IO

MISO VDDD

MOSI

SCK GNDD

10µ

VDDA

SSS VDDA

FSS

10µF

SCANEN GNDA

GND

RST

FPL

GND

The pull-up must be implemented for the master controller. The noise should be lower than 30 mV peak to peak on VDDA.

Figure 2. Pin Description

NC NC NC NC GNDD GNDA VDDD VDDA SCK TESTA MOSI VDD_IO MISO SCANEN SSS IRQ FSS RST FPL

1 2 3 4 5 6 7 8

10 11 12 13 14 15 16 17 18 19

The TESTA pin is only used for testing and debugging. The SCANEN pin is not used in the final application and must be connected to ground.

Warning: SSS and FSS must never be low at the same time. When both SSS and FSS

equal 0, the chip switches to scan test mode. With the SPI protocol, this configuration is not possible as only one slave at a time can be selected. However, this configuration works when debugging the system.

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Specifications

Table 2. Absolute Maximum Ratings

Parameter Symbol Comments Value

Power supply voltage VDDD, VDDA -0.5 to 4.6V Note: Stresses beyond those listed

Front plane FPL GND to V

Digital input

Input/output pads power supply

Storage temperature T

Lead temperature (soldering 10 seconds)

SSS, FSS,

SCK, MOSI

GND to VDD +0.5V

VDD_IO GND to V

-50 to +95°C

stg

leads

Do not solder Forbidden

+0.5V

Table 3. Recommended Conditions of Use

Parameter Symbol Comments Min Typ Max Unit

Positive supply voltage V

2.5 ±5%

3.3 ±1 0%

Front plane FPL Must be grounded GND V

Digital input voltage CMOS levels V

2.3

under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2.5

3.3

3.6 V

Digital output voltage CMOS levels V

Digital load C

Operating temperature range T

amb

Industrial “V” grade -40 to +85 °C

20 50 pF

Maximum current on VDDA IVDDA 0 - 60 mA

Table 4. Resistance

Parameter Min Value Standard Method

ESD

On pins HBM (Human Body Model) CMOS I/O 2 kV (TBC) MIL-STD-883 method 3015.7

On die surface (zap gun) air discharge

Mechanical Abrasion

Number of cycles without lubricant Multiply by a factor of 20 for correlation with a real finger

Chemical Resistance

Cleaning agent, acid, grease, alcohol, diluted acetone 4 hours Internal method

±16 kV

(TBC)

NF EN 6100-4-2

200 000 MIL E 12397B

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AT77C105A [Preliminary]

Note: TBC = To be confirmed

Table 5. Explanation of Test Levels

Level Description

I 100% production tested at +25°C

II 100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)

III Sample tested only

IV Parameter is guaranteed by design and/or characterization testing

V Parameter is a typical value only

VI 100% production tested at temperature extremes

D 100% probe tested on wafer at T

Table 6. Specifications

Parameter Symbol Test Level Min

= +25°C

amb

(1)

Typ Max

(1)

Unit

Resolution IV 50 Micron

Size IV 8 × 232 Pixel

Yield: number of bad pixels I 5 Bad pixels

Power Consumption and DC Characteristics

The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: power supply = 3.3V; T C

120 pF on digital outputs unless otherwise specified.

LOAD

Table 7. Power Requirements

Name Parameter Conditions Test Level Min

DDNAV

DDCLI

DDSLP

DDSTB

Positive supply voltage I 2.3 2.5/3.3 3.6 V

Current on VDD in acquisition mode I 3 4.5 6 mA

Current on VDD in navigation mode I 1 1.5 2 mA

Current on VDD in click mode I 0.2 0.3 0.5 mA

Current on VDD in sleep mode I 10 µA

Current on VDD in stand-by mode I Refer to “Power Management” on page 32

= 25°C; F

amb

= 12 MHz (1600 slices per second); duty cycle = 50%

SCK

(1)

Typ Max

(1)

Unit-

Note: 1. Min and max values are to be confirmed.

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VDD_IO = 1.8V

Table 8. Digital Inputs

Logic Compatibility CMOS

Name Parameter Conditions Test Level Min Typ Max Unit

IOZ

HYST

Low level input current without pullup device

High level input current without pull-down device

Tri-state output leakage without pull-up/down device

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

(1)

VI = 0V I 1 µA

VI = V

DD_IO

VI = 0V or V

DD_IO

I1µA

IV 1 µA

0.15

DD_IO

(1)

I0.6 V

0.4

DD_IO

0.3

DD_IO

(1)

Table 9. Digital Outputs

Logic Compatibility CMOS

Name Parameter Conditions Test Level Min Typ Max Unit

= 4 mA

Low level output voltage

High level output voltage

= 1.8V ±8%

= -4 mA

= 3.3V ±10%

I0.85 V

DD_IO

0.15

(1)

Note: 1. A minimum noise margin of 0.05 VDD should be taken for Schmitt trigger input threshold switching levels compared to V

and VIH values.

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AT77C105A [Preliminary]

VDD_IO = 2.3V to 3.6V

Table 10. Digital Inputs

Logic Compatibility CMOS

Name Parameter Conditions Test Level Min Typ Max Unit

IOZ

HYST

Low level input current without pullup device

High level input current without pull-down device

Tri-state output leakage without pull-up/down device

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

(1)

VI = 0V I 1 µA

VI = V

DD_IO

VI = 0V or V

DD_IO

I1µA

IV 1 µA

0.5

DD_IO

0.09

DD_IO

0.6

DD_IO

(1)

0.06

DD_IO

(1)

Table 11. Digital Outputs

Logic Compatibility CMOS

Name Parameter Conditions Test Level Min Typ Max Unit

= 4 mA

Low level output voltage

DD _IO

= 2.3V to

3.6V

= -4 mA

High level output voltage

DD_IO

= 2.3V to

I0.90 V

3.6V

DD_IO

0.10

(1)

Input/Output Voltage Level Compatibility

The I/O voltage level compatibility is set by the power voltage driven on the VDD_IO pad. For 1.8V level compatibility, connect VDD_IO to a 1.8V power supply.

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Switching Performances

The following characteristics are applicable to the operating temperature -40°C ≤ T ≤ +85°C. Typical conditions are: nominal value; T specified otherwise.

Table 12. Timings

Parameter Symbol Test Level Min Typ Max Unit

Clock frequency acquisition mode

Clock frequency navigation mode and chip control

Duty cycle (clock SCK) DC IV 20 50 80 %

Reset setup time T

Slave select setup time T

Slave select hold time T

Note: 1. T

SCK

= 1/F

(clock period)

CTRL

Table 13. 3.3V ±10% Power Supply

Parameter Symbol Test Level Min Typ Max Unit

Data in setup time T

Data in hold time T

Data out valid T

Data out disable time from SS high

IRQ hold time T

Note: All power supplies = +3.3V

amb

ACQ

CTRL

RSTSU

SSSU

SSHD

DIS

IRQ

= 25°C; F

= 12 MHz; duty cycle = 50%; C

SCK

120 pF in digital output unless

LOAD

IV 8 16 MHz

I- 0.2MHz

I½ T

SCK

(1)

IV 3 ns

IV 1 ns

I30ns

IV 3.8 ns

IV 3 µs

Table 14. 2.5V ±5% Power Supply

Parameter Symbol Test Level Min Typ Max Unit

Data in setup time T

Data in hold time T

Data out valid T

Data out disable time from SS high

IRQ hold time T

Note: All power supplies = +2.5V

AT77C105A [Preliminary]

DIS

IRQ

IV 3 ns

IV 1 ns

I30ns

IV 3.8 ns

IV 3 µs

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AT77C105A [Preliminary]

Table 15. 1.8V ±5% Power Supply

Parameter Symbol Test Level Min Typ Max Unit

Data in setup time T

Data in hold time T

Data out valid T

Data out disable time from SS high

IRQ hold time T

DIS

IRQ

µs

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Timing Diagrams: Slow and Fast SPI Interface

Figure 3. Read Timing Fast SPI Slave Mode

RST

sssu

rstsu

SCK

MISO

Figure 4. Read/Write Timing Slow SPI Slave Mode

SCK

sssu

sshd

dis

sshd

MOSI

MISO

Figure 5. Read Status Register to Release IRQ

SCK

MOSI

IRQ

11 0 0 0 X

Figure 6. Chip Initialization

RST

SCK

Min = 10 µs

rstsu

irq

MISO

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Functional Description

AT77C105A [Preliminary]

The AT77C105A is a fingerprint sensor based on FingerChip technology. It is controlled by an SPI serial interface through which output data is also transferred (a slow SPI for the pointing function and a fast one for acquisition). Six modes are implemented:

– Sleep Mode: A very low consumption mode controlled by the reset pin RST.

In this mode, the internal clocks are disabled and the registers are initialized.

– Stand-by Mode: Also a low consumption mode that waits for an action from

the host. The slow serial port interface (SSPI) and control blocks are activated. In this mode the oscillator can remain active.

– Click Mode: Waits for a finger on the sensor. The SSPI and control blocks

are activated. The local oscillator, the click array and the click block are all activated.

– Navigation Mode: Calculates the finger’s x and y movements across the

sensor. The SSPI and control blocks are still activated. The local oscillator, the navigation array and the navigation block are also activated.

– Acquisition Mode: Slices are sent to the host for finger reconstruction and

identification. The SSPI and control blocks are still activated. The fast serial port interface block (FSPI) and the acquisition array are activated, as well as the local oscillator when watchdog is required.

– Test: This mode is reserved for factory testing.

In the final application, three main modes are used:

– Stand-by: Low consumption mode – Pointing: Equivalent to click and navigation modes – Acquisition: Fingerprint image capture

Note: The term”host” describes the processor (controller, DSP...) linked to the sensor. It is the

master. In the description of n-bit registers (see “Function Registers” on page 13), the term “b0” describes the Least Significant Bit (LSB). The term “b(n-1)” describes the Most Significant Bit (MSB). Binary data is written as 0b_ and hexadecimal data as 0x_.

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Sensor and Block Diagram

Figure 7. Functional Block Diagram

FPL VDDA GNDA VDDD

Pixel Array

(232 x 8)

Array

CTRL

GNDD RST

VDD_IO

Fast Serial

Interface

Acquisition

Navigation Algorithms

SPI

(8-16 MHz)

FSS

SCK

MISO

Oscillator (420 kHz)

Click Pixels

(12)

Click

CTRL

Click

Algorithm

Watchdog

Heating

The circuit is divided into the following main sections:

• An array or frame of 8 × 232 pixels + 1 dummy column

• An analog to digital converter

• An on-chip oscillator

• Control and status registers

• Navigation and click units

• Slow and fast serial interfaces

Slow Serial

Interface

SPI

(200 kHz)

Control

Test

MOSI

SSS

IRQ

SCANEN

TESTA

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