Rainbow Electronics AT75C310 User Manual

Features

• ARM7TDMI

• Two 16-bit Fixed-point OakDSPCore

• 256 x 32-bit Boot ROM

• 88K Bytes of Integrated Fast RAM for Each DSP

• Flexible External Bus Interface with Programmable Chip Selects

• Dual Codec Interface

• Multi-level Priority, Individually Maskable, Vectored Interrupt Controller

• Three 16-bit Timer/Counters

• Additional Watchdog Timer

• Two USARTs with FIFO and Modem Control Lines

• Industry-standard Serial Peripheral Interface

• Up to 23 General-purpose I/O Pins

• On-chip DRAM Controller

• JTAG Debug Interface

• Software Development Tools Available for ARM7TDMI and OakDSPCore

• Supported by a Wide Range of Ready-to-use Application Software, including

Multitasking Operating System, Networking, Modems and Voice-processing Functions

• Available in a 160-lead PQFP Package

• 3.3V Power Supply

™

ARM® Thumb® Processor Core

Cores

Description

The Atmel AT75C310 Smart Internet Appliance Processor (SIAP™) is a high-performance processor designed for internet appliance applications such as Internet Telephony (Voice over Internet Protocol – VoIP). The AT75C310 is built around an ARM7TDMI microcontroller core running at 20 MIPS with two DSP co-processors running at 40 MIPS each. All three processors deliver unmatched performance for low power consumption.

In a typical standalone VoIP phone, one DSP handles the voice-processing functions (voice compression, acoustic echo cancellation, etc.) while the other deals with the telephony functions such as dialing, line echo cancellation, caller ID detection, highspeed modem, etc. In such an application, the power of the ARM7TDMI allows it to run the VoIP protocol stack as well as all the system control tasks.

Atmel provides the AT75C310 with three levels of software modules:

• A special port of the Linux kernel as the proposed operating system

• A comprehensive set of tunable DSP algorithms for modems and voice processing,

tailored to be run by the DSP subsystems

• A broad range of application-level software modules such as H323 telephony or

POP-3/SMTP e-mail services

Smart Internet Appliance Processor (SIAP™)

AT75C310 – CPU Peripherals

Rev. 1369A–01/01

AT75C310 Pin Configuration

Table 1. AT75C310 Pinout in 160-lead PQFP Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

VDD

D11

NCE3

VSS

NDOE

D12

D13

NWE0

D14

VSS

VDD

NWE1

D15

NDWE

VDD

VSS

VDD

MOSI

MISO

SPCK

NPCSS

RXDA

TXDA

VSS

VDD

NRTSA

NCTSA

NDTRA

NDSRA/BOOTN

VSS

VDD

NDCDA

TXDB

RXDB

VDD

PB7/NCE1

VSS

PB6/NWDOVF

PB5/NRIA

PB4

VSS

VDD

PB3

RESET

VDD

IRQ0

PB2/TIOB1

PB9

PB1/TIOA1

PB8/NCE2

PB0/TCLK1

VDD

XREF80

VSS

XTALIN

XTALOUT

VSS

XREF96

VDD

TST

NTRST

TCK

TMS

TDI

TDO

VSS

PA0/OakAIN0

PA1/OakAIN1

PA2/OakAOUT0

PA3/OakAOUT1

VSS

VDD

PA4/OakBIN0

PA5/OakBIN1

PA6/OakBOUT0

PA7/OakBOUT1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

VDD

PA8/TCLK0

PA 9 /T I O A 0

VSS

PA10/TIOB0

PA11/SCLKA

VSS

PA12/NPCS1

VDD

VSS

VDD

NREQ

FIQ

NGNT

VSS

VDD

SCLKA

FSA

STXA

SRXA

VDD

VSS

A10

A11

A12

A13

A14

A15

VSS

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

VSS

A16

A17

VDD

VSS

A18

A19

A20

A21

VDD

VSS

NCAS0

NCAS1

VSS

NRAS0

NRAS1

VSS

VDD

SRXB

STXB

FSB

VDD

VSS

SCLKB

NSOE

VDD

VSS

NCE0

D10

VDD

AT75C310

AT75C310 Pin Description

Table 2. AT75C310 Pin Description

Block Pin Name Type Function

A[21:0] O Address Bus

AT75C310

Common Bus

Dynamic Memory Controller

Static Memory Controller

I/O Port A PA[12:0] I/O General Purpose I/O Lines. Multiplexed with peripheral I/Os

I/O Port B PB[9:0] I/O General Purpose I/O Lines. Multiplexed with peripheral I/Os

DSP Subsystem A

DSP Subsystem B

Timer/Counter 0

D[15:0] I/O Data Bus

NREQ I Bus Request

NGNT O Bus Grant

NRAS[1:0] O Row Address Strobe

NCAS[1:0] O Column Address Strobe

NDWE O DRAM Write Enable

NDOE O DRAM Output Enable

NCE[3:0] O Chip Selects

NWE[1:0] O Byte Select/Write Enable

NSOE O SRAM Output Enable

OakAIN[1:0] I OakDSPCore A User Inputs

OakAOUT[1:0] O OakDSPCore A User Outputs

OakBIN[1:0] I OakDSPCore B User Inputs

OakBOUT[1:0] O OakDSPCore B User Outputs

TCLK0 I Timer 0 External Clock

TIOA0 I/O Timer 0 Signal A

TIOB0 I/O Timer 0 Signal B

TCLK1 I Timer 1 External Clock

Timer/Counter 1

Watchdog NWDOVF O Watchdog Overflow

Serial Peripheral Interface

TIOA1 I/O Timer 1 Signal A

TIOB1 I/O Timer 1 Signal B

MISO I/O Master In/Slave Out

MOSI I/O Master Out/Slave In

SPCK I/O Serial Clock

NPCSS I/O Chip Select/Slave Select

NPSC1 O Optional SPI Chip Select 1

Table 2. AT75C310 Pin Description (Continued)

Block Pin Name Type Function

RXDA I Receive Data

TXDA O Transmit Data

NRTSA O Ready to Send

NCTSA I Clear To Send

USART A

NDTRA O Data Terminal Ready

NDSRA/BOOTN I Data Set Ready

NDCDA I Data Carrier Detect

NRIA I Ring Indicator

SCLKA I/O Serial Clock

USART B

JTAG Interface

Codec Interface A

Codec Interface B

RXDB I Receive Data

TXDB O Transmit Data

NTRST I JTAG Test Reset

TCK I JTAG Test Clock

TMS I JTAG Test Mode Select

TDI I JTAG Test Data Input

TDO O JTAG Test Data Output

SCLKA I/O Codec Serial Clock

FSA I/O Frame Sync Pulse

STXA O Transmit Data to Codec

SRXA I Receive Data from Codec

SCLKB I/O Codec Serial Clock

FSB I/O Frame Sync Pulse

STXB O Transmit Data to Codec

SRXB I Receive Data from Codec

RESET I Master Reset

FIQ/LOWP I Fast Interrupt/Low Power

IRQ0 I External Interrupt request

Miscellaneous

XREF96 I External 96 MHz PLL Reference

XREF80 I External 80 MHZ PLL Reference

XTALIN I External Crystal Input

XTALOUT O External Crystal Output

TST I Test Mode

AT75C310

Block Diagram

Figure 1. AT75C310 Block Diagram

AT75C310

OakDSPCore 0

DSP Subsystem

OakDSPCore 1

DSP Subsystem

JTAG

Embedded

ICE

ARM7TDMI Core

Boot ROM

IRQ

Controller

AMBA

ASB

Bridge

Reset

Clocks

DRAM

Controller

External Bus

Interface

SRAM

Controller

Peripheral Data

Controller

SPI

PIO 0

PIO 1

Watchdog

Timer

USART 0

USART 1

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

APB

Architectural Overview

The AT75C310 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).

The ASB is designed for maximum performance. It interfaces the processor with the on-chip DSP subsystems and the external memories and devices by means of the External Bus Interface (EBI).

The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and the memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, microcontroller performance is increased and power consumption reduced.

The AT75C310 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has a 16 KB address space allocated in the upper part of the address space. The peripheral register set is composed of control, mode, data, status and interrupt registers.

To maximize the efficiency of bit manipulation, frequentlywritten registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can

™

thus be modified without having to use costly read-modifywrite and complex bit-manipulation instructions, and without having to store-disable-restore the interrupt state.

All external signals of the on-chip peripherals are controlled by the parallel I/O controllers. The PIO controllers can be programmed to insert an input filter on each pin or to generate an interrupt on a signal change. After reset, the user must carefully program the PIO controllers in order to define which peripheral signals are connected with off-chip logic.

The ARM7TDMI processor operates in little-endian mode in the AT75C310. The processor’s internal architecture and the ARM and Thumb instruction sets are described in theAtmel ARM7TDMI datasheet, literature number 0673. The memory map and the on-chip peripherals are described in this datasheet. The DSP subsystems are described in the datasheet entitled “AT75C310 DSP Subsystem”, literature number 1368. Electrical characteristics are documented in a separate datasheet entitled “AT75C310 Electrical and Mechanical Characteristics”, literature number 1370.

PDC: Peripheral Data Controller

The AT75C310 has a four-channel PDC dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART.

The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end of transfer interrupt is generated by the corresponding USART. For more details on PDC operation and programming, see the section “USART: Universal Synchronous/Asynchronous Receiver/Transmitter” on page 53.

AT75C310

Memory Map

The memory map is divided into memory regions of 64 megabytes. The top seven memory regions are reserved and subdivided for internal memory blocks or peripherals within the AT75C310. The AT75C310 can define up to six other active external memory regions by means of the static memory controller and DRAM memory controller.

The memory map assumes default values on reset. External memory regions can be reprogrammed to other base addresses. For details, see the sections “SMC: Static Memory Controller” on page 15 and “DMC: Dynamic Memory Controller” on page 24. It should be noted that the internal memory regions have fixed locations that cannot be reprogrammed.

Table 3. Memory Map

Default Base Address Region Type Normal Mode

There are no hardware locks to prevent incorrect programming of the regions. Programming two or more regions to have the same base address results in undefined behavior.

The ARM reset vector with address 0x00000000 is mapped to internal ROM or external memory depending on the signal pin NDSRA/BOOTN. After booting, the ROM region can be disabled and some external memory such as DRAM or Flash can be mapped to the bottom of the memory map by programming SMC_CS0 or DMC_MR0.

AT75C310

0xFF000000

0xFE000000

0xFD000000

0xFC000000

0xFB000000

0xFA000000

0xF9000000

0x50000000

0x40000000

0x30000000

0x20000000

0x10000000

0x00000000

Internal Peripherals

Internal OAK B (24K x 16 Program SRAM)

Internal OAK A (24K x 16 Program SRAM)

Internal Reserved

Internal Dual-port Mailbox for Oak B (2K x 16)

Internal Dual-port Mailbox for Oak A (2K x 16)

Internal Boot ROM (1K x 16)

External DMC_MR1

External DMC_MR0

External SMC_CS3

External SMC_CS2

External SMC_CS1

External/Internal SMC_CS0

Boot Mode

0x000003FF

Boot ROM

0x00000000

Peripheral Memory Map

The register maps for each peripheral are described in the corresponding sections of this datasheet. The peripheral memory map has 16KB reserved for each peripheral.

Table 4. Peripheral Memory Map

Base Address Peripheral Description

0xFF000000 MODE Mode Controller

0xFF004000 SMC Static Memory Controller

0xFF008000 DMC DRAM Memory Controller

0xFF00C000 PIO A Programmable I/O

0xFF010000 PIO B Keypad PIO

0xFF014000 TC Timer/Counter Channels

0xFF018000 USART A USART

0xFF01C000 USART B USART

0xFF020000 SPI Serial Peripheral Interface

0xFF024000 Reserved

0xFF028000 WDT Watchdog Timer

0xFF030000 AIC Advanced Interrupt Controller

AT75C310

Initialization

Reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT75C310 must be held at valid logic levels.

There are three ways in which the AT75C310 can enter reset:

1. Hardware reset. Caused by asserting the RESET pin, e.g., at power-up.

2. Watchdog timer reset. The watchdog timer can be programmed so that if it is timed out, a pulse is generated that forces a chip reset.

3. Software reset. There are two software resets which are asserted by writing to bits [11:10] of the AT75C310 mode register. SIAP_MD[11] forces a software reset with RM set low and SIAP_MD[10] forces a reset with RM set high.

AT75C310

Reset Pin

The reset pin should be asserted for a minimum of 10 clock cycles. However, if external DRAM is fitted, reset should be applied for the time interval specified by the DRAM datasheet, typically 200 µs. The OakDSPCores are only released from reset by ARM program control.

When reset is released, the pin NDSRA/BOOTN is sampled to determine if the ARM should boot from internal ROM or from external memory connected to NCS0. The details of this boot operation are described in the section “Boot Mode” on page 11.

Processor Synchronization

The ARM and the OakDSPCore processors have their own PLLs and at power-on each processor has its own indeterminate lock period. To guarantee proper synchronization of inter-processor communication through the mailboxes, a specific reset sequence should be followed.

Once the ARM core is out of reset, it should set and clear the reset line of each OakDSPCore three times. This guarantees message synchronization between the ARM and the OakDSPCores.

Clocking

The AT75C310 uses an external 16 MHz crystal (XCLK) and two on-chip PLLs to generate the internal clocks. One PLL generates a 96 MHz clock that is divided down to produce the ARM clocks and the other produces an 80 MHz clock used to generate the Oak and Codec interface clocks.

The ARM core runs at 24 MHz whereas the DSP subsystems run at 40 MHz.

Figure 2. AT75C310 Clock Circuitry Diagram

Note that there is a common synchronous mode where the ARM and OAK systems both run from the Oak PLL. This results in the ARM running at 20 MHz and the Oak at 40 MHz.

A block diagram of the clock circuitry can be seen below in Figure 2.

. .

10 pF

16 MHz

XTAL

XTALIN

1 MΩ

XTALOUT

Oscillator

16 MHz

100 Ω 10 nF

PLL

. .

PLL

XREF 96

XREF 80

96 MHz

80 MHz

. .

Phase

Generator

Phase

Generator

24 MHz

40 MHz

ARM Clock Core

DSP Subsystem A Clocks

DSP Subsystem B Clocks

AT75C310

Boot Mode

When the reset pin is deasserted, i.e., when the AT75C310 exits from reset state, the NDSRA/BOOTN pin is sampled. If NDSRA/BOOTN is high, the ARM starts fetching from address 0x00000000, which corresponds to the external memory. In a typical application, the external memory located at 0x00000000 is a nonvolatile memory containing the application.

If NDSRA/BOOTN is low, the internal boot ROM is remapped to 0x00000000 and the internal boot program is executed.

The boot program configures the USART A, waits for a sync pattern, undertakes handshake processes and copies all the incoming serial data into the Oak A internal program

AT75C310

memory. Note that this memory is in the ARM memory space whereas the Oak A memory is in reset. Following download, the ARM executes a jump and starts to fetch out of the Oak A program memory. The downloaded routine is typically more complex and faster and is able to program a true application into the Flash memory.

If the initial handshake process fails, the AT75C310 falls back into the normal boot mode, i.e., out of the external memory.

The assembly source code of the boot program is given in section “Assembly Source Code – Boot Program” on page

126.

AT75C310 Mode Controller

The mode controller is a memory-mapped peripheral which sits on the APB. It is used to configure the mode in which the AT75C310 operates.

Table 5. Mode Controller Registers Map

0x0 SIAP_MD Mode Register Read/write 0x00000001 if NDSRA/BOOTN is 1; else0x00000000

0x4 SIAP_ID ID Register Read 0x00010001 for 240-lead package;

0x8 SIAP_RST Reset Status

Name Description Access Reset Value

0x00000001 for 160-lead package

Read/write 0x00000001 after hard reset

Mode Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

CRB CRA DBB DBA SW2 SW1 LPCS

76543210 – LP CS IB IA RB RA RM

• RM: Remap

When reset is released, this flag is set to the value of NDSRA/BOOTN. When RM is active low, the Boot ROM is mapped to 0x00000000. Subsequently, this flag can be set high by software so that the ROM mapping is disabled and another memory controller region (e.g., Flash) is mapped to location 0x00000000.

• RA: OAKA Reset

This flag resets to active low so that the Oak A is held in reset. The Oak A is released from reset by asserting this flag high and then low three times. This generates the required reset sequence to the Oaks of 010101.

• RB: OAKB Reset

This flag resets to active low so that Oak B is held in reset. The Oak B is released from reset by asserting this flag high and then low three times. This generates the required reset sequence to the Oaks of 010101.

• IA: Inhibit Oak A Clock

This flag resets to active low so that the Oak A clock is enabled. The Oak A clock is inhibited by asserting this flag high.

• IB: Inhibit Oak B Clock

This flag resets to active low so that the Oak B clock is enabled. The Oak B clock is inhibited by setting this flag high.

• CS: Synchronous Clock Mode

When high, the ARM, Oak A and Oak B run from the OakDSPCore clock, thus the ARM runs at 20 MHz and the OakDSPCores at 40 MHz. When low, the ARM and OakDSPCores run from asynchronous clocks.

AT75C310

• LP: Low Power Mode

When high, the ARM is clocked at the low-power frequency. The DMC clock is disabled so the DRAM refresh is also disabled. This field can only be set to high. Writing a zero to this field has no effect. Low-power mode can only be exited by a reset. See the section “Clocking” on page 10 for more details.

• LPCS: Low Power Clock Select

This field is used to select a slower clock frequency for the ARM system clock. This field is sampled when the LP flag is changed from low to high. When the LP flag is low, this field is ignored. Once the LP flag has been set high, further changes to this field have no effect. See the section “Clocking” on page 10 for more details.

LPCS Divisor ACLK Frequency

01 8 MHz

132 500 kHz

0 128 125 kHz

11024 16 kHz

• DBA: Oak A Debug Mode

This flag resets low. This bit should be set to enter Oak A debug mode (test-specific pins are multiplexed out on functional pins).

• DBB: Oak B Debug Mode

This flag resets low. This bit should be set to enter Oak B debug mode (test-specific pins are multiplexed out on functional pins).

• CRA: Codec A Reset

This flag resets to active low so that the Codec A is held in reset. The Codec A is released from reset by asserting this flag high.

• CRB: Codec B Reset

This flag resets to active low so that the Codec A is held in reset. The Codec A is released from reset by asserting this flag high.

• SW1: Software Reset 1

Writing a one to this bit forces the AT75C310 into reset with RM set to zero.

• SW2: Software Reset 2

Writing a one to this bit forces the AT75C310 into reset with RM set to one.

ID Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

PKG –––––––

76543210 –––––VERS VERS VERS

• PKG: Package

This bit reflects the state of the data bus width signal DBW and indicates the AT75C310 package size, 1 for the 240lead PQFP option and 0 for the 160-lead PQFP option. The signal DBW is bonded to either power or ground depending on the package used during manufacturing.

• VERS[2:0]: Version

This flag indicates the version number of the AT75C310. This field is reset to 0 x 1.

Reset Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––RST RST RST

• RST[2:0]: Reset

These bits indicate the cause of the last reset.

RST Reset Event

0 1 Hardware

1 0 Watchdog Timer

0 0 Software

AT75C310

EBI: External Bus Interface

The EBI generates the signals which control access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64 megabytes. Its main characteristic is to allow the connection of both static and dynamic memories on the same bus. The address and data lines are shared between static and dynamic devices whereas the control lines are distinct. The control lines are driven by two separate subsystems: the SMC (static memory controller) and the DMC (dynamic memory controller). The static devices include regular static memories and memory-mapped peripherals. The supported dynamic devices are mainly EDO RAMs.

SMC: Static Memory Controller

The static memory controller (SMC) is used by the AT75C310 to access external static memory devices. Static memory devices include external Flash, SRAM or peripherals.

The SMC provides a glueless memory interface to external memory using the common address and data bus and some dedicated control signals. The SMC is highly programmable and has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. The SMC supports different access protocols allowing single clockcycle accesses. The SMC is programmed as an internal peripheral that has a standard APB bus interface and a set

AT75C310

of memory-mapped registers. The SMC shares the external address and data buses with the DMC and any external bus master.

External Memory Mapping

The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories. Note that A2 - A23 is only significant for 32-bit memory and A1 - A23 for 16-bit memory.

If the physical memory-mapped device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The SMC correctly handles any valid access to the memory device within the page.

In the event of an access request to an address outside any programmed page, an abort signal is generated by the internal decoder. Two types of abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are 0x0000000C and 0x00000010. It is up to the system programmer to program the exception handling routine used in case of an abort.

If the AT75C310 is in internal boot mode, any chip select configured with a base address of zero will be disabled as the internal ROM is mapped to address zero.

Signal Interface Table 6. Signal Interface

FPDRAM Description Type Notes

A[23:0] Address bus O

D[31:0] Data bus I/O

NCE[3:0] Active low chip enables O

NWE[3:0] Active low byte select/write strobe signals O

NWR Active low write strobe signals O

NSOE Active low read enable signal O

NWAIT Active low wait signal I

Data Bus Width

A data bus width of 32 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the Chip Select Register (SMC_CSR) of the corresponding chip select.

The AT75C310 always boots up with a data bus width of 16 bits set in SMC_CSR0.

Byte-write or Byte-select Mode

Each chip select with a 32-/16-bit data bus operates with one or two different types of write mode:

1. Byte-write mode supports four (32-bit bus) or two (16-bit bus) byte writes and a single read signal.

2. Byte-select mode selects the appropriate byte(s) using four (32-bit bus) or two (16-bit bus) byte-select lines and separate read and write signals.

This option is controlled by the BAT field in SMC_CSR for the corresponding chip select.

Byte-write access can be used to connect four 8-bit devices as a 32-bit memory page or two 8-bit devices as a 16-bit memory page.

For a 32-bit bus:

• The signal NWE0 is used as the write enable signal for

byte 0.

• The signal NWE1 is used as the write enable signal for

byte 1.

• The signal NWE2 is used as the write enable signal for

byte 2.

• The signal NWE3 is used as the write enable signal for

byte 3.

• The signal NSOE enables memory reads to all memory

blocks.

For a 16-bit bus:

• The signal NWE0 is used as the write enable signal for

byte 0.

D[15:0] used when Data Bus Width is 16

NCE[3] can be configured for LCD interface mode

• The signal NWE1 is used as the write enable signal for

byte 1.

• The signal NSOE enables memory reads to all memory

blocks.

Byte-select mode can be used to connect one 32-bit device or two 16-bit devices in a 32-bit memory page or one 16-bit device in a 16-bit memory page.

For a 32-bit bus:

• The signal NWE0 is used to select byte 0 for read and

write operations.

• The signal NWE1 is used to select byte 1 for read and

write operations.

• The signal NWE2 is used to select byte 2 for read and

write operations.

• The signal NWE3 is used to select byte 3 for read and

write operations.

• The signal NWR is used as the write enable signal for

the memory block.

• The signal NSOE enables memory reads to the memory

block.

For a 16-bit bus:

• The signal NWE0 is used to select byte 0 for read and

write operations.

• The signal NWE1 is used to select byte 1 for read and

write operations.

• The signal NWR is used as the write enable signal for

the memory block.

• The signal NSOE enables memory reads to the memory

block.

During boot, the number of external devices (number of active chip selects) and their configurations must be programmed as required. The chip select addresses that are programmed take effect immediately. Wait states also take effect immediately when they are programmed to optimize boot program execution.

AT75C310

Read Protocols

The SMC provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the NSOE (read cycle) waveform.

The protocol is selected by the DRP field in the memory control register (SMC_MCR) and is valid for all memory devices. Standard read protocol is the default protocol after reset.

• Standard Read Protocol

Standard read protocol implements a read cycle in which NSOE and the write strobes are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access, as well as the output of address and NCE before the read cycle begins.

During a standard read protocol external memory access, NCE is set low and ADDR is valid at the beginning of the access, whereas NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The write strobes are the same in both protocols. The write strobes always go low in the second half of the master clock cycle.

• Early Read Protocol

Early read protocol provides more time for a read access from the memory by asserting NSOE at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NSOE remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contention on the external bus.

In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e., data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing.

Write Protocol

During a write cycle, the data becomes valid after the falling edge of the write strobe signal and remains valid after the rising edge of the write strobe. The external write strobe waveform (on the appropriate write strobe pin) is used to control the output data timing to guarantee this operation.

Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. In early read protocol, the data can remain

valid longer than in standard read protocol due to the additional wait cycle that follows a write access.

Wait States

The SMC can automatically insert wait states. The different types of wait states are:

• Standard wait states

• Data float wait states

• External wait states

• Chip select change wait states

• Early read wait states (see “Read Protocols” on page 17

for details)

• Standard wait states

Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same register. The correspondence between the number of standard wait states programmed and the number of cycles during which the write strobe pulse is held low is found in Table 7. For each additional wait state programmed, an additional cycle is added.

Table 7. Correspondence Wait States/Number of Cycles

Wait States Cycles

01/2

• Data Float Wait State

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory.

The data float output time (TDF) for each external memory device is programmed in the TDF field of the SMC_CSR register for the corresponding chip select. The value (0 - 7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go high-impedance after the memory is disabled.

The SMC keeps track of the programmed external data float time even when making internal accesses, thus ensuring that the external memory system is not accessed while it is still busy.

Internal memory accesses and consecutive accesses to the same external memory do not have added data float wait states.

When data float wait states are being used, the SMC prevents the DMC or external master from accessing the external data bus.

• External Wait

The NWAIT input can be used to add wait states at any time NWAIT is active low and is detected on the rising edge of the clock. If NWAIT is low at the rising edge of the clock, the SMC adds a wait state and does not change the output signals.

• Chip Select Change Wait States

A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories and no wait states have been inserted. If wait states have been inserted (e.g., data float wait), then none are added.

LCD Interface Mode

NCE3 can be configured for use with an external LCD controller by setting the LCD bit in the SMC_CSR3 register.

Table 8. SMC Register Map

Offset Register Description Register Name Access Reset State

Additionally, WSE must be set and NWS programmed with a value of 1 or more.

In LCD mode, NCE3 is shortened by one-half clock cycle at the leading and trailing edges, providing positive address setup and hold. For read cycles, the data is latched in the SMC as NCE3 is raised at the end of the access.

SMC Register Map

The SMC is programmed using the registers listed in Table

8. The memory control register (SMC_MCR) is used to program the number of active chip selects and data read protocol. Four chip select registers (SMC_CSR0 to SMC_CSR3) are used to program the parameters for the individual external memories. Each SMC_CSR must be programmed with a different base address even for unused chip selects. The AT75C310 resets such that SMC_CSR0 is configured as having a 16-bit data bus.

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

Chip Select Register

Reserved

Memory Control Register

SMC_CSR0 Read/write 0x0000203D

SMC_CSR1 Read/write 0x10000000

SMC_CSR2 Read/write 0x20000000

SMC_CSR3 Read/write 0x30000000

–– –

SMC_MCR Read/write 0

AT75C310

SMC Chip Select Register

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

BA –––LCD

15 14 13 12 11 10 9 8

––CSEN BAT TDF PAGES

76543210

PA GE S – WSE NWS DBW

• DBW: Data Bus Width

DBW Data Bus Width

00Reserved

0 1 16-bit external bus

1 0 32-bit external bus

11Reserved

• WSE: Wait State Enable

• NWS: Number of Wait States

This field is valid only if WSE is set.

NWS WSE Wait States

• PAGES: Page Size

PAGES Page Size

0 0 1 MB BA[31 - 20]

0 1 4 MB BA[31 - 22]

1 0 16 MB BA[31 - 24]

11 Reserved –

• TDF: Data Float Output Time

TDF Cycles after Transfer

00 0 0

00 1 1

01 0 2

01 1 3

10 0 4

10 1 5

Base

Address

11 0 6

11 1 7

• BAT: Byte Access Mode

0 = Byte-write Mode 1 = Byte-select Mode

• CSEN: Chip Select Enable

Active high

• LCD: LCD Mode Enable

Active high. SMC_CSR3 only.

• BA: Base Address

This field contains the high-order bits of the base address. If the page size is larger than 1 MB, then the unused bits of the base address are ignored by the SMC decoder.

AT75C310

SMC Memory Control Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––DRP ––––

• DRP: Data Read Protocol

0 = Standard Read Mode 1 = Early Read Mode

AT75C310

Switching Waveforms

Figure 3 shows a write to memory 0, followed by a write and a read to memory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 0. SMC_MCR is programmed for early reads from all memories.

The write to memory 0 is a 32-bit word access and, therefore, all four NWE strobes are active. As BAT = 0, they are configured as write strobes and have the same timing as NWR. As the access employs a single wait state, the write strobe pulse is one clock cycle long.

There is a chip select change wait state between the memory 0 write and the memory 1 write. The new address is output at the end of the memory 0 access but the strobes are delayed for one clock cycle.

The write to memory 1 is a half-word (16-bit) access to an odd half-word address and, therefore, NWE2 and NWE3 are active. As BAT = 1 they are configured as byte-select

Figure 3. Write to Memory 0, Write and Read to Memory 1

BCLK

signals and have the same timing as NCE. As the access has no internal wait states, the write strobe pulse is onehalf clock cycle long. Data and address are driven until the write strobe rising edge is sensed at the SIAP pin to guarantee positive hold times.

There is an early read wait state between the memory 1 write and the memory 1 read to provide time for the AT75C310 to disable the output data before the memory is read. If the read was normal mode, i.e., not early, the NSOE strobe would not fall until the rising edge of BCLK and no wait state would be inserted. If the write and early read were to different memories, then the early read wait state is not required as a chip select wait state will be implemented.

The read from memory 1 is a byte access to an address with a byte offset of two and, therefore, only NWE2 is active.

NCE0

NCE1

NWR

NSOE

NWE0

NWE1

NWE2

NWE3

D (SIAP)

D (MEM)

AT75C310

Figure 4 shows a write and a read to memory 0, followed by a read and a write to memory 1. SMC_CSR0 is programmed for zero wait states with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 1. SMC_MCR is programmed for normal reads from all memories

The write to memory 0 is a byte access and, therefore, only one NWE strobe is active. As BAT = 0, they are configured as write strobes and have the same timing as NWR.

The memory 0 read immediately follows the write as early reads are not configured and an early read wait state is not required. As early reads are not configured, the read strobe pulse is one-half clock cycle long.

output at the end of the memory 0 access but the strobes are delayed for one clock cycle.

The write to memory 1 is a half-word (16-bit) access to an even half-word address and, therefore, NWE0 and NWE1 are active. As BAT = 1, they are configured as byte select signals and have the same timing as NCE.

As DFT = 1 for memory 1, a wait state is implemented between the read and write to provide time for the memory to stop driving the data bus. DFT wait states are only implemented at the end of read accesses.

The read from memory 1 is a byte access to an address with a byte offset of two and, therefore, only NWE2 is

active. There is a chip select change wait state between the memory 0 write and the memory 1 read. The new address is

Figure 4. Write and Read to Memory 0, Read and Write to Memory 1

Chip Select

Wait State

BCLK

NCE0

Data Float Wait State

NCE1

NWR

NSOE

NWE0

NWE1

NWE2

NWE3

D (SIAP)

D (MEM)

DMC: Dynamic Memory Controller

The ARM can access external DRAM by means of the DRAM memory controller. The DMC sits on the ASB bus and provides a glueless memory interface to external EDO DRAM using the common address and data buses.

The AT75C310 supports two DRAM memory regions, each with its own RAS signal. Both DRAM regions share the same CAS, OE, WE, address and data signals.

The DRAM controller is programmed as an internal peripheral that has a standard APB bus interface and a set of memory-mapped registers.

The DMC is designed to operate with extended data-out (EDO) DRAM. It supports two 16-MByte address spaces and a programmable 16- or 32-bit data bus. The controller multiplexes the processor address to form DRAM row and column addresses. The row and column addresses can be configured to support various combinations of DRAM memory size, page size and data bus width.

The DMC supports:

• One or two DRAM memory regions

• DRAM memory region size of 2, 4, 8 or 16 megabytes

• DRAM page size of 256, 512, 1024 or 2048 columns

• Up to 15 row- and 11 column-address bits

• Asymmetric row and column addressing

• 16- or 32-bit DRAM data bus

• Automatic page breaking of burst accesses

• Automatic CAS-before-RAS refresh on timer trigger

• Automatic power-up initialization sequence

DMC Operation

The DMC multiplexes the ASB address to DRAM row and column addresses. The column address must be between eight and eleven bits. The row address is the required number of higher-order bits to support all combinations of permitted page- and memory-region sizes and both data bus widths.

The DMC automatically inserts precharge and RAS cycles and supplies an updated row address to the DRAM when a sequential burst access from an ASB bus master crosses a

DRAM page boundary. The necessary number of wait

states is inserted to hold the bus master during the pre-

charge and RAS cycles.

The DMC performs a CAS-before-RAS refresh cycle on

both DRAM memory regions on the rising edge of a trigger

signal from the AT75C310 on-chip timer. If the DMC is per-

forming a DRAM access when the trigger occurs, the

access will finish before the refresh operation is performed.

In the case of a burst access, the refresh is not performed

until the end of the burst.

The DMC is capable of limiting the length of a burst access

if a refresh trigger has been received. If the feature is

enabled, the DMC performs the refresh operation once it

has been pending for 32 accesses in a burst sequence.

The DMC includes the functionality to interface the 32-bit

ASB data bus with a 16-bit DRAM data bus. It automatically

performs two accesses to the DRAM to service a 32-bit

access from the ASB.

Initialization Sequence

The DMC performs eight CAS-before-RAS refresh opera-

tions to both DRAM banks at the end of the AT75C310

reset pulse. The processor is not required to perform any

DRAM initialization operations. However, it is required to

initialize the DMC.

Data Alignment

The DMC only supports accesses to the appropriate data

boundary, i.e., word accesses must be word-aligned and

half-word accesses must be half-word-aligned. Misaligned

accesses will be ignored by the DMC, and the AMBA

decoder will therefore flag an abort to the appropriate ASB

bus master.

The ARM processor does not guarantee the level of the

bottom two address bits for an instruction access in ARM

state or the bottom address bit for an instruction fetch in

Thumb state. Therefore, the DMC will service misaligned

instruction fetches and force alignment, e.g., a 16-bit

instruction fetch from address 0x00000003 is performed as

a 16-bit read of address 0x00000002.

Table 9. DMC Register Map

0x0

0x4

0x8

DRAM Region 0 Configuration Register

DRAM Region 1 Configuration Register

DRAM Common Configuration Register

AT75C310

DMC_MR0 Read/write

DMC_MR1 Read/write

DMC_CR Read/write

AT75C310

DRAM Memory Region Configuration Register

For each of the two DRAM memory regions there is a memory-mapped register. Register Name: DMC_MR0..DMC_MR1 Reset value of DMC_MR0 is 0x40000000; reset value of DMC_MR1 is 0x50000000

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

BA –––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––– SZ PS EMR

• EMR: Enable Memory Region

When low, the memory region is not enabled; any access to this region will generate an abort.

• PS: Page Size

This field should be set to the number of column address lines that are required by the external DRAM. It also indicates the number of columns per page. The controller breaks sequential bursts on page boundaries.

PS Columns No. Column Address LInes

1 1

256 8

512 9

1024 10

2048 11

• SZ: Size

This field indicates the size of the memory region.

SZ Size of Memory Region

00 2 MB

01 4 MB

10 8 MB

1 1 16 MB

• BA: Base Address

This field indicates the base address of the memory region. It should be programmed with the top 11 bits of the required base address. The number of bits used for address decoding is dependent on the SZ field.

SZ BA Bits Used

2 MB BA[31:21]

4 MB BA[31:22]

8 MB BA[31:23]

16 MB BA[31:24]

DRAM Common Configuration Register (DMC_CR)

The Common Configuration Register defines parameters which are common to the two DRAM regions. Register Name: DMC_CR Reset Value is 0x00000000

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––ROR BBR DBW

• DBW: Data Bus Width

When high, the DRAM data bus is 32 bits wide. When low, the DRAM data bus is only 16 bits wide. The DMC splits 32bit transfers into two 16-bit transfers which are transparent to the ASB.

• BBR: Break Burst for Refresh

When this flag is high, the controller breaks long burst accesses every 32 CAS cycles if a refresh cycle is pending in order to allow the refresh cycle to be performed. This prevents excessively long bursts from delaying refresh cycles.

• ROR: RAS-only Refresh

When high, the CAS signal is held inactive (high) during normal DRAM accesses, thereby generating a RAS-only Refresh cycle. This feature allows software to generate the row address and initiate the refresh cycle. When low, memory operations behave as normal and CAS is not inhibited.

DRAM Interface

Table 10. DRAM Interface

FPDRAM Description Type Notes

NRAS[1:0]

NCAS[3:0]

NWE

NOE

A[14:0]

D[31:0]

Row Address Strobe O

Column Address

Strobe

Write Enable O

Output Enable O

Address Bus O

Data Bus I/O

One strobe per DRAM region. Common to four bytes in each region

One strobe per byte. Common to both DRAM regions. Only NCAS[1:0] used when Data Bus Width is 16

Common to both regions

Multiplexed row and column addresses

D[15:0] used when Data Bus Width is 16

AT75C310

Dynamic Memory Accesses

Figure 5 and Figure 6 describe the different bus operations that can be performed by DMC.

Write Access Followed by Burst Read Access

Figure 5 shows a write to DRAM0 followed by a burst of two reads from the same device.

The write access takes two clock cycles. During the first cycle, the row address is output and the RAS strobe is asserted. In the next cycle, the column address is output and the CAS strobes are asserted. The read is a half-word (16-bit) access to an odd half-word address so only CAS2 and CAS3 are active.

Figure 5. Write to DRAM0 Waveform

BCLK

AT75C310

The read access is not sequential to the write access

(regardless of the addresses) and the RAS strobe is there-

fore raised for a precharge cycle between the accesses.

The read accesses take two clock cycles to read the first

word of data and one additional clock cycle for the second

word. The row address and RAS are asserted in the same

manner as for the read access. The column address and

CAS strobes are asserted earlier for a read access than for

a write access in order to provide time for the data to read

the processor core. The read accesses shown are word

(32-bit) accesses and all four CAS strobes are therefore

active.

The DMC asserts BWAIT to the ARM during the row

address and precharge cycles.

RAS0

RAS1

CAS0

CAS1

CAS2

CAS3

NDOE

NDWE

D (SIAP)

D (MEM)

Read and Write Accesses Followed by CAS before RAS Refresh

Figure 6 shows a read access followed by a write. As the accesses are to different devices, there is no need for a precharge cycle.

Figure 6. Read Access Followed by a Write

BCLK

RAS0

RAS1

CAS0

The read is a byte access (one CAS strobe is active) and

the write is a half-word access (two CAS strobes are

active).

The CAS before RAS refresh cycle refreshes all DRAM

devices controlled by the DMC. All RAS and CAS strobes

are therefore active.

CAS1

CAS2

CAS3

NDOE

NDWE

D (SIAP)

D (MEM)

AT75C310

AIC: Advanced Interrupt Controller

The AT75C310 has an eight-level priority, individually maskable interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts.

The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines IRQ0 and FIQ.

Figure 7. Interrupt Controller Block Diagram

AT75C310

The eight-level priority encoder allows the customer to

define the priority between the different NIRQ interrupt

sources.

Internal sources are programmed to be level-sensitive or

edge-triggered. External sources can be programmed to be

positive- or negative-edge triggered or high- or low-level

sensitive.

The interrupt sources are listed in Table 11 and the AIC

programmable registers in Table 12.

FIQ Source

Advanced Peripheral

Bus (APB)

Internal Interrupt Sources

External Interrupt Sources

Note: After a hardware reset, the AIC pins are controlled by the PIO controller. They must be configured to be controlled by the periph-

eral before being used.

Memorization

Control

Logic

Memorization

Prioritization

Controller

NFIQ

Manager

NIRQ

Manager

NFIQ

ARM7TDMI

Core

NIRQ

Table 11. AIC Interrupt Sources

Interrupt Source Interrupt Name Interrupt Description

0 FIQ/LOWP

1 WDIRQ

2SWIRQ

3UAIRQ

4TC0IRQ

5TC1IRQ

6TC2IRQ

7PIOAIRQ

8 LCDIRQ

9 SPIIRQ

10 IRQ0

11 –

12 OAKIRQ

13 OAKBIRQ

14 UBIRQ

15 PIOBIRQ

16 –

17 –

18 –

19 –

20 –

21 –

22 –

23 –

24 –

25 –

26 –

27 –

28 –

29 –

30 –

31 –

Fast interrupt (external), low-power

Watchdog

Software (Generated by AIC)

USART A

Timer/Counter0

Timer/Counter1

Timer/Counter2

PIO A

LCD Controller

SPI

External 0

Reserved

OAK A Semaphore

OAK B Semaphore

USART B

PIO B

Reserved

AT75C310

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