Rainbow Electronics AT75C220 User Manual

Features

• ARM7TDMI

• One 16-bit Fixed-point OakDSPCore

• Dual Ethernet 10/100 Mbps MAC Interface with Voice Priority

• Multi-layer AMBA

• 256 x 32-bit Boot ROM

• 88K bytes of Integrated Fast RAM

• Flexible External Bus Interface with Programmable Chip Selects

• Codec Interface

• Multi-level Priority, Individually-maskable, Vectored Interrupt Controller

• Three 16-bit Timer/Counters

• Additional Watchdog Timer

• Two USARTs with FIFO and Modem Control Lines

• Industry-standard Serial Peripheral Interface (SPI)

• Up to 24 General-purpose I/O Pins

• On-chip SDRAM Controller for Embedded ARM7TDMI and OakDSPCore

• JTAG Debug Interface

• Software Development Tools Available for ARM7TDMI and OakDSPCore

• Supported by a Wide Range of Ready-to-use Application Software,

including Multi-tasking Operating System, Networking and Voice-processing Functions

• Available in a 208-lead PQFP Package

™

ARM® Thumb™ Processor Core

™

Architecture

Smart Internet Appliance Processor (SIAP™)

AT75C220 –

Description

The AT75C220, Atmel’s latest device in the family of smart internet appliance processors (SIAP), is a high-performance processor designed for professional internet appliance applications such as the Ethernet IP phone. The AT75C220 is built around an ARM7TDMI microcontroller core running at 40 MIPS with an OakDSPCore co-processor running at 60 MIPS and a dual Ethernet 10/100 Mbps MAC interface.

In a typical standalone IP phone, the DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.) while the dual-port Ethernet 10/100 Mbps MAC interface establishes the connection to the Ethernet physical layer (PHY) that links the network and the PC. In such an application, the power of the ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control tasks.

Atmel provides the AT75C220 with three levels of software modules:

• a special port of the Linux kernel as the proposed operating system

• a comprehensive set of tunable DSP algorithms for voice processing, tailored to be run by the DSP subsystem

• a broad range of application-level software modules such as H323 telephony or POP-3/SMTP E-mail services

CPU Peripherals

Rev. 1396A–05/01

AT75C220 Pin Configuration

Figure 1. AT75C220 Pinout in 208-lead PQFP Package

VDD3V3

B0256

GND

DBW32

VDD3V3

PB9

PB8/NCE2

PB7/NCE1

PB6/NWDOVF

PB5/NRIA

PB4

PB3/NCTSA

PB2/TIOB1

PB1/TIOA1

PB0/TCLK1

GND

TXDB

RXDB

NDCDA

NDSRA

NDTRA

NCTSA

NRTSA

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

GND SCLKA VDDV3

FSA STXA SRXA

NTRST

MA_COL

MA_CRS MA_TXER MA_TXD0 MA_TXD1 MA_TXD2 MA_TXD3 MA_TXEN

XVDDV3

MA_TXCLK

GND MA_RXD0 MA_RXD1 MA_RXD2 MA_RXD3 MA_RXER

MA_RXCLK

GND

VDD2V5

MA_RXDV

MA_MDC

MA_MDIO

MA_LINK

MB_COL MB_CRS

GND

VDD2V5

VDD3V3 MB_TXER MB_TXD0 MB_TXD1 MB_TXD2

GND MB_TXD3 MB_TXEN

MB_TXCLK

MB_RXD0 MB_RXD1 MB_RXD2 MB_RXD3 MB_RXER

MB_RXCLK

MB_RXDV

MB_MDC

VDDV3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

186

TXDA

185

RXDA

184

GND

183

PA0/OAKAIN0

PA1/OAKAIN1

PA2/OAKAOUT0

PA3/OAKAOUT1

182

181

180

179

PA4

PA5NCVDD3V3

178

177

176

175

PA6

174

PA7

PA8/TCLK0

173

172

PA9/TIOA0

PA10/TIOB0

PA11/SCKA

171

170

169

VDD3V3

GND

168

167

PA12/NPCS1

GND

VDD2V5

PA19/ACLK

166

165

164

163

TCK

162

TMS

161

100

TDI

160

101

TDO

159

102

VDD3V3

GND

158

157

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

103

104

VDD3V3 NC VDD2V5 GND TST IRQ0 FIQ RESET GND VDD3V3 NPCSS SPCK MOSI MISO NWAIT VDD2V5 GND NSOE NWR NWE3 GND VDD3V3 NWE2 NWE1 NWE0 NCE3 VDD3V3 NCE2 NCE1 NCE0 VDD2V5 XTALIN XTALOUT GND PLL_GND XREF240 PLL_VDD2V5 GND VDD2V5 NC GND NC DQM1 DQM0 WE NC CAS RAS CS1 CS0 DCLK GND

A0A1A2A3A4A5A6A7A8

GND

MB_LINK

MB_MDIO

AT75C220

A10

A11

A12

A13

A14

A15

A16

A17

GND

A18

VDD3V3

A19

A20

A21

D0D1D2

GND

D5D6D7D8D9

VDD3V3

D10

D11

D12

D13

D14

GND

VDD2V5

D15

GND

VDD3V3

NGNT

NREQ

VDD3V3

AT75C220

Pin Description

Table 1. AT75C220 Pin Description List

Block Pin Name Function Type

Common Bus A[21:0] Address Bus Output

D[15:0] Data Bus Input/Output

NREQ Bus Request Input

NGNT Bus Grant Output

Synchronous Dynamic Memory Controller

Static Memory Controller NCE0, NCE3 Chip Selects Output

I/O Port A PA[12:0] General-purpose I/O lines. Multiplexed with

I/O Port B PB[9:0] General-purpose I/O lines. Multiplexed with

DSP Subsystem OAKAIN[1:0] OakDSPCore User Input Input

DCLK SDRAM Clock Output

DQM[1:0] SDRAM Byte Masks Output

CS0 SDRAM Chip Select 0 Output

CS1 SDRAM Chip Select 1 Output

RAS Row Address Strobes Output

CAS Column Address Strobes Output

WE SDRAM Write Enable Output

NWE[1:0] Byte Select/Write Enable Output

NSOE Output Enable Output

NWR Memory Block Write Enable Output

NWAIT Enable Wait States Input

Input/Output

peripheral I/Os.

PA[19] General-purpose I/O line. Multiplexed with

peripheral I/Os.

Input/Output

OAKAOUT[1:0] OakDSPCore User Output Output

Timer/Counter 0 TCLK0 Timer 0 External Clock Input

TIOA0 Timer 0 Signal A Input/Output

TIOB0 Timer 0 Signal B Input/Output

Timer/Counter 1 TCLK1 Timer 1 External Clock Input

TIOA1 Timer 1 Signal A Input/Output

TIOB1 Timer 1 Signal B Input/Output

Watchdog NWDOVF Watchdog Overflow Output

Table 1. AT75C220 Pin Description List (Continued)

Block Pin Name Function Type

Serial Peripheral Interface MISO Master In/Slave Out Input/Output

MOSI Master Out/Slave In Input/Output

SPCK Serial Clock Input/Output

NPCSS Chip Select/Slave Select Input/Output

NPCS1 Optional SPI Chip Select 1 Output

USART A RXDA Receive Data Input

TXDA Transmit Data Output

NRTSA Ready to Send Output

NCTSA Clear to Send Input

NDTRA Data Terminal Ready Output

NDSRA/BOOTN Data Set Ready Input

NDCDA Data Carrier Detect Input

USART B RXDB Receive Data Input

TXDB Transmit Data Output

JTAG Interface NTRST Test Reset Input

TCK Test Clock Input

TMS Test Mode Select Input

TDI Test Data Input Input

TDO Test Data Output Output

Codec Interface SCLKA Serial Clock Input/Output

FSA Frame Pulse Input/Output

STXA Transmit Data to Codec Input

SRXA Receive Data to Codec Output

MAC A Interface MA_COL MAC A Collision Detect Input

MA_CRS MAC A Carrier Sense Input

MA_TXER MAC A Transmit Error Output

MA_TXD[3:0] MAC A Transmit Data Bus Output

MA_TXEN MAC A Transmit Enable Output

MA_TXCLK MAC A Transmit Clock Input

MA_RXD[3:0] MAC A Receive Data Bus Input

MA_RXER MAC A Receive Error Input

MA_RXCLK MAC A Receive Clock Input

MA_RXDV MAC A Receive Data Valid Output

MA_MDC MAC A Management Data Clock Output

MA_MDIO MAC A Management Data Bus Input/Output

MA_LINK MAC A Link Interrupt Input

AT75C220

Table 1. AT75C220 Pin Description List (Continued)

Block Pin Name Function Type

MAC B Interface MB_COL MAC B Collision Detect Input

MB_CRS MAC B Carrier Sense Input

MB_TXER MAC B Transmit Error Output

MB_TXD[3:0] MAC B Transmit Data Bus Output

MB_TXEN MAC B Transmit Enable Output

MB_TXCLK MAC B Transmit Clock Input

MB_RXD[3:0] MAC B Receive Data Bus Input

MB_RXER MAC B Receive Error Input

MB_RXCLK MAC B Receive Clock Input

MB_RXDV MAC B Receive Data Valid Output

MB_MDC MAC B Management Data Clock Output

MB_MDIO MAC B Management Data Bus Input/Output

MB_LINK MAC B Link Interrupt Input

Miscellaneous RESET Power on Reset Input

FIQ/LOWP Fast Interrupt/Low Power Input

IRQ0 External Interrupt Requests Input

XREF240 External 240 MHz PLL Reference Input

XTALIN External Crystal Input Input

XTALOUT External Crystal Ouptut Output

TST Test Mode Input

B0256 Package Size Option (1 = 256 pins) Input

DBW32 External Data Bus Width for CS0 (1 = 32 bits) Input

Figure 2. AT75C220 Block Diagram

Dual Ethernet 10/100 Mbps MAC Interface

OakDSPCore

DSP Subsystem

ASB

Reset

Clocks

JTAG

Embedded

ICE

ARM7TDMI Core

Boot ROM

IRQ

Controller

PIO A

PIO B

Watchdog

Timer

SDRAM

Controller

External Bus

Interface

SRAM

Controller

Peripheral Data

Controller

AMBA Bridge

SPI

USART A

USART B

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

APB

AT75C220

Figure 3. DSP Subsystem Block Diagram

Oak Program Bus Oak Data Bus

AT75C220

2K x 16 X-RAM

Codec Interface

2K x 16 Y-RAM

24K x 16

Program RAM

OakDSPCore

Emulation

Bus Interface Unit

DSP Subsystem

ASB

Figure 4. Application Example – Standalone Ethernet Telephone

Network

Speaker

Microphone

Handset

Ethernet

10/100 Mbps PHY

Ethernet

10/100 Mbps PHY

Speaker

Phone

Interface

Analog Front End

Voice

Codec

Dual-port

Ethernet

10/100 Mbps

MAC

Interface

Voice

Processing

DSP Subsystem

On-chip

Module

Keyboard Screen

Protocol

ARM7TDMI Core

VolP

Stack

16K x 16 General-

purpose RAM

256 x 16

Dual-port

Mailbox

SDRAM

Controller

External Bus

Interface

SRAM

Controller

SDRAM

Flash

AT75C220

Architectural Overview

The AT75C220 integrates an embedded ARM7TDMI processor. External SDRAM and SRAM/Flash interfaces are provided so that processor code and data may be stored off-chip.

The AT75C220 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB).

The ASB is designed for maximum performance. It interfaces the processor with the on-chip DSP subsystem and the external memories and devices by the means of the external bus interface (EBI).

The APB is designed for access to on-chip peripherals and is optimized for low power consumption. The AMBA bridge provides an interface between the ASB and APB.

The AT75C220 uses a multi-layer AMBA bus:

• It integrates two independent AMBA ASB buses. The two buses are connected by a bridge that is not visible to the other devices on the bus.

• The primary bus (ARM bus) is the main processor bus to which most peripherals are connected.

• The secondary bus (MAC bus) is used exclusively for Ethernet traffic.

The ARM7TDMI, USART DMA and ASB-ASB bridge devices are masters on the ARM ASB bus, the MAC DMA and ASB-ASB Bridge are masters on the MAC ASB bus and the Flash/SRAM and SDRAM interfaces are ASB slaves. For more details on bus arbitration, see “Arbitration Using Multi-layer AMBA” on page 31.

All the peripherals are accessed by means of the APB bus. An on-chip peripheral data controller (PDC) transfers data

between the on-chip USARTs and the memories without processor intervention. Most importantly, the PDC removes the processor input-handling overhead and significantly reduces the number of clocks required for data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and power consumption reduced.

The AT75C220 peripherals are designed to be programmed with a minimum number of instructions. Each

peripheral has 16K bytes of address space allocated in the upper part of the address space. The peripheral register set is composed of control, mode, data, status and interrupt registers.

To maximize the efficiency of bit manipulation, frequentlywritten registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bit and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit-manipulation instructions and without having to store-disable-restore the interrupt state.

All of the external signals of the on-chip peripherals are under the control of the parallel I/O controllers. The PIO controllers can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO controllers in order to define which peripherals are connected with offchip logic. The ARM7TDMI processor operates in little-endian mode in the AT75C220. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet, literature number 0673. The memory map and the on-chip peripherals are described in this datasheet.

Peripheral Data Controller

The AT75C220 has a four-channel peripheral data controller (PDC) dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART.

The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-oftransfer interrupt is generated by the corresponding USART. For more details on PDC operation and programming, see the section describing the USART on page 74 .

AT75C220

Memory Map

AT75C220

The memory map is divided into regions of 256 megabytes. The top memory region (0xF000_0000) is reserved and subdivided for internal memory blocks or peripherals within the AT75C220. The device can define up to six other active external memory regions by means of the static memory controller and SDRAM memory controller. See Table 2.

The memory map is divided between the two ASB buses. All regions except the 16 megabytes between 0xFB00_0000 and 0xFBFF_FFFF are located on the ARM ASB bus. Accesses to locations between 0xFB00_0000 and 0xFBFF_FFFF are routed to the MAC ASB bus.

The memory map assumes default values on reset. External memory regions can be reprogrammed to other base

addresses. For details, see “SMC: Static Memory Controller” on page 16 and “SDMC: SDRAM Controller” on page

24. Note that the internal memory regions have fixed locations that cannot be reprogrammed.

There are no hardware locks to prevent incorrect programming of the regions. Programming two or more regions to have the same base address results in undefined behavior.

The ARM reset vector with address 0x00000000 is mapped to internal ROM or external memory depending on the signal pin NDSRA/BOOTN. After booting, the ROM region can be disabled and some external memory such as SDRAM or Flash can be mapped to the bottom of the memory map by programming SMC_CS0 or DMC_MR0.

Table 2. AT75C220 Memory Map

Default Base Address Region Type Normal Mode Boot Mode

0xFF000000 Internal APB Bridge

0xFE000000 Internal Reserved

0xFD000000 Internal Oak A Program RAM

(24K x 16 bits)

0xFC000000 Frame Buffer (16K x 16 bits)

0xFB000000 Internal Reserved (MAC ASB Bus)

0xFA000000 Internal Oak A DPMB (256 x 16 bits)

0xF9000000 Internal Boot ROM (1 KB)

0x50000000 External SDMC_CS1

0x40000000 External SDMC_CS0

0x30000000 External SMC_CS3

0x20000000 External SMC_CS2

0x10000000 External SMC_CS1

0x00000000 External/Internal SMC_CS0 Boot ROM

0x000003FF 0x00000000

Peripheral Memory Map

The register maps for each peripheral are described in the corresponding section of this datasheet. The peripheral memory map has 16K bytes reserved for each peripheral.

Table 3. AT75C220 Peripheral Memory Map

Base Address (Normal Mode) Peripheral Description

0xFF000000 MODE AT75C220 Mode Controller

0xFF004000 SMC Static Memory Controller

0xFF008000 SDMC SDRAM Controller

0xFF00C000 PIOA Programmable I/O

0xFF010000 PIO B Keypad PIO

0xFF014000 TC Timer/Counter Channels

0xFF018000 USARTA USART

0xFF01C000 USARTB USART

0xFF020000 SPI Serial Peripheral Interface

0xFF024000 Reserved

0xFF028000 WDT Watchdog Timer

0xFF030000 AIC Interrupt Controller

0xFF034000 MACA MAC Ethernet

0xFF038000 MACB MAC Ethernet

0xFFFFF000 AIC (alias) Interrupt Controller

Initialization

Reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT75C220 must be held at valid logic levels.

There are three ways in which the AT75C220 can enter reset:

1. Hardware reset. Caused by asserting the RESET

pin, e.g., at power-up.

2. Watchdog timer reset. The WD timer can be pro-

grammed so that if timed out, a pulse is generated that forces a chip reset.

3. Software reset. There are two software resets which

are asserted by writing to bits [11:10] of the SIAP mode register. SIAP_MD[11] forces a software reset with RM set low and SIAP_MD[10] forces a reset with RM set high.

Reset Pin

The reset pin should be asserted for a minimum of 10 clock cycles. However, if external DRAM is fitted, then reset should be applied for the time interval specified by the SDRAM datasheet, typically 200 µs. The OakDSPCores are only released from reset by the ARM program control.

When reset is released, the pin NDSRA/BOOTN is sampled to determine if the ARM should boot from internal ROM or from external memory connected to NCS0. The details of this boot operation are described in the section “Boot Mode” on page 11.

Processor Synchronization

The ARM and the OakDSPCore processors have their own PLLs and at power-on each processor has its own indeterminate lock period. To guarantee proper synchronization of inter-processor communication through the mailboxes, a specific reset sequence should be followed.

Once the ARM core is out of reset, it should set and clear the reset line of the OakDSPCore three times. This guarantees message synchronization between the ARM and the OakDSPCore.

AT75C220

Clocking

AT75C220

The AT75C220 mode register controls clock generation.

Oscillator and PLL

The AT75C220 uses an external 16 MHz crystal (XCLK) and an on-chip PLL to generate the internal clocks. The PLL generates a 240 MHz clock that is divided down to produce the ARM clock and Oak clock.

Oak System Clock

The Oak subsystem runs at 60MHz.

Other Clocks

The codec interfaces run from 800 kHz that is seperate from the Oak clock.

The USARTs and timers operate from divided ARM clocks.

ARM System Clock

The ARM subsystem runs at 40 MHz.

Table 4. Clock Source and Frequency

Source Frequency Comment

Crystal 16 MHz External crystal

PLL Output 240 MHz Crystal multiplied by 15

ARM Clock 40 MHz PLL divided by 6

Oak Clock 60 MHz PLL divided by 4

Figure 5. AT75C220 Clocking

16 MHz

XTAL

XTALIN

. .

40 MHz

ARM Core Clock

10 pF

1 MΩ

XTALOUT

Oscillator

16 MHz

PLL

XREF 240F 100 Ω 10 nF

Boot Mode

The AT75C220 has an integrated 1-Kbyte ROM to support the boot software. When the device is released from reset, the ARM starts fetching from address 0x00000000. If the RM flag in the SIAP-E mode register (SIAP_MD on page

12) is low, the internal boot ROM is mapped to the bottom 1K byte of the memory map. If RM is high, the bottom 16M bytes of memory address will default to external memory region 0.

If NDSRA/BOOTN is asserted on reset, the internal boot ROM program is executed. The boot program reads data from USART A and writes it to the Oak Program RAM (in the ARM memory map whereas the Oak is in reset). The downloaded software can then configure the various con-

240 MHz

. .

60 MHz

Phase

Generator

40 MHz

DSP Subsystem Clock

trol registers in the AT75C220 and its peripherals so as to perform external memory accesses. This allows the Flash to be written.

The boot ROM code:

• sets CTS active

• waits for approximately three seconds for the start of a

Flash download sequence from the USART.

If the special header is not received, the AT75C220 boots normally, i.e., from external memory at 0x00000000.

If the special header is received, the boot ROM enters the code download process.

AT75C220 Mode Controller

The ARM configures the mode of the AT75C220 by means of the SIAP-E mode controller.

The SIAP-E mode controller is a memory-mapped peripheral that sits on the APB bus.

Register Map

Base Address: 0xFF000000

Table 5. AT75C220 Register Map

0x0 SIAP_MD SIAP-E Mode Register Read/write 0x00B0340

0x4 SIAP_ID SIAP-E ID Register Read-only 0x0000220

0x8 SIAP_RST SIAP-E Reset Status

0xC SIAP_CLKF SIAP-E Clock Status

Note: 1. If the PKG flag is set, the reset value is 0x00010220 since the AT75C220 is bonded in large bond-out mode.

Read/write 0x0000001

Read-only 0x0000001

SIAP-E Mode Register

31 30 29 28 27 26 25 24

–– JCIDBG OUTDIV INDIV

(1)

23 22 21 20 19 18 17 16

ICP IPOLTST

15 14 13 12 11 10 9 8

– CRA – DBA SW2 SW1 LPCS

76543210

SA LP ––IA – RA RM

• RM: Remap

On reset being released this flag is set to the value of NDSRA/BOOTN. When RM is active low the Boot ROM is mapped to location 0x00000000. Subsequently, this flag can be set high by software so that the ROM mapping is disabled and another memory controller region (e.g. FLASH) is mapped to location 0x00000000.

• RA: OAKA Reset

This flag resets to active low so that the OAKA is held in reset. The OAKA is be released from reset by asserting this flag high.

• IA: Inhibit OAKA Clock

This flag resets to active low so that the OAKA clock is enabled. The OAKA clock is be inhibited by asserting this flag high.

• LP: Low Power Mode

On reset this field is high. When written high the PLL is disabled and the ARM and OAK cores and logic are clocked at the low power clock frequency. Note, in this mode the ARM and OAK are clocked at the same frequency determined by the LPCS field. When LP is written low the PLL is enabled and once it has locked the clock is switched over to the normal operating frequency.

AT75C220

• SA: Slow ARM Mode

On reset this field is low. In normal operating mode, if bit SA is set. The ARM clock is 34Mhz (i.e. the PLL value is divided by 7). IF SA is not set the ARM clock is 40MHz (i..e the PLL divisor is 6). SA can be switched during low power mode but should not be changed when LP is low.

• LPCS: Low Power Clock Select

This field is used to select a slower clock frequency for the ARM system clock as per the table below.

Oscillator Clock

LPCS

00 1 8 MHz

0 1 16 1 MHz

1 0 64 250 kHz

1 1 512 32 kHz

Divisor

ARM and Oak System Clock

• SW1: Software Reset 1

Writing a 1 to this bit forces the SIAP into reset with RM set to 0.

• SW2: Software Reset 2

Writing a 1 to this bit forces the SIAP into reset with RM set to 1.

• DBA: OAKA Debug Mode

This flag resets low. To enter OAKA debug mode (specific pins are multiplexed out on functional pins), this bit should be set.

• CRA: CODECA Reset

This flag resets to active low so that the CODECA is held in reset. The CODECA is released from reset by asserting this flag high.

• IPOLTST: PLL Bias Adjustment

This can be used to tune the PLL if the bias current is not correct after manufacture.

Bias Factor 15 IPOLTST–()4⁄=

• ICP: PLL Charge Pump Current

This can be used to tune the PLL if it does not function with the default current of 2.5 µA.

IICP

( 1 )+ 2.5µA×=

• INDIV

Input frequency range of PLL.

INDIV PLL Input Frequency Range

0 0 5 kHz to 40 MHz

0 1 40 MHz to 80 MHz

1 0 80 MHz to 160 MHz

1 1 160 MHz to 250 MHz

• OUTDIV

Output frequency range of PLL.

OUTDIV PLL Output Frequency Range

0 0 40 MHz to 250 MHz

0 1 20 MHz to 40 MHz

1 0 10 MHz to 20 MHz

1 1 5 MHz to 10 MHz

• JCIDBG

This field controls the mode of the JCI. The Oak subsystem has its own JTAG port. This port is used to communicate serially with the Oak OCEM module.

SIAP-E ID Register

0x0001220 in large bond-out mode

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––––PKG

15 14 13 12 11 10 9 8

76543210

IDENT

• IDENT: Identifier

This field indicates the device identifier 0x0220.

• PKG: Package

This bit reflects the state of the data bus width signal DBW and indicates the SIAP package size.

AT75C220

SIAP-E Reset Status Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––RST RST RST

• RST[2:0]: Reset

These bits indicate the cause of the last reset.

RST Reset Event

0 0 1 Hardware

0 1 0 Watchdog Timer

100 Software

SIAP-E Clock Status Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––CLK

• CLK: Clock Status

This bit indicates which clock is in use by the system. When set, the low power clock is in use. When cleared, the PLL is locked and the high power clock is in use. This can be used by software to determine when the power mode has changed after the LP bit has been written.

External Bus Interface

The external bus interface (EBI) generates the signals which control access to external memories or peripheral devices.

SMC: Static Memory Controller

The static memory controller (SMC) is used by the AT75C220 to access external static memory devices. Static memory devices include external Flash, SRAM or peripherals.

The SMC provides a glueless memory interface to external memory using the common address and data bus and some dedicated control signals. The SMC is highly programmable and has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. The SMC supports different access protocols allowing single clockcycle accesses. The SMC is programmed as an internal peripheral that has a standard APB bus interface and a set of memory-mapped registers. The SMC shares the external address and data buses with the DMC and any external bus master.

Table 6. Signal Interface

FPDRAM Description Type Notes

External Memory Mapping

The memory map associates the internal 32-bit address space with the external 24-bit address bus. The memory map is defined by programming the base address and page size of the external memories. Note that A[2:23] is only significant for 32-bit memory and A[1:23] for 16-bit memory.

If the physical memory-mapped device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The SMC correctly handles any valid access to the memory device within the page.

In the event of an access request to an address outside any programmed page, an abort signal is generated by the internal decoder. Two types of abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are 0x0000000C and 0x00000010. It is up to the system programmer to program the exception handling routine used in case of an abort.

If the AT75C220 is in internal boot mode, any chip select configured with a base address of zero will be disabled as the internal ROM is mapped to address zero.

A[23:0] Address bus Output

D[31:0] Data bus I/O

NCE[3:0] Active low chip enables Output

NWE[3:0] Active low byte select/write strobe signals Output

NWR Active low write strobe signals Output

NSOE Active low read enable signal Output

NWAIT Active low wait signal Input

Data Bus Width

A data bus width of 32 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the Chip Select Register (SMC_CSR) of the corresponding chip select.

The AT75C220 always boots up with a data bus width of 16 bits set in SMC_CSR0.

Byte-write or Byte-select Mode

Each chip select with a 32-/16-bit data bus operates with one or two different types of write mode:

1. Byte-write mode supports four (32-bit bus) or two

2. Byte-select mode selects the appropriate byte(s)

This option is controlled by the BAT field in SMC_CSR for the corresponding chip select.

Byte-write access can be used to connect four 8-bit devices as a 32-bit memory page or two 8-bit devices as a 16-bit memory page.

D[15:0] used when data bus width is 16

NCE[3] can be configured for LCD interface mode

(16-bit bus) byte writes and a single read signal.

using four (32-bit bus) or two (16-bit bus) byte-select lines and separate read and write signals.

AT75C220

For a 32-bit bus:

• The signal NWE0 is used as the write enable signal for byte 0.

• The signal NWE1 is used as the write enable signal for byte 1.

• The signal NWE2 is used as the write enable signal for byte 2.

• The signal NWE3 is used as the write enable signal for byte 3.

• The signal NSOE enables memory reads to all memory blocks.

For a 16-bit bus:

• The signal NWE0 is used as the write enable signal for byte 0.

• The signal NWE1 is used as the write enable signal for byte 1.

• The signal NSOE enables memory reads to all memory blocks.

Byte-select mode can be used to connect one 32-bit device or two 16-bit devices in a 32-bit memory page or one 16-bit device in a 16-bit memory page.

For a 32-bit bus:

• The signal NWE0 is used to select byte 0 for read and write operations.

• The signal NWE1 is used to select byte 1 for read and write operations.

• The signal NWE2 is used to select byte 2 for read and write operations.

• The signal NWE3 is used to select byte 3 for read and write operations.

• The signal NWR is used as the write enable signal for the memory block.

• The signal NSOE enables memory reads to the memory block.

For a 16-bit bus:

• The signal NWE0 is used to select byte 0 for read and write operations.

• The signal NWE1 is used to select byte 1 for read and write operations.

• The signal NWR is used as the write enable signal for the memory block.

• The signal NSOE enables memory reads to the memory block.

During boot, the number of external devices (number of active chip selects) and their configurations must be programmed as required. The chip select addresses that are programmed take effect immediately. Wait states also take effect immediately when they are programmed to optimize boot program execution.

Read Protocols

The SMC provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the NSOE (read cycle) waveform.

The protocol is selected by the DRP field in the Memory Control Register (SMC_MCR) and is valid for all memory devices. Standard read protocol is the default protocol after reset.

• Standard Read Protocol

Standard read protocol implements a read cycle in which NSOE and the write strobes are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access, as well as the output of address and NCE before the read cycle begins.

During a standard read protocol external memory access, NCE is set low and ADDR is valid at the beginning of the access, whereas NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The write strobes are the same in both protocols. The write strobes always go low in the second half of the master clock cycle.

• Early Read Protocol

Early read protocol provides more time for a read access from the memory by asserting NSOE at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NSOE remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contention on the external bus.

In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e., data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Early read wait states affect the external bus only. They do not affect internal bus timing.

Write Protocol

During a write cycle, the data becomes valid after the falling edge of the write strobe signal and remains valid after the rising edge of the write strobe. The external write strobe waveform on the appropriate write strobe pin is used to control the output data timing to guarantee this operation.

Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. In early read protocol, the data can remain

valid longer than in standard read protocol due to the additional wait cycle that follows a write access.

Wait States

The SMC can automatically insert wait states. The different types of wait states are:

• standard wait states

• data float wait states

• external wait states

• chip select change wait states

• early read wait states (see “Read Protocols” on page 17

for details)

• standard wait states

Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same register. The correspondence between the number of standard wait states programmed and the number of cycles during which the write strobe pulse is held low is found in Table 7. For each additional wait state programmed, an additional cycle is added.

Table 7. Correspondence Wait States/Number of Cycles

Wait States Cycles

01/2

SMC_CSR register for the corresponding chip select. The value (0 - 7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go high impedance after the memory is disabled.

The SMC keeps track of the programmed external data float time even when it makes internal accesses to ensure that the external memory system is not accessed while it is still busy.

Internal memory accesses and consecutive accesses to the same external memory do not have added data float wait states.

When data float wait states are being used, the SMC prevents the DMC or external master from accessing the external data bus.

• External Wait

The NWAIT input can be used to add wait states at any time NWAIT is active low and is detected on the rising edge of the clock. If NWAIT is low at the rising edge of the clock, the SMC adds a wait state and does not change the output signals.

• Chip Select Change Wait States

A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait states have already been inserted (e.g., data float wait), then none are added.

• Data Float Wait State

Some memory devices are slow to release the external bus. For such devices it is necessary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory.

The Data Float Output Time (TDF) for each external memory device is programmed in the TDF field of the

LCD Interface Mode

NCE3 can be configured for use with an external LCD controller by setting the LCD bit in the SMC_CSR3 register. Additionally, WSE must be set and NWS programmed with a value of one or more.

In LCD mode, NCE3 is shortened by one-half clock cycle at the leading and trailing edges, providing positive address setup and hold. For read cycles, the data is latched in the SMC as NCE3 is raised at the end of the access.

AT75C220

SMC Register Map

The SMC is programmed using the registers listed in the Table 8. The memory control register (SMC_MCR) is used to program the number of active chip selects and data read protocol. Four chip select registers (SMC_CSR0 to SMC_CSR3) are used to program the parameters for the

Table 8. SMC Register Map

Offset Register Name Description Access Reset Value

0x00

SMC_CSR0

Chip Select Register

individual external memories. Each SMC_CSR must be programmed with a different base address, even for unused chip selects. The AT75C220 resets such that SMC_CSR0 is configured as having a 16-bit data bus.

Read/write 0x0000203D

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

SMC_CSR1

SMC_CSR2

SMC_CSR3

–

SMC_MCR

Chip Select Register

Reserved

Memory Control Register

Read/write 0x10000000

Read/write 0x20000000

Read/write 0x30000000

––

Read/ write 0

SMC Chip Select Register

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

BA –––LCD

15 14 13 12 11 10 9 8

––CSEN BAT TDF PAGES

76543210

PAGES MWS WSE NWS DBW

• DBW: Data Bus Width

DBW Data Bus Width

00Reserved

0 1 16-bit external bus

1 0 32-bit external bus

11Reserved

• NWS: Number of Wait States

This field is valid only if WSE is set.

Table 9. NWS, WSE Values

NWS WSE Wait States

XX X 0 0

0001 1

0011 2

0101 3

0111 4

1001 5

1011 6

1101 7

1111 8

• WSE: Wait State Enable

• MWS: Multiply Wait States

See Table 9, where

WS NWS 1+()81+×=

• PAGES: Page Size

PAGES Page Size

0 0 1M byte BA[31 - 20]

0 1 4M bytes BA[31 - 22]

1 0 16M bytes BA[31 - 24]

11 Reserved –

• TDF: Data Float Output Time

TDF Cycles after Transfer

00 0 0

00 1 1

01 0 2

01 1 3

10 0 4

10 1 5

11 0 6

11 1 7

Base

Address

• BAT: Byte Access Mode

0 = Byte Write Mode 1 = Byte Select Mode

AT75C220

• CSEN: Chip Select Enable

Active high.

• LCD: LCD Mode Enable

Active high. SMC_CSR3 only.

• BA: Base Address

This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of the base address are ignored by the SMC decoder.

SMC Memory Control Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––DRP ––––

• DRP: Data Read Protocol

0 = Standard Read Mode 1 = Early Read Mode

Switching Waveforms

Figure 6 shows a write to memory 0 followed by a write and a read to memory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 0. SMC_MCR is programmed for early reads from all memories.

The write to memory 0 is a word access and therefore all four NWE strobes are active. As BAT = 0, they are configured as write strobes and have the same timing as NWR. As the access employs a single wait state, the write strobe pulse is one clock cycle long.

There is a chip select change wait state between the memory 0 write and the memory 1 write. The new address is output at the end of the memory 0 access, but the strobes are delayed for one clock cycle.

The write to memory 1 is a half-word access to an odd halfword address and, therefore, NWE2 and NWE3 are active.

Figure 6. Write to Memory 0, Write and Read to Memory 1

Internal Wait State Chip Select Wait State Early Read Wait State

BCLK

As BAT = 1, they are configured as byte select signals and have the same timing as NCE. As the access has no internal wait states, the write strobe pulse is one- half clock cycle long. Data and address are driven until the write strobe rising edge is sensed at the SIAP pin to guarantee positive hold times.

There is an early read wait state between memory 1 write and memory 1 read to provide time for the AT75C220 to disable the output data before the memory is read. If the read was normal mode, i.e., not early, the NSOE strobe would not fall until the rising edge of BCLK and no wait state would be inserted. If the write and early read were to different memories, then the early read wait state is not required as a chip select wait state will be implemented.

The read from memory 1 is a byte access to an address with a byte offset of 2 and therefore only NWE2 is active.

NCE0

NCE1

NWR

NSOE

NWE0

NWE1

NWE2

NWE3

D (SIAP)

D (MEM)

AT75C220

Figure 7 shows a write and a read to memory 0 followed by a read and a write to memory 1. SMC_CSR0 is programmed for zero wait states with BAT = 0 and DFT = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and DFT = 1. SMC_MCR is programmed for normal reads from all memories

The write to memory 0 is a byte access and, therefore, only one NWE strobe is active. As BAT = 0, they are configured as write strobes and have the same timing as NWR.

The memory 0 read immediately follows the write as early reads are not configured and an early read wait state is not required. As early reads are not configured, the read strobe pulse is one-half clock cycle long.

There is a chip select change wait state between the memory 0 write and the memory 1 read. The new address is output at the end of the memory 0 access but the strobes are delayed for one clock cycle.

The write to memory 1 is a half-word access to an odd halfword address and, therefore, NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and have the same timing as NCE.

As DFT = 1 for memory 1, a wait state is implemented between the read and write to provide time for the memory to stop driving the data bus. DFT wait states are only implemented at the end of read accesses.

The read from memory 1 is a byte access to an address with a byte offset of 2 and, therefore, only NWE2 is active.

Figure 7. Write and Read to Memory 0, Read and Write to Memory 1

Chip Select

Wait State

BCLK

NCE0

Data Float Wait State

NCE1

NWR

NSOE

NWE0

NWE1

NWE2

NWE3

D (SIAP)

D (MEM)

SDMC: SDRAM Controller

The AT75C220 integrates an SDRAM controller (SDMC). The ARM accesses external SDRAM by means of the

SDRAM memory controller. The SDMC shares the same address and data pins as the

static memory controller but has separate control signals. The SDMC interface is a memory-mapped APB slave. For very low frequency selection in low power mode, the

SDRAM should be refreshed frequently.

Table 10. External Memory Interface

Signal Name Type Description

DCLK Output SDRAM Clock

A[21:0] Output Memory address (Shared with SMC)

D[15:0] Input Memory data input (Shared with SMC)

DQM[1:0] Output SDRAM byte masks

CS0 Output SDRAM chip select, active low

CS1 Output SDRAM chip select, active high

Main features of the SDMC are:

• External memory mapping

• Up to 4 chip select lines

• 32- or 16-bit data bus

• Byte write or byte select lines

• Two different read protocols

• Programmable wait state generation

• External wait request

• Programmable data float time

• Programmable burst mode

WE Output SDRAM write enable, active low

RAS Output Row Address Select, active low

CAS Output Column Address Select, active low

The signals RAS, CAS, WE, A[21:0], and D[15:0] have functions similar to those of a conventional DRAM.

DCLK is the free-running, normally continuous clock to which all other signals are synchronized; CKE is an enable signal that gates the other control inputs. Note that CKE is not bonded out since it is always active high.

APB Interface

The SDMC interface is a memory-mapped APB slave.

ASB Interface

The SDMC is also an ASB slave and has a reserved memory region in the ASB memory map.

Read and Write Bursts

The SDMC has been modified so read accesses are performed in bursts of four for accesses to 32-bit memory or bursts of eight for 32-bit access to 16-bit memory. Read accesses are performed as shown in Figure 8, Figure 9 and Figure 10. Note that read bursts are terminated if a non-sequential access is detected. However, pipelined commands from the SDRAM may be still be executed but the resultant read data is ignored.

Three separate read accesses are shown in Figure 8, Figure 9 and Figure 10. In Figure 8, the data from all four reads is used, in Figure 9 the data from the last two reads is discarded. Figure 10 shows a single non-sequential access to a new row.

AT75C220

Figure 8. Read with Burst Length of 4 and CAS Latency of 2

BCLK

AT75C220

BTRAN

BWAIT

SDRAM CMD

addr

sdmc_data

NOP PRE NOP ACT NOP READ READ READ READ NOP NOP NO

A0 A2 A3A1

NSEQ SEQ SEQ SEQ NSEQ

BANK ROW COL0 COL1 COL2 COL3

Figure 9. Read with Burst Length of 2 and CAS Latency of 2

D0 D1 D2 D3

BCLK

BTRAN

BWAIT

SDRAM CMD

Addr

sdmc_data

A0 A2 A3A1

NSEQ SEQ SEQ SEQ

NOP PRE NOP ACT NOP READ READ READ READ NOP NOP PRE

BANK ROW COL0 COL1 COL2 COL3

D0 D1 D2 D3

D0 D1 x x

BANK

Figure 10. Read Showing a Single Access for a Non-sequential Read to a New Row

BCLK

BTRAN

hburst_h

BWAIT

SDRAM CMD

Addr

sdmc_data

A0 A1

NSEQ NSEQ

INCR INCR

NOP PRE NOP ACT NOP READ NOP NOP

BANK ROW COL0 COL1

NOP

Writes can burst continuously until any of the following conditions are achieved:

1. The following access is a read.

2. The following access is to a new row.

3. The following access is non-sequential.

When any of these conditions occur, the write burst is broken and SDMC goes inactive.

Table 11. SDRAM Refresh Rates

Clock Speed (MHz) Tick (us) Counter Needed

40 0.25 62.5

81.2512.5

1 10 1.5625

0.025 400 0.0390625

0.0032 3125 0.005

SDRAM Refresh

Table 11 shows the counter values needed for a refresh rate of 15.625 µs in the SDMC. As can be seen, at clock speeds of 1 MHz and below it is unfeasible to maintain data integrity in the SDRAM. Note that in low power modes it is not a requirement to maintain data in the SDRAM.

AT75C220

SDMC Register Map

Base Address: 0xFF008000

Table 12. SDMC Register Map

Offset Register Name Description Access Reset Value

0x0000 SDRAM_MODE Mode Register Read/write 0x00000000

0x0004 SDRAM_TIMER Timer Register Read/write 0x00000000

0x0008 SDRAM_CFG Configuration Register Read/write 0x00000000

0x000C SDRAM_16BIT Selects 16-/32-bit modes Read/write 0x00000001

0x0010 SDRAM_CS0_ADDR Base address for CS0 Read/write 0x00000040

0x0014 SDRAM_CS1_ADDR Base address for CS1 Read/write 0x00000050

SDRAM_MODE Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––––MODE

76543210

MODE ––––––

• MODE

MODE Description

000 Normal mode. Any access to the SDRAM will be decoded normally.

001 The NOP command is issued to the SDRAM when the host accesses the SDRAM memory area, regardless of the

cycle.

010 The all banks precharge command is issued to the SDRAM when the host accesses the SDRAM memory area,

regardless of the cycle.

011 The load mode register command is issued to the SDRAM when the host accesses the SDRAM memory area,

regardless of the cycle. The address offset with respect to the SDRAM memory base address is used to program the mode register. For example, when this mode is activated, an access to the “SDRAM_BASE + offset” generates a load mode register command with the value offset written to the mode register of the SDRAM.

100 A refresh command is issued to the SDRAM. An all banks precharge command must precede.

others Reserved

SDRAM_TIMER Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––– CNT

76543210

CNT

• CNT

This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The length of this refresh burst (number of rows refreshed) can be adjusted at compile time by modifying the value RFSH_LEN. The refresh commands will begin when the timer is loaded for the first time. The value to be loaded depends on the clock frequency used in the SDMC configuration module, the refresh rate of the SDRAM and the refresh burst length where 15.6 microseconds is a typical value for a burst of length one.

SDRAM_CFG Register

31 30 29 28 27 26 25 24

––––– TRAS

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

TRP TRC TWR

76543210

TWR CAS NB NR NC

TRCD TRP

• NC

Sets the number of column bits. Default is eight column bits.

NC Column Bits

00 8

01 9

10 10

11 11

AT75C220

• NR

Sets the number of row bits. Default is 11 row bits.

NR Row Bits

00 11

01 12

10 13

11 Reserved

• NB

Sets the number of banks. Default is two banks.

NB Number of Banks

• CAS

Sets the CAS latency. The SDMC has been modified so that it only supports a CAS latency of two. Writing to this register will have no effect.

• TWR

Sets the value of TWR expressed in number of cycles. Default is two cycles.

• TRC

Sets the value of TRC expressed in number of cycles. Default is eight cycles.

• TRP

Sets the value of TRP expressed in number of cycles. Default is three cycles.

• TRCD

Sets the value of TRCD expressed in number of cycles. Default is three cycles.

• TRAS

Sets the value of TRAS expressed in number of cycles. Default is five cycles.

SDRAM_16bit Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210

–––––––16BIT

• 16BIT

This bit is used to set the width of the external memory. If this field is set, the address is assumed to be 16 bits wide. If not set, the memory bus is assumed to be 32 bits wide.

SDRAM_CS0_ADDR Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––––CS0_ADDR

76543210

CS0_ADDR

• CS0_ADDR

This bit is used to set the eight most significant bits of the address of CS0.

SDRAM_CS1_ADDR Register

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––––CS1_ADDR

76543210

• CS1_ADDR

This bit is used to set the eight most significant bits of the address of CS1.

CS1_ADDR

AT75C220

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