Rainbow Electronics AT73C502 User Manual

Features

• Fulfills IEC 1036, Class 1 Accuracy Requirements

• Fulfills IEC 687, Class 0.5 and Class 0.2 Accuracy, with External Temperature

Compensated Voltage Reference

• Fulfills IEC 1268, Requirements for Reactive Power

• Simultaneous Active, Reactive and Apparent Power and Energy Measurement

• Power Factor, Frequency, Voltage and Current Measurement

• Single- and Poly-phase Operation

• Three Basic Operating Modes: Stand-alone Mode, Microprocessor Mode and Multi-

Channel Mode

• Flexible Interfacing, 8-bit Microprocessor Interface, 8-bit Status Output and Eight

Impulse Outputs

• Calibration of Gain and Phase Error

• Compensation of the Non-linearity of Low Power Measurement

• Adjustable Starting Current and Meter Constant

• Measurement Bandwidth of 1000 Hz

• Tamper-proof Design

• Single +5V Supply

Description

A two chip solution, co ns isting of AT73C500 and AT73C501 (or AT 7 3C50 2) , offer s all main features required for the measurement and calculation of various power and energy quantiti es in static Watt-h our meters. The dev ices operate acc ording to IEC1036, class 1, specification. IEC 687, class 0.5 and 0.2 requirements are fulfilled when used with external temperature compensated voltage reference.

The AT73C501 contains six, high-performance, Sigma-Delta analog-to-digital converters (ADC). The A T73 C500 is an effic ient di gita l si gnal p roc essor (DSP ) that supp orts interfacing both with the AT73C501 and with an external microprocessor. The AT73C500 can also be used with the differential input ADC, AT73C502.

With this chipset, only a minimum of discrete components is required to develop products ranging from si mple domestic Wa tt-hour meters to sop histicated indus trial meters. The chipset can be used in single-phase as well as in poly-phas e systems. The AT73C500 is easy to configure. By changing the mode of the AT73C500, the device can be operated in a stand-alone environment or be used with a separate control processor. It is also possible to configure the circuit to perform the functions of three independent single phase Wh meters.

The chips support calibration of gain and phase error. All calibrations are done in the digital domain and no trimming components are needed. The calibration coefficients are either stored in an EEPROM memory or supplied by an external microprocessor.

(continued)

Chipset Solution for Watt-hour Meters

AT73C500 with AT73C501 or AT73C502

Rev. 1035B–09/99

Figure 1. Block diagram of the AT73C500 chipset in stand-alone configuration

EXTERNAL CONNECTOR

L1 L2 L3

RESET

VREF

BGD

AIN2 AIN4 AIN6

AIN1 AIN3 AIN5

RESET

VDA

VDDA

AT73C501

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA

CONVERTERS

XI XO MODE

VCC

VSA

VSSA

PFAIL

ACK DATA CLKR CLK

AGND

VGND

GND

BRDY

IRQ0 IRQ1

SIN

SCLK

CLK

XRES

CS SK

The AT73C500 is progr amme d to meas ure act ive, rea ctive and apparent phase powers. Phase factors, phase voltages, phase currents and line frequenc y are also measured, simultaneously. Based on the individual p hase powers, total active power is determined.

The power value s are calcul ated over one-line frequency cycle. The negative and positive results are accumulated in different registers, which allows for separate billing of imported and e xported ac tive energ y. Also, the reactive results are sorted depending on whether capacitive or inductive load is applied.

VCC

STROBE RD/WR

DEDICATED DSP

AT73C500

FOR ENERGY

METERING

GND

DGND

AT93C46

EEPROM

128*8 bit

ADDR1 ADDR0

SOUT1 SOUT0

DATA BUS

STATUS BUS

MODE2 MODE1 MODE0

1 1 1 1

-VArh +VArh

-Wh +Wh +Wh

-Wh +VArh

-VArh

Eight pulse outputs are provided. Each billing quantity (+Wh, -Wh, +VArh, -Varh) is supplied with its own meter constant output, as well as a display counter output. In multi-channel mode, AT73C500 performs the fu nctions of three independent s ingle phase Wh me ters and three impulse outputs are available, one for each meter element.

All measurement inform ation is avai lable on an 8-bit mi croprocessor bus. The results are output in s ix packages, 16 bytes each. Mode and s tatus information of the meter is also transferred with each data block.

TAMP STUP L3 L2 L1 FAIL DATRDY INI

Figure 2. Block diagram of the AT73C500 chipset in microprocessor configuration

RESET

L1 L2 L3

VREF

BGD

AIN2 AIN4 AIN6

AIN1 AIN3 AIN5

RESET

VDA

VDDA

VCC

AT73501

SIX SINGLE-ENDED,

INDEPENDENT

SIGMA-DELTA CONVERTERS

XI XO MODE

VSA

VSSA

AT73C500

VGND

GND

PFAIL

ACK DATA CLKR CLK

AGND

BRDY

IRQ0 IRQ1

SCLK

XRES

SIN

VCC

AT73500

DEDICATED DSP

FOR ENERGY

METERING

GND

DGND

STROBE RD/WR ADDR1 ADDR0

SOUT1 SOUT0

DATA BUS

STATUS BUS

MODE2 MODE1 MODE0

AT90Sxx

DATRDY

1 1 1 1

B14 B13 B12

MICROCONTROLLER

MODEM

LCD

EEPROM

Pin Description

AT73C501 Single-ended ADC

AT73C500

Figure 3. PLCC-28 package pin layout

DAT

FSRACKCLKRCLKXIXO

BGD

VCC

VCIN

VSSAVDDAAIN2 AIN4 AIN6 AIN1 AIN3

PFAI

AGN

VREF

Power

Supply

Pins Pin I/O Description

VDDA 13 PWR Analog Supply, Positive, +5V VSSA 12 PWR Analog Supply, Negative, 0V

VDA 21 PWR Analog Supply, Positive, +5V VSA 20 PWR Analog Supply, Negative, 0V

AGND 9 PWR

VREF 11 PWR

Analog Ground Reference Input

Referenc e Voltage Output/Input

VCC 7 PWR Digital Supply, Positive, +5V

VGND 23 PWR Digital Supply, Negative, 0V

Crystal Osc

Signals Pin I/O Description

XI 3 I Crystal Oscillator Input

XO 4 O Crystal Oscillator Output

26272812

18171615141312

RESET

N/C

VGND

AIN5

Analog

Signals Pin I/O Description

AIN1 17 I Current, Channel 1 AIN2 14 I Voltage, Channel 1 AIN3 18 I Current, Channel 2 AIN4 15 I Voltage, Channel 2 AIN5 19 I Current, Channel 3 AIN6 16 I Voltage, Channel 3

VCIN 10 I

Input to Voltage Monitoring Block

Digital Control Signals Pin I/O Description

BGD 5 I

By-pass Control for Reference Voltage

CS 6 I Chip Select Input

PD 22 I

Power Down Control for A/D Modulators

N/C 24 I Connect to VGND

RESET 25 I Reset Input, Active High

Status

Flags Pin I/O Description

PFAIL 8 O

Output of Voltage Monitoring Block

Output Bus

Signals Pin I/O Description

CLK 2 O Master Clock Output CLKR 1 O Serial Bus Clock Output DATA 26 O Serial Data Output

FSR 27 O

Output Sample Frame Signal

ACK 28 O

Data Ready Acknowledge Output

AT73C502 Differential-Ended ADC

BGD N/C

CLKRCLK

N/CN/CN/C

RESETXO

322

133

4344

42 41 40 39 38 37 36 35 34

DATAACK

FSR

VGND

VDA

VSA

SINGLE

AIN5N

AIN5P

AIN3N

1312 14 15 16 17 18 19 20 21 22

VCC

PFAIL

AGND

VCIN

VREF

N/C

VSA

AIN1NAIN6NAIN4NAIN2NVDA

AIN3PAIN1PAIN6PAIN4PAIN2PVDA

Figure 4. QFP-44 package pin layout

Power

Supply

Pins Pin I/O Description

VDA

VSA

AGND 6 PWR

VREF 8 PWR

VCC 3, 4 PWR Digital Supply, Positive, +5V

VGND 32 PWR Digital Supply, Negative, 0V

12, 13,

29, 30

10, 11,

27, 28

PWR

Analog Supply, Positive, +5V

Analog Supply, Negative, 0V Analog Ground Reference

Input Referenc e Voltage

Output/Input

Analog

Signals Pin I/O Description

AIN6P 18 I Voltage, Channel 3, Positive AIN6N 19 I Voltage, Channel 3, Negative AIN1P 20 I Current, Channel 1, Positive AIN1N 21 I Current, Channel 1, Negative AIN3P 22 I Current, Channel 2, Positive AIN3N 23 I Current, Channel 2, Negative AIN5P 24 I Current, Channel 3, Positive AIN5N 25 I Current, Channel 3, Negative

VCIN 7 I

Input to Volta ge Mo nitoring Block

N/C 9 I Must be left floating

Digital Control Signals Pin I/O Description

BGD 1 I

By-pass Control for Referenc e Voltage

CS 2 I Chip Select Input

PD 31 I

Power Down Control for A/D Modulators

N/C 33 I Connect to VGND

RESET 34 I Reset Input, Active High

Single / Differential selector.

SINGLE 26 I

· Low: Differential

· High or n/c: Single-ended

Status

Flags Pin I/O Description

Crystal

Osc

Signals Pin I/O Description

XI 43 I Crystal Oscillator Input

XO 44 O Crystal Oscillator Output

Analog

Signals Pin I/O Description

AIN2P 14 I Voltage, Channel 1, Positive AIN2N 15 I Volta ge, Channel 1, Negative AIN4P 16 I Voltage, Channel 2, Positive AIN4N 17 I Volta ge, Channel 2, Negative

AT73C500

PFAIL 5 O

Output of V oltage Monitorin g Block

Output

Bus

Signals Pin I/O Description

CLK 41 O Master Clock Output

CLKR 39 O Serial Bus Clock Output

DATA 35 O Serial Data Output

FSR 36 O

ACK 37 O

Output Sample Frame Signal

Data Ready Acknowledge Output

AT73C500 DSP

AT73C500

Figure 5. PLCC-44 package pin layout

SOUT15SOUT0

GND

GND ADDR0

7 39

GND

B12

B13

B14

GND

B15

IRQ0 /

GND2GND1CLK44STROBE43VCC42NC41ADDR1

PFAIL

B419GND20B521B622B723N/C24B825B926GND27B10

Power

Supply

Pins Pin I/O Description

VCC 35, 42 PWR Digital Supply, Positive, +5V

1, 2, 6, 7,

GND

1 1, 12,16,

20, 27, 30,

PWR Digital Supply, Negative, 0V

Digital Inputs Pin I/O Description

CLK 44 I Clock Input

XRES 38 I Reset Input, active low

Interrupt Input, usually

IRQ0 3 I

connected to PF AIL output of AT73C501

IRQ1 31 I

Interrupt Input, connec ted to ACK Output of AT73C501

Status/

Mode

Bus Pin I/O Description

B15 17 I/O Status/Mode Bus, Bit7 B14 15 I/O Status/Mode Bus, Bit6 B13 14 I/O Status/Mode Bus, Bit5 B12 13 I/O Status/Mode Bus, Bit4 B11 29 I/O Status/Mode Bus, Bit3

XRES

BRDY

RD/WR

VCC

GND

SIN

SCLK

IRQ1 / ACK

GND

B11

Microprocessor

Bus Pin I/O Description

B7 23 I/O µP Bus, Bit7 B6 22 I/O µP Bus, Bit6 B5 21 I/O µP Bus, Bit5 B4 19 I/O µP Bus, Bit4 B3 18 I/O µP Bus, Bit3 B2 10 I/O µP Bus, Bit2 B1 9 I/O µP Bus, Bit1 B0 8 I/O µP Bus, Bit0

AT73C501 /

AT73C502 and

EEPROM

Interface Pin I/O Description

SOUT0 4 O

Serial Out put, used as a clock for EEPROM

Serial Output, used as Chip

SOUT1 5 O

Select (CS) for AT73C501 and as Data Input (DI) for EEPROM

SIN 33 I

SCLK 32 I

Serial Data Input, data from A T73C501 or from EEPROM

Serial Clock Input, bit clock from AT73C501

Control Signals

of µP Bus and

Status/Mode

Bus Pin I/O Description

STROBE 43 O Strobe Output

BRDY 37 I

ADDR1 40 O

Microprocessor ready for I/O, Active Low

Address Output 1, used for µP bus

Address Output 0, used for

ADDR0 39 O

Status/ Mode bus and for Impulse Outputs

RD/WR 36 O Read/Write Signal

B10 28 I/O Status/Mode Bus, Bit2

B9 26 I/O Status/Mode Bus, Bit1 B8 25 I/O Status/Mode Bus, Bit0

AT73C501 and AT73C502

The AT73C501 consi sts o f six, 16 -bit a nalog-to -digi tal c onverters. The converters are equipped with single-ended inputs. For differenti al ended appli cations, the AT73 C502 chip is used.

Figure 6. Block diagram of the single-ended ADC chip, AT73C501

VOLTAGE

MONITORING

The converters contain a reference volta ge gen erator, vo ltage monitoring bloc k and serial output interf ace. Both c onverters are based on high-performance, oversampling Sigma-Delta modulators and digital decimation filters.

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

SIGMA-DELTA

MODULATOR

VOLTAGE

REFERENCE

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

DECIMATION

FILTER

In a 50 Hz meter, the nominal decimated sampling rate of 3200 Hz is used. This corre spo nds to 64 samples per each line frequency cycle. 60 Hz meters operate with 3840 Hz sample rate. The master clock frequency of the ADC is 1024 times higher than the above frequencies, i.e.

3.2768 MHz in 50 Hz meters and 3.93216 MHz in 60 Hz systems. The default meter constant of AT73C500 energy counters is based on the above sample rates.

Other sample frequencie s can be used, bu t the energy results have to be scaled accordingly. If higher sampling rate is selected, the meter constant will also be increased by the same ratio.

The three current inputs of AT73C501 are fed from secondary outputs of current transformers, from Hall sensors or other similar sensors. In differential-ended applications, such as with current shunt resistors, the AT73C502 ADC can be used. On both of these converters, the voltage inputs must be equipped with simple external voltage dividers.

The input voltage range of each converter is 2V

. The characteristics of a Watt-hour meter operating, according to IEC1036 specification, are based on a certain basic current, I

. As a default, the basic current of AT73C500

chipset is to 6.25% of the current input full scale value. This means that if a meter is designed for I

= 5A

RMS

, the full

scale range of the current channels will be:

SERIAL OUTPUT

LOGIC

TIMING AND

CONTROL

100

IFS = 5 A

-----------

× 80 A

RMS

6.25

RMS

The following current transformer and voltage divider configuration is rec ommended fo r a 230V, 3-phas e system, with 5A basic current:

Voltage Inputs Current Inputs

Converter full-scale input 2.0V Corresponding full-scale

line voltage / current

270V

RMS

2.0V

80A

RMS

With the above settings, the nominal pulse rate of the meter constant outp uts is 1250 impulses/kWh (125 0 impulses/kVArh) and the rate of four display outputs 100 impulses/kWh (100 imp/kVArh).

When used in a 5A transformer operated meter, the maximum current range ca n be scaled down to 8A f or exam pl e. In this case, the me ter constan t will be ten time s higher than in an 80A meter, i.e. 12500 impulses/kWh. Similarly, the starting current level will be transferred to 2mA, from 20mA.

AT73C500

If the nominal voltage is chosen to be 120V, the vo ltage divider can either have the same config uration as in the 230V meter, or it can be modified to produce 2.0V

with 140V phase voltage. In the latter case, the default meter constant will be roughly twice the constant of 230V meter, i.e. 2411 impulses/ kWh. T he mete r cons tant ca n be sca led to an even number value by means of calibration.

As described above, th e config uration of voltag e divider s and current tra nsformer s affects to almost all paramet ers being metered, like energy counters and i mpulse outputs. A calibration coefficient is provided for the adjustment of the display pulse rates. With this coefficient, the effect of various voltage divider and cur rent transformer c onfigurations can be compensated. Care should be tak en that the dynamic range of the A/D converters is always effectively utilized. The use o f calibrat ion coeff icients is described in the next section.

Current and voltage samples of AT73C501/AT73C502 are multiplexed and transferred to AT73C500 through a serial interface. The ti ming of the interf ace is presented in the next section.

AT73C501/AT73C502 con tain a n int ernal b andgap vol tage reference. When used in cl ass 0.5 and 0.2 me ters, smaller temperature drift is required. This can be achieved by bypassing the internal reference and using temperature

compensated external reference instead. The reference is selected with the BGD input.

BGD Reference

0 (V

) Internal

1 (VDD)External

There is an integrated volt age mo ni torin g blo ck on the converter chip. The PFAIL output is forced high if the level of voltage supplied to V

input drops below 4.2V. There is a

CIN

hysteresis in the monitoring function and PFAIL returns low if voltage at V

is raised back above 4.3V.

CIN

PFAIL output of AT73C501/AT73C502 can be connected to an interrupt input o f AT73C500. A T73C500 detects the rising edge of PFAIL. To as sure reliable power-down procedure after voltage break, the V

supply of AT73C500

must be equipped with a 470 µF or larger capacitor.

AT73C500

AT73C500 performs p ower and en er gy c alc ulati ons . It a lso controls the interfacing to the AT73C501 (or AT 73C502) and to an external microprocessor. The block diagram of the DSP is presented below.

Figure 7. Block diagram of DSP software

FREQUENCY

MEASUREMENT

u1(n) u2(n) u3(n)

i1(n) i2(n) i3(n)

DC OFFSET

SUPPRESSION

VOLTAGE

MEASUREMENT

PHASE

CALIBRATION

ACTIVE POWER MEASUREMENT

HILBERT

TRANSFORM

REACTIVE POWER

MEASUREMENT

Serial Bus Interface

The timing of the serial b us interface c onnecting the AD C and DSP devices is presented in Figure 8. The same bus is used to read the calibration data from an ex ternal EEPROM. This operation is described in section “Loading of Calibration Coefficients” on page 19.

f I U W P PF Q Wq

GAIN

CALIBRATION

GAIN AND OFFSET

CALIBRATION

GAIN AND OFFSET

CALIBRATION

APPARENT POWER

EVALUATION

CURRENT

DERIVATION

ACTIVE ENERGY

CALCULATION

POWER FACTOR

DERIVATION

REACTIVE ENERGY

CALCULATION

When the three current and three voltage samples are ready, AT73C50 1/AT73C502 raises t he ACK output. AT73C500 detects the ri si ng e dge of A CK, a nd, after a few clock cycles, it is ready to read the samples th rough the serial bus. Th e transfer is initiated by CS /SOUT1 sig nal and the data bits are strobed in at the falling edge of CLKR/SCLK clock. Six 16-bit samples is transferred in the following sequence: I1, U1, I2, U2, I3 and U3.

Figure 8. Serial bus timing

CLK

CLKR

ACK

FSR

6 * 16 BITS

DATA

CH1, B15

MSB

CH1, B14 CH1, B0

LSB

CH2, B15

MSB

CH2, B0

LSB

CH6, B1 CH6, B0

Operating Modes of AT73C500

The AT73C500 chips et has six operating modes. The mode is selected by three mode control inputs which AT73C500 reads through a bus during the initialization procedure after a reset state. The operation of AT73C501/AT73C502 is independent of the mode selected.

Mode Number Mode Bit 2 Mode Bit 1 Mode Bit 0 Operating Mode Calibration Data Storage

0000Not in use

In operating mode 7, the default display pul se rate is 10 impulses per kWh, instead of 100 impulses per kWh, as in other modes.

1001Normal operationEEPROM 2010Multi-channel operationEEPROM 3011Normal operationMicro-processor 4100Multi-channel operationMicro-processor 5101Test mode None 6110Not in use 7111Normal operationEEPROM

Normal Measurement Mode

AT73C500 devices support both stand-alone and microprocessor configurati on. The calib ratio n coeffi cient s ca n either be supplied by a processor or stored in an 128 x 8-bit EEPROM. The ROM is interfaced with AT73C500 via three pin serial bus. AT73C500 and the processor communicate through an 8-bit bus.

The only operational difference be tween stand-al one and µP mode is the way of reading calibration co effi ci en ts. Th is allows variou s combi nati ons of t hese tw o conf igurat ions t o be utilized. For example, th e calib ration data can be sto red in an EEPROM even though the processor reads and displays the measurement results supplied by AT73C500 device.

In most cases, the use of external EEPROM gives flexibility to the meter testing and calibratio n, and also makes the processor inte rface easier to implement. T herefore, th is

configuration is recommended even in meters equipped with a separate microprocessor.

The same sequence of basic ca lculations is performed both in poly-phase and single-phase meters. This sequence consists of DC offset suppression, phase, gain and offset c alibr atio n, c alc ula tions of mea surem en t qu antities and data transfer to µP bus and pulse outputs. AT73C500 constantl y m oni tors v ario us ta mpe ring an d faul t situations, which are indicated by status bits.

After a reset state, AT73C500 goes through an initialization sequence. The device reads the operating mode and fetches the calibration coefficients an d adjustment factors for output pulse rate and starting current level, either from a non-volatile memory or from a microprocessor. After that the normal measurement starts. The reset state is normally activated by power-up reset following the r ecovery from a voltage interruption.

AT73C500

Measurements and Calculations

The first operation performed by AT73C500 is digital highpass filtering. The purpose of the filtering is to remove the DC offset of both current and voltage samples.

From offset free samples, active power is calcul ated phase-by-phase with simple multiplication and additio n operations.

First, the current samples are multiplied by voltage samples. The multiplic ation resu lts are summed ov er one lin e period and finally the sum value is divided by 64. This discrete time operati on gi ve s the av erag e power of one 50 Hz period and the result corresponds to the following continuous time formula:

 

---

ANUNsin n wt×{}ANINsin n wt ∅+×



∑

n0=

∫

 



-- -

∑

n0=

nAnUnIn



{}dt×××××[]

cos ∅

()×××××

where

T = 1/50 Hz, n = 1, 2, 3,..., 20 (bas ic 50 Hz frequenc y and the har-

monics),

= frequency response of calculations.

This method of calculation does take into account the effect of harmonics.

The total power is calculated by summing the power of each line phase. Reactive power calculation is based on a similar procedure. Before multipl ying the curr ent and voltage samples AT73C500 performs a frequency independent 90 degree phase sh ift o f the voltage signal. This is re a lize d with a digit al H ilb ert t ran sform ati on f ilt er. T he ban dwidth of reactive power measuremen t is limited to 360 Hz.

Based on the active and reactive results apparent power and power factors ar e determined. RMS phase voltages are calculated by squaring and summing the voltage samples and fina lly ta king a s quare r oot of the re sults . Cur rent is determined by divi ding apparent po wer result by corr esponding phase voltage.

Frequency measurement is based on a comparison of the line frequency and AT73C500 sampling clock frequency. The measurement range is from 20 Hz to 350 Hz.

All measurements and calculations, except frequency measurement, are mad e over 1 0 l ine cy c le perio ds . T he re su lts are updated and transferred to processor bus once in 200 ms.

Measurement Registers

For the measurement parameters 25 registers are allocated:

REG0 Phase 1, active power, P1(10T), 32-bit register; REG1 Phase 2, active power, P2(10T), 32-bit register; REG2 Phase 3, active power, P3(10T), 32-bit register; REG3 Phase 1, reactive power, Q1(10T), 32-bit regi ste r; REG4 Phase 2, reactive power, Q2(10T), 32-bit regi ste r; REG5 Phase 3, reactive power, Q3(10T), 32-bit regi ste r; REG6 Phase 1, apparent power, S1(10T), 16-bit register; REG7 Phase 2, apparent power, S2(10T), 16-bit register; REG8 Phase 3, apparent power, S3(10T), 16-bit register; REG9 Phase 1, power factor, PF1, 16-bit register; REG10 Phase 2, power factor, PF2, 16-bit register; REG11 Phase 3, power factor, PF3, 16-bit register;

REG12

REG13

REG14

REG15

REG16

REG17 Frequency, f, 16-bit regi ste r; REG18 Reserved for further use, 16-bit register; REG19 Phase 1, voltage U1, 16-bit register; REG20 Phase 2, voltage U2, 16-bit register; REG21 Phase 3, voltage U3, 16-bit register; REG22 Phase 1, current I1, 16-bit register; REG23 Phase 2, current I2, 16-bit register; REG24 Phase 3, current I3, 16-bit register.

Active exported energy since the latest rese t, +Wp, 32-bit counter;

Active imported energy sin ce the latest rese t, -Wp, 32-bit counter;

Reactive energy, inductive load, Wqind, 32-bit counter;

Reactive energy, capacitive load, Wqcap, 32-bit counter;

Number of 10T periods elapsed since the latest reset, 32-bit counter;

The size of the registers is either 16-bit or 32-bit. IEC specifications apply to the calculations of active and reactive power and energy (REG 0-5 and REG 12-15). Other results are intended mainly for demand recording and for va rious diagnostic and display functions. The accuracy of those are limited due to the finite resolution.

In multi-chan nel mode the ac tive energy of each three meters (phases ) is stored in regist ers 12-14 . REG15 i s not in use.

The maximum value of different power registers differs, depending on the calculation formulas used. The scaling of registers is described below.

If a full scale sine signal is applied to voltage and current inputs and the voltage and current channels are exactly in the same phase, a value of 258F C2F7H will be produced in the 32-bit P1, P2 and P 3 regist ers. The LS bit wi ll correspond to about 34 microwatts in nominal input conditions of 270V maximum phase voltage and 80A maximum current.

If the load is fully reactiv e ( scale signals are applied, the Q1, Q2 and Q3 register content will be 2231 594DH positive or negative, and the LSB will represent about 38 µVAr. The maximum value of the 16-bit S registers is 258EH and this val ue is obtained if a full scale amplitude is produced to the current and voltage inputs. LS bit of the S registers correspond to about 2.25VA power.

The following formula is used to calculate the power factor:

PF sign Q

The PF register contents 7FFFH represents power factor value one and the contents 0000H value zero. Negative PF values are stored corres pondi ngly a s nega tive b inary nu mbers. It should b e note d that the s ign of pow er fact or res ult indicates whether the loading is inductive (+) or capacitive (-).

The contents of fr equ enc y r egi st er ( REG 1 7) actually represents a 16-bit fi gure whi ch corresp onds to the du ration o f 50 line frequency cycles. The measurement is made by comparing the line frequency with one of the sampling clocks of AT73C500 and therefore the result depends on the crystal frequency used. With default 3.2768 MHz crystal, the resolution of time value is 1.25 ms . To get the frequency, the following calculation has to be made:

If the master clock frequency (MCLK) of AT73C500 is not nominal, the following formula gives frequency results:

40000

-------------------

REG17

± 90° phase differenc e) and full

abs P()

------------------

()

×=

abs S()

40000

-------------------

REG17

Hz=

MCLK

------------------------------

× Hz=

3.2768MHz

In the default condition, value 7FFFH of register 17 corresponds to 1.22 Hz frequency, value 0320H represents 50 Hz and 0001H 40 kHz. However, in practice, the bandwidth of frequency measurement is limited to 20 Hz to 350 Hz.

The frequency measurement is locked with one of the phase voltages. If th is volt age disa ppears, AT7 3C500 tries to track one of the other phases. The frequency measurement works down to about 10% level of the full scale voltage range. The harmonics content of phase voltage should be below 10%. If it is hi gher, err oneous fre quency results may be obtained.

The voltage registers (REG19-REG 21) are scaled so that full scale sinusoidal input signal at AT73C501/AT73C502 voltage channels will produce 7A 8BH value into vo ltage registers. This means that the resolution of the registers is about 8.6 mV. Accordingly, full scale current will produce 7DA4H to current registers (REG22-REG24) pr oviding a resolution of about 2.5 mA. In practice, the voltage can be measured down to about 25V leve l and current down to about 100mA.

If either voltage or current, or both, contain a considerable amount of harmonics pr oducing a squ are wave type waveform, it is recommended to scale the input range so that the maximum peak-to-peak v alue i s at l east 1 0% below the full scale range of inputs. This is to avoid overflow in the calculations performed by AT73 C500 .

Energy Counters

Four 32-bit counters (REG12-REG15 ) measure energy consumption. In nominal situations, the counters are always increm ented wh en 0.4W h (0.4VA rh) energ y is consumed. The counters can store minimum of 1100 days consumption, provided that AT73C501/AT73C502 and AT73C500 are used with default settings.

Impulse outputs are generated from these counters. The meter constant rate represents 2 LSBs of a counter which equals 0.8 Wh (0.8 VArh) and produces 1250 impulses/kWh. (1250 impulses/kVArh). In modes 1 to 4, the display pulses are generated from 25 LSBs of a counter. This corresponds to an impulse rate of 100 impulses/kWh (100 impulses/kVArh). It is possible to adjust this rate with MCC calibration c oefficient. In mode 7, 2 50 LSBs o f the energy register is needed to gene rate one impu lse (10 impulses/kWh).

The default values above are based on 80A current, 270V rate.

The crystal frequency will affect the va lue s o f en er gy r egisters (REG12-REG15) and time register (REG 16). It will also change the pulse rates of the impulse outputs.

full scale voltage and 3.2768 MHz clock

RMS

full scale

RMS

AT73C500

+ 21 hidden pages