Rainbow Electronics AT6010LV User Manual
Features
• High-performance
– System Speeds > 100 MHz
– Flip-flop Toggle Rates > 250 MHz
– 1.2 ns/1.5 ns Input Delay
– 3.0 ns/6.0 ns Output Delay
• Up to 204 User I/Os
• Thousands of Registers
• Cache Logic
– Complete/Partial In-System Reconfiguration
– No Loss of Data or Machine State
– Adaptive Hardware
• Low Voltage and Standard Voltage Operation
– 5.0 (V
– 3.3 (V
• Automatic Component Generators
– Reusable Custom Hard Macro Functions
• Very Low-power Consumption
– Standby Current of 500 µA/ 200 µA
– Typical Operating Current of 15 to 170 mA
• Programmable Clock Options
– Independently Controlled Column Clocks
– Independently Controlled Column Resets
– Clock Skew Less Than 1 ns Across Chip
• Independently Configurable I/O (PCI Compatible)
– TTL/CMOS Input Thresholds
– Open Collector/Tristate Outputs
– Programmable Slew-rate Control
– I/O Drive of 16 mA (combinable to 64 mA)
• Easy Migration to Atmel Gate Arrays for High Volume Production
®
Design
= 4.75V to 5.25V)
CC
= 3.0V to 3.6V)
CC
Coprocessor
Field
Programmable
Gate Arrays
AT6000(LV)
Series
Description
AT6000 Series SR AM-bas ed Field P rogramm able Gate Arrays (FPGAs) are ideal f or
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series de vices are i deal for high-speed , comput e-inte nsive
designs. These FP GAs are desig ned to imple men t Cach e Logi c
user with the ability to imp lement adaptive hardware an d perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
®
, which provides th e
(continued)
AT6000 Series Field Programmable Gate Arrays
Device AT6002 AT6003 AT6005 AT6010
Usable Gates 6,000 9,000 15,000 30,000
Cells 1,024 1,600 3,136 6,400
Registers (m aximum) 1,024 1,600 3,136 6,400
I/O (maximum) 96 120 108 204
Typ. Operating Cur rent (mA) 15 - 30 25 - 45 40 - 80 85 - 170
Cell Rows x Columns 32 x 32 40 x 40 56 x 56 80 x 80
Rev. 0264F–10/99
1
Devices range in size from 4,000 to 30,000 us able gates,
and 1024 to 6400 registe rs. Pin locati ons are consiste nt
throughout the AT6000 Series for easy design migration.
High-I/O versions are available for the lower gate count
devices.
AT6000 Series FP GAs util ize a relia ble 0.6 µ m singl e-po ly,
double-metal CMOS process and are 100% factory-tested.
Atmel's PC- and workstation-based Integrated Development System is used to create AT6000 Series designs.
Multiple design entry methods are supported.
The Atmel architectu re was devel oped to provi de the highest levels of perf ormance, functiona l density a nd design
flexibility in an FPGA. The cells in the Atmel array are
small, very efficient and contain the most important and
most commonly used logic and wiring functions. The cell’s
small size leads to arrays with large numbers of cells,
greatly multipl ying the fu nctional ity in each ce ll. A sim ple,
high-speed busing network provides fast, efficient communication over medium and long distances.
The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array
of identical cells ( Figure 1). The arr ay is continuous and
completely uninterrupted from one edge to the other,
except for bus repeaters spaced every eight cells
(Figure 2).
In addition to logic and storage, cells can also be used as
wires to connect functions together over shor t distances
and are useful for routing in tight spaces.
The Busing Network
There are two kinds of buses: local and express (see
Figures 2 and 3).
Local buses ar e the link betwe en the array of c ell s and th e
busing network. There are two local buses – North-South 1
and 2 (NS1 and NS2) – for every column of cells, and two
local buses – East-West 1 and 2 (EW1 and EW2) – for
every row of cells. In a sector (an 8 x 8 array of cells
enclosed by repeaters) each local bus is connected to
every cell in its column or row, thus providing every cell in
the array with read/write ac cess to two North-S outh and
two East-West buses.
Figure 1. Symmetrical Array Surrounded by I/O
2
AT6000(LV) Series
Figure 2. Busing Network (one sector)
AT6000(LV) Series
CELL
REPEATER
Figure 3. Cell-to-cell and Bus-to-bus Connections
3
Each cell, in addition, provides the ability to route a signal
on a 90° turn between the NS1 bus and EW1 bus and
between the NS2 bus and EW2 bus.
Express buses are not con nec ted dir ec tly to cells, and thus
provide higher speeds. They are the fastest way to cover
long, straight-line distances within the array.
Each express bus is paired with a local bus, so there are
two express buses for ever y column and two express
buses for every row of cells.
Connective units, c alled repeaters , spaced every eight
cells, divide each bus, both lo cal and express, into
segments spanning eight cells. Repeaters are aligned in
rows and columns thereby partitioning the array into 8 x 8
sectors of cells. Each repeater is associated with a
local/express pair, and on each side of the repeater are
connections to a local-bus segment and an expr ess-bus
segment. The repeater can be prog rammed to provide any
one of twenty-one connecting functions. These functions
are symmetric with respect to both the two repeater sides
and the two types of buses.
Among the functions provided are the ability to:
• Isolate bus segments from one another
• Connect two local-bus segments
• Connect two express-bus segments
• Implement a local/express transfer
In all of these cases, each connection provides signal
regeneration and is thus u nidirectiona l. For bid irectional
connections, the basic repeater function for the NS2 and
EW2 repeaters is augment ed with a spec ial prog ramm able
connection allowing bidir ectional c ommunicati on between
local-bus segments. This option is primarily used to implement long, tristate buses.
The Cell Structure
The Atmel cell (Figure 4) is simple and small and yet
can be programmed to perform all the logic and wiring
functions needed to implement any digital circuit. Its four
sides are functionall y identical , so each cell is comp letely
symmetrical.
Read/write access to the four local buses – NS1, EW1,
NS2 and EW2 – is controlled, in part, by four bidirectional
pass gates connecte d dir ec tl y to the buse s. T o read a local
bus, the pass gate for that bus is turned on and the threeinput multiplexer is set accordingly. To write to a local bus,
the pass gate for that bus and the pass gate for the associated tristate driver are both turned on. The two-input
multiplexer supplying th e control sig nal to the drivers permits either: (1) active drive, or (2) dy namic tristating
controlled by the B input. Turning between L
between L
NS2
and L
is accomplished by turning on the
EW2
NS1
and L
two associated pass gates. The operations of reading, writing and turning are subject to the restriction that each bus
can be involved in no more than a single operation.
EW1
or
Figure 4. Cell Structure
4
AT6000(LV) Series
AT6000(LV) Series
In addition to the four local-bus connections, a cell receives
two inputs and provides two outputs to ea ch of its
North (N), South (S), East (E) and West (W) neighbors.
These inputs and outputs are divided into two classes: “A”
and “B”. There is an A input and a B input from each neighboring cell and an A output and a B output driving all four
neighbors. Between c el ls, an A out put is al way s co nnec te d
to an A input and a B output to a B input.
Within the cell, the four A inputs and the four B inputs enter
two separate, independently configurable multiplexers. Cell
flexibility is enhanced by allowing each multiplexer to select
also the logical constant “1”. The two multiplexer outputs
enter the two upstream AND gates.
Downstream from these two AND gates are an ExclusiveOR (XOR) gate, a register, an AND gate, an inverter and
two four-input multiplexers producing the A and B outputs.
These multiplexers are controlled in tandem (unlike the
A and B input mult iplexe rs) and determi ne the function of
the cell.
• In State 0 – corresponding to the “0” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s A output, and the output of
the right-hand upstream AND gate is connected to the
cell’s B output.
• In State 1 – corresponding to the “1” inputs of the
multiplexers – the output of the left-hand upstream AND
gate is connected to the cell’s B output, the output of the
right-hand upstream AND gate is connected to the cell’s
A output.
• In State 2 – corresponding to the “2” inputs of the
multiplexers – the XOR of the outputs from the two
upstream AND gates is provided to the cell’s A output,
while the NAND of these two outputs is provided to the
cell’s B output.
• In State 3 – corresponding to the “3” inputs of the
multiplexers – the XOR function of State 2 is provided to
the D input of a D-type flip-flop, the Q output of which is
connected to the cell’s A output. Clock and
asynchronous reset signals are supplied externally as
described later. The AND of the outputs from the two
upstream AND gates is provided to the cell's B output.
Logic States
The Atmel cell implements a rich and powerful set of logic
functions, stemming from 44 logica l cell states which pe rmutate into 72 physical states. Some states use both A and
B inputs. Other states are created by selecting the “1” input
on either or both of the input multiplexers.
There are 28 combinatoria l primitives created from the
cell’s tristate capabilities and the 20 physical states represented in Figure 5. Five logical primitives are derived from
the physical constants shown in Figure 7. More complex
functions are created by using cells in combination.
A two-input AND feeding an XOR (Figure 8) is produced
using a single cell (F igure 9). A two-to-one multiplexer
selects the logical constant “0” and feeds it to the righthand AND gate. The AND gate acts as a feed- through, l etting the B input pa ss through to the XO R. Th e th r ee-to- on e
multiplexer on the right side selects the local-bus input,
LNS1, and passes it to the left-hand AND gate. The A and
LNS1 signals are the inputs to the AND gat e. Th e outp ut of
the AND gate feeds into the XOR, producing the logic state
l
L) XOR B.
(A
5
Figure 5. Combinatorial Physical States
A
B
D
Q
"0"
A
B
D
Q
B
D
Q
B
B
D
Q
A
B
D
Q
D
Q
BA
D
Q
A
B
D
Q
B
B
D
Q
BA
B
D
Q
BA
D
Q
B
1
0
L
i
L
i
L
i
L
i
L
i
L
i
L
i
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
A, L
o
L
i
L
i
L
i
Figure 7. Physical Constants
"0" "0"
"0" "1"
"1" "0"
"1" "1"
A, L
BBABBBB
A, L
o
L
ABBABBABA
i
A, L
o
L
i
A, L
o
L
i
A, L
o
o
L
i
A, L
o
B
B
BA
B
BB A
L
i
A, L
B
o
BA
B
A, L
o
Figure 6. Register States
A, L
A, L
L
A, L
L
A, L
B
A, L
A, L
o
L
i
o
i
o
A, L
A, L
o
L
o
L
i
o
A, L
o
L
i
A
i
A, L
B
o
B
BA
L
i
A, L
B
o
Figure 8. Two-in put AND Feeding XOR
o
B
o
A
i
A, L
BL
B
o
A, L
BA, L
o
A
B
i
B
o
A, L
BA
L
i
B
o
1BA0
A, L
L
i
o
l
Figure 9. Cell Configuration (A
L) XOR B
6
AT6000(LV) Series
AT6000(LV) Series
A
D
Q
"1"
GLOBAL
CLOCK
EXPRESS
BUS
GLOBAL
CLOCK
EXPRESS
BUS
R
O
U
T
I
N
G
B
U
R
I
E
D
D
E
D
I
C
A
T
E
D
CELL
D
Q
CELL
A
D
Q
EXPRESS
BUS
GLOBAL
RESET
EXPRESS
BUS
GLOBAL
RESET
CELL
D
Q
CELL
"1"
Clock Distribution
Along the top edge of the array is logic for distributing clock
signals to the D flip-flop in each logic cell (Figure 10). The
distribution network is organiz ed by colum n and permits
columns of cells to be independently clocked. At the head
of each column is a use r- c onf igu ra bl e mul t ip le xe r pr ov id in g
the clock signal for that column. It has four inputs:
• Global clock supplied through the CLOCK pin
• Express bus adjacent to the distribution logic
•“A” output of the cell at the head of the column
• Logical constant “1” to conserve power (no clock)
Through the global clock, the network provides low-skew
distribution of an externa lly supplied clock to any or all of
the columns of the array. The global clock pin is also connected direct ly to the arra y via the A input of the upp er left
and right corner cells (AW on the l eft , an d A N on the r ig ht) .
The express bus is useful in distributing a secondary clock
to multiple colum ns whe n th e glob al cl ock li ne is used a s a
primary clock. The A output of a cell is useful in providing a
clock signal to a single column. T he constan t “1” is used to
reduce power dissipation in columns using no registers.
Figure 10. Column Clock and Column Reset
Asynchronous Reset
Along the bottom edge of the array is logic for asynchronously resetting the D flip-flo ps in the logic cells
(Figure 10). Like the clock network, the asynchronous reset
network is organiz ed by co lu mn a nd p e rmi ts columns to be
independently reset. At the bottom of each column is a
user-configurable multiplexer providing the reset signal for
that column. It has four inputs:
• Global asynchronous reset supplied through the
RESET
• Express bus adjacent to the distribution logic
•“A” output of the cell at the foot of the column
• Logical constant “1” to conserve power
The asynchrono us res et l ogic uses t hese four input s in the
same way that the clock distribution logic does. Through
the global asynchr onous re set, any or all columns can b e
reset by an externally supplied signal. The global asynchronous reset pin is also connected directly to the array via the
A input of the lower left and right corner cells (AS on the
left, and AE on the ri ght). T he expr ess bu s can be used t o
distribute a secondary reset to multiple columns when the
global reset line is used as a prim ary reset, the A outp ut of
a cell can also pro vide an asyn chrono us reset signal to a
single column, and the constant “1” is used by columns
with registers requi ring no re se t. A ll regis te rs are re se t du ring power-up.
pin
Input/Output
The Atmel architecture provides a flexible interface
between the logic arra y, the confi gurati on contro l logic an d
the I/O pins.
Two adjacent cells – an “exit” and an “entranc e” cell – on
the perimeter of the logic array are associated with each
I/O pin.
There are two type s of I/Os: A-type (F igure 11) and B-typ e
(Figure 12). For A-type I/Os, the edge-facing A output of an
exit cell is connected to an output driver, and the edgefacing A input of the adjacent entr ance cell is connecte d to
an input buffer. The output of the output driver and the input
of the input buffer are connected to a common pin.
B-type I/Os are the same as A-type I/Os, but use the B
inputs and outputs of their respective entrance and exit
cells. A- and B-type I/Os altern ate arou nd the array Control
of the I/O logic is provided by user-configurable memory
bits.
7
Figure 11. A-type I/O Logic
Figure 12. B-type I/O Logic
Slew Rate Control
A user-configurabl e bit co ntrols th e slew rate – fast or slow
– of the output buffer. A s low slew rate, which reduces
noise and ground bounce, is recommended for outputs that
are not speed-critical. Fast and slow slew rates have the
same DC-current sinking capabilities, but the rate at which
each allows the output devices to reach full drive differs.
Pull-up
A user-configurab le bit cont rols the pull -up tran sistor in the
I/O pin. It’s primary function is to pro vide a logica l “1” to
unused input pi ns. When on , it is appro ximat ely equi valen t
to a 25K resistor to V
Enable Select
User-configurable bits determine the output-enable for the
output driver. The output driver can be static – always on or
always off – or dynamically controlled by a signal generated in the array. Four options are ava il able fr om the array :
(1) the control is low and always driv ing; (2) the control is
high and never driving; (3) the control is connected to a vertical local bus associated with the output cell; or (4) the
control is connected to a horizontal local bus assoc iated
with the output cell. On power- up, the us er I/Os ar e configured as inputs with pull-up resistors.
In addition to the fu nction al ity p ro vided b y the I/O l ogi c , th e
entrance and exit cells provide the ability to register both
inputs and outputs . Also , th ese per imeter c ells (unli ke in terior cells) are conne cted directly to expres s buses: the
edge-facing A and B outputs of the entrance cell are c onnected to express buses, as are the edge-facing A and B
inputs of the exit cell. These buses are perpendicular to the
edge, and provide a rapid means of bringing I/O signals to
and from the array interi or and the opposite ed ge of the
chip.
CC
.
TTL/CMOS Inputs
A user-configurable bit determines the threshold level –
TTL or CMOS – of the input buffer.
Open Collector/Tristate Outputs
A user-configurable bit which enables or disables the active
pull-up of the output device.
8
AT6000(LV) Series
Chip Configuration
The Integrated Development System generates the SRAM
bit pattern required to con f ig ure a AT 60 00 S erie s d ev ice. A
PC parallel port, microprocessor, EPROM or serial configuration memory can be used to download configuration
patterns.
Users select from several configuration modes. Many factors, including board area, configuration speed and the
number of designs implemented in parallel can influence
the user’s final choice.
Configuration is controlled by dedicated configuration pins
and dual-function pins that double as I/O pins when the
device is in op eration. T he number of dual-funct ion pins
required for each mode varies.
AT6000(LV) Series
The devices can be partially reconfigured while in operation. Portions of the device not being modified remain
operational during recon figuratio n. Simul taneous configuration of more th an one device is al so possible. Full
configuration takes as little as a millisecond, partial configuration is even faster.
Refer to the Pin Function Description section following for a
brief summary of the pins used in configur ation. For more
information about c onfi gurat ion, refer to the AT6 000 Series
Configuration data sheet.
Pin Function Description
This section provides abbreviated descriptions of the various AT6000 Series pins. For more complete descriptions,
refer to the AT6000 Series Configuration data sheet.
Pinout tables for the AT6000 series of devices follow.
Power Pins
VCC, VDD, GND, V
VCC and GND are the I/O supply pins, VDD and VSS are the
internal logic supply pins. V
same trace on the printed circuit board. GND and V
should be tied to the same trace on the printed circuit
board.
Input/Output Pins
All I/O pins can be used in the same way ( refer to the I/O
section of the architecture description). Some I/O pins are
dual-function pins used during configuration of the array.
When not being used for configu ration, dua l-functio n I/Os
are fully functional as normal I/O pins. On initial power-up,
all I/Os are configured as TTL inputs with a pull-up.
Dedicated Timing and Control Pins
CON
Configuration-in-process pin. After power-up, CO N staysLow until power-up init ial ization is complete, at which tim e
is then released. CON is an open collecto r signal .
CON
After power-up initialization, forcing CON
configuration process.
CS
Configuration enable p in. Al l conf igura tion pi ns are i gnore d
is high. CS must be held low thro ughout the conf igu-
if CS
ration pr ocess. CS
SS
and VDD should be tied to the
CC
is a TTL input pin.
SS
low begins the
M0, M1, M2
Configuration mo de pins are used to d etermine the confi guration mode. All three are TTL input pins.
CCLK
Configuration clock pin. CCLK is a TTL input or a CMOS
output depending on the mod e of o per at ion . In m ode s 1, 2,
3, and 6 it is an input. In modes 4 and 5 it i s an outp ut with
a typical frequency of 1 MHz. In all modes, the rising edge
of the CCLK signal is used to sample inputs and change
outputs.
CLOCK
External logic s ourc e us ed to d rive the in ter nal gl oba l c lock
line. Registers toggle on the risi ng edge of CLOCK. T he
CLOCK signal is neither used nor affected by the configuration modes. It is always a TTL input.
RESET
Array register async hrono us reset. RESET drives the internal global reset. The RESET
affected by the configuration modes. It is always a TTL
input.
Dual-function Pins
When CON
I/Os; when CON
figuration c ontrol or data si gnals as deter mined by the
configuration modes. Care must be taken wh en using
these pins to ens ure that conf iguration ac tivity does no t
interfere with other circuitry connected to these pins in the
application.
D0 or I/O
Serial configuration modes use D0 as the serial data input
pin. Parallel configuratio n modes us e D0 as the least-significant bit. Input d ata must meet setup and hold
requirements with respect to the rising edge of CCLK. D0 is
a TTL input during configuration.
D1 to D7 or I/O
Parallel conf iguration mo des use these pi ns as inputs.
Serial configuration modes do not use them. Data must
meet setup and hold requirements with respect to the rising
edge of CCLK. D1 - D7 are TTL inputs during configuration.
A0 to A16 or I/O
During configuration in modes 1, 2 and 5, these pins are
CMOS outputs and act as the address pins for a parallel
EPROM. A0 - A16 eliminates the need for an external
address counter when using an external parallel nonvolatile
is high, dual -functio n I/O pins ac t as devic e
is low, dual-function pins are used as con-
signal is neither used nor
9
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