Rainbow Electronics AT49LV040 User Manual
Features
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
432
1
323130
14151617181920
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
A18
VCCWEA17
• Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
• Fast Read Access Time – 70 ns
• Internal Program Control and Timer
• 16K Bytes Boot Block with Lockout
• Fast Chip Erase Cycle Time – 10 seconds
• Byte-by-byte Programming – 30 µs/Byte Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Small Packaging
– 8 x 14 mm VSOP/TSOP
Description
4-megabit
(512K x 8)
Single 2.7-volt
Battery-Voltage
™
The AT49BV/LV040 are 3-volt only, 4-megabit Flash memories organized as 524,288
words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over
the commercial temperature range. When the device is deselected, the CMOS
standby current is less than 50 µA.
The device contains a user-enabled “boot block” protection feature. The
AT49BV/LV040 locates the boot block at lowest order addresses (“bottom boot”).
(continued)
Pin Configurations
Pin Name Function
A0 - A18 Addresses
CE
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
PLCC Top View
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Flash Memory
AT49BV040
AT49LV040
A11
A13
A14
A17
VCC
A18
A16
A15
A12
1
2
A9
3
A8
4
5
6
7
WE
8
9
10
11
12
13
A7
14
A6
15
A5
16
A4
OE
32
A10
31
CE
30
I/O7
29
I/O6
28
I/O5
27
I/O4
26
I/O3
25
GND
24
I/O2
23
I/O1
22
I/O0
21
A0
20
A1
19
A2
18
A3
17
Rev. 0679D–03/01
1
To allow for simple in-system reprogrammability, the
AT49BV/LV040 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV040 is performed by erasing the entire four megabits of memory and then
programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle
can be optionally detected by the Data
Polling feature.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
Once the end of a byte program cycle has been detected, a
new access for a read or program can begin. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The optional 16K bytes boot block section includes a reprogramming write lockout feature to provide data integrity.
The boot sector is designed to contain user-secure code,
and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(496K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
7FFFFH
04000H
03FFFH
00000H
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM.
When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the highimpedance state whenever CE
control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the 512K
bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a six-byte software code. The
software chip erase code consists of six-byte load commands to specific address locations with a specific data
pattern (please refer to “Chip Erase Cycle Waveforms” on
page 8).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.
and OE are low and WE is high, the data stored
or OE is high. This dual-line
. If the boot block lockout feature has
EC
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a four-bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE
latched on the rising edge of WE
first. Programming is completed after the specified t
time. The Data
or CE, whichever occurs last, and the data
or CE, whichever occurs
cycle
BP
Polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
2
AT49BV/LV040
AT49BV/LV040
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write-protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular programming method. To activate the lockout feature, a series
of six program commands to specific addresses with specific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel.
It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see “Operating Modes” on page 5 (for hardware operation) or “ Software Product Identification
Entry/Exit” on page 10. The manufacturer and device
codes are the same for both modes.
DATA POLLING: The AT49BV/LV040 features Data
Polling to indicate the end of a program cycle. During a
program cycle, an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to Data Polling, the
AT49BV/LV040 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: The Hardware Data
Protection feature protects against inadvertent programs to
the AT49BV/LV040 in the following ways: (a) V
is below 1.8V (typical), the program function is inhib-
V
CC
ited. (b) Program inhibit: holding any one of OE
sense: if
CC
low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE
or CE inputs
will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
+ 0.6V.
CC
3
Command Definition (in Hex)
1st Bus
Command
Sequence
Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D
Boot Block Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH.
(2)
(2)
2. Either one of the Product ID Exit commands can be used.
Bus
Cycles
(1)
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
3 5555 AA 2AAA 55 5555 F0
1 XXXX F0
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
OUT
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
IN
6th Bus
Cycle
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Voltage on OE
with Respect to Ground..................................-0.6V to + 13.5V
4
AT49BV/LV040
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