Rainbow Electronics AT49LV001NT User Manual

Features

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A7
A6
A5
A4
A3
A2
A1
A0

I/O0

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

432

1

323130

14151617181920

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

RESET*

VCCWENC

• Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV)

• Fast Read Access Time - 70 ns

• Internal Program Control and Timer

• Sector Architecture

– One 16K Byte Boot Block with Programming Lockout
– Two 8K Byte Parameter Blocks
– Two Main Memory Blocks (32K, 64K Bytes)

• Fast Erase Cycle Time - 10 seconds

• Byte-by-byte Programming - 30 µs/Byte Typical

• Hardware Data Protection

• DATA Polling For End Of Program Detection

• Low Power Dissipation

– 25 mA Active Current
– 50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49BV/LV001(N)(T) is a 3-volt-only in-system reprogrammable Flash memory.
Its 1 megabit of memor y is organi zed as 13 1,072 wor ds by 8 bits. Ma nufact ured wit h
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
70 ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA. For the

(continued)

Pin Configurations

DIP Top View

1-megabit
(128K x 8)
Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV001
AT49LV001

™

Pin Name Function

A0 - A16 Addresses
CE
OE

Chip Enable

Output Enable
WE Write Enable
RESET

RESET
I/O0 - I/O7 Data Inputs/Outputs
DC Don’t Connect
NC No Connect

PLCC Top View

*Note: This pin is a DC on the AT49BV001N(T) and AT49LV001N(T).

1

*RESET

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14

I/O1

15

I/O2

16

GND

VSOP To p View (8 x 14mm) or

TSOP Top View (8 x 20mm)

Type 1

1

A11

2

A9

3

A8

4

A13

5

A14

6

NC

7

WE

8

VCC

A16
A15
A12

9
10
11
12
13

A7

14

A6

15

A5

16

A4

*RESET

VCC

32

WE

31

NC

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

I/O7

21

I/O6

20

I/O5

19

I/O4

18

I/O3

17

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

AT49BV001N
AT49LV001N
AT49BV001T
AT49LV001T
AT49BV001NT
AT49LV001NT

Rev. 1110B–08/99

1

AT49BV/LV001N(T ) pin 1 for the DIP and P LCC packag es
and pin 9 for the TSOP package are don’t connect pins.

To allow for simple in-system reprogrammability, the
AT49BV/LV001(N)(T) does not require high input voltages
for programming. Three-volt-only commands determine the
read and programming operation of the dev ice. Reading
data out of the device is similar to reading from an EPROM;
it has standard CE

, OE, and WE inputs to av oid bus con­tention. Reprogra mming the AT4 9BV/LV00 1(N)(T) is per­formed by erasing a block of data and then programming
on a byte-by-byte basis. The byte programming time is a
fast 50 µs. The end of a program cycle can be optionally
detected by the DATA

polling feature. Once the end of a
byte program cycle h as be en dete cted, a n ew acc ess for a
read or program can begin. T he typica l number of progra m
and erase cycles is in excess of 10,000 cycles.

Block Diagram

DATA INPUTS/OUTPUTS

VCC

GND

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

The device is erased by executing the er ase command
sequence; the device internally controls the erase opera­tions. There are two 8K byte para meter bloc k sectio ns and
two main memory blocks.

The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
The 16K byte boot block se ct ion includes a reprogram ming
lock out feature to prov ide data in tegr i ty. The boot sector is
designed to contai n user secur e code, and when the fea­ture is enabled, the boot sector is protected from being
reprogrammed.

In the AT49BV/LV001 N(T), once the bo ot block prog ram­ming lockout feature is enabled, the contents of the boot
block are perman ent and cannot be chan ged. In the
AT49BV/LV001(T), once the boot block programming lock­out feature is enabled, the contents of the boot block can­not be changed with input voltage levels of 5.5 volts or less.

AT49BV/LV001(N)

I/O7 - I/O0

8

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

1FFFF

10000
0FFFF

08000
07FFF

06000
05FFF

04000
03FFF

00000

AT49BV/LV001(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

INPUT/OUTPUT

BUFFERS

PROGRAM

DATA LATCHES

Y-GATING

BOOT BLOCK

(16K BYTES)

PARAMETER

BLOCK 1

(8K BYTES)

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

1FFFF

1C000
1BFFF

1A000
19FFF

18000
17FFF

10000
0FFFF

00000

2

AT49BV/LV001(N)(T)

Device Operation

READ: The AT49BV /LV001(N)(T) is accessed like an

EPROM. When CE
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE
high. This dual-line con tr ol gi v es design er s fl ex ibili ty in pre­venting bus contention.

COMMAND SEQUENCES: When the device is first pow­ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table.
The command sequences are written by applying a low
pulse on the WE
tively) and OE
edge of CE
latched by the first rising edge of CE
microprocessor write timings are used. The address loca­tions used in the command sequences are not affected by
entering the command sequences.

RESET: A RESET
tem application s. When RE SET
device is in its standa rd oper at ing mod e. A low l evel on th e
RESET
the outputs of the device in a high impedance state. If the
RESET
gram or eras e operation, the operat ion may n ot be suc­cessfully compl eted and the opera tion will have t o be
repeated after a high level is applied to the RESET
When a high level is reasserted on the RESET
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V

0.5V input signal to the RESET pin, the boot block array
can be reprogrammed even if the boot block lockout fea­ture has been enabled (see Boot Block Programming Lock­out Override section). The RESET feature is not available
on the AT49BV/LV001N(T).

ERASURE: Before a byte can be repr ogramme d, the main
memory block or parameter block which contains the byte
must be erased. The erased state of the memor y bits is a
logical “1”. The entire dev ice can be eras ed at one tim e by
using a 6 byte software code. The software chip erase
code consists of 6 byte load commands to specific address
locations with a specific data pattern (please refer to the
Chip Erase Cycle Waveforms).

After the software c hi p e ra se has been initiate d, the d evi c e
will internally time the er ase operation so that no e xternal
clocks are required. The maximum time needed to erase
the whole chip is t
been enabled, the data in the boot sector will not be
erased.

or WE, whichever occurs last. The data is

input halts the prese nt device oper ation and puts
pin makes a hig h-to-low tr ansition during a pr o-

and OE are low and WE is high, the

or OE is

or CE input with CE or WE low (respec-

high. The address is latched on the falling

or WE. Standard

input pin is provided to ease some sys-

is at a logic high level, the

pin.

pin, the

. If the boot block lockout feature has

EC

AT49BV/LV001(N)(T)

CHIP ERASE: If the boot block lockout has been enabled,

the Chip Erase function will erase Parameter Block 1,
Parameter Block 2, M ain Me mory B lock 1, a nd Mai n Mem­ory Block 2 but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase
the entire chip. After the full chip erase the device will
return back to read mode. Any c omm and dur ing chip er as e
will be ignored.

SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections
and two main memory blocks. The 8K-byte parameter
block sections can be independently erased and repro­grammed. The two main memory sections are designed to
be used as alternative memory sectors. That is, whenever
one of the blocks has bee n er as ed and repr og ramme d, the
other block should be erased and r eprogrammed be fore
the first block i s ag ain e ra se d. The Se ctor Erase comman d
is a six bus cycle operation. The sector address is latched
on the falling WE
input command is latched at the ri sing edge of WE
sector erase starts after the rising edge of WE
cycle. The erase op eration is in ternally contr olled; it will
automatically time to completion.

BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte bas is. Please not e that a data “0” cannot b e
programmed ba ck to a “1”; only erase operations can con­vert “0”s to “1”s. Programming i s accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatic al ly generate the required internal

±

program pulses.
The program cyc le has addres ses latched on the falling

edge of WE
latched on the rising edge of WE
first. Programming is completed after the specified t
time. The DATA
cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in th e
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enablin g the l ockou t featur e wil l allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’s usage as a write protec ted reg io n is
optional to the user. The address range of the boot block is
00000 to 03FFF for the AT49BV/LV001(N) while the
address range of the boot block is 1C000 to 1FFFF for the
AT49BV/LV001(N)T.

edge of the sixth cycle while the 30H data

or CE, whichever occurs last, and the data

or CE, whichever occurs

polling feature may also be used to indi-

. The

of the sixth

cycle

BP

3

Once the feature is enabled, the data in th e boot blo ck ca n
no longer be erased or programmed with input voltage level
of 5.5V or less. Data in the ma in memory bl ock can still be
changed through the regular programming method. To acti­vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product i dentifica tion mode (see Sof tware Pr oduct
Identification Entry and Exit sections) a read from address
location 00002H will s how if progr ammin g the boot bl ock is
locked out for the AT49BV/LV001(N ) and a read from
address 1C002H will show if programming the boot block is
locked out for the AT49BV/LV001(N)T. If the data on I/O0
is low, the boot block can be programmed; if the data on
I/O0 is high, the program lockout feature has been acti­vated and the block cannot be programmed. The software
product identification code should be used to return to stan­dard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override th e boot block programm ing lock out
by taking the RESET
erase, sector erase or byte programming operation. When
the RESET
programming lockout feature is again active. This feature is
not available on the AT49BV/LV001N(T).

PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The

pin is brought back to TTL levels the boot block

pin to 12 volts during the entire chip

hardware operation mode can be used by an external pro­grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Oper ating Mo des (for hardw are ope ratio n)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT49BV/LV001(N)(T) features

polling to indicate the end of a program cycle. During

DATA
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA
AT49BV/LV001 (N)(T) pr ovides an other metho d for dete r­mining the end of a program or erase cycle. During a pro­gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
toggling and valid data will be read . Examining the toggle
bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV001(N)(T) in the following ways: (a) V
if V

is below 1.8V (typic al), th e progra m functi on is inhi b-

CC

ited. (b) Program inhi bit: holding a ny one of OE
high or WE high inhibits program cyc les. (c) Noise filter :
pulses of less than 15 ns (typical) on the WE
will not initiate a program cycle.

polling the

sense:

CC

low, CE

or CE inputs

4

AT49BV/LV001(N)(T)

AT49BV/LV001(N)(T)

Cycle

(1)

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

(4)

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA
Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr D
Boot Block Lockout
Product ID Entry 3 5555 AA 2AAA 55 5555 90
Product ID Exit
Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)

(3)

(3)

2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV001(N) and
1C000H to 1FFFFH for the AT49BV/LV001(N)T.

3. Either one of the Product ID Exit commands can be used.

4. SA = sector addresses:
For the AT4 9BV/LV001(N):
SA = 00000 to 03FFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2

Bus

Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0
1 XXXX F0

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

30

For the AT4 9BV/LV001(N)T:
SA = 1C000 to 1FFFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1
SA = 18000 to 19FFF for PARAMETER BLOCK 2
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi­tions beyond those indicated in the operational sec­tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.

5

DC and AC Operating Range

AT49LV001(N)(T)-70 AT49BV/LV001(N)(T)-90 AT49BV/LV001(N)(T)-12

Operating
Temperature (Case)

Power Supply 3.0V - 3.6V 2.7V - 3.6V/3.0V - 3.6V 2.7V - 3.6V/3.0V - 3.6V

V

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE RESET

Read V
Program/Erase

(2)

Standby/Write Inhibit V

IL

V

IL

IH

V

IL

V

IH
(1)

X
Program Inhibit X X V
Program Inhibit X V
Output Disable X V

IL

IH

V

IH

V

IL

XV

IH

XV

XV
Reset X X X V
Product Identification

Hardware

Software

V

IL

(5)

V

IL

V

IH

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.
= 12.0V ± 0.5V.

3. V

H

4. Manufacturer Code: 1FH, Device Code: 05H - AT49BV/LV001(N), 04H - AT49BV/LV001(N)T.

5. See details under Software Product Identification Entry/Exit.

6. This pin is not available on the AT49BV/LV001N(T).

(6)

V

IH

V

IH

IH

V

IH

IH

IH

IL

A1 - A16 = VIL, A9 = VH,
A1 - A16 = VIL, A9 = VH,

A0 = VIL, A1 - A16=V

A0 = VIH, A1 - A16=V

Ai

Ai D
Ai D

I/O

OUT

IN

X High Z

High Z

X High Z

(3)

, A0 = V

(3)

, A0 = V

IL

IL

Manufacturer Code

IL

Device Code

IH

Manufacturer Code
Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I
I
I
I
I
V
V
V
V

LI

LO

SB1

SB2

CC

(1)

IL

IH

OL

OH

Input Load Current VIN = 0V to V
Output Leakage Current V
VCC Standby Current CMOS CE = V
VCC Standby Current TTL CE = 2.0V to V
V

Active Current f = 5 MHz; I

CC

Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 2.1 mA 0.45 V
Output High Voltage IOH = -400 µA 2.4 V

Note: 1. In the erase mode, ICC is 50 mA.

6

AT49BV/LV001(N)(T)

= 0V to V

I/O

CC

CC

- 0.3V to V

CC

OUT

CC

CC

= 0 mA 25 mA

10 µA
10 µA
50 µA

3mA

AC Read Characteristics

AT49BV/LV001(N)(T)

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

(1)

(2)

(3)(4)

Address to Output Delay 70 90 120 ns
CE to Output Delay 70 90 120 ns
OE to Output Delay 0 35 0 40 0 50 ns
CE or OE to Output Float 0 25 0 25 0 30 ns
Output Hold from OE, CE or

t

OH

Address, whichever occu rred
first

AC Read Waveforms

(1)(2)(3)(4)

ADDRESS

CE

OE

AT49LV001(N)(T)-

70

Min Max Min Max Min Max

AT49BV/LV001(N)(T)-

90

AT49BV/LV001(N)(T)-

12

Units

00 0ns

ADDRESS VALID

t

CE

t

OE

t

DF

t

ACC

t

OH

Notes: 1. CE may be delayed up to t

2. OE

3. t

may be delayed up t o tCE - t

without impact on t

is specified from OE or CE whichever occurs first (CL = 5 pF).

DF

ACC

.

OUTPUT

- tCE after the address transition without impact on t

ACC

after the falling edge of CE without im pact on tCE or by t

OE

HIGH Z

OUTPUT

VALID

ACC

.

- tOE after an address change

ACC

4. This parameter is characterized and is not 100% tested.

Input Test Waveform and Measurement Level

2.4V

AC

DRIVING

LEVELS

1.5V

0.4V

AC
MEASUREMENT
LEVEL

Output Load Test

3.0V

1.8K
OUTPUT

1.3K

PIN

30 pF

tR, tF < 5 ns

Pin Capacitance

(f = 1 MHz, T = 25°C)

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% test ed.

(1)

46pFV
812pFV

IN

OUT

= 0V

= 0V

7