Rainbow Electronics AT49F8192AT User Manual

Features

• Single-voltage Operation

–5V Read
– 5V Programming

• Fast Read Access Time – 90 ns

• Internal Erase/Program Control

• Sector Architecture

– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 496K Word (992K Bytes) Main Memory Array Block

• Fast Sector Erase Time – 10 seconds

• Byte-by-byte or Word-by-word Programming – 10 µs Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Low Power Dissipation

– 50 mA Active Current
– 100 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49F008A(T) and AT49F8192A(T) are 5-volt, 8-megabit Flash memories orga­nized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 90 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F008A/8192A locates the boot block at lowest
order addresses (“bottom boot”); the AT49F008AT/8192AT locates it at highest order
addresses (“top boot”).

To allow for simple in-system reprogrammability, the AT49F008A(T)/8192A(T) does
not require high-input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE
bus contention. Reprogramming the AT49F008A(T)/8192A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.

, OE and WE inputs to avoid

(continued)

8-megabit
(1M x 8/
512K x 16)
Flash Memory

AT49F008A
AT49F008AT
AT49F8192A
AT49F8192AT

Pin Configurations

Pin Name Function

A0 - A18 Addresses

CE

OE

WE Write Enable

RESET

RDY/BUSY

I/O0 - I/O14 Data Inputs/Outputs

I/O15 (A-1)

BYTE

NC No Connect

Chip Enable

Output Enable

Reset

Ready/Busy Output

I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

Rev. 1199F–04/01

1

AT49F8192A(T) TSOP Top View

Typ e 1

A15
A14
A13
A12
A11
A10

RESET

A18
A17

1
2
3
4
5
6
7

A9

8

A8

9

NC

10

NC

11

WE

12
13

NC

14

NC

15

NC

16
17
18

A7

19

A6

20

A5

21

A4

22

A3

23

A2

24

A1

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE
GND
I/O15 / A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0

AT49F008A(T) TSOP Top View

Type 1

1

A16

2

A15

3

A14

4

A13

5

A12

6

A11

7

A9

8

A8

9

WE

10

RESET

11

NC

A18

12
13
14

A7

15

A6

16

A5

17

A4

18

A3

19

A2

20

A1

RDY/BUSY

AT49F8192A(T) SOIC (SOP) Top View

1

44

NC

2

A18

3

A17

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

CE

13

GND

14

OE

15

I/O0

16

I/O8

17

I/O1

18

I/O9

19

I/O2

20

I/O10

21

I/O3

22

I/O11

40

A17

39

GND

38

NC

37

A-1

36

A10

35

I/O7

34

I/O6

33

I/O5

32

I/O4

31

VCC

30

VCC

29

NC

28

I/O3

27

I/O2

26

I/O1

25

I/O0

24

OE

23

GND

22

CE

21

A0

RESET

43

WE

42

A8

41

A9

40

A10

39

A11

38

A12

37

A13

36

A14

35

A15

34

A16

33

BYTE

32

GND

31

I/O15

30

I/O7

29

I/O14

28

I/O6

27

I/O13

26

I/O5

25

I/O12

24

I/O4

23

VCC

Note: “•” denotes a white dot marked on the package.

The device is erased by executing the Erase command
sequence; the device internally controls the erase opera­tion. The memory is divided into four blocks for erase oper­ations. There are two 4K word parameter block sections:
the boot block, and the main memory array block. The typi­cal number of program and erase cycles is in excess of
10,000 cycles.

The optional 8K word boot block section includes a repro­gramming lockout feature to provide data integrity. This
feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in
the boot block cannot be changed when input levels of 5.5

2

AT49F008A(T)/8192A(T)

volts or less are used. The boot sector is designed to con­tain user secure code.

For the AT49F8192A(T), the BYTE

pin controls whether
the device data I/O pins operate in the byte or word config­uration. If the BYTE

pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE

If the BYTE

and OE.

pin is set at logic “0”, the device is in byte con­figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE

and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.

1199F–04/01

AT49F008A(T) Block Diagram

VCC

GND

OE

WE

CE

CONTROL

LOGIC

RESET

ADDRESS

INPUTS

Y DECODER

X DECODER

AT49F8192A(T) Block Diagram

VCC

GND

AT49F008A AT49F008AT

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

Y-GATING

MAIN MEMORY

(992K BYTES)

PARAMETER

BLOCK 2

8K BYTES

PARAMETER

BLOCK 1

8K BYTES

BOOT BLOCK

16K BYTES

AT49F8192A AT49F8192AT

DATA INPUTS/OUTPUTS

I/O0 - I/O15

AT49F008A(T)/8192A(T)

DATA INPUTS/OUTPUTS

I/O0 - I/O7

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

FFFFF FFFFF

08000

07FFF

06000

05FFF

04000

03FFF

00000 00000

DATA INPUTS/OUTPUTS

Y-GATING

BOOT BLOCK

16K BYTES

PARAMETER

BLOCK 1

8K BYTES

PARAMETER

BLOCK 2

8K BYTES

MAIN MEMORY

(992K BYTES)

I/O0 - I/O15

FC000
FBFFF

FA000
F9FFF

F8000

F7FFF

OE

WE

CE

RESET

ADDRESS

INPUTS

CONTROL

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

Y-GATING

MAIN MEMORY
(496K WORDS)

PARAMETER

BLOCK 2

4K WORDS

PARAMETER

BLOCK 1

4K WORDS

BOOT BLOCK

8K WORDS

INPUT/OUTPUT

BUFFERS

PROGRAM DATA

LATCHES

7FFFF 7FFFF

04000
03FFF

03000

02FFF

02000
01FFF

00000 00000

Y-GATING

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK 1

4K WORDS

PARAMETER

BLOCK 2

4K WORDS

MAIN MEMORY
(496K WORDS)

7E000

7DFFF

7D000

7CFFF

7C000

7BFFF

Device Operation

READ: The AT49F008A(T)/8192A(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data

stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high­impedance state whenever CE

COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending
upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are
entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care
inputs for the command codes). The command sequences are written by applying a low pulse on the WE

or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.

CE
The data is latched by the first rising edge of CE
locations used in the command sequences are not affected by entering the command sequences.

or OE is high. This dual line control gives designers flexibility in preventing bus contention.

or CE input with

or WE. Standard microprocessor write timings are used. The address

1199F–04/01

3

RESET: A RESET input pin is provided to ease some sys-

tem applications. When RESET
device is in its standard operating mode. A low level on the
RESET
the outputs of the device in a high-impedance state. When
a high level is reasserted on the RESET
returns to the read or standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).

ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of memory bits is a logic
“1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is t

If the boot block lockout has been enabled, the chip erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.

SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six-bus cycle operation. The
sector address is latched on the falling WE
sixth cycle while the 30H data input command is latched at
the rising edge of WE
rising edge of WE
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro­grammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro­grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro­grammed, the main memory block and the parameter
blocks should be erased and reprogrammed before the
boot block is erased again.

BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logic “0”) on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a four-bus
cycle operation. The device will automatically generate the
required internal program pulses.

input halts the present device operation and puts

pin, the boot block array can be repro-

. The sector erase starts after the

of the sixth cycle. The erase operation is

is at a logic high level, the

pin, the device

.

EC

edge of the

Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset
happens during programming, the data at the location
being programmed will be corrupted. Please note that a
data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is com­pleted after the specified t
feature may also be used to indicate the end of a program
cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti­vated; the boot block’s usage as a write-protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49F008A; FC000H to
FFFFFH for the AT49F008AT; 00000H to 01FFFH for the
AT49F8192A; and 7E000H to 7FFFFH for the
AT49F8192AT.

Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of

5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft­ware product identification mode (see Software Product
Identification Entry and Exit sections), a read from the
following address location will show if programming the
boot block is locked out – 00002H for the AT49F008A and
AT49F8192A; FC002H for the AT49F008AT; and 7E002H
for the AT49F8192AT. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block
cannot be programmed. The software product identification
exit code should be used to return to standard operation.

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:

The user can override the boot block programming lockout
by taking the RESET
erase, sector erase or word programming operation. When
the RESET
block programming lockout feature is again active.

PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The

pin is brought back to TTL levels, the boot

pin to 12 volts during the entire chip

cycle time. The Data Polling

BP

4

AT49F008A(T)/8192A(T)

1199F–04/01

AT49F008A(T)/8192A(T)

hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the
Atmel product.

For details, see “Operating Modes” (for hardware operation) or “Software Product Identification Entry/Exit” on page 12. The
manufacturer and device codes are the same for both modes.

DATA

POLLING: The AT49F008A(T)/8192A(T) features Data Polling to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the pro­gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector
erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true
data will be read from the device. Data

TOGGLE BIT: In addition to Data
a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.

READY/BUSY

detecting the end of a program or erase operation. RDY/BUSY
cycles and it is released at the completion of the cycle. The open-drain connection allows for OR-tying of several devices to
the same RDY/BUSY

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the
AT49F008A(T)/8192A(T) in the following ways: (a) V
ited. (b) V
cal) before programming. (c) Program inhibit: holding any one of OE
Noise filter: pulses of less than 15 ns (typical) on the WE

: For the AT49F008A(T), pin 12 is an open-drain Ready/Busy output pin, which provides another method of

line.

power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typi-

CC

Polling may begin at any time during the program cycle.

Polling, the AT49F008A(T)/8192A(T) provides another method for determining the end of

is actively pulled low during the internal program and erase

sense: if VCC is below 3.8V (typical), the program function is inhib-

CC

low, CE high or WE high inhibits program cycles. (d)

or CE inputs will not initiate a program cycle.

1199F–04/01

5