Rainbow Electronics AT49F1025 User Manual

Features

• Single-voltage Operation

–5V Read – 5V Reprogramming

• Fast Read Access Time – 35 ns

• Internal Program Control and Timer

• 8K Word Boot Block with Lockout

• Fast Erase Cycle Time – 10 seconds

• Word-by-word Programming – 10 µs/Word Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Small 10 x 14 mm VSOP Package

• Typical 10,000 Write Cycles

1-megabit (64K x 16)

Description

The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 35 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The only difference between the AT49F1024 and the AT49F1025 is the package.

To allow for simple in-system reprogrammability, the AT49F1024/1025 does not require high-input voltages for programming. Five-volt-only commands determine the

(continued)

Pin Configurations

Pin Name Function

A0 - A15 Addresses

WE Write Enable

I/O0 - I/O15 Data Inputs/Outputs

NC No Connect

I/O12

I/O11

I/O10

I/O9

I/O8

GND

I/O7

I/O6

I/O5

I/O4

Chip Enable

Output Enable

AT49F1025

PLCC Top View

I/O13

I/O14

I/O15CENCNCVCCWENC

65432

1819202122232425262728

I/O3

I/O2

I/O1

I/O0

A15

4443424140

A0A1A2A3A4

A14

39 38 37 36 35 34 33 32 31 30 29

A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5

AT49F1024 VSOP Top View

Typ e 1

10 x 14 mm

A10

A11

A12

A13

A14

A15

VCC

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

GND

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

5-volt Only Flash Memory

AT49F1024 AT49F1025

Rev. 0765I–05/01

Block Diagram

read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by erasing a block of data (entire chip or main memory block) and then programming on a word-by-word basis. The typical word programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the Data

Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.

DATA INPUTS/OUTPUTS

VCC

GND

I/O15 - I/O0

Device Operation

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

FFFFH

2000H 1FFFH

0000H

READ: The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low and WE

is high, the data stored at the memory location determined by the address pins

is asserted on the outputs. The outputs are put in the high impedance state whenever

or OE is high. This dual line control gives designers flexibility in preventing bus

CE contention.

CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command (See Command Definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE of WE

of the sixth cycle. Please see main memory erase cycle waveforms. The main

. The main memory erase starts after the rising edge

memory erase operation is internally controlled; it will automatically time to completion.

WORD PROGRAMMING: Once the memory array is erased, the device is programmed (to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a four-bus cycle

AT49F1024/1025

0765I–05/01

AT49F1024/1025

operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE Programming is completed after the specified t

cycle time. The Data Polling feature

may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write-protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method and can be erased using either the Chip Erase or the Main Memory Block Erase command. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

or CE, whichever occurs first.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections), a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

POLLING: The AT49F1024/1025 features Data Polling to indicate the end of a

DATA

program or erase cycle. During a program cycle, an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data Polling may begin at any time during the program cycle.

TOGGLE BIT: In addition to Data

Polling, the AT49F1024/1025 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

0765I–05/01

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F1024/1025 in the following ways: (a) V

sense: if VCC is below 3.8V

(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

Command Definition (in Hex)

1st Bus

Command Sequence

Read 1 Addr D

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30

Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Boot Block Lockout

Product ID Entry 3 5555 AA 2AAA 55 5555 90

Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

(3)

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex); A15 (Don’t Care).

2. The 8K word boot sector has the address range 00000H to 1FFFH.

3. Either one of the Product ID Exit commands can be used.

Bus

Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0

1xxxxF0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F1024/1025

0765I–05/01

DC and AC Operating Range

AT49F1024/1025

AT49F1024-35 AT49F1025-35

Operating Temperature (Case)

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C

Ind. -40°C - 85°C-40°C - 85°C

AT49F1024-45 AT49F1025-45 AT49F1024-50

AT49F1024-55 AT49F1025-55

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

(1)

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

(5)

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 001FH, Device Code: 0087H.

5. See details under “Software Product Identification Entry/Exit” on page 11.

Ai D

OUT

X X High-Z

X High-Z

A1 - A15 = VIL, A9 = V

A0 = VIL, A1 - A15 = V

A0 = VIH, A1 - A15 = V

(3)

, A0 = V

Manufacturer Code

Device Code

Manufacturer Code

Device Code

AT49F1024-70 AT49F1025-70

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

(1)

OH1

OH2

Note: 1. In the erase mode, I

0765I–05/01

Input Load Current VIN = 0V to V

Output Leakage Current V

= 0V to V

I/O

10.0 µA

Com. 100.0 µA

VCC Standby Current CMOS CE = VCC - 0.3V to V

VCC Standby Current TTL CE = 2.0V to V

Active Current f = 5 MHz; I

OUT

Ind. 300.0 µA

3.0 mA

= 0 mA 50.0 mA

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 2.1 mA 0.45 V

Output High Voltage IOH = -400 µA 2.4 V

Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

is 90 mA.

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