Rainbow Electronics AT49F1025 User Manual

Features

• Single-voltage Operation

–5V Read
– 5V Reprogramming

• Fast Read Access Time – 35 ns

• Internal Program Control and Timer

• 8K Word Boot Block with Lockout

• Fast Erase Cycle Time – 10 seconds

• Word-by-word Programming – 10 µs/Word Typical

• Hardware Data Protection

• Data Polling for End of Program Detection

• Small 10 x 14 mm VSOP Package

• Typical 10,000 Write Cycles

1-megabit
(64K x 16)

Description

The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash memories. Their
1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to
35 ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA. The
only difference between the AT49F1024 and the AT49F1025 is the package.

To allow for simple in-system reprogrammability, the AT49F1024/1025 does not
require high-input voltages for programming. Five-volt-only commands determine the

(continued)

Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE

OE

WE Write Enable

I/O0 - I/O15 Data Inputs/Outputs

NC No Connect

7

I/O12

8

I/O11

9

I/O10

10

I/O9

11

I/O8

12

GND

13

NC

14

I/O7

15

I/O6

16

I/O5

17

I/O4

Chip Enable

Output Enable

AT49F1025

PLCC Top View

I/O13

I/O14

I/O15CENCNCVCCWENC

65432

1819202122232425262728

I/O3

I/O2

I/O1

I/O0

1

NC

OE

A15

4443424140

A0A1A2A3A4

A14

39
38
37
36
35
34
33
32
31
30
29

A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5

AT49F1024 VSOP Top View

Typ e 1

10 x 14 mm

1

A9

2

A10

3

A11

4

A12

5

A13

6

A14

7

A15

8

NC

9

WE

10

VCC

11

NC

12

CE

13

I/O15

14

I/O14

15

I/O13

16

I/O12

17

I/O11

18

I/O10

19

I/O9

20

I/O8

GND

40

A8

39

A7

38

A6

37

A5

36

A4

35

A3

34

A2

33

A1

32

A0

31

OE

30

I/O0

29

I/O1

28

I/O2

27

I/O3

26

I/O4

25

I/O5

24

I/O6

23

I/O7

22

GND

21

5-volt Only
Flash Memory

AT49F1024
AT49F1025

Rev. 0765I–05/01

1

Block Diagram

read and programming operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block) and then programming on a
word-by-word basis. The typical word programming time is a fast 10 µs. The end of a
program cycle can be optionally detected by the Data

Polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming write lockout feature
to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is permanently protected from being erased
or reprogrammed.

DATA INPUTS/OUTPUTS

VCC

GND

I/O15 - I/O0

16

Device Operation

OE

WE

CE

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

FFFFH

2000H
1FFFH

0000H

READ: The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low
and WE

is high, the data stored at the memory location determined by the address pins

is asserted on the outputs. The outputs are put in the high impedance state whenever

or OE is high. This dual line control gives designers flexibility in preventing bus

CE
contention.

CHIP ERASE: When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE
of WE

of the sixth cycle. Please see main memory erase cycle waveforms. The main

. The main memory erase starts after the rising edge

memory erase operation is internally controlled; it will automatically time to completion.

WORD PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming
is accomplished via the internal device command register and is a four-bus cycle

2

AT49F1024/1025

0765I–05/01

AT49F1024/1025

operation (please refer to the Command Definitions table). The device will automatically
generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE
Programming is completed after the specified t

cycle time. The Data Polling feature

BP

may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write-protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro­grammed. Data in the main memory block can still be changed through the regular
programming method and can be erased using either the Chip Erase or the Main Mem­ory Block Erase command. To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be performed. Please refer to
the Command Definitions table.

or CE, whichever occurs first.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sec­tions), a read from address location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on
I/O0 is high, the program lockout feature has been activated and the block cannot be
programmed. The software product identification exit code should be used to return to
standard operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identifi­cation. The manufacturer and device code is the same for both modes.

POLLING: The AT49F1024/1025 features Data Polling to indicate the end of a

DATA

program or erase cycle. During a program cycle, an attempted read of the last byte
loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.

TOGGLE BIT: In addition to Data

Polling, the AT49F1024/1025 provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro­gram cycle.

0765I–05/01

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT49F1024/1025 in the following ways: (a) V

sense: if VCC is below 3.8V

CC

(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15
ns (typical) on the WE

or CE inputs will not initiate a program cycle.

3

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Main Memory Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 30

Word Program 4 5555 AA 2AAA 55 5555 A0 Addr D

Boot Block Lockout

Product ID Entry 3 5555 AA 2AAA 55 5555 90

Product ID Exit

Product ID Exit

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).

(3)

(3)

The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex); A15 (Don’t Care).

2. The 8K word boot sector has the address range 00000H to 1FFFH.

3. Either one of the Product ID Exit commands can be used.

Bus

Cycles

(2)

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 F0

1xxxxF0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

4

AT49F1024/1025

0765I–05/01

DC and AC Operating Range

AT49F1024/1025

AT49F1024-35
AT49F1025-35

Operating
Temperature (Case)

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

V

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C

Ind. -40°C - 85°C-40°C - 85°C

AT49F1024-45
AT49F1025-45 AT49F1024-50

AT49F1024-55
AT49F1025-55

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

V

IL

V

IH

(1)

X

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

IL

IH

Product Identification

Hardware V

Software

(5)

IL

V

IL

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 001FH, Device Code: 0087H.

5. See details under “Software Product Identification Entry/Exit” on page 11.

V

IH

V

IL

Ai D

Ai D

OUT

IN

X X High-Z

IH

X

X High-Z

V

IH

A1 - A15 = VIL, A9 = V

A1 - A15 = VIL, A9 = V

A0 = VIL, A1 - A15 = V

A0 = VIH, A1 - A15 = V

(3)

H

(3)

H

, A0 = V

, A0 = V

IL

IL

Manufacturer Code

IL

Device Code

IH

Manufacturer Code

Device Code

AT49F1024-70
AT49F1025-70

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

Note: 1. In the erase mode, I

0765I–05/01

Input Load Current VIN = 0V to V

Output Leakage Current V

= 0V to V

I/O

CC

CC

10.0 µA

10.0 µA

Com. 100.0 µA

VCC Standby Current CMOS CE = VCC - 0.3V to V

VCC Standby Current TTL CE = 2.0V to V

V

Active Current f = 5 MHz; I

CC

OUT

CC

CC

Ind. 300.0 µA

3.0 mA

= 0 mA 50.0 mA

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 2.1 mA 0.45 V

Output High Voltage IOH = -400 µA 2.4 V

Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

is 90 mA.

CC

5

AC Read Characteristics

Symbol Parameter

t

t

t

t

t

ACC

CE

OE

DF

OH

(1)

(2)

(3)(4)

Address to Output Delay 35 45 50 55 70 ns

CE to Output Delay 3545505570ns

OE to Output Delay025030303035ns

CE or OE to Output Float 0 25 0 25 25 0 25 0 25 ns

Output Hold from OE,
CE

or Address,

whichever occurred first

AC Read Waveforms

AT49F1024-35
AT49F1025-35

00000ns

AT49F1024-45
AT49F1025-45 AT49F1024-50

AT49F1024-55
AT49F1025-55

AT49F1024-70
AT49F1025-70

UnitsMin Max Min Max Min Max Min Max Min Max

(1)(2)(3)(4)

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t

without impact on t

is specified from OE or CE, whichever occurs first (CL = 5 pF).

3. t

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

- tCE after the address transition without impact on t

ACC

ACC

.

- tOE after an address change

ACC

6

AT49F1024/1025

0765I–05/01

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

5.0V

1.8K
OUTPUT

PIN

1.3K

30 pF

AT49F1024/1025

Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

(1)

46pFV

812pFV

IN

OUT

= 0V

= 0V

0765I–05/01

7

AC Word Load Characteristics

Symbol Parameter Min Max Units

tAS, t

t

AH

t

CS

t

CH

t

WP

t

DS

tDH, t

t

WPH

OES

OEH

Address, OE Setup Time 0 ns

Address Hold Time 50 ns

Chip Select Setup Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE)50ns

Data Setup Time 50 ns

Data, OE Hold Time 0 ns

Write Pulse Width High 40 ns

AC Word Load Waveforms

WE Controlled

CE

Controlled

OE

ADDRESS

CE

WE

DATA IN

OE

ADDRESS

WE

t

OES

t

t

t

OES

t

AS

CS

AS

t

OEH

t

AH

t

WP

t

DS

t

AH

t

CH

t

OEH

t

CH

t

WPH

t

DH

t

CS

CE

t

WPH

t

WP

t

DS

t

DH

DATA IN

8

AT49F1024/1025

0765I–05/01

AT49F1024/1025

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

t

BP

t

AS

t

AH

t

DS

t

DH

t

WP

t

WPH

t

EC

Program Cycle Waveforms

Word Programming Time 10 50 µs

Address Setup Time 0 ns

Address Hold Time 50 ns

Data Setup Time 50 ns

Data Hold Time 0 ns

Write Pulse Width 50 ns

Write Pulse Width High 40 ns

Erase Cycle Time 3 seconds

A0-A15

Main Memory or Chip Erase Cycle Waveforms

OE

CE

t

WP

WE

A0-A15

DATA

t

AS

5555

t

AH

AA

WORD 0

t

DH

2AAA 2AAA

t

DS

55 55

WORD 1 WORD 2

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 10H. For a main memory erase, the data should be 30H.

t

5555

WPH

5555

80

AA

WORD 3

WORD 4

5555

NOTE 2

WORD 5

t

EC

0765I–05/01

9

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

spec in “AC Read Characteristics” on page 6.

OE

Data Polling Waveforms

ns

Toggle Bit Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 10 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

OE High Pulse 150 ns

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

Toggle Bit Waveforms

spec in “AC Read Characteristics” on page 6.

OE

(1)(2)(3)

ns

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

10

AT49F1024/1025

specification must be met by the toggling

OEHP

0765I–05/01

AT49F1024/1025

Software Product Identification Entry

Software Product Identification Exit

LOAD DATA AA

TO

ADDRESS 5555

(1)

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 90

TO

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

(2)(3)(5)

MODE

OR

LOAD DATA F0

TO

ANY ADDRESS

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA F0

TO

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). Address Format: A15 - A0 (Hex); A15 (Don’t Care).

2. A1 - A15 = V

Manufacturer Code is read for A0 = V
Device Code is read for A0 = VIH.

.

IL

.

IL

3. The device does not remain in identification mode if powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 001FH

Device Code: 0087H

0765I–05/01

11

Boot Block Lockout Enable Algorithm

ADDRESS 2AAA

ADDRESS 2AAA

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

LOAD DATA 40

TO

ADDRESS 5555

PAUSE 1 second

(2)

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). Address Format: A15 - A0 (Hex); A15 (Don’t Care).

2. Boot Block Lockout feature enabled.

12

AT49F1024/1025

0765I–05/01

AT49F1024/1025

AT49F1024 Ordering Information

I

(mA)

t

ACC

(ns)

35 50 0.1 AT49F1024-35VC 40V Commercial

45 50 0.1 AT49F1024-45VC 40V Commercial

50 50 0.1 AT49F1024-50VC 40V Commercial

55 50 0.1 AT49F1024-55VC 40V Commercial

70 50 0.1 AT49F1024-70VC 40V Commercial

CC

Ordering Code Package Operation RangeActive Standby

(0° to 70°C)

(0° to 70°C)

(0° to 70°C)

(0° to 70°C)

50 0.3 AT49F1024-55VI 40V Industrial

(-40° to 85°C)

(0° to 70°C)

50 0.3 AT49F1024-70VI 40V Industrial

(-40° to 85°C)

AT49F1025 Ordering Information

I

(mA)

t

ACC

(ns)

35 50 0.1 AT49F1025-35JC 44J Commercial

45 50 0.1 AT49F1025-45JC 44J Commercial

55 50 0.1 AT49F1025-55JC 44J Commercial

70 50 0.1 AT49F1025-70JC 44J Commercial

CC

Ordering Code Package Operation RangeActive Standby

(0° to 70°C)

(0° to 70°C)

(0° to 70°C)

50 0.3 AT49F1025-55JI 44J Industrial

(-40° to 85°C)

(0° to 70°C)

50 0.3 AT49F1025-70JI 44J Industrial

(-40° to 85°C)

Package Type

44J 44-lead, Plastic J-leaded Chip Carrier Package (PLCC)

40V 40-lead, 10 mm x 14 mm, Thin Small Outline Package (VSOP)

0765I–05/01

13

Packaging Information

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AC

.045(1.14) X 45°

.032(.813)
.026(.660)

.050(1.27) TYP

PIN NO. 1
IDENTIFY

.045(1.14) X 30° - 45°

.656(16.7)

SQ

.650(16.5)

.695(17.7)
.685(17.4)

.500(12.7) REF SQ

.022(.559) X 45° MAX (3X)

SQ

.012(.305)
.008(.203)

.630(16.0)
.590(15.0)

.021(.533)
.013(.330)

.043(1.09)
.020(.508)

.120(3.05)

.090(2.29)
.180(4.57)
.165(4.19)

40V, 40-lead, Plastic Thin Small Outline
Package (VSOP)
Dimensions in Millimeters and (Inches)*

*Controlling dimension: millimeters

14

AT49F1024/1025

0765I–05/01

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Fax-on-Demand

North America:

e-mail

[e-mail]

1-[phone]

International:
1-[phone]

Web Site

http://www.atmel.com

BBS

1-[phone]

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
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Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0765I–05/01/xM