Rainbow Electronics AT49BV512 User Manual

Features

• Single Supply Voltage Range, 2.7V to 3.6V

• Single Supply for Read and Write

• Fast Read Access Time – 70 ns

• Internal Program Control and Timer

• 8K Bytes Boot Block with Lockout

• Fast Erase Cycle Time – 10 Seconds

• Byte-by-Byte Programming – 30 µs/Byte Typical

• Hardware Data Protection

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 25mAActiveCurrent
– 50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 70 ns with power dissipation of just 90 mW over the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50 µA.

To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing

512K (64K x 8)
Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV5 12

™

Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

VSOP Top View (8 x 14 mm) or

TSOPTopView(8x20mm)

A11

A9

A8
A13
A14

NC

WE

VCC

NC

NC
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Chip Enable

Output Enable

Write Enable

Type 1

DIP Top View

1

A15
A12

I/O0
I/O1
I/O2

GND

NC

2

NC

3
4
5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13
14
15
16

VCC

32

WE

31

NC

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

I/O7

21

I/O6

20

I/O5

19

I/O4

18

I/O3

17

PLCC Top View

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

I/O0

A7
A6
A5
A4
A3
A2
A1
A0

A12

A15NCNC

432

5
6
7
8
9
10
11
12
13

1

14151617181920

I/O1

I/O2

I/O3

GND

VCCWENC

323130

I/O4

I/O5

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

Rev. 1026E–FLASH–06/02

1

Block Diagram

the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typ­ical byte programming time is a fast 30 µs. The end of a program cycle can be optionally
detected by the DATA

polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a reprogramming write lock out fea­ture to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
reprogrammed.

DATA INPUTS/OUTPUTS

VCC

GND

I/O0 - I/O7

Device Operation

OE

WE

CE

ADDRESS

INPUTS

OE, CE AND WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K BYTES)

OPTIONAL BOOT

BLOCK (8K BYTES)

FFFFH

2000H
1FFFH

0000H

READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and
WE

is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.

ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K
bytes if the boot block featured is used) must be erased. The erased state of the mem­orybitsisalogical“1”. The entire device can be erased at one time by using a 6-byte
software code. The software chip erase code consists of 6-byte load commands to spe­cific address locations with a specific data pattern (please refer to the Chip Erase Cycle
Waveforms).

After the software chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time needed to erase
the whole chip is t

. If the boot block lockout feature has been enabled, the data in the

EC

boot sector will not be erased.

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be pro­grammed back to a “1”; only erase operations can convert “0”sto“1”s. Programming is
accomplished via the internal device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The device will automatically generate
the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE
occurs last, and the data latched on the rising edge of WE
Programming is completed after the specified t

cycle time. The DATA polling feature

BP

or CE, whichever occurs first.

or CE, whichever

may also be used to indicate the end of a program cycle.

2

AT49BV512

1026E–FLASH–06/02

AT49BV512

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block

that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
bytes. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro­grammed. Data in the main memory block can still be changed through the regular
programming method. To activate the lockout feature, a series of six program com­mands to specific addresses with specific data must be performed. Please refer to the
Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from address location 00002H will show if programming the boot block is locked
out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and the block cannot be pro­grammed. The software product identification code should be used to return to standard
operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identifi­cation. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT49BV512 features DATA

polling to indicate the end of a pro­gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com­pleted, true data is valid on all outputs and the next cycle may begin. DATA

polling may

begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA

polling the AT49BV512 provides another method for
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT49BV512 in the following ways: (a) V

sense: if VCCis below 1.8V

CC

(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

1026E–FLASH–06/02

INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE
affecting the operation of the device. The I/O lines can only be driven from 0 to V

,CEand WE) may be driven from 0 to 5.5V without adversely

CC

0.6V.

+

3

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Byte
Program

Boot Block
Lockout

Product ID
Entry

Product ID
Exit

Product ID
Exit

Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.

(1)

(2)

(2)

2. Either one of the Product ID exit commands can be used.

Bus

Cycles

4 5555 AA 2AAA 55 5555 A0 Addr D

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 90

3 5555 AA 2AAA 55 5555 F0

1 XXXX F0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias ............................... -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

4

AT49BV512

1026E–FLASH–06/02

DC and AC Operating Range

AT49BV512

AT49BV512-70 AT49BV512-90 AT49BV512-12 AT49BV512-15

Operating
Temperature (Case)

V

Power Supply 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V

CC

Com. 0°C-70°C0°C-70°C0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C-40°C-85°C-40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

V

IL

V

IH

(1)

X

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

IL

IH

Product Identification

Hardware V

Software

(5)

IL

V

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1FH, Device Code: 03H.

5. See details under Software Product Identification Entry/Exit.

V

IH

V

IL

Ai D

Ai D

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A15 = VIL,A9=VH,

A1 - A15 = VIL,A9=VH,

A0 = VIL,A1-A15=V

A0 = VIH,A1-A15=V

(3)

,A0=V

(3)

,A0=V

IL

IL

Manufacturer Code

IL

Device Code

IH

Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

V

IL

V

IH

V

OL

V

OH

Note: 1. In the erase mode, I

1026E–FLASH–06/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

CC

= 0 mA 25 mA

OUT

CC

10 µA

10 µA

50 µA

1mA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-100µA;VCC=3.0V 2.4 V

is 50 mA.

CC

5

AC Read Characteristics

AT49BV512-70 AT49BV512-90 AT49BV512-12 AT49BV512-15

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)

(2)

(3, 4 )

Address to Output Delay 70 90 120 150 ns

CE to Output Delay 70 90 120 150 ns

OE to Output Delay 0 35 40 50 0 70 ns

CE or OE to Output Float 0 25 0 25 0 30 0 40 ns

Output Hold from OE,CEor
Address, whichever occurred first

AC Read Waveforms

(1)(2)(3)(4)

ADDRESS

OUTPUT

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL - 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

CE

OE

ACC-tCE

UnitsMin Max Min Max Min Max Min Max

0000ns

ADDRESS VALID

tCE

ACC

.

tDF

ACC-tOE

after an address change

tACC

HIGH Z

tOH

OUTPUT VALID

after the address transition without impact on t

6

AT49BV512

1026E–FLASH–06/02

Input Test Waveforms and Measurement Level

Output Test Load

Pin Capacitance

f=1MHz,T=25°C

(1)

AC

DRIVING

LEVELS

tR, tF < 5 ns

2.4V

0.4V

1.8K

1.3K

1.5V

3.0V

AT49BV512

AC

MEASUREMENT

LEVEL

OUTPUT

PIN

100 pF

Symbol Typ Max Units Conditions

C

IN

C

OUT

Note: 1. This parameter is characterized and is not 100% tested.

46pFV

812pFV

IN

OUT

=0V

=0V

1026E–FLASH–06/02

7

AC Byte Load Characteristics

Symbol Parameter Min Max Units

t

AS,tOES

t

AH

t

CS

t

CH

t

WP

t

DS

t

DH,tOEH

t

WPH

Address, OE Set-up Time 0 ns

Address Hold Time 100 ns

Chip Select Set-up Time 0 ns

Chip Select Hold Time 0 ns

Write Pulse Width (WE or CE) 200 ns

Data Set-up Time 100 ns

Data, OE Hold Time 0 ns

Write Pulse Width High 200 ns

AC Byte Load Waveforms

WE Controlled

OE

ADDRESS

CE

tAS

tCS

tOES

tAH

tOEH

tCH

Controlled

CE

WE

DATA IN

OE

ADDRESS

WE

CE

DATA IN

tAS

tCS

tWP tWPH

tDS tDH

tOES

tAH

tWP tWPH

tDS tDH

tOEH

tCH

8

AT49BV512

1026E–FLASH–06/02

AT49BV512

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

t

BP

t

AS

t

AH

t

DS

t

DH

t

WP

t

WPH

t

EC

Byte Programming Time 30 µs

Address Set-up Time 0 ns

Address Hold Time 100 ns

Data Set-up Time 100 ns

Data Hold Time 0 ns

Write Pulse Width 200 ns

Write Pulse Width High 200 ns

Erase Cycle Time 10 seconds

Program Cycle Waveforms

OE

CE

WE

tAS

A0-A15

5555 2AAA 5555

tWP

tAH

PROGRAM CYCLE

tWPH

tDH

ADDRESS

tBP

tDS

DATA

AA 55 A0

Chip Erase Cycle Waveforms

OE

CE

tWP

WE

tAS

A0-A15

DATA

5555 2AAA 5555

Note: OE must be high only when WE and CE are both low.

tAH

tDS

AA 55 80

BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5

tWPH

tDH

INPUT

DATA

5555

2AAA 5555

AA 55 10

tEC

1026E–FLASH–06/02

9

Data Polling Characteristics

(1)

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

WR

Data Hold Time 0 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

spec in AC Read Characteristics.

OE

Data Polling Waveforms

WE

CE

tOEH

OE

tDH

I/O7

A0-A15

Toggle Bit Characteristics

(1)

tOE

An

ns

tWR

An An AnAn

Symbol Parameter Min Typ Max Units

t

DH

t

OEH

t

OE

t

OEHP

t

WR

Data Hold Time 0 ns

OE Hold Time 10 ns

OE to Output Delay

(2)

OE High Pulse 150 ns

Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t

Toggle Bit Waveforms

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t

spec in AC Read Characteristics.

OE

(1)(2)(3)

WE

CE

tOEH

OE

tDH

I/O6

tOEHP

tOE

HIGH Z

tWR

specification must be met by the toggling

OEHP

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

ns

10

AT49BV512

1026E–FLASH–06/02

AT49BV512

Software Product
Identification Entry

LOAD DATA AA

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA 90

ADDRESS 5555

ENTER PRODUCT

IDENTIFICATION

MODE

Software Product
Identification Exit

(1)

(1)

TO

TO

TO

(2)(3)(5)

Boot Block Lockout Feature
Enable Algorithm

(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA F0

TO

ADDRESS 5555

EXIT PRODUCT

IDENTIFICATION

MODE

(4)

OR

LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A15 = V

.

IL

Manufacture Code is read for A0 = V
Device Code is read for A0 = V

3. The device does note remain in identification mode if
powered down.

4. The device returns to standard operation mode.

5. Manufacturers Code: 1FH
Device Code: 03H.

TO

MODE

.

IH

LOAD DATA 40

TO

ADDRESS 5555

(4)

PAUSE 1 second

(2)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Boot block lockout feature enabled.

;

IL

1026E–FLASH–06/02

11

(mA)

(1)

Ordering Code Package Operation RangeActive Standby

AT49BV512-70PC
AT49BV512-70TC
AT49BV512-70VC

AT49BV512-70PI
AT49BV512-70TI
AT49BV512-70VI

AT49BV512-90PC
AT49BV512-90TC
AT49BV512-90VC

AT49BV512-90PI
AT49BV512-90TI
AT49BV512-90VI

AT49BV512-12PC
AT49BV512-12TC
AT49BV512-12VC

AT49BV512-12PI
AT49BV512-12TI
AT49BV512-12VI

AT49BV512-15PC
AT49BV512-15TC
AT49BV512-15VC

AT49BV512-15PI
AT49BV512-15TI
AT49BV512-15VI

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

32J
32P6
32T
32V

Commercial

(0°C-70°C)

Industrial

(-40°C-85°C)

Commercial
(0°C-70°C)

Industrial

(-40°C-85°C)

Commercial
(0°C-70°C)

Industrial

(-40°C-85°C)

Commercial
(0°C-70°C)

Industrial

(-40°C-85°C)

Ordering Information

I

t

ACC

(ns)

70 25 0.05 AT49BV512-70JC

90 25 0.05 AT49BV512-90JC

120 25 0.05 AT49BV512-12JC

150 25 0.05 AT49BV512-15JC

Note: 1. The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices

with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring boot block protection to be in the
higher address range should contact Atmel.

CC

25 0.05 AT49BV512-70JI

25 0.05 AT49BV512-90JI

25 0.05 AT49BV512-12JI

25 0.05 AT49BV512-15JI

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)

12

AT49BV512

1026E–FLASH–06/02

Packaging Information

32J–PLCC

AT49BV512

1.14(0.045) X 45˚

B

e

0.51(0.020)MAX

45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1

IDENTIFIER

D1

D

D2

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

E2

B1

A2

A1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 3.175 – 3.556

A1 1.524 – 2.413

A2 0.381 – –

D 12.319 – 12.573

D1 11.354 – 11.506 Note 2

D2 9.906 – 10.922

E 14.859 – 15.113

E1 13.894 – 14.046 Note 2

E2 12.471 – 13.487

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

MIN

NOM

MAX

NOTE

10/04/01

2325 Orchard Parkway

R

San Jose, CA 95131

1026E–FLASH–06/02

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

32J

REV.

B

13

32P6–PDIP

PIN

1

E1

A1

B

REF

E

B1

C

L

SEATING PLANE

A

D

e

0º ~ 15º

eB

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 4.826

A1 0.381 – –

D 41.783 – 42.291 Note 1

E 15.240 – 15.875

E1 13.462 – 13.970 Note 1

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

MIN

NOM

MAX

DRAWING NO.

32P6

NOTE

09/28/01

REV.

B

14

AT49BV512

1026E–FLASH–06/02

32T – TSOP

AT49BV512

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

SYMBOL

A ––1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

c

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

2325 Orchard Parkway

R

San Jose, CA 95131

1026E–FLASH–06/02

TITLE

32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

32T

10/18/01

REV.

B

15

32V – VSOP

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

SEATING PLANE

A1

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 8º

L

SYMBOL

A ––1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 13.80 14.00 14.20

D1 12.30 12.40 12.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

c

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

16

2325 Orchard Parkway

R

San Jose, CA 95131

AT49BV512

TITLE

32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline

Package, Type I (VSOP)

DRAWING NO.

32V

1026E–FLASH–06/02

10/18/01

REV.

B

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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
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AT ME L®is the registered trademark of Atmel. Battery-Voltage™is the trademark of Atmel.

Other terms and product names may be the trademarks of others.

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1026E–FLASH–06/02 xM