Rainbow Electronics AT49BV512 User Manual

Features

• Single Supply Voltage Range, 2.7V to 3.6V

• Single Supply for Read and Write

• Fast Read Access Time – 70 ns

• Internal Program Control and Timer

• 8K Bytes Boot Block with Lockout

• Fast Erase Cycle Time – 10 Seconds

• Byte-by-Byte Programming – 30 µs/Byte Typical

• Hardware Data Protection

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 25mAActiveCurrent
– 50 µA CMOS Standby Current

• Typical 10,000 Write Cycles

Description

The AT49BV512 is a 3-volt only, 512K Flash memories organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 70 ns with power dissipation of just 90 mW over the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50 µA.

To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing

512K (64K x 8)
Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV5 12

™

Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

VSOP Top View (8 x 14 mm) or

TSOPTopView(8x20mm)

A11

A9

A8
A13
A14

NC

WE

VCC

NC

NC
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Chip Enable

Output Enable

Write Enable

Type 1

DIP Top View

1

A15
A12

I/O0
I/O1
I/O2

GND

NC

2

NC

3
4
5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13
14
15
16

VCC

32

WE

31

NC

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

I/O7

21

I/O6

20

I/O5

19

I/O4

18

I/O3

17

PLCC Top View

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

I/O0

A7
A6
A5
A4
A3
A2
A1
A0

A12

A15NCNC

432

5
6
7
8
9
10
11
12
13

1

14151617181920

I/O1

I/O2

I/O3

GND

VCCWENC

323130

I/O4

I/O5

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

Rev. 1026E–FLASH–06/02

1

Block Diagram

the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typ­ical byte programming time is a fast 30 µs. The end of a program cycle can be optionally
detected by the DATA

polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a reprogramming write lock out fea­ture to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
reprogrammed.

DATA INPUTS/OUTPUTS

VCC

GND

I/O0 - I/O7

Device Operation

OE

WE

CE

ADDRESS

INPUTS

OE, CE AND WE

LOGIC

Y DECODER

X DECODER

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K BYTES)

OPTIONAL BOOT

BLOCK (8K BYTES)

FFFFH

2000H
1FFFH

0000H

READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and
WE

is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.

ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K
bytes if the boot block featured is used) must be erased. The erased state of the mem­orybitsisalogical“1”. The entire device can be erased at one time by using a 6-byte
software code. The software chip erase code consists of 6-byte load commands to spe­cific address locations with a specific data pattern (please refer to the Chip Erase Cycle
Waveforms).

After the software chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time needed to erase
the whole chip is t

. If the boot block lockout feature has been enabled, the data in the

EC

boot sector will not be erased.

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be pro­grammed back to a “1”; only erase operations can convert “0”sto“1”s. Programming is
accomplished via the internal device command register and is a 4 bus cycle operation
(please refer to the Command Definitions table). The device will automatically generate
the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE
occurs last, and the data latched on the rising edge of WE
Programming is completed after the specified t

cycle time. The DATA polling feature

BP

or CE, whichever occurs first.

or CE, whichever

may also be used to indicate the end of a program cycle.

2

AT49BV512

1026E–FLASH–06/02

AT49BV512

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block

that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
bytes. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or pro­grammed. Data in the main memory block can still be changed through the regular
programming method. To activate the lockout feature, a series of six program com­mands to specific addresses with specific data must be performed. Please refer to the
Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from address location 00002H will show if programming the boot block is locked
out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and the block cannot be pro­grammed. The software product identification code should be used to return to standard
operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identifi­cation. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT49BV512 features DATA

polling to indicate the end of a pro­gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com­pleted, true data is valid on all outputs and the next cycle may begin. DATA

polling may

begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA

polling the AT49BV512 provides another method for
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT49BV512 in the following ways: (a) V

sense: if VCCis below 1.8V

CC

(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE

or CE inputs will not initiate a program cycle.

1026E–FLASH–06/02

INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE
affecting the operation of the device. The I/O lines can only be driven from 0 to V

,CEand WE) may be driven from 0 to 5.5V without adversely

CC

0.6V.

+

3

Command Definition (in Hex)

1st Bus

Command
Sequence

Read 1 Addr D

Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Byte
Program

Boot Block
Lockout

Product ID
Entry

Product ID
Exit

Product ID
Exit

Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.

(1)

(2)

(2)

2. Either one of the Product ID exit commands can be used.

Bus

Cycles

4 5555 AA 2AAA 55 5555 A0 Addr D

6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

3 5555 AA 2AAA 55 5555 90

3 5555 AA 2AAA 55 5555 F0

1 XXXX F0

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

OUT

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

IN

6th Bus

Cycle

Absolute Maximum Ratings*

Temperature Under Bias ............................... -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

4

AT49BV512

1026E–FLASH–06/02

DC and AC Operating Range

AT49BV512

AT49BV512-70 AT49BV512-90 AT49BV512-12 AT49BV512-15

Operating
Temperature (Case)

V

Power Supply 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V 2.7V to 3.6V

CC

Com. 0°C-70°C0°C-70°C0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C-40°C-85°C-40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

V

IL

V

IH

(1)

X

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

IL

IH

Product Identification

Hardware V

Software

(5)

IL

V

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1FH, Device Code: 03H.

5. See details under Software Product Identification Entry/Exit.

V

IH

V

IL

Ai D

Ai D

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A15 = VIL,A9=VH,

A1 - A15 = VIL,A9=VH,

A0 = VIL,A1-A15=V

A0 = VIH,A1-A15=V

(3)

,A0=V

(3)

,A0=V

IL

IL

Manufacturer Code

IL

Device Code

IH

Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

(1)

I

CC

V

IL

V

IH

V

OL

V

OH

Note: 1. In the erase mode, I

1026E–FLASH–06/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

CC

= 0 mA 25 mA

OUT

CC

10 µA

10 µA

50 µA

1mA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-100µA;VCC=3.0V 2.4 V

is 50 mA.

CC

5

AC Read Characteristics

AT49BV512-70 AT49BV512-90 AT49BV512-12 AT49BV512-15

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)

(2)

(3, 4 )

Address to Output Delay 70 90 120 150 ns

CE to Output Delay 70 90 120 150 ns

OE to Output Delay 0 35 40 50 0 70 ns

CE or OE to Output Float 0 25 0 25 0 30 0 40 ns

Output Hold from OE,CEor
Address, whichever occurred first

AC Read Waveforms

(1)(2)(3)(4)

ADDRESS

OUTPUT

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL - 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

CE

OE

ACC-tCE

UnitsMin Max Min Max Min Max Min Max

0000ns

ADDRESS VALID

tCE

ACC

.

tDF

ACC-tOE

after an address change

tACC

HIGH Z

tOH

OUTPUT VALID

after the address transition without impact on t

6

AT49BV512

1026E–FLASH–06/02