The QuickMIPS™ Embedded Standard Products
(ESPs) family provides an out-of-the box solution
consisting of the QL901M QuickMIPS chip and
the QuickMIPS development environment. The
development environment includes a Reference
Design Kit (RDK) with drivers, real-time
operating systems, and QuickMIPS system
model. With the RDK, software and hardware
engineers can evaluate, debug, and emulate
their system in parallel.
CPU
• High-performance MIPS 4Kc processor runs
up to 133 MHz in .25µ
(173 Dhrystone MIPS)
• 1.3 Dhrystone MIPS per MHz
• MDU supports MAC instructions for
DSP functions
• 16 Kbytes of Instruction Cache
(4-way set associative)
• 16 Kbytes of Data Cache (4-way set
associative) with lockout capability per line
• 16 Kbytes of on-chip, high-speed SRAM for
use by multiple AHB Bus Masters
• 32-bit 66/33 MHz PCI Host and Satellite
(Master/Target) operation with DMA
channels and FIFO for full bandwidth
• Two MAC10/100s with MII ports connect
easily to external transceivers/PHY devices
• One AHB 32-bit master port/one AHB
32-bit slave port to Programmable Fabric
• Global System Configuration and Interrupt
Controller
Peripheral Bus (AMBA APB)
• 32-bit APB runs at half the CPU clock
frequency (the same as the AHB clock)
• Three APB slave ports in the programmable
fabric
• Two serial ports (one with Modem control
signals and one with IRDA-compliant signals)
• Four general-purpose 32-bit timer/counters
on one APB port
16 Kbytes
SRAM
MIPS 4Kc
w/Caches
32-bit PCI
66/33 MHz
Ethernet
10/100 MAC
Ethernet
10/100 MAC
Memory
Controller
Interrupt
Controller
High-Perf ormance Bus (AMBA AHB)
• High-performance 32-bit AMBA AHB bus
standard for high-speed system bus running
at half the CPU clock
• High-bandwidth memory controller for
SDRAM, SRAM, and EPROM
• SDRAM support for standard SDRAMs up to
256 MBytes with auto refresh, up to 4 banks
non-interleaved
• Support for PC100 type memories with up
to two chip enables
• EPROM controller for boot code
• 8-bit, 16-bit, and 32-bit device width support
QL901M QuickMIPSTM Data Sheet Rev B
ECI to AHB
32-bit Advanced High-Performance Bus
AHB to APB
3 APB
Slave
I/F
1 AHB
Master I/F
1 AHB
Slave I/F
Two 16550
UARTs
32-bit Advanced Peripheral Bus
36 RAM Blocks (Configurations 128x18; 256x9; 512x4; or 1024x2)
Via-Link Programmable Fabric
18 ECU Blocks-- 8x8 Multiply, 16-bit carry/add
Four 32-bit
Timer/Counters
Configurable
Logic Analyzer
Monitor (CLAM)
Figure 1: Embedded QuickMIPS Block Diagram
JTAG
•
•
1
•
•
•
•
Programmable Via-Link Fabric
• Embedded memory configurable as RAM or FIFO
• 252 programmable I/Os
• High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with
3-bit instructions
• Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3
Table 1: Programmable Fabric F eatures
Maximum System Gates*
536,47272x282,0164,7883682,94418
* 75K ASIC gates
Logic Arrays
Columns x Rows
Logic Cells
** Possible Configurations:
128x18, 256x9, 512x4, or 1024x2
Maximum
Flip-Flops
RAM Blocks** RAM Bits ECU Blocks***
*** 8x8 Multiply ,
16-bit carry-add
On-Chip Debug Blocks
• On-chip instrumentation blocks for debug and trace capabilities
• Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look
at selected signals from IP function in fabric
Development and Programming
• Complete QuickLogic software suite of development tools enables rapid implementation of IP
functions for complete SOC solution
• Complete chip simulation of user-defined programmable-logic IP functions with the processor,
caches, memory, and all hardwired functions on-chip
• Synthesis of IP functions into the programmable fabric
• Place-and-Route tool for efficient implementation of IP functions in the programmable fabric
• Extensive timing analysis of IP functions with the rest of the chip to ensure full chip functionality
• Programming and debug support of the entire chip through JTAG port
• Integrated debug support for the MIPS 4Kc processor
• MIPS Language and Debug tool support for the MIPS 4Kc processor from approved third party
MIPS vendors
• ECU support for a variety of DSP algorithms and functions
• QuickLogic library of standard IP functions for plug-and-play implementation of standard IP functions
in the programmable fabric for a complete SOC solution
• QuickMIPS Reference Design Kit (RDK) provides a complete Board Support Package for
• QuickWorks, the complete product suite, supports Windows 95/98/NT/2000. It includes SpDE
(layout including place & route, timing analysis, and back-annotation), Synplify-Lite (synthesis), Turbo
Writer (HDL-enhanced text editor), etc.
• QuickTool supports Solaris. It has only the layout software (SpDE).
• QuickMIPS simulation is enabled through either:
• a SmartModel (VMC-generated model, encrypted RTL, relatively slow). This option supports both
Verilog and VHDL.
• SaiLAhead co-verification platform from Saivision (very fast C model). This option only supports
Verilog (no VHDL) at this time.
Table 2: Design Tools Platform Support
SolarisWindows NTWindows 2000Linux
SynthesisSynplify-Lite X (in QuickWorks) X (in Qui ckW orks)
LayoutSpDEX (in QuickTool) X (in QuickWorks) X (in QuickWorks)
SmartModel
Simulation
SaiLAhead
ModelSim/VCSXX
Verilog XL/NCX
ModelSimXXX
Verilog XL/NCXX
SaiLAhead Platform
The “SaiLAhead for QuickMIPS” co-verification platform is tailored for QuickMIPS devices. It enables
simulation of user-defined logic functions that are to be implemented in the QuickMIPS programmable
fabric with the rest of the QuickMIPS fixed system logic functions, which verifies overall QuickMIPS
functionality. Simultaneously, the SaiLAhead platform has a powerful, feature-rich debugger, which
enables QuickMIPS users to develop and debug their application code (C and MIPS assembly). The
SaiLAhead platform accelerates the speed of simulation of the QuickMIPS device in a simulator such as
NC-Verilog by using C models for various fixed system logic functions in the QuickMIPS device. This
platform also provides a standalone C environment offering additional speed-up of simulation of the
entire QuickMIPS design. Please refer to
SaiLAhead platform.
http://www.saivision.com for more information on the
QL901M QuickMIPS™ Data Sheet Rev B
•
3
•
•
•
•
•
2.0 Embedded Computational Units (ECUs)
Traditional programmable logic architectures do not implement arithmetic functions efficiently or
effectively. These functions require high logic cell usage while garnering only moderate performance
results. By embedding a dynamically reconfigurable computational unit, the QuickMIPS chip can address
various arithmetic functions efficiently and effectively providing for a robust DSP platform. This
approach offers greater performance than traditional programmable logic implementations. The ECU
block is ideal for complex DSP, filtering, and algorithmic functions. The QuickMIPS architecture allows
functionality above and beyond that achievable using DSP processors or programmable logic devices.
The embedded block is implemented at the transistor level with the following block diagram in
Figure 2.
Abus
Xbus
Ybus
I bus
Sign
Multiply
Sequencer
AddRegister
Logic CellMemory
16
8
8
3
2
1
17
Rbus
Figure 2: Embedded Computational Unit (ECU) Block Diagram
Table 3: ECU Comparisons
FunctionDescription
16 bit8 ns2.5 ns
Adder
Multiplier
System Clock200 MHz400 MHz
32 bit10 ns5.6 ns
64 bit12 ns6.7 ns
8 x 810 ns4.3 ns
16 x 1612ns6.7 ns
Slowest Speed
Grade
Fastest Speed Grade
Implementation of the equivalent ECU block as HDL in a programmable logic architecture requires 205
logic cells with a 10 ns delay in a -4 speed grade. There are a maximum of 18 ECU blocks and a
minimum of 10 ECU blocks in the QuickMIPS chip. The ECU blocks are placed next to the RAM
circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.
Eighteen 8-bit Multiply Accumulate functions can be implemented per cycle for a total of 2.6 billion
MACs/s when clocked at 144 MHz. Further Multiply Accumulate functions also can be implemented in
the programmable logic.
The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 4.
The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.
The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an
external software driven algorithm, or an internal state machine. This flexibility allows the designer to
reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock
cycle, such as adaptive filtering.
3.0 Design Flow
The QuickMIPS design flow, similar to ASIC design flow, is shown in Figure 3.
MIPS ProgrammingSystem ConfigurationCustomer IP Design in FPGA
A typical design process goes through the flow shown above. After passing postlayout simulation,
QuickMIPS devices can be programmed for testing on the hardware testbench. Because QuickLogic
devices are One-Time-Programmable (OTP), it is recommended that these devices are programmed only
after they pass postlayout simulation to minimize development cost and reduce bench debugging time.
The QuickMIPS design flow is supported by QuickLogic's QuickWorks™ (for Microsoft Windows) and
QuickTool™ (for UNIX) design software suites version 9.2 and up. Many third-party synthesis and
simulation tools are also supported. The QuickWorks software suite can be downloaded from
QuickLogic's Web site
(www.quicklogic.com). Please contact a QuickLogic sales representative to
obtain a license or get QuickTool software.
Both Verilog and VHDL design methodologies are fully supported. The flow described below assumes
that the QuickWorks or QuickTool 9.2 software has been installed.
3.1 Simulation
QuickLogic provides the system simulation environment. This environment includes the QuickMIPS
VMC model, ROM and RAM models, reset and clock generation, boot code, and sample programs (read
and write to memory). This environment allows customers to focus on their RTL code and not have to
worry about bringing up the system simulation environment.
The simulation behavior of the QuickMIPS ESP core is provided by the VMC model. VMC (Verilog
Model Compiler) is a tool from Synopsys that compiles Verilog RTL (Register-Transfer-Level) code into
binary code. A VMC model (the binary code) implements the same logic functions as the RTL code while
providing IP protection. In simulation, it communicates to the simulator via PLI (Programmable
Language Interface) for Verilog or FLI (Foreign Language Interface) for VHDL.
Because of the VMC model, the Silos III Verilog simulator and Active-HDL VHDL simulator bundled in
QuickWorks are not supported in QuickMIPS simulation flow. A third-party simulator must be used. The
currently supported simulators include:
Layout is performed in SpDE, which is the QuickLogic layout environment in both QuickWorks and
QuickTool. The input to the layout is a netlist from synthesis. SpDE can accept netlists in both the
QuickLogic format
(.qdf) and industry standard EDIF.
3.4 Programming
Once it has been determined that the design is functionally correct and meets the desired timing
constraints, run the sequencer and save the <design>.chp file. You can either import the design into
QuickPro if you want to program it yourself, or submit the file to QuickLogic's WebASIC service to obtain
programmed devices overnight at the following URL:
QuickPro is the software to program a .chp file into QuickLogic devices. It is freeware and does not
require a license. You can download it from the QuickLogic Web site. It runs only on Microsoft Windowsbased PCs. To program your device, you also need a programmer called DeskFab and a programming
adapter for the package you are using. Please contact a QuickLogic sales representative when you are
handling the programming.
www.quicklogic.com/webasic.
QL901M QuickMIPS™ Data Sheet Rev B
•
7
•
•
•
•
•
4.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=0.74)
The AC Specifications, Logic Cell diagrams, and waveforms are provided below.
Figure 4: QuickMIPS Logic Cell
Table 5: Logic Cells
SymbolParameter
Logic Cells
tPDCombinatorial delay: time taken by the combinatorial circuit to output0.257
tSU
tCLK
tCWHIClock High Time: the length of time that the clock stays high0.46
tCWLOClock Low Time: the length of time that the clock stays low0.46
tSET
tRESET
tSW
tRW
Setup time: the amount of time the synchronous input of the flip flop must be stable before
the active clock edge
Hold time: the amount of time the synchronous input of the flip flop must be stable after the
thl
active clock edge
Clock to out delay: the amount of time the synchronous input of the flip flop must be stable
after the active clock edge
Set Delay: amount of time between when the flip flop is “set” (high)
and when Q is consequent “set” (high)
Reset Delay: amount of time between when the flip flop is “reset” (low) and when Q is
consequent “reset” (low)
Set Width: length of time that the SET signal remains high
(low if active low)
Reset Width: length of time that the RESET signal remains high
(low if active low)
TonFloat to Active Delay22ns
ToffActive to Float Delay1428ns
Tsu
Tsu (ptp)
ThInput Hold Time from PCI_CLK00ns
TrstReset Active Time after power stable11ms
Trst-clkReset Active Time after PCI_CLK stable100100
Trst-off
TrhfaPCI_RST_n high to first configuration access22clocks
TrhffPCI_RST_n high to first PCI_FRAME_n assertion55clocks
PCI_CLK to Signal Valid Delay
point-to-point signals
Input Setup Time to PCI_CLK
bused signals
Input Setup Time to PCI_CLK
point-to-point
c
Reset Active to output float delay4040ns
b
26212ns
37ns
510, 12ns
Units
µ
s
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n.
b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n.
c. All output drivers must be 3-stated when PCI_RST_n is active.
TXCLK(in)
TXEN(out)
t
en_c2q
TXD[3:0](out)
t
en_c2q
t
data_v
t
data_h
t
data_h
Figure 19: Ethernet MAC Transmit Interface Waveforms
Table 17: Ethernet MAC Transmit Interface AC Timing
ParameterMinMaxUnits
Time from the rising clock edge of TXCLK to
the change in TXEN
Time from the rising clock edge of TXCLK to all
data signals having valid stable values
Time in which the output data is still valid after
the rising clock edge of TXCLK
t
data_v
0.0ns
8.0ns
9.0ns
QL901M QuickMIPS™ Data Sheet Rev B
•
19
•
•
•
•
•
RXCLK(in)
RXDV(in)
t
dv_h
t
dv_s
RXER(in)
t
er_h
t
er_s
RXD[3:0](in)
t
data_s
Figure 20: Ethernet MAC Receive Interface Waveforms
Table 18: Ethernet MAC Receive Interf a c e AC Timing
ParameterMinMaxUnits
t
dv_s
t
dv_h
t
er_s
t
er_h
t
data_s
t
data_h
RXDV (receive data valid) to RXCLK setup time2.0ns
RXDV (receive data valid) from RXCLK hold time2.0ns
RXER (receive data error) to RXCLK setup time2.0ns
RXER (receive data error) from RXCLK hold time2.0ns
RXD (receive data) to RXCLK setup time2.0ns
RXD (receive data) from RXCLK hold time2.0ns
The timing of the MII Management Interface listed below depends on the system clock frequency. The
numbers displayed are correct for a processor clock frequency of 100 MHz and an AMBA bus system
clock frequency of 50 MHz. Note that for a system clock of 133 MHz, the mandatory MDC minimum
clock cycle of 400ns for some PHY devices will not be met.
Figure 21: MII Management Interface Waveforms (1 of 2)
Table 19: MII Management Interface AC Timing (1 of 2)
ParameterMinMaxUnits
MDC cycle time520ns
MDC high time260ns
MDC low time260ns
MDIO output high impedance to valid time from rising edge of MDC40ns
MDIO output valid to high impedance time from rising edge of MDC40ns
MDIO output valid before MDC rising edge440ns
MDIO output valid from MDC rising edge40ns
t
mdovz
t
t
mdis
mdih
MDC(out)
MDIO(in)
t
mdis
Figure 22: MII Management Interface Waveforms (2 of 2)
Table 20: MII Management Interface AC Timing (2 of 2)
ParameterMinMaxUnits
MDIO setup time to MDC25ns
MDIO hold time to MDC0ns
t
mdih
QL901M QuickMIPS™ Data Sheet Rev B
•
21
•
•
•
•
•
SD_CS_n[3:0]
SD_CKE[3:0]
SD_DQM[3:0]
DATA(output)[31:0]
DATA(input[31:0]
SD_CLKIN
Tco_sdram
ADDR[23:0]
SD_RAS_n
SD_CAS_n
SD_WE_n
Tsu_sdramTh_sdram
Figure 23: SDRAM Waveforms
Table 21: SDRAM AC Timing
Parameter
Tco
TsuDATA12ns
ThDATA2ns
a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF
load except for SD_CLKOUT, which has a load of 15 pF.
a. “x” indicates that this timing delay does not apply to the signal.
b. The ahbm_hprot
ters besides the processor-AHB-bridge generates this signal. Therefore the re is no setup or hold timing for
ahbm_hprot.
•
•
www.quicklogic.com
•
•
•
•
signal is NOT used by any slave within the standard cell part of the chip. None of the mas-
PCI Address and Data. PCI_AD[31:0] contain the multiplexed address and data. A bus transaction
consists of a single address phase (or two address phases for 64-bit addresses) followed by one or
more data phases. The QuickMIPS chip supports both read and write bursts.
The address phase occurs in the first clock cycle when PCI_FRAME_n is asserted. During the address
PCI_AD[31:0]I/O
phase, PCI_AD[31:0] contain a 32-bit physical address. F or I/O , this is a byte address; f or configuration
and memory, it is a DWORD (32-bit) address. During data phases, PCI_AD[7:0] contain the leastsignificant byte, and PCI_AD[31:24] contain the most-significant byte.
Write data is stable and valid when PCI_IRDY_n is asserted; read data is stable and valid when
PCI_TRDY_n is asserted. Data is transferred when both PCI_IRD Y_n and PCI_TRDY_n are asserted.
Bus Command and Byte Enables. Bus commands and byte enables are multiplexed on
PCI_C_BE_n[3:0]. During the address phase of a transaction (PCI_FRAME_n is asserted),
PCI_C_BE_n[3:0] define the bus command as shown in the following table (only v alid combinations are
shown).
During each data phase, PCI_C_BE_n[3:0] are byte enables. The byte enables are v alid for the entire
data phase and determine which byte lanes contain meaningful data. PCI_C_BE_n[0] applies to byte
0 (PCI_AD[7:0]) and PCI_C_BE_n[3] applies to byte 3 (PCI_AD[31:24]).
PCI Device Select. When asserted low, PCI_DEVSEL_n indicates the driving device has decoded its
address as the target of the current access. As an input, PCI_DEVSEL_n indicates whether any device
on the bus has responded.
PCI Cycle Frame. The current master asserts PCI_FRAME_n to indicate the beginning and duration of
a bus transaction. While PCI_FRAME_n is asserted, data transfers continue. When PCI_FRAME_n is
deasserted, the transaction is in the final data phase or has completed.
(Sheet 1 of 6)
QL901M QuickMIPS™ Data Sheet Rev B
•
27
•
•
•
•
•
PinI/OFunction
PCI_GNT_nI
PCI_IDSELI
PCI_INTA_nO
PCI_IRDY_nI/O
PCI_LOCK_nI
PCI_PARI/O
PCI_PERR_nI/O
PCI_REQ_nO
PCI_RST_nI
Table 27: Pin Descriptions (Continued)
PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been
granted. PCI_GNT_n is ignored while PCI_RST_n is asserted.
PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write
transactions (PCI_C_BE_n[3:0] = 1010 or 1011).
PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip.
PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains
asserted until the interrupt is cleared.
Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only.
However, such an interrupt controller can be built into the fabric.
PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator)
asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD[31:0] during a write, or that it is
ready to accept data on PCI_AD[31:0] during a read.
A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a
low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD[31:0]. During a read, a low
assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until
both PCI_IRDY_n and PCI_TRDY_n are asserted together.
PCI Lock. A low assertion on PCI_LOCK_n indicates an atomic operation to a bridge that might take
multiple transactions to complete. When PCI_LOCK_n is asserted, non-exclusive transactions can
proceed to a bridge that is not currently locked. Control of PCI_LOCK_n is obtained under its own
protocol in conjunction with PCI_GNT_n. It is possible for different agents to use PCI while a single
master retains ownership of PCI_LOCK_n. Locked transactions can be initiated only by host bridges,
PCI-to-PCI bridges, and expansion bus bridges.
PCI Parity. Parity is driven high or low to create even parity across PCI_AD[31:0] and
PCI_C_BE_n[3:0]. The master drives PCI_PAR for address and write data phases; the target drives
PCI_PAR for read data phases.
PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI
transactions except a Special Cycle. The Quic kMIPS chip drives PCI_PERR_n low two clocks f ollowing
the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n
is one clock for each data phase that a data parity error is detected. (If sequential data phases each
have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.)
PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals.
PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus.
PCI_REQ_n is 3-stated while PCI_RST_n is asserted.
PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When
PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and
PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset).
28
PCI_SERR_nO
PCI_STOP_nI/O
•
•
www.quicklogic.com
•
•
•
•
The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK.
PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data
parity error on the Special Cycle command, or any other system error where the result is catastrophic.
PCI_SERR_n is open drain and is actively driven f or a single PCI clock. The assertion of PCI_SERR_n
is synchronous to the clock and meets the setup and hold times of all bused signals. However, the
restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as
used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can
take two to three clock periods to fully restore PCI_SERR_n.
PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop
the current transaction.
PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave
(target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD[31:0] during a read, or
that it is ready to accept data on PCI_AD[31:0] during a write.
A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a
low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD[31:0]. During a write, a
low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both
PCI_IRDY_n and PCI_TRDY_n are asserted together.
PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of
PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz.
Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon
detection of a collision on the medium. COL remains asserted while the collision condition persists.
The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK.
The QuickMIPS MAC core ignores the COL signal when operating in the full-duplex mode.
Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either
transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and
receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of
a collision condition.
The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK.
Ethernet Management Data Clock. MDC is sourced by the MAC110 core to the Ethernet PHY
Controller as the timing reference for transfe r of information on the MDIO signals. MDC is an aperiodic
signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns
each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and
RXCLK.
Ethernet Management Data In/Out. When used as an input, MDIO is the data input signal from the
Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock
during the read cycles.
When used as an output, MDIO is the data output signal from the MAC110 core that drives the control
information during the Read/Write cycles to the External PHY Controller. The MAC110 core drives the
MDIO signal synchronously with respect to the MDC.
Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference f or the transfer
of the RXDV and RXD[3:0] signals from the Ethernet PHY Controller to the MAC110 core. The Ethernet
PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the
received signal on the Ethernet cable.
Ethernet Receive Data. RXD[3:0] transition synchronously with respect to RXCLK. The Ethernet PHY
Controller chip drives RXD[3:0]. For each RXCLK period in which RXD V is asserted, RXD[3:0] transfer
four bits of recovered data from the PHY to the MAC110 core. RXD0 is the least-significant bit. While
RXDV is deasserted low, RXD[3:0] has no effect on the MAC110 core.
Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the
MAC110 core that it is presenting the recovered and decoded data bits on RXD[3:0] and that the data
on RXD[3:0] is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXD V
remains asserted continuously from the first recovered nibble of the frame through the final recovered
nibble, and is deasserted low prior to the first RXCLK that follows the final nibble.
Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK
periods to indicate to the MAC110 core that an error (a coding error or any error that the PHY is capable
of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame
presently being transferred from the PHY to the MAC110 core. RXER transitions synchronously with
respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC110 core.
(Sheet 3 of 6)
QL901M QuickMIPS™ Data Sheet Rev B
•
29
•
•
•
•
•
Table 27: Pin Descriptions (Continued)
PinI/OFunction
Ethernet T ransmit Cloc k. TXCLK is a continuous cloc k that provides a timing ref erence for the tr ansf er
M1_TXCLK/M2_TXCLKI
M1_TXD[3:0]/M2_TXD[3:0]O
M1_TXEN/M2_TXENO
Memory Controller Interface Signals
BLS_n[3:0]OByte Enables. These signals determine the validity of the bytes on the DATA bus.
CS_n[7:0]OChip Selects. These signals are the active-low chip selects for the SRAM.
ADDR[23:0]OMemory Address. This 24-bit address contains the memory address.
DATA[31:0]I/OMemory Data. This 32-bit bus contains the memory data.
OEN_nOSRAM Output Enable. OEN_n is the active-low output enable to the external SRAM.
SD_CAS_nO
SD_CKE[3:0]OSDRAM Output Clock Enables. SD_CKE[3:0] determine whether the next clock is valid or not.
SD_CLKINISDRAM Input Clock. SD_CLKIN is the external SDRAM clock.
SD_CLKOUTOSDRAM Output Clock. SD_CLKOUT is the clock from the QuickMIPS chip to the external SDRAMs.
SD_CS_n[3:0]OSDRAM Output Chip Select. SD_CS_n[3:0] are the active-low chip selects for the external SDRAMs.
SD_DQM[3:0]OSDRAM Data Mask. SD_DQM[3:0] are the data masks for DATA[31:0]
SD_RAS_nO
SD_WE_nOSDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs.
WEN_nO
UART Interface Signals
U1_CTS_nIUART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data.
U1_DCD_nIUART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected.
U1_DSR_nI
U1_DTR_nO
U1_RI_nIUART1 Ring Indicator. This input is an active-low ring indicator.
U1_RTS_nO
U1_RXD_SIRINI
of the TXEN and TXD signals from the MAC110 core to the Ethernet PHY Controller. The Ethernet PHY
Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at
100 Mbps and 2.5 MHz when operating at 10 Mbps.
Ethernet Transmit Data. The QuickMIPS MAC110 core drives TXD[3:0]. TXD[3:0] transition
synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD[3:0]
have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit.
While TXEN is deasserted, ignore the data presented on TXD[3:0].
Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC110 core is presenting
nibbles on the MII for transmission. The QuickMIPS MAC110 core asserts TXEN with the first nibble of
the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII.
TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is
transitions synchronously with respect to TXCLK.
SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external
SDRAM.
SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external
SDRAM.
SRAM T ransf er Direction. WEN_n indicates whether transactions between the QuickMIPS chip and the
external SRAM are reads (WEN_n is high) or writes (WEN_n is low).
UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the
link to the QuickMIPS UART.
UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to
establish the external communication link.
UART1 Request To Send. The QuickMIPS chip asserts this signal low to inform the external device that
the UART is ready to send data.
UART1 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the
UART or the IrDA block.
UART1 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from
either the UART or the IrDA block.
UART2 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the
UART or the IrDA block.
UART2 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from
either the UART or the IrDA block.
Test Interface Signals
EJTAG Test Clock. This clock controls the updates to the TAP controller and the shifts through the
EJTAG_TCKI
EJTAG_TDII
EJTAG_TDOO
EJTAG_TMSI
EJTAG_TRSTI
EJTAG_DEBUGMO
EJTAG_DINTI
Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are
used.
EJT AG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register.
This input is sampled on the rising edge of EJTAG_TCK.
EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or
data register. This signal changes on the falling edge of EJTAG_TCK.
EJTAG Test Mode Select. This input is the control signal for the TAP controller. It is sampled on the
rising edge of EJTAG_TCK.
EJTAG Test Reset. This signal is asserted high asynchronously to reset the TAP controller, Instruction
register, and EJTAGBOOT indication.
Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be
used to bring the chip out of low power mode.
Debug Exception Request. Assertion high of this input indicates a debug exception request is pending.
The request is cleared when debug mode is entered. Requests that occur while the chip is in debug
mode are ignored.
Fabric Interface Signals
I/O<A>53:0I/OProgrammable Input/Output/3-State/Bidirectional pin in Bank A.
I/O<B>71:0I/OProgrammable Input/Output/3-State/Bidirectional pin in Bank B.
I/O<C>71:0I/OProgrammable Input/Output/3-State/Bidirectional pin in Bank C.
I/O<D>53:0I/OProgrammable Input/Output/3-State/Bidirectional pin in Bank D.
CLK<8:0>I/OProgrammable Global Clock Pin. Tie to VCC or GND if unused.
INREF<A:D>I/ODifferential I/O Reference Voltage. Connect to GND when using TTL, PCI or LVCMOS.
IOCTRL<A:D>I/OLow Skew I/O Control Pins. Tie to GND if unused.
TCLKIJTAG Clock. Tie to GND if unused.
TDIIJTAG Data In. Tie to VCC if unused.
TDOOJTAG Data Out. Leave unconnected if unused.
TMSOJTAG Test Mode Select. Tie to VCC if unused.
TRSTBIJTAG Reset. Tie to GND if unused.
Timer Interface Signals
TM_OVERFLOWOTimer Overflow. This output is asserted high when an internal timer overflows.
TM_ENABLEITimer Enable. This signal is asserted high to enable the internal timer.
CPU_EXTINT_n<6:0>ICPU Interrupts. Asserting Low any of these inputs causes an interrupt to the QuickMIPS chip.
PL_BYPASSI
PL_CLKOUTOOutput Clock from PLL.
PL_CLOCKINIInput Clock to PLL.
PL_ENABLEI
PL_LOCKO
PL_RESET_nIPLL Reset.
PL_WARMRESET_nIPLL Warm Reset.
STMIQuickLogic Reserved pin. Tie to GND on the PCB.
Power and Ground Signals
GNDIGround pin. Tie to GND on the PCB.
GNDPLLIGround for the PLL.
VCCIOI
VCCIO<A:D>IVCCIO port for each of the four I/O banks.
VCCPLLISupply for the PLL.
VCCISupply pin. Tie to 2.5V supply.
Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates
little-endian byte ordering.
PLL Bypass. When High, the 2X multiplication of the input clock is not performed and the output clocks
are half their normal frequencies.
PLL Enable. A High assertion of this signal powers down the PLL when it is not being used to reduce
overall device power and puts the QuickMIPS chip into a quiescent current testing mode. When
PL_ENABLE is Low, the PLL is not functional, but the clock outputs can be used if the PL_BYPASS
input is High.
PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid
output clocks.
Supply pin for I/O. Set to 2.5V for 2.5V I/O, 3.3V for 3.3V compliant I/O, or refer to the I/O Standards
table.
The information contained in this product brief, and the accompanying software programs are protected by
copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make
periodic modifications of this product without obligation to notify any person or entity of such revision. Copying,
duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an
authorized representative of QuickLogic is prohibited.
QuickLogic, pASIC, and ViaLink are registered trademarks, and QuickMIPS, SpDE and QuickWorks are
trademarks of QuickLogic Corporation.
Verilog is a registered trademark of Cadence Design Systems, Inc.
SaiLAhead
TM
is a registered trademark of Saivision.
QL901M QuickMIPS™ Data Sheet Rev B
•
37
•
•
•
•
•
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.