QUICK LOGIC QL901M-6PS680C, QL901M-6PS680I Datasheet

QL901M QuickMIPS™ Data Sheet

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QuickMIPS ESP Family

1.0 Overview

The QuickMIPS™ Embedded Standard Products (ESPs) family provides an out-of-the box solution consisting of the QL901M QuickMIPS chip and the QuickMIPS development environment. The development environment includes a Reference Design Kit (RDK) with drivers, real-time operating systems, and QuickMIPS system model. With the RDK, software and hardware engineers can evaluate, debug, and emulate their system in parallel.

CPU

• High-performance MIPS 4Kc processor runs

up to 133 MHz in .25µ (173 Dhrystone MIPS)

• 1.3 Dhrystone MIPS per MHz

• MDU supports MAC instructions for

DSP functions

• 16 Kbytes of Instruction Cache

(4-way set associative)

• 16 Kbytes of Data Cache (4-way set

associative) with lockout capability per line

• 16 Kbytes of on-chip, high-speed SRAM for

use by multiple AHB Bus Masters

• 32-bit 66/33 MHz PCI Host and Satellite

(Master/Target) operation with DMA channels and FIFO for full bandwidth

• Two MAC10/100s with MII ports connect

easily to external transceivers/PHY devices

• One AHB 32-bit master port/one AHB

32-bit slave port to Programmable Fabric

• Global System Configuration and Interrupt

Controller

Peripheral Bus (AMBA APB)

• 32-bit APB runs at half the CPU clock

frequency (the same as the AHB clock)

• Three APB slave ports in the programmable

fabric

• Two serial ports (one with Modem control

signals and one with IRDA-compliant signals)

• Four general-purpose 32-bit timer/counters

on one APB port

16 Kbytes

SRAM

MIPS 4Kc

w/Caches

32-bit PCI

66/33 MHz

Ethernet

10/100 MAC

Ethernet

10/100 MAC

Memory

Controller

Interrupt

Controller

High-Perf ormance Bus (AMBA AHB)

• High-performance 32-bit AMBA AHB bus

standard for high-speed system bus running at half the CPU clock

• High-bandwidth memory controller for

SDRAM, SRAM, and EPROM

• SDRAM support for standard SDRAMs up to

256 MBytes with auto refresh, up to 4 banks non-interleaved

• Support for PC100 type memories with up

to two chip enables

• EPROM controller for boot code

• 8-bit, 16-bit, and 32-bit device width support

QL901M QuickMIPSTM Data Sheet Rev B

ECI to AHB

32-bit Advanced High-Performance Bus

AHB to APB

3 APB

Slave

I/F

1 AHB

Master I/F

1 AHB

Slave I/F

Two 16550

UARTs

32-bit Advanced Peripheral Bus

36 RAM Blocks (Configurations 128x18; 256x9; 512x4; or 1024x2)

Via-Link Programmable Fabric

18 ECU Blocks-- 8x8 Multiply, 16-bit carry/add

Four 32-bit

Timer/Counters

Configurable

Logic Analyzer

Monitor (CLAM)

Figure 1: Embedded QuickMIPS Block Diagram

JTAG

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Programmable Via-Link Fabric

• Embedded memory configurable as RAM or FIFO

• 252 programmable I/Os

• High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with

3-bit instructions

• Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3

Table 1: Programmable Fabric F eatures

Maximum System Gates*

536,472 72x28 2,016 4,788 36 82,944 18

* 75K ASIC gates

Logic Arrays

Columns x Rows

Logic Cells

** Possible Configurations:

128x18, 256x9, 512x4, or 1024x2

Maximum

Flip-Flops

RAM Blocks** RAM Bits ECU Blocks***

*** 8x8 Multiply , 16-bit carry-add

On-Chip Debug Blocks

• On-chip instrumentation blocks for debug and trace capabilities

• Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look

at selected signals from IP function in fabric

Development and Programming

• Complete QuickLogic software suite of development tools enables rapid implementation of IP

functions for complete SOC solution

• Complete chip simulation of user-defined programmable-logic IP functions with the processor,

caches, memory, and all hardwired functions on-chip

• Synthesis of IP functions into the programmable fabric

• Place-and-Route tool for efficient implementation of IP functions in the programmable fabric

• Extensive timing analysis of IP functions with the rest of the chip to ensure full chip functionality

• Programming and debug support of the entire chip through JTAG port

• Integrated debug support for the MIPS 4Kc processor

• MIPS Language and Debug tool support for the MIPS 4Kc processor from approved third party

MIPS vendors

• ECU support for a variety of DSP algorithms and functions

• QuickLogic library of standard IP functions for plug-and-play implementation of standard IP functions

in the programmable fabric for a complete SOC solution

• QuickMIPS Reference Design Kit (RDK) provides a complete Board Support Package for

chip evaluation

• Programming and debug support

• Device-driver support for standard IP functions

• Boot-up code and diagnostics

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Design Tools Platform Support

• QuickWorks, the complete product suite, supports Windows 95/98/NT/2000. It includes SpDE

(layout including place & route, timing analysis, and back-annotation), Synplify-Lite (synthesis), Turbo Writer (HDL-enhanced text editor), etc.

• QuickTool supports Solaris. It has only the layout software (SpDE).

• QuickMIPS simulation is enabled through either:

• a SmartModel (VMC-generated model, encrypted RTL, relatively slow). This option supports both

Verilog and VHDL.

• SaiLAhead co-verification platform from Saivision (very fast C model). This option only supports

Verilog (no VHDL) at this time.

Table 2: Design Tools Platform Support

Solaris Windows NT Windows 2000 Linux

Synthesis Synplify-Lite X (in QuickWorks) X (in Qui ckW orks)

Layout SpDE X (in QuickTool) X (in QuickWorks) X (in QuickWorks)

SmartModel

Simulation

SaiLAhead

ModelSim/VCS XX

Verilog XL/NC X

ModelSim XXX

Verilog XL/NC X X

SaiLAhead Platform

The “SaiLAhead for QuickMIPS” co-verification platform is tailored for QuickMIPS devices. It enables simulation of user-defined logic functions that are to be implemented in the QuickMIPS programmable fabric with the rest of the QuickMIPS fixed system logic functions, which verifies overall QuickMIPS functionality. Simultaneously, the SaiLAhead platform has a powerful, feature-rich debugger, which enables QuickMIPS users to develop and debug their application code (C and MIPS assembly). The SaiLAhead platform accelerates the speed of simulation of the QuickMIPS device in a simulator such as NC-Verilog by using C models for various fixed system logic functions in the QuickMIPS device. This platform also provides a standalone C environment offering additional speed-up of simulation of the entire QuickMIPS design. Please refer to SaiLAhead platform.

http://www.saivision.com for more information on the

QL901M QuickMIPS™ Data Sheet Rev B

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2.0 Embedded Computational Units (ECUs)

Traditional programmable logic architectures do not implement arithmetic functions efficiently or effectively. These functions require high logic cell usage while garnering only moderate performance results. By embedding a dynamically reconfigurable computational unit, the QuickMIPS chip can address various arithmetic functions efficiently and effectively providing for a robust DSP platform. This approach offers greater performance than traditional programmable logic implementations. The ECU block is ideal for complex DSP, filtering, and algorithmic functions. The QuickMIPS architecture allows functionality above and beyond that achievable using DSP processors or programmable logic devices. The embedded block is implemented at the transistor level with the following block diagram in

Figure 2.

Abus Xbus

Ybus

I bus

Sign

Multiply

Sequencer

Add Register

Logic CellMemory

Rbus

Figure 2: Embedded Computational Unit (ECU) Block Diagram

Table 3: ECU Comparisons

Function Description

16 bit 8 ns 2.5 ns

Adder

Multiplier

System Clock 200 MHz 400 MHz

32 bit 10 ns 5.6 ns 64 bit 12 ns 6.7 ns

8 x 8 10 ns 4.3 ns

16 x 16 12ns 6.7 ns

Slowest Speed

Grade

Fastest Speed Grade

Implementation of the equivalent ECU block as HDL in a programmable logic architecture requires 205 logic cells with a 10 ns delay in a -4 speed grade. There are a maximum of 18 ECU blocks and a minimum of 10 ECU blocks in the QuickMIPS chip. The ECU blocks are placed next to the RAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Eighteen 8-bit Multiply Accumulate functions can be implemented per cycle for a total of 2.6 billion MACs/s when clocked at 144 MHz. Further Multiply Accumulate functions also can be implemented in the programmable logic.

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The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 4. The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.

Table 4: ECU Mode Select Criteria

Instruction Set Operation

0 0 0 Multiply 0 0 1 Multiply - Add 010 Accumulate 0 1 1 Add 1 0 0 Multiply (registered) 1 0 1 Multiply - Add (registered) 1 1 0 Multiple - Accumulate 1 1 1 Add (registered)

The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an external software driven algorithm, or an internal state machine. This flexibility allows the designer to reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock cycle, such as adaptive filtering.

3.0 Design Flow

The QuickMIPS design flow, similar to ASIC design flow, is shown in Figure 3.

MIPS Programming System Configuration Customer IP Design in FPGA

Compiler,

Assembler, Linker

Debugger

EJTAG

Board-level

Support Package

Functional Co-simulation

Global Register

Configuration

QuickMIPS

System

Model

Full-System

with Timing

RTL

Synthesis

Place & Route

Timing Analysis

Final Netlist

& Timing

Chip Programming

QuickIP Models

Synthesis Lib

Timing Lib

QuickIP Netlist

Figure 3: QuickMIPS Hardware/Software Co-Development Flow

QL901M QuickMIPS™ Data Sheet Rev B

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A typical design process goes through the flow shown above. After passing postlayout simulation, QuickMIPS devices can be programmed for testing on the hardware testbench. Because QuickLogic devices are One-Time-Programmable (OTP), it is recommended that these devices are programmed only after they pass postlayout simulation to minimize development cost and reduce bench debugging time.

The QuickMIPS design flow is supported by QuickLogic's QuickWorks™ (for Microsoft Windows) and QuickTool™ (for UNIX) design software suites version 9.2 and up. Many third-party synthesis and simulation tools are also supported. The QuickWorks software suite can be downloaded from QuickLogic's Web site

(www.quicklogic.com). Please contact a QuickLogic sales representative to

obtain a license or get QuickTool software.

Both Verilog and VHDL design methodologies are fully supported. The flow described below assumes that the QuickWorks or QuickTool 9.2 software has been installed.

3.1 Simulation

QuickLogic provides the system simulation environment. This environment includes the QuickMIPS VMC model, ROM and RAM models, reset and clock generation, boot code, and sample programs (read and write to memory). This environment allows customers to focus on their RTL code and not have to worry about bringing up the system simulation environment.

The simulation behavior of the QuickMIPS ESP core is provided by the VMC model. VMC (Verilog Model Compiler) is a tool from Synopsys that compiles Verilog RTL (Register-Transfer-Level) code into binary code. A VMC model (the binary code) implements the same logic functions as the RTL code while providing IP protection. In simulation, it communicates to the simulator via PLI (Programmable Language Interface) for Verilog or FLI (Foreign Language Interface) for VHDL.

Because of the VMC model, the Silos III Verilog simulator and Active-HDL VHDL simulator bundled in QuickWorks are not supported in QuickMIPS simulation flow. A third-party simulator must be used. The currently supported simulators include:

• Verilog simulators: Verilog-XL, NC Verilog, VCS, ModelSim

• VHDL simulators: VSS, ModelSim

3.2 Synthesis

Synthesis is the process of turning the HDL code describing the fabric behavior into gates. Three thirdparty synthesis tools are supported:

• Synplify-Lite from Synplicity (bundled in QuickWorks)

• Exemplar Leonardo Spectrum

• Synopsys Design Compiler

Refer to the corresponding QuickNotes on the QuickLogic support Web site for further information.

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3.3 Layout

Layout is performed in SpDE, which is the QuickLogic layout environment in both QuickWorks and QuickTool. The input to the layout is a netlist from synthesis. SpDE can accept netlists in both the QuickLogic format

(.qdf) and industry standard EDIF.

3.4 Programming

Once it has been determined that the design is functionally correct and meets the desired timing constraints, run the sequencer and save the <design>.chp file. You can either import the design into QuickPro if you want to program it yourself, or submit the file to QuickLogic's WebASIC service to obtain programmed devices overnight at the following URL:

QuickPro is the software to program a .chp file into QuickLogic devices. It is freeware and does not require a license. You can download it from the QuickLogic Web site. It runs only on Microsoft Windowsbased PCs. To program your device, you also need a programmer called DeskFab and a programming adapter for the package you are using. Please contact a QuickLogic sales representative when you are handling the programming.

www.quicklogic.com/webasic.

QL901M QuickMIPS™ Data Sheet Rev B

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4.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=0.74)

The AC Specifications, Logic Cell diagrams, and waveforms are provided below.

Figure 4: QuickMIPS Logic Cell

Table 5: Logic Cells

Symbol Parameter

Logic Cells

tPD Combinatorial delay: time taken by the combinatorial circuit to output 0.257

tSU

tCLK

tCWHI Clock High Time: the length of time that the clock stays high 0.46

tCWLO Clock Low Time: the length of time that the clock stays low 0.46

tSET

tRESET

tSW

tRW

Setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge

Hold time: the amount of time the synchronous input of the flip flop must be stable after the

thl

active clock edge Clock to out delay: the amount of time the synchronous input of the flip flop must be stable

after the active clock edge

Set Delay: amount of time between when the flip flop is “set” (high) and when Q is consequent “set” (high)

Reset Delay: amount of time between when the flip flop is “reset” (low) and when Q is consequent “reset” (low)

Set Width: length of time that the SET signal remains high (low if active low)

Reset Width: length of time that the RESET signal remains high (low if active low)

Propagation

delay (ns)

0.22

0.255

0.18

0.09

0.3

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SET

CLK

SET

RESET

CLK

RESET

Figure 5: Logic Cell Flip Flop

tCWI (min)

tCWLO (min)

CLK

tRESET

tRW

tSET

tSW

Figure 6: Logic Cell Flip Flop Timings - First Waveform

tSU

tHL

tCLK

Figure 7: Logic Cell Flip Flop Timings - Second Waveform

QL901M QuickMIPS™ Data Sheet Rev B

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Figure 8: QuickMIPS Global Clock Structure

Table 6: QuickMIPS Clock Performance

Clock Performance

Global Dedicated

Macro

I/O

Skew

Symbol

Input Register Cell Only

tGCKP Global clock pin delay to quad net 1.34

GCKB Global clock buffer delay (quad net to flip flop) 0.56

Programmable Clock

Hardware Clock

1.51 ns 1.59 ns

2.06 ns 1.73 ns

0.55 ns 0.14 ns

Table 7: QuickMIPS Input Register Cell

Parameter Propagation delay (ns)

Global Clock Buffer

Global Clock

tPGCK tBGCK

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Figure 9: Global Clock Structure Schematic

[9:0]

[17:0]

WCLK

[1:0]

MODE ASYNCRD

Quick RAM Mod ule

Figure 10: RAM Module

Table 8: RAM Cell Synchronous Write Timing

Symbol Parameter

RAM Cell Synchronous Write Timing

tSWA

tHWA

tSWD

tHWD

tSWE

tHWE

tWCRD

WA setup time to WCLK: the amount of time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK

WA hold time to WCLK: the amount of time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK

WD setup time to WCLK: the amount of time the WRITE DATA must be stable before the active edge of the WRITE CLOCK

WD hold time to WCLK: the amount of time the WRITE DATA must be stable after the active edge of the WRITE CLOCK

WE setup time to WCLK: the amount of time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK

WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK

WCLK to RD (WA=RA): the amount of time between the activ e WRITE CLOCK edge and the time when the data is available at RD

RCLK

[9:0]

[17:0]

Propagation

delay (ns)

0.675

0.654

0.623

4.38

QL901M QuickMIPS™ Data Sheet Rev B

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WCLK

tSWA

tSWD

tSWE

old data

Figure 11: RAM Cell Synchronous Write Timing

Table 9: RAM Cell Synchronous & Asynchronous Read Timing

Symbol Parameter

RAM Cell Synchronous Read Timing

tSRA

tHRA

tSRE

tHRE

tRCRD

RAM Cell Asynchronous Read Timing

rPDRD

RA setup time to RCLK: the amount of time the READ ADDRESS must be stable before the active edge of the READ CLOCK

RA hold time to RCLK: the amount of time the READ ADDRESS must be stable after the active edge of the READ CLOCK

RE setup time to WCLK: the amount of time the READ ENABLE must be stable before the active edge of the READ CLOCK

RE hold time to WCLK: the amount of time the READ ENABLE must be stable after the active edge of the READ CLOCK

RCLK to RD: the amount of time between the active READ CLOCK edge and the time when the data is available at RD

RA to RD: amount of time between when the READ ADDRESS is input and when the DATA is output

tHWA

tHWD

tHWE

new data

tWCRD

Propagation

delay (ns)

0.686

0.243

4.38

2.06

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