-3-layer metal ViaLink process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
3
pASIC 2
192
Logic
Cells
3-5
QL2003
PRODUCT
SUMMARY
FEATURES
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of
the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique
combination of architecture, technology, and software tools to provide high
speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high
performance silicon solution for designs described using HDLs such as
Verilog and VHDL, as well as schematics.
The QL2003 contains 192 logic cells. With 118 maximum I/Os, the
QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP
packages.
Software support for the complete pASIC families, including the QL2003, is
available through three basic packages. The turnkey QuickWorks package
provides the most complete FPGA software solution from design entry to
logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickToolsTM and QuickChipTM packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other thirdparty tools for design entry, synthesis, or simulation.
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin,
or any input or I/O pin, or any logic cell output or I/O cell feedback
TDITest Data In for JTAGHold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TRSTBActive low Reset for JTAGHold LOW during normal operation. Connect to
ground if not used for JTAG.
TMSTest Mode Select for JTAGHold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TCKTest Clock for JTAGHold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
TDOTest data out for JTAGOu t p u t t h a t m u s t b e l e f t u n c onnected if not used for JTAG.
STMSpecial Test ModeMust be grounded during normal operation.
I/ACLKHigh-drive input and/or array
network driver
I/GCLKHigh-drive input and/or global
network driver
IHigh-drive inputUse for input signals with high fanout.
I/OInput/Output pinCan be configured as an input and/or output.
VCCPower supply pinConnect to 3.3V supply.
GNDGround pinConnect to ground.
Can be configured as either or both.
Can be configured as either or both.
ORDERING
INFORMATION
QuickLogic
pASIC device
pASIC 2 device
part number
Speed Grade
X = quick
0 = fast
1 = faster
2 = fastest
Supply Voltage ……………….. -0.5 to 7.0VStorage Temperature……..…….. -65°C to + 150°C
Input Voltage ……….… -0.5 to VCC +0.5VLead Temperature ………….…………...…. 300°C
ESD Pad Protection ….…………… ±2000V
DC Input Current ….……………… ±20 mA
Latch-up Immunity ………………. ±200 mA
5 Volt OPERATING RANGE
SymbolParameterIndustrialCommercialUnit
MinMaxMinMax
VCCSupply Voltage4.55.54.755.25V
TAAmbient Temperature-4085070
TCCase Temperature
-X Speed Grade0.42.750.462.55
KDelay Factor-0 Speed Grade0.42.000.461.85
-1 Speed Grade0.41.610.461.50
-2 Speed Grade0.41.350.461.25
°C
°C
DC CHARACTERISTICS over 5V operating range
SymbolParameterConditionsMinMaxUnit
VIHInput HIGH Voltage2.0V
VILInput LOW Voltage0.8V
IOH = -4 mA3.7V
VOHOutput HIGH VoltageIOH = -24 mA/-16 mA [1]2.4V
IOH = -10 µA
VOLOutput LOW VoltageIOL = 24 mA/16 mA [1]0.45V
IOL = 10 µA
IIInput Leakage CurrentVI = VCC or GND-1010
IOZ3-State Output Leakage CurrentVI = VCC or GND-1010
CIInput Capacitance [2]10pF
IOSOutput Short Circuit Current [3]VO = GND-15-120mA
VO = VCC40210mA
ICCD.C. Supply Current [4]VI, VIO = VCC or GND2 (typ)10mA
VCC-0.1V
0.1V
3
pASIC 2
µA
µA
Notes:
[1]-24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are
also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications.
[2]Capacitance is sample tested only.
[3]Only one output at a time. Duration should not exceed 30 seconds.
[4]For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade
devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer
VIHInput HIGH Voltage2.0V
VILInput LOW Voltage0.8V
VOHOutput HIGH VoltageIOH = -2.4 mA2.4V
IOH = -10 µA
VOLOutput LOW VoltageIOL = 4 mA0.4V
IOL = 10 µA
IIHInput High Current Sink
(for tolerance to 5V devices)
IIInput Leakage CurrentVI = VCC or GND-1010
IOZ3-State Output Leakage CurrentVI = VCC or GND-1010
CIInput Capacitance [5]10pF
IOSOutput Short Circuit Current [6]VO = GND-10-70mA
ICCD.C. Supply Current [7]VI, VIO = VCC or GND0.5 (typ)3mA
5.5V > VI > VCC12mA
VO = VCC25130mA
VCC-0.1V
°C
0.1V
µA
µA
Notes:
[5]Capacitance is sample tested only.
[6]Only one output at a time. Duration should not exceed 30 seconds.
[7]For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC
AC CHARACTERISTICS at VCC = 5V, TA = 25°°C (K = 1.00)
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.
Logic Cells
Propagation Delays (ns)
SymbolParameter
12348
tPDCombinatorial Delay [9]1.41.72.02.33.5
tSUSetup Time [9]1.81.81.81.81.8
tHHold Time0.00.00.00.00.0
tCLKClock to Q Delay0.81.11.41.72.9
tCWHIClock High Time2.02.02.02.02.0
tCWLOClock Low Time2.02.02.02.02.0
tSETSet Delay1.41.72.02.33.5
tRESETReset Delay1.21.51.82.13.3
tSWSet Width1.91.91.91.91.9
tRWReset Width1.81.81.81.81.8
tISUInput Register Set-Up Time4.84.84.84.84.84.8
tIHInput Register Hold Time0.00.00.00.00.00.0
tlOCLKInput Register Clock To Q0.81.11.41.72.93.6
tlORSTInput Register Reset Delay0.71.01.31.62.83.5
tlESUInput Register clock Enable Set-Up Time4.14.14.14.14.14.1
tlEHInput Register Clock Enable Hold Time0.00.00.00.00.00.0
Propagation Delays (ns)
SymbolParameter
Output Load Capacitance (pF)
305075100150
tOUTLHOutput Delay Low to High2.63.03.64.15.2
tOUTHLOutput Delay High to Low2.83.33.94.55.7
tPZHOutput Delay Tri-state to High2.12.63.13.74.8
tPZLOutput Delay Tri-state to Low2.63.34.14.96.5
tPHZOutput Delay High to Tri-State [11]2.9
tPLZOutput Delay Low to Tri-State [11]3.3
[8]
[10]
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
[11] The following loads are used for tPXZ:
1K
tPHZ
Ω
5 pF
1K
Ω
3-14
tPLZ
5 pF
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