QUICK LOGIC QL16x24B-1PL84I, QL16x24B-1PL84M, QL16x24B-2CF160C, QL16x24B-2CF160I, QL16x24B-2CF160M Datasheet

QL16x24B

pASIC

®

1 Family

Very-High-Speed CMOS FPGA

4-21

Very High Speed

– ViaLink



metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density

– A 16-by-24 array of 384 logic cells

provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin

PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin

CQFP packages.

Low-Power, High-Output Drive

– Standby current typically 2 mA.

A 16-bit counter operating at 100 MHz consumes less than 50 mA.

Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools

– Designs entered and

simulated using QuickLogic's new QuickWorks



development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

=

Up to 114 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

pASIC 1

4

pASIC

HIGHLIGHTS

QL16x24B

Block Diagram

Rev C

…4,000

usable ASIC gates,

122 I/O pins

384 Logic Cells

QL16x24B

4-22

The QL16x24B is a member of the pASIC 1 Family of very-high-speed

CMOS user-programmable ASIC devices. The 384 logic cell field-

programmable gate array (FPGA) offers 4,000 usable ASIC gates

(equivalent to 7,000 PLD gates) of high-performance general-purpose

logic in 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA, and

160-pin CQFP.

Low-impedance, metal-to-metal, ViaLink interconnect technology

provides nonvolatile custom logic capable of operating above 150 MHz.

Logic cell delays under 2 ns, combined with input delays of under 1.5 ns

and output delays under 3 ns, permit high-density programmable devices

to be used with today’s fastest microprocessors and DSPs.

Designs can be entered using QuickLogic’s QuickWorks Toolkit or most

populart third-party CAE tools. QuickWorks combines Verilog/VHDL

design entry and simulation tools with device-specific place & route and

programming software. Ample on-chip routing channels allow fast, fully

automatic place and route of designs using up to 100% of the logic and

I/O cells, while maintaining fixed pin-outs.

Total of 122 I/O pins

– 114 Bidirectional Input/Output pins

– 6 Dedicated Input/High-Drive pins

– 2 Clock/Dedicated input pins with fanout-independent, low-skew

clock networks

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of logic and I/O cells

and functional testing with Automatic Test Vector Generation

(ATVG) software after programming

Packages are 84-pin PLCC, 100-pin and 144-pin TQFP, 144-pin

CPGA, and 160-pin CQFP

84-pin PLCC compatible with QL12x16B

100-pin TQFP compatible with QL8x12B and QL12x16B

144-pin TQFP compatible with QL24x32B

0.65µ CMOS process with ViaLink programming technology

FEATURES

PRODUCT

SUMMARY

QL16x24B

4-23

pASIC 1

4

Pinout

Diagram

84-pin PLCC

Pinout

Diagram

100-pin TQFP