Quatech RS-422, MPA-200, MPA-300, RS-485 User Manual
MPA-200/300
RS-422/485 SYNCHRONOUS
ADAPTER CARD
for ISA compatible machines
INTERFACE CARDS FOR IBM PC/AT AND PS/2
User's Manual
QUATECH, INC. TEL: (330) 655-9000
5675 Hudson Industrial Parkway FAX: (330) 655-9010
Hudson, Ohio 44236 http://www.quatech.com
Warranty Information
Quatech Inc. warrants the MPA-200/300 to be free of defects for
one (1) year
adapter that fails to perform under normal operating conditions and in accordance
with the procedures outlined in this document during the warranty period. Any
damage that results from improper installation, operation, or general misuse voids
all warranty rights.
The authors have taken due care in the preparation of this document and any
associated software program(s). In no event will Quatech Inc. be liable for
damages of any kind, incidental or consequential, in regard to or arising out of the
performance or form of the materials presented herein and in the program(s)
accompanying this document. No representation is made regarding the suitability
of this product for any particular purpose.
Quatech Inc. reserves the right to edit or append to this document or the product(s)
to which it refers at any time and without notice.
Please complete the following information and retain for your records. Have this
information available when requesting warranty service.
from the date of purchase. Quatech Inc. will repair or replace any
Date of purchase:
Model Number:
Serial Number:
MPA-200/300
Single Channel RS-232 SynchronousProduct Description:
Communication ISA Adapter
Quatech Inc., MPA-200/300 Manual
The information contained in this document cannot be reproduced in any form
without the written consent of Quatech, Inc. Likewise, any software programs
that might accompany this document can be used only in accordance with any
license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc.
reserves the right to change this documentation or the product to which it refers at
any time and without notice.
The authors have taken due care in the preparation of this document and every
attempt has been made to ensure its accuracy and completeness. In no event will
Quatech, Inc. be liable for damages of any kind, incidental or consequential, in
regard to or arising out of the performance or form of the materials presented in
this document or any software programs that might accompany this document.
Quatech, Inc. encourages feedback about this document. Please send any written
comments to the Technical Support department at the address listed on the cover
page of this document.
Copyright ©2004 by
Quatech Inc.
5675 Hudson Industrial Parkway
Hudson, Ohio 44236
All rights reserved. Printed in the U.S.A.
Quatech Inc, MPA-200/300 Manual
Compliances - Electromagnetic Emissions
EC - Council Directive 89/336/EEC
This equipment has been tested and found to comply with the limits of the
following standards for a digital device:
EN50081-1 (EN55022, EN60555-2, EN60555-3)
EN50082-1 (IEC 801-2, IEC 801-3, IEC 801-4)
Type of Equipment: Information Technology Equipment
Equipment Class: Commercial, Residential, & Light Industrial
FCC - Class B
This equipment has been tested and found to comply with the limits for a Class B
digital device, pursuant to part 15 of the FCC Rules. These limits are designed to
provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency
energy and if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee
that interference will not occur in a particular installation, If this equipment does
cause harmful interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to
correct the interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to
which the receiver is connected.
Consult the dealer or an or an experienced radio/TV technician for help.
This equipment has been certified to comply with the limits for a Class B
computing device, pursuant to FCC Rules. In order to maintain compliance with
FCC regulations, shielded cables must be used with this equipment. Operation
with non-approved equipment or unshielded cables is likely to result in
interference to radio and TV reception. The user is cautioned that changes and
modifications made to the equipment without the approval of the manufacturer
could void the user's authority to operate this equipment.
Quatech Inc., MPA-200/300 Manual
TABLE OF CONTENTS
1 INTRODUCTION
2 HARDWARE INSTALLATION
3 SCC GENERAL INFORMATION
3.1 Accessing the registers ...................................
3.2 Baud Rate Generator Programming .....................
3.3 SCC Data Encoding Methods ............................
4 JUMPER BLOCK CONFIGURATIONS
4.1 J4 - Interrupt Configuration .............................
4.2 J5 & J6 - Interrupt Level Selection .......................
4.3 J10 - Transmit DMA Channel Selection ....................
4.4 J11 - Receive DMA Channel Selection .....................
4.5 J7 - Line Driver Control Selection ........................
4.6 J8 - SYNCA to RLEN control ............................
5 ADDRESSING
6 INTERRUPTS
7 DIRECT MEMORY ACCESS
7.1 Using Terminal Count to Generate an Interrupt .............
8 CONFIGURATION REGISTER
9 COMMUNICATIONS REGISTER
10 DTE / DCE Configuration
10.1 DTE Configuration ...................................
10.2 DCE Configuration ...................................
11 EXTERNAL CONNECTIONS
11.1 MPA-200 and EIA-530 Compatibility ....................
11.2 Null-Modem Cables ...................................
12 DEFINITION OF INTERFACE SIGNALS
13 SPECIFICATIONS
.......................................
.........................
......................
................
.........................................
.........................................
..........................
.......................
.....................
.............................
........................
...........
...................................
2
4
5
6
9
10
11
11
11
12
13
13
14
15
17
18
20
21
23
25
26
27
29
32
32
33
37
Quatech Inc., MPA-200/300 Manual
3 Quatech Inc., MPA-200/300 Manual
1 INTRODUCTION
The Quatech MPA-200/300 is a single channel, synchronous serial communication port for systems utilizing the architecture of the IBM AT personal or compatible computers. The MPA-200 is RS-422 compatible.
The MPA-300 has RS-485 data line drivers and receivers in place of the
MPA-200's RS-422 drivers and receivers. The MPA-300's RS-485 interface will
allow multiple systems to be connected in a multi-drop configuration. Hereafter,
the MPA-200 and MPA-300 will be collectively referred to as the MPA-200
except where noted.
The ports of the MPA-200 occupy an 8 byte block of I/O address space. The base
address of this block may be located anywhere within the available I/O address
space of the system.
The MPA-200 is available with a variety of serial communications controlers
(SCC). All of the available SCC's can support asynchronous formats, byteoriented protocols such as IBM Bisync, and bit-oriented protocols such as HDLC
and IBM SDLC. The SCC's also offer internal functions such as on-chip baud rate
generators, and digital phase-lock loops (DPLL).
The MPA-200 also supports Direct Memory Access (DMA) and interrupts. DMA
channels 1 - 3 can be used for high data transfer rates, while interrupt levels 2 - 7,
10 - 12, and 14 - 15 are available for several interrupt sources.
On the MPA-200, communications is controlled by the SCC labeled U17. There
are seven jumper blocks on the MPA-200 that allow the user to select such
options as DMA channels, interrupt levels and driver control. If the MPA-200 is
configured for data terminal equipment (DTE), external connections are made
through a male D-25 connector CN2. If the MPA-200 is configured for data
communications equipment (DCE), external connections are made through a a
female D-25 connector CN1. These configurations are determined when the board
is manufactured, prior to shipment.
On the MPA-200, the driver circuit consists of one RS-422 driver (U18), one
RS-422 receiver (U26), four RS-422/485 transceivers (U19, U20, U22, U23), two
RS-423 drivers (U24, U25). Each differential pair that is received by the
MPA-200 has a 100 ohm termination resistor.
On the MPA-300, the driver circuit consists of one RS-485 driver (U19), one
RS-485 receiver (U26), four RS-422/485 transceivers (U19, U20, U22, U23), two
RS-423 drivers (U24, U25). Each differential pair that is received by the
MPA-300 has a 150 ohm termination resistor.
Quatech Inc., MPA-200/300 Manual 2
Figure 1 MPA-200 board drawing
Quatech, Inc.
U29
MPA-200
U4
U5
U1
U2
SW1 SW2
U3
J4
U6
U7
U8
J5 J6
U9
U10
U11
U12
U13
U14
U15
J7
X1
U28
U17
U23
J10
J11
U16
J8
U18
U19
U20
U22
U26
CN2CN1
U24
U25
U21
3 Quatech Inc., MPA-200/300 Manual
2 HARDWARE INSTALLATION
If the default address and interrupt settings are sufficient, the MPA-200 can be
quickly installed and put to use. The factory default settings are listed below in
Table 1.
Table 1 Default Board Configuration
RxDMATxDMAInterruptAddress
DMA/DRQ 1DMA/DRQ 3IRQ 5300 hex
1. If the default settings are correct, skip to step 2, otherwise refer to the
chapters ADDRESSING on page 15, INTERRUPTS on page 17, and
DIRECT MEMORY ACCESS on page 18 for detailed information on
how to set the address, IRQ, and DMA levels.
2. Turn off the power of the computer system in which the MPA-200 is
to be installed.
3. Remove the system cover according to the instructions provided by the
computer manufacturer.
4. Install the MPA-200 in any vacant expansion slot. The board should
be secured by installing the Option Retaining Bracket (ORB) screw.
5. Replace the system cover according to the instructions provided by the
computer manufacturer.
6. Attach and secure the cable connectors to the desired equipment.
Quatech Inc., MPA-200/300 Manual 4
3 SCC GENERAL INFORMATION
The Serial Communications Controller (SCC) is a dual channel, multi-protocol
data communications peripheral. The MPA-200 provides a single channel for
communications, however, to provide full DMA capabilities, both channels of the
SCC can be utilized. The SCC can be software configured to satisfy a wide
variety of serial communications applications. Some of its protocol capabilities
include:
1) Asynchronous Communications
5, 6, 7, or 8 bits per character
1, 1-1/2, or 2 stop bits
Odd, even, or no parity
Times 1, 16, 32, or 64 clock modes
Break generation and detection
Parity, overrun and framing error detection
2) Byte-oriented Synchronous Communications
Internal/external character synchronization
1 or 2 sync characters in separate registers
Automatic Cyclic Redundancy Check (CRC) generation/detection
3) SDLC/HDLC (Bit Synchronous) Communications
Abort sequence generation and checking
Automatic zero insertion and deletion
Automatic flag insertion between messages
Address field recognition
I-field residue handling
CRC generation and detection
SDLC loop mode with EOP recognition/loop entry and exit
4) NRZ, NRZI, or FM encoding/decoding
5 Quatech Inc., MPA-200/300 Manual
3.1 Accessing the registers
The mode of communication desired is established and monitored through the bit
values of the internal read and write registers. The register set of the SCC includes
16 write registers and 9 read registers. These registers only occupy four address
locations, which start at the MPA-200's physical base address that is configured
via the on board switches. This and all other addresses are referenced from this
base address in the form Base + Offset. An example of this is Base + 1 for the
SCC Control Port, Channel A.
There are two register locations per SCC channel, a data port and a control port .
Accessing the internal SCC registers is a two step process that requires loading a
register pointer to perform the addressing to the correct data register. The first
step is to write to the control port the operation and address for the appropriate
channel. The second step is to either read data from or write data to the control
port. The only exception to this rule is when accessing the transmit and receive
data buffers. These registers can be accessed with the two step process described
or with a single read or write to the data port. The following examples illustrate
how to access the internal registers of the SCC. Also, Table 2 SCC read register
description describes the read registers and Table 3 SCC write register description describes the write registers for each channel.
The MPA-200 has been designed to assure that all back to back access timing
requirements of the SCC are met without the need for any software timing
control. The standard of adding jmp $+2 between IO port accesses is not required
when accessing the MPA-200.
Example 1: Enabling the transmitter on channel A.
mov dx,base ; load base address
add dx,ContA ; add control reg A offset
mov al,05h ; write the register number
out dx,al ;
mov al,08h ; write the data to the register
out dx,al
Example 2: Monitoring the status of the transmit and receive buffers in RR0
of Channel A. Register 0 is addressed by default if no register
number is written to WR0
mov dx,base ; load base address
add dx,ContA ; add control reg A offset
in al,dx ; read the status
Quatech Inc., MPA-200/300 Manual 6
Example 3: Write data into the transmit buffer of channel A.
mov dx,base ; load base address
out dx,al ; write data in ax to buffer
Example 4: Read data from the receive buffer of channel A.
mov dx,base ; load base address
in al,dx ; write data in ax to buffer
Table 2 SCC read register description.
Transmit, Receive buffer statuses and external status RR0
Special Receive Condition status, residue codes, error conditions RR1
RR2
The SCC can perform three basic forms of I/O operations: polling, interrupts, and
block transfer. Polling transfers data, without interrupts, by reading the status of
RR0 and then reading or writing data to the SCC buffers via CPU port accesses.
Interrupts on the SCC can be sourced from the receiver, the transmitter, or
External/Status conditions. At the event of an interrupt, Status can be determined,
then data can be written to or read from the SCC via CPU port accesses. For
block transfer mode, DMA transfers accomplish data transfers from the SCC to
memory or from memory to the SCC, interrupting the CPU only when the Block
is finished. Further information on these subjects are found in the chapters titled
INTERRUPTS, and DIRECT MEMORY ACCESS.
Modified Channel B interrupt vector and Unmodified Channel A
interrupt vector
Interrupt Pending bits RR3
LSB of frame byte count register RR6
MSB of frame byte count and FIFO status registerRR7
Receive buffer RR8
Miscellaneous status parameters RR10
Lower byte of baud rate time constantRR12
Upper byte of baud rate time constantRR13
External/Status interrupt information RR15
The SCC incorporates additional circuitry supporting serial communications. This
circuitry includes clocking options, baud rate generator (BRG), data encoding, and
internal loopback. The SCC may be programmed to select one of several sources
to provide the transmit and receive clocks. These clocks can be programmed in
WR11 to come from the RTXC pin, the TRXC pin, the output of the BRG, or the
transmit output of the DPLL. The MPA-200 uses the TRXC pin for its transmit
7 Quatech Inc., MPA-200/300 Manual
clock (TCLK) and the RTXC pin for its receive clock (RCLK). Programming of
the clocks should be done before enabling the receiver, transmitter, BRG, or
DPLL.
Table 3 SCC write register description.
WR0
WR4
WR10
Command Register, Register Pointer, CRC initialization, resets for
various modes
Interrupt control, Wait/DMA request controlWR1
Interrupt vectorWR2
Receiver initialization and control WR3
Transmit/Receive miscellaneous parameters and codes, clock rate,
stop bits, parity
Transmitter initialization and control WR5
Sync character (1st byte) or SDLC address field WR6
Sync character (2nd byte) or SDLC FlagWR7
HDLC enhancement registerWR7'
Transmit bufferWR8
Master interrupt control and reset WR9
Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM
coding, CRC reset
Clock mode and source controlWR11
Lower byte of baud rate time constant WR12
Lower byte of baud rate time constant WR13
WR14
Quatech Inc., MPA-200/300 Manual 8
Miscellaneous control bits: baud rate generator, DPLL control, auto
echo
External/Status interrupt control WR15
Loading...