Quatech ES-3000 Owner's Manual

WARRANTY INFORMATION

Quatech Inc. warrants the ES-2000/ES-3000 free of defects for one purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Quatech Inc. assumes no liability for damages resulting from errors in this document. Quatech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: ES-2000/ES-3000

PRODUCT DESCRIPTION: EIGHT

(1) year from the date of

CHANNEL RS-422/RS-485

to be

ASYNC.

SERIAL NUMBER:

IBM PC/XT/ATTM, PS/2TM, and Micro ChannelTM are trademarks of International Business Machines.

COMMUNICATIONS ADAPTER

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TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16552 FUNCTIONAL DESCRIPTION . . . . . . . . 3

INTERRUPT ENABLE REGISTER . . . . . . . . 4

INTERRUPT IDENTIFICATION REGISTER . . . . 5

FIFO CONTROL REGISTER . . . . . . . . . . 7

LINE CONTROL REGISTER . . . . . . . . . . 8

MODEM CONTROL REGISTER . . . . . . . . . 10

LINE STATUS REGISTER . . . . . . . . . . 11

MODEM STATUS REGISTER . . . . . . . . . . 13

ALTERNATE FUNCTION REGISTER . . . . . . . 14

SCRATCHPAD REGISTER . . . . . . . . . . . 14

IV. FIFO MODE OPERATION . . . . . . . . . . . . 15

FIFO INTERRUPT OPERATION . . . . . . . . 15

FIFO POLLED OPERATION . . . . . . . . . . 15

V. BAUD RATE SELECTION . . . . . . . . . . . . 16

VI. ADDRESSING . . . . . . . . . . . . . . . . . 18

VII. INTERRUPTS . . . . . . . . . . . . . . . . . 18

INTERRUPT STATUS REGISTER . . . . . . . . 19

VIII. PROGRAMMABLE OPTION SELECT . . . . . . . . . 20

IX. OUTPUT CONFIGURATIONS . . . . . . . . . . . 22

AUXILIARY CHANNEL CONFIGURATION . . . . . 22

HALF DUPLEX OPERATION . . . . . . . . . . 23

X. EXTERNAL CONNECTIONS . . . . . . . . . . . . 25

XI. HARDWARE INSTALLATION . . . . . . . . . . . 26

XII. ADDITIONAL ADDRESSING . . . . . . . . . . . 27

XIII. SPECIFICATIONS . . . . . . . . . . . . . . . 32

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LIST OF FIGURES

Figure 1. ES-2000/ES-3000 board layout . . . . . 2

Figure 2. 16552 register map . . . . . . . . . . 3

Figure 3. Interrupt identification register . . 6

Figure 4. FIFO receiver trigger levels . . . . . 7

Figure 5. Parity options . . . . . . . . . . . . 9

Figure 6. Word length and stop bit options . . . 9

Figure 7. Multi-function output pin control . . 14

Figure 8. Input clock frequency options . . . . 16

Figure 9. Baud rate selections . . . . . . . . . 17

Figure 10. Baud rate selections . . . . . . . . . 17

Figure 11. ES-2000/ES-3000 address assignments . 18

Figure 12. Interrupt selections . . . . . . . . . 20

Figure 13. ES-2000/ES-3000 POS implementation . . 21

Figure 14. Auxiliary channel control jumpers . . 22

Figure 15. Half duplex operation control jumper . 23

Figure 16. Output control block diagram . . . . . 24

Figure 17. Output control block diagram . . . . . 24

Figure 18. Output connector . . . . . . . . . . . 25

Figure 19. Output connector signal definitions . 25

Figure 20. QTINSTAL.EXE opening menu . . . . . . 28

Figure 21. QTINSTAL.EXE address selection menu . 29

Figure 22. QTINSTAL.EXE address input . . . . . . 30

Figure 23. QTINSTAL.EXE updated address menu . . 31

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INTRODUCTION

I. INTRODUCTION

The Quatech ES-2000 provides eight independent asynchronous RS-422 serial communication channels for systems utilizing the MicroChannel architecture. The ES3000 is an RS-485 version of the adapter. The eight ports of the ES-2000/ES-3000 occupy a contiguous 64 byte block of I/O address space. The base address of this block may be located anywhere within the available I/O address range of the system.

The ES-2000/ES-3000 serial interfaces are realized through four 16552 DUARTs (Dual Universal Asynchronous Receiver / Transmitters). The 16552 is a two channel version of the 16550 used in the IBM PS/2 family of personal computers and is compatible with the 8250 and 16450 UARTs used in the PC/XT/AT models. In addition, the 16550 and 16552 support transmit and receive FIFOs to reduce CPU overhead at higher data rates.

Address and interrupt selections are accessed through the Programmable Option Select using the IBM installation utilities. In addition, jumpers are provided to select input clock frequency and to control the information exchanged on the auxiliary channels.

II. BOARD

DESCRIPTION

A component diagram of the ES-2000/ES-3000 showing the locations of the 16552 DUARTs, clock frequency jumper, auxiliary channel control jumpers, and D-62 output connector is shown in figure 1. Channels 1 and 2 are contained in the DUART labeled U4, channels 3 and 4 in U9, 5 and 6 in U14, and 7 and 8 in U19. Channels 1 - 4 of the ES-2000/ES-3000 also have an auxiliary channel available for exchange of the RTS-CTS handshake pair. The auxiliary channels are controlled by jumpers J2 - J5 respectively. The input clock frequency for all channels is selected using jumper J1. All channels are output via the high density D-62 connector CN1.

On the ES-2000, the driver circuit consists of four RS422 drivers (U20, U21, U24, and U26), three RS-422 receivers (U25, U27, and U28) and twelve 100_ termination resistors (R2 - R13). On the ES-3000, these are replaced by RS-485 drivers and receivers and 120_ termination resistors.

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FUNCTIONAL DESCRIPTION

Figure 1. ES-2000/ES-3000 board layout.

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FUNCTIONAL DESCRIPTION

III. 16552 FUNCTIONAL DESCRIPTION

The 16552 is two channel version of the 16550 Universal Asynchronous Recevier / Transmitter (UART). The two channels are completely independent except for the common clock oscillator input. Each channel of the 16552 enters character mode after reset and in this mode appears as a 16450 to application software. An additional FIFO mode can be selected to reduce CPU overhead at high data rates. The FIFO mode increases performance by providing two internal 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features include: Programmable baud rate, character length, parity, and number of stop bits Automatic addition and removal of start, stop, and parity bits Independent and prioritized transmit, receive and status interrupts Transmitter clock output to drive receiver logic

The following pages provide a brief summary of the internal registers available for each channel of the 16552 DUART. The registers are addressed as shown in figure 2 below.

+---------------+----------------------------------------+ | DLAB A2 A1 A0 | REGISTER DESCRIPTION | +---------------+----------------------------------------+ | 0 0 0 0 | Receive buffer (read only) | | | Transmit holding register (write only) | | 0 0 0 1 | Interrupt enable | | 0 0 1 0 | Interrupt identification (read only) | | | FIFO control (write only) | | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (least significant byte) | | 1 0 0 1 | Divisor latch (most significant byte) | | 1 0 1 0 | Alternate function | +---------------+----------------------------------------+

Figure 2. Register map for one channel of the 16552 DUART. DLAB is accessed through the Line Control Register.

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FUNCTIONAL DESCRIPTION

INTERRUPT

ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmitter holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupt on overrun, parity, and framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupt on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupt on received data available or FIFO trigger level.

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FUNCTIONAL DESCRIPTION

INTERRUPT

+------+ D7 | FFE |--+ +------+ +-- FIFO enable D6 | FFE |--+ +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

FFE - FIFO Enable:

IIDx - Interrupt Identification:

IDENTIFICATION REGISTER

When logic 1, indicates FIFO mode enabled.

Indicates highest priority interrupt pending if any. See IP and figure 3. NOTE: IID2 is always a logic 0 in character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and figure 3.

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FUNCTIONAL DESCRIPTION

Figure 3. Interrupt identification bit definitions.

Receiver Line Status:

Indicates overrun, parity, or framing errors or break interrupts. The interrupt is cleared by reading the line status register.

Received Data Ready:

Indicates receiver data available. The interrupt is

cleared by reading the receiver buffer register FIFO mode: Indicates the receiver FIFO trigger level has been

reached. The interrupt is reset when the FIFO drops

below the the trigger level.

Character Timeout: (FIFO mode only)

Indicates no characters have been removed from or

input to the receiver FIFO for the last four

character times and there is at least one character

in the FIFO during this time. The interrupt is

cleared by reading the receiver FIFO.

Transmitter Holding Register Empty:

Indicates the transmitter holding register is empty.

The interrupt is cleared by reading the interrupt

identification register or writing to the

transmitter holding register.

MODEM Status:

Indicates clear to send, data set ready, ring

indicator, or data carrier detect have changed

state. The interrupt is cleared by reading the

MODEM status register.

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FUNCTIONAL DESCRIPTION

FIFO

CONTROL REGISTER

+------+ D7 | RXT1 |--+ +------+ +-- Receiver trigger D6 | RXT0 |--+ +------+ D5 | x |--+ +------+ +-- Reserved D4 | x |--+ +------+ D3 | DMAM |----- DMA mode select +------+ D2 | XRST |----- Transmit FIFO reset +------+ D1 | RRST |----- Receive FIFO reset +------+ D0 | FE |----- FIFO enable +------+

RXTx - Receiver FIFO Trigger Level:

Determines the trigger level for the FIFO interrupt

as given in figure 4 below.

+-----------+-----------------------+ | | RCVR FIFO | | RXT1 RXT0 | Trigger level (bytes) | +-----------+-----------------------+ | 0 0 | 1 | | 0 1 | 4 | | 1 0 | 8 | | 1 1 | 14 | +-----------+-----------------------+

Figure 4. FIFO trigger levels.

DMAM - DMA Mode Select:

When set (logic 1), RxRDY and TxRDY change from mode

0 to mode 1. (DMA mode is not supported on the ES-

2000/ES-3000.)

XRST - Transmit FIFO Reset:

When set (logic 1), all bytes in the transmitter

FIFO are cleared and the counter is reset. The

shift register is not cleared. XRST is self-

clearing.

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FUNCTIONAL DESCRIPTION

RRST - Receive FIFO Reset:

When set (logic 1), all bytes in the receiver FIFO

are cleared and the counter is reset. The shift

register is not cleared. RRST is self-clearing.

FE - FIFO Enable:

When set (logic 1), enables transmitter and receiver

FIFOs. When cleared (logic 0), all bytes in both

FIFOs are cleared. This bit must be set when other

bits in the FIFO control register are written to or

the bits will be ignored.

LINE

CONTROL REGISTER

+------+ D7 | DLAB |----- Divisor latch access bit +------+ D6 | BKCN |----- Break control +------+ D5 | STKP |----- Stick parity +------+ D4 | EPS |----- Even parity select +------+ D3 | PEN |----- Parity enable +------+ D2 | STB |----- Number of stop bits +------+ D1 | WLS1 |--+ +------+ +-- Word length select D0 | WLS0 |--+ +------+

DLAB - Divisor Latch Access Bit:

DLAB must be set to logic 1 to access the baud rate

divisor latches and the alternate function register.

DLAB must be logic 0 to access the receiver buffer,

transmitting holding register and interrupt enable

register.

BKCN - Break Control:

When set (logic 1), the serial output (SOUT) is

forced to the spacing state (logic 0).

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