Quatech DSCLP-200, DSCLP-300, SSCLP-300, SSCLP-200 User Manual

DSCLP/SSCLP-200/300
Two and One Channel RS-422/485
Low Profile Asynchronous
Communications Adapter
for PCI bus
User's Manual
QUATECH, INC. TEL: (330) 655-9000 5675 Hudson Industrial Parkway FAX: (330) 655-9010 Hudson, Ohio 44236 http://www.quatech.com
WARRANTY INFORMATION
Quatech, Inc. warrants the DSCLP-200/300 or SSCLP-200/300 to be
free of defects for five (5) years from the date of purchase. Quatech, Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.
Please complete the following information and retain for your records.
Have this information available when requesting warranty service.
DATE OF PURCHASE:
MODEL NUMBER: DSCLP-200/300 or SSCLP-200/300
PRODUCT DESCRIPTION: DSCLP: Two Channel RS-422/485 Asynchronous
PCI Bus Communications Adapter SSCLP: One Channel RS-422/485 Asynchronous PCI Bus Communications Adapter
SERIAL NUMBER:
DSCLP/SSCLP-200/300 User's Manual ii
2006 Quatech, Inc.
NOTICE
The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice.
The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness. In no event will Quatech, Inc. be liable for damages of any kind, incidental or consequential, in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document.
Quatech, Inc. encourages feedback about this document. Please send any written comments to the Technical Support department at the address listed on the cover page of this document.
DOS, Windows 95, Windows NT are trademarks or registered trademarks of Microsoft Corporation. OS/2 is a registered trademark of IBM Corporation. All other trademarks or
registered trademarks are property of their respective owners.
DSCLP/SSCLP-200/300 User's Manual iii
Declaration of Conformity
Manufacturer's Name: Quatech Inc.
Manufacturer's Address: 5675 Hudson Industrial Parkway
Hudson, Ohio 44236 (USA)
Application of Council Directive: 89/336/EEC
Standards to which Conformity is Declared: * EN50081-1 (EN55022,
EN60555-2, EN60555-3) * EN50082-1 (IEC 801-2, IEC 801-3, & IEC 801-4)
Type of Equipment: Information Technology
Equipment
Equipment Class: Commercial, Residential, & Light Industrial
Product Name: PCI Two Port or One Port Serial
Communications Card
Model Number : DSCLP-200/300 / SSCLP-200/300
DSCLP/SSCLP-200/300 User's Manual iv
Table of Contents
1 General Information 2 Hardware Configuration
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.........................
2.1 RS-422 or RS-485 Signal Line Termination
2.2 Signal Connections
2.3 Full-duplex/Half-duplex Operation
2.3.1 CTS0_SEL, CTS1_SEL (J10, 17)
.................................
..................
.................
2.3.2 AUX0_SEL1,0, AUX1_SEL1,0 (J12, 11, 19, 18)
2.3.3 RCLK0_SEL, RCLK1_SEL (J13, 20)
............
2.3.4 TGL0_SEL1,0, TGL1_SEL1,0 (J15, 14, 22, 21)
2.3.5 RXEN0_SEL, RXEN1_SEL (J16, 23)
2.4 Clock Rate and Optional Registers
..................
............
2.4.1 Enable Scratchpad Register (SPAD, J2)
2.4.2 Force High-Speed UART Clock (X2, X4, or X8; J3, 4, 5)
3 Hardware Installation
...............................................
...........................
4 Address Map and Special Registers
4.1 Base Address and Interrupt Level (IRQ)
4.2 Enabling the Special Registers
4.3 Interrupt Status Register
............................
4.4 Quatech Modem Control Register
4.5 Options Register
....................................
......................
...................
4.5.1 Enhanced Serial Adapter Identification
4.5.2 Clock Rate Multiplier
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.............
...........
...
....
..........
...........
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8
9
9 10 10 12 12 12 12 12 13 13
13
15
16 16 17 17 18 19 19 20
5 Windows Configurations
5.1 Windows Millennium
5.2 Windows 2000
5.3 Windows 98
5.4 Windows 95
5.5 Windows NT
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........................................
........................................
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5.6 Viewing Resources with Device Manager
...............................
........................
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5.6.1 Changing Resource Settings with Device Manager
6 Other Operating Systems
v DSCLP/SSCLP-200/300 User's Manual
.......................
21 21 22 23 25 26 27
.
30
35
6.1 OS/2
...............................................
6.2 DOS and other operating systems
6.2.1 QTPCI.EXE
.....................................
...................
35 35 36
7 External Connections
7.1 RTS/cts Handshake
7.2 RCLK
7.3 TCLK
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..............................................
7.4 AUXIN/AUXOUT Loopback
.................................
............................
........................
7.5 Half-Duplex/Full-Duplex/Auto-Toggle Selection
7.6 Termination Resistors
7.7 RS-422/485 Peripheral Connection
8 PCI Resource Map 9 Specifications
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10 Troubleshooting
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38 39 39 40 40 41 43 44
45
46
47
vi DSCLP/SSCLP-200/300 User's Manual
DSCLP/SSCLP-200/300 User's Manual 7
1 General Information
The Quatech, Inc. DSCLP-200/300 (two-port) and SSCLP-200/300 (one-port) provide RS-422 or RS-485 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the PCI expansion bus. For general purposes, this manual usually makes reference only to the DSCLP-200/300. All information pertains equally to the SSCLP-200/300, with the exception that with the SSCLP there is just one port instead of two. The DSCLP-200/300 uses Quatech's new Enhanced Serial Adapter design. Legacy serial port data rates are limited to a maximum of 115,200 bits per second. Quatech Enhanced Serial Adapters can achieve data rates as high as 921,600 bits per second.
As a PCI device, the DSCLP-200/300 requires no hardware configuration. The card is automatically configured by the computer's BIOS or operating system. The two serial ports share a single interrupt line and are addressed in a contiguous block of 16 bytes. A special interrupt status register is provided to help software to manage the shared interrupt.
The DSCLP-200/300's serial ports are implemented using 16550 Universal Asynchronous Receiver/Transmitters (UARTs). These UARTs contain hardware buffers (FIFOs) which reduce processing overhead and allow higher data rates to be achieved. The 16550 contains a 16-byte FIFO and can transmit and receive data at a rate of up to 921,000 bits per second.
The DSCLP-200/300 is supported under several popular operating systems and environments. Contact the sales department for details on current software offerings. Most device drivers are available for download from the Quatech world wide web site at http://www.quatech.com.
DSCLP/SSCLP-200/300 User's Manual 8
2 Hardware Configuration
The DSCLP-200/300 is automatically configured at boot time by the computer's BIOS or operating system. There are no required switches or jumpers to set for installation.
This chapter lists a number of optional hardware features. Jumpers J1-J4, located in a column near the D-type connector (D-25 for DSCLP, D-9 for SSCLP), control the RS-422 or RS-485 signal line termination. Jumpers J5-J8, located in a column just to the right of J1-J4, control how signals are routed from the UARTs to the connector, as well as full- or half­duplex operation. Jumpers J10-J22, grouped together at the end of the board opposite the D-type connector (D-25 for DSCLP, D-9 for SSCLP), control special options.
Any changes from the factory default should be made before installing the DSCLP-200/300 in the computer. These settings can also be changed in Device Manager under Windows operating systems.
2.1 RS-422 or RS-485 Signal Line Termination
Jumpers J6-J9 allow the selection of 100-ohm RS-422 termination, 120-ohm RS-485 termination, or no termination at all. The factory default, shown in Figure 1, is RS-422 termination. For full details, see section 7.6.
jumper settings that control various
Jumpers J6-J9
2
1
RS-422 termination
(100 ohms)
(factory default)
Figure 1 --- Factory default signal termination settings
4
3
DSCLP/SSCLP-200/300 User's Manual 9
2.2 Signal Connections
The DSCLP-200/300 provides each of two serial ports with four differential signal pairs: TxD, RxD, AUXOUT, and AUXIN. TxD and RxD are always present at the connector. The AUXOUT and AUXIN signals can be used to support RTS/CTS handshaking, external clocking, or external signal loopback. The factory default configuration, as shown in Figure 2, is a loopback of AUXOUT to AUXIN at the connector, with RTS and CTS looped back on the board. There is an extensive discussion of this topic in section 7.
2.3 Full-duplex/Half-duplex Operation
The DTR or RTS modem control output of the UART can be used to enable and disable the transmit drivers. The inverse of these signals can also be used to enable and disable the receivers. These options are selectable per channel. The factory default, as shown in Figure 2, is for both the drivers and receivers of both channels to be continuously enabled. Two spare jumpers are installed in neutral positions. For details, refer to section 7.5.
The DSCLP-200/300 is shipped from the factory with each channel configured with No jumpers on J10-23. The following conditions occur: CTS=AUXIN, AUXOUT=RTS, RCLK=TCLK, TXEN=1 AND RXEN=1.
DSCLP/SSCLP-200/300 User's Manual 10
Jumpers J10-J23 define the options for this card:
J3
SPAD
J2
X8 J4 J5
J10 J11 J12
J13 J14 J15
J16 J17 J18
J19 J20 J21
X4
X2 CTS0_SEL AUX0_SEL0
AUX0_SEL1 RCLK0_SEL TGL0_SEL0
TGL0_SEL1 RXEN0_SEL
CTS1_SEL
AUX1_SEL0 AUX1_SEL1 RCLK1_SEL
TGL1_SEL0
J22
J23
TGL1_SEL1 RXEN1_SEL
Figure 2 - Right Card Edge Jumpers
DSCLP/SSCLP-200/300 User's Manual 11
2.3.1 CTS0_SEL, CTS1_SEL (J10, 17)
With NO jumpers on J10 or J17 the mode selection is CTS=AUXIN.
With Jumpers installed the mode selection is CTS=RTS.
2.3.2 AUX0_SEL1,0, AUX1_SEL1,0 (J12, 11, 19, 18)
With NO jumpers on J12 or J19 the mode selection is AUXOUT=RTS.
With Jumpers installed on J12 or J19 and NO jumpers installed on J11 or J18, the mode selection is AUXOUT=TCLK. With Jumpers installed on J12, J11 or J19, J18, the mode selection is AUXOUT=AUXIN.
2.3.3 RCLK0_SEL, RCLK1_SEL (J13, 20)
With NO jumpers on J13 or J20 the mode selection is RCLK=TCLK.
With Jumpers installed on J13 or J20 the mode selection is RCLK=AUXIN.
2.3.4 TGL0_SEL1,0, TGL1_SEL1,0 (J15, 14, 22, 21)
With NO jumpers on J15,14, or J22,21 the mode selection is TXEN=1.
With Jumpers installed on J14 or J21 and NO jumpers on J15 or J22, the mode selection is TXEN=DTR. With Jumpers installed on J15 or J22 and NO jumpers on J14 or J21, the mode selection is TXEN=RTS. With Jumpers installed on J15, J14 or J22, J21, the mode selection is TXEN=”Auto Toggle”.
2.3.5 RXEN0_SEL, RXEN1_SEL (J16, 23)
With NO jumpers on J16 or J23 the mode selection is RXEN=1. With
Jumpers installed on J16 or J23 the mode selection is RCLK=!TXEN.
DSCLP/SSCLP-200/300 User's Manual 12
2.4 Clock Rate and Optional Registers
Figure 3 shows the jumper configuration as shipped from the factory, with two spare jumpers applied in neutral positions. Remove one or both and apply as shown in following subsections to set optional features.
J3
SPAD
J2
X8 J4 J5
X4
X2
Figure 3 --- Factory default clock rate and options settings
2.4.1 Enable Scratchpad Register (SPAD, J2)
In the default configuration (see page 11), an Interrupt Status Register and an Options Register replace the scratchpad (base address + 7) of each UART. If the SPAD jumper is applied as in Figure 4, the UART scratchpad registers are enabled, and the Interrupt Status Register and the Options Register are not available.
J3
SPAD
J2
J4 J5
X8
X4
X2
Figure 4 --- Enable scratchpad registers
2.4.2 Force High-Speed UART Clock (X2, X4, or X8; J3, 4, 5)
These jumpers force an increase of the UART input clock frequency by a factor of two, four, or eight. This feature can allow legacy software to use baud rates above 115,200 bits per second. It is also useful if the serial port device driver does not directly support setting the higher baud rates through the Options Register (see section 4.5).
If one of these jumpers is applied, it overrides any value written to the Options Register to set the clock multiplier by software. The effective baud rate will be either two, four, or eight times the value for which the UART itself is programmed.
DSCLP/SSCLP-200/300 User's Manual 13
The factory default is none of these jumpers applied, which allows for software control of the clock multiplier via the Options Register. The Options Register powerup default is for a standard times-1 clock of 1.8432 MHz for compatibility with standard serial ports.
Figure 5 --- Clock multiplier jumper options
J3
SPAD
J2
X8
SPAD
SPAD
J4 J5
factory default
J3
J2
J4 J5
X8 mode
J3
J2
J4
X4
X2
X8 X4
X2
X8 X4
J5
X2
X4 mode
SPAD
J2
J4 J5
X8 X4
X2
J3
X2 mode
DSCLP/SSCLP-200/300 User's Manual 14
3 Hardware Installation
1. Turn off the power of the computer system in which the DSCLP-200/300 is to be installed.
2. Remove the system cover according to the instructions provided by the computer manufacturer.
3. Make any desired optional jumper setting changes.
4. Install the DSCLP-200/300 in any empty PCI expansion slot. The board should be secured by installing the Option Retaining Bracket (ORB) screw.
5. Replace the system cover according to the instructions provided by the computer manufacturer.
6. Attach and secure the cable connectors to the desired equipment.
7. Turn on the power of the computer system. The output of the DSCLP-200/300 is a 25-pin D-connector. A cable is
provided to convert the D-25 into two standard female D-9 connectors. Please see section 7.7 for a pin-out of the D-9 connector. The SSCLP-200/300 has a single D-9 connector.
Figure 6 --- Jumper/connector locations
DSCLP/SSCLP-200/300 User's Manual 15
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