Quatech DS-202 User Manual

WARRANTY INFORMATION

Quatech Inc. warrants the DS-202 to be free of defects for one

(1) year from the

/ DS-302

date of purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Quatech Inc. assumes no liability for damages resulting from errors in this document. Quatech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: DS-202

PRODUCT DESCRIPTION: DUAL ASYNCHRONOUS

/ DS-302

CHANNEL RS-422 / RS-485

COMMUNICATION BOARD

SERIAL NUMBER:

IBMTM, PC/XTTM, PC/ATTM, and PS/2TM are trademarks of International Business Machines.

i

TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16450/16550

*

FUNCTIONAL DESCRIPTION . . . . 1

INTERRUPT ENABLE REGISTER . . . . . . . . 4

INTERRUPT IDENTIFICATION REGISTER . . . . 5

FIFO CONTROL REGISTER

*

. . . . . . . . . 7

LINE CONTROL REGISTER . . . . . . . . . . 8

MODEM CONTROL REGISTER . . . . . . . . . 10

LINE STATUS REGISTER . . . . . . . . . . 11

MODEM STATUS REGISTER . . . . . . . . . . 13

SCRATCHPAD REGISTER . . . . . . . . . . . 14

FIFO INTERRUPT MODE OPERATION

*

. . . . . 14

IV. BAUD RATE SELECTION . . . . . . . . . . . . 14

V. ADDRESSING . . . . . . . . . . . . . . . . . 16

VI. INTERRUPTS . . . . . . . . . . . . . . . . . 18

VII. OUTPUT CONFIGURATIONS . . . . . . . . . . . 19

VIII. EXTERNAL CONNECTIONS . . . . . . . . . . . . 23

IX. INSTALLATION . . . . . . . . . . . . . . . . 24

X. SPECIFICATIONS . . . . . . . . . . . . . . . 24

*

with optional 16550.

i

INTRODUCTION

LIST OF FIGURES

Figure 1. DS-202/DS-302 board layout . . . . . . 2

Figure 2. 16450/16550

*

internal registers . . . 3

Figure 3. Interrupt source identification . . . 6

Figure 4. FIFO receiver trigger levels

*

. . . . 7

Figure 5. Parity options . . . . . . . . . . . . 9

Figure 6. Word length and stop bit options . . . 9

Figure 7. Input clock frequency selections . . . 15

Figure 8. Divisor latch options . . . . . . . . 15

Figure 9. Address selection switches . . . . . . 16

Figure 10. Address selection examples . . . . . . 17

Figure 11. Channel enable/disable selection . . . 17

Figure 12. System interrupt connection . . . . . 18

Figure 13. Interrupt mode selection . . . . . . . 18

Figure 14. Output control block diagram . . . . . 19

Figure 15. Auxiliary channel jumper definition . 20

Figure 16. Auxiliary channel signal selection . . 21

Figure 17. Half duplex control jumper . . . . . . 21

Figure 18. Output connector definition . . . . . 23

*

with optional 16550.

iii

INTRODUCTION

I. INTRODUCTION

The DS-202 is a dual channel RS-422 asynchronous serial communications adapter for systems implementing an ISA compatible I/O bus. Data is communicated through two shielded D-9 connectors which provide greater shielding from environmental noise. The DS-302 is an RS-485 version of the adapter.

The serial interface is implemented with a pair of 16450 Asynchronous Communication Elements (ACEs). The 16450 is compatible with the 8250 ACE found in the original IBM PC/XT models. The optional 16550 ACE provides an additional FIFO mode of operation which reduces CPU overhead at higher data rates.

The DS-202 / DS-302 allows independent addressing of each channel through a pair of address decode switches (SW1 and SW2). These switches allow each channel to be addressed in the I/O address range 0000H through 07FFH. Each channel is also capable of selecting and / or sharing one of six possible interrupt request lines (IRQ 2,3,4,5,6,7).

II. BOARD

DESCRIPTION

A component diagram of the DS-202 / DS-302 showing the locations of the 16450 ACEs, configuration jumpers, address selection switches, and output connectors is shown in figure 1. The first communication channel is controlled by the ACE labeled U7, switch SW1 for addressing, jumpers J2 and J5 for interrupt request selection, jumpers J7 and J8 for output signal control, and is output through connector CN1. The second channel is controlled by the ACE labeled U8, switch SW2 for addressing, jumpers J3 and J6 for interrupt request selection, jumpers J8 and J10 for output signal control, and is output through connector CN2.

III. 16450/16550

FUNCTIONAL DESCRIPTION

The 16450 is an improved specification version of the 8250 Asynchronous Communications Element (ACE) found in the original IBM PC and PC/XT systems and is functionally equivalent to the 8250. This ACE performs serial-to-parallel conversion on received data and parallel-to-serial conversion on data output from the CPU.

iii

Figure 1. DS-202 / DS-302 component layout.

FUNCTIONAL DESCRIPTION

Designed to be compatible with the 16450, the 16550 ACE enters character mode on reset and in this mode appears as a 16450 to application software. An additional mode, FIFO mode, can be invoked through software to reduce CPU overhead by providing two 16byte FIFOs (one transmit, one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features of the 16450/16550 include: Programmable baud rate, character length, parity, and number of stop bits. Automatic addition and removal of start, stop, and parity bits. Independent and prioritized transmit, receive and status interrupts.

The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs. The registers are addressed as shown in figure 2 below. Registers and functions specific to the optional 16550 are indicated with an asterisk (*).

*

(write only) | | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (LSB) | | 1 0 0 1 | Divisor latch (MSB) | +---------------+------------------------------+

Figure 2. Internal register map for 16450/16550 ACE.

DLAB is accessed through the Line Control Register.

*

with optional 16550.

FUNCTIONAL DESCRIPTION

INTERRUPT

ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmitter holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupts on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt: When set (logic 1), enables interrupts on

overrun, parity, framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupts on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupts on received data available or the receiver FIFO trigger level*.

*

with optional 16550.

FUNCTION AL DESCRIPTION

INTERRUPT IDENTIFICATION REGISTER

+------+ D7 | FFE |--+ +------+ +-- FIFO enable

*

D6 | FFE |--+ +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

FFE - FIFO Enable:

*

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if any. See IP and figure 3. NOTE: IID2 is always a logic 0 in the 16450 and in the 16550 character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and figure 3.

*

with optional 16550.

FUNCTIONAL DESCRIPTION

Figure 3. Interrupt Identification bit definitions.

Receiver Line Status:

Indicates overrun, parity, framing errors or break interrupts. The interrupt is cleared by reading the line status register.

*

|

Received Data Ready:

Indicates receive data available. The interrupt is cleared by reading the receive buffer.

FIFO mode:

*

Indicates the receiver FIFO trigger level has been reached. The interrupt is reset when the FIFO drops below the the trigger level.

Character Timeout: (FIFO mode only)

*

Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is at least one character in the receiver FIFO. The interrupt is cleared by reading the receiver FIFO.

Transmitter Holding Register Empty:

Indicates the transmitter holding register is empty. The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register.

MODEM Status: Indicates clear to send, data set ready, ring

indicator, or data carrier detect have changed state. The interrupt is cleared by reading the MODEM status register.

*

with optional 16550.

FUNCTION AL DESCRIPTION

FIFO CONTROL REGISTER

*

+------+ D7 | RXT1 |--+ +------+ +-- Receiver trigger D6 | RXT0 |--+ +------+ D5 | x |--+ +------+ +-- Reserved D4 | x |--+ +------+ D3 | DMAM |----- DMA mode select +------+ D2 | XRST |----- Transmit FIFO reset +------+ D1 | RRST |----- Receive FIFO reset +------+ D0 | FE |----- FIFO enable

*

+------+

RXTx - Receiver FIFO Trigger Level:

Determines the trigger level for the FIFO interrupt as given in figure 4 below.

*

+-----------+-----------------------+ | | RCVR FIFO | | RXT1 RXT0 | Trigger level (bytes) | +-----------+-----------------------+ | 0 0 | 1 | | 0 1 | 4 | | 1 0 | 8 | | 1 1 | 14 | +-----------+-----------------------+

Figure 4. FIFO trigger levels.

DMAM - DMA Mode Select:

*

When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1. (DMA mode is not supported by the DS-202 / DS-302.)

XRST - Transmit FIFO Reset:

*

When set (logic 1), all bytes in the transmitter

FIFO are cleared and the counter is reset. The shift register is not cleared. XRST is selfclearing.

*

with optional 16550.

FUNCTIONAL DESCRIPTION

RRST - Receive FIFO Reset:

*

When set (logic 1), all bytes in the receiver FIFO are cleared and the counter is reset. The shift register is not cleared. RRST is selfclearing.

FE - FIFO Enable:

*

When set (logic 1), enables transmitter and receiver FIFOs. When cleared (logic 0), all bytes in both FIFOs are cleared. This bit must be set when other bits in the FIFO control register are written to or the bits will be ignored.

LINE

CONTROL REGISTER

+------+ D7 | DLAB |----- Divisor latch access bit +------+ D6 | BKCN |----- Break control +------+ D5 | STKP |----- Stick parity +------+ D4 | EPS |----- Even parity select +------+ D3 | PEN |----- Parity enable +------+ D2 | STB |----- Number of stop bits +------+ D1 | WLS1 |--+ +------+ +-- Word length select D0 | WLS0 |--+ +------+

DLAB - Divisor Latch Access Bit:

DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register.

BKCN - Break Control:

When set (logic 1), the serial output (SOUT) is forced to the spacing state (logic 0).

*

with optional 16550.

FUNCTIONAL DESCRIPTION

STKP - Stick Parity:

Forces parity to logic 1 or logic 0 if parity is enabled. See EPS, PEN, and figure 5.

EPS - Even Parity Select:

Selects even or odd parity if parity is enabled. See STKP, PEN, and figure 5.

PEN - Parity Enable:

Enables parity generation on transmission and verification on reception. See EPS, STKP, and figure 5.

+--------------+---------+ | STKP EPS PEN | Parity | +--------------+---------+ | x x 0 | None | | 0 0 1 | Odd | | 0 1 1 | Even | | 1 0 1 | Logic 1 | | 1 1 1 | Logic 0 | +--------------+---------+

Figure 5. 16450/16550 parity selections.

STB - Number of Stop Bits:

Defines the number of stop bits per character.

See WLSx and figure 6.

WLSx - Word Length Select:

Defines the number of data bits per character.

See STB and figure 6.

+---------------+-------------+-----------+ | STB WLS1 WLS0 | Word length | Stop bits | +---------------+-------------+-----------+ | 0 0 0 | 5 bits | 1 | | 0 0 1 | 6 bits | 1 | | 0 1 0 | 7 bits | 1 | | 0 1 1 | 8 bits | 1 | | 1 0 0 | 5 bits | 1½ | | 1 0 1 | 6 bits | 2 | | 1 1 0 | 7 bits | 2 | | 1 1 1 | 8 bits | 2 | +---------------+-------------+-----------+

Figure 6. Word length and stop bit selections.

FUNCTIONAL DESCRIPTION

MODEM

CONTROL REGISTER

+------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | LOOP |----- Loopback enable +------+ D3 | OUT2 |----- Output 2 +------+ D2 | OUT1 |----- Output 1 +------+ D1 | RTS |----- Request to send +------+ D0 | DTR |----- Data terminal ready +------+

LOOP - Loopback Enable:

When set (logic 1), the transmitter shift register is internally connected to the receiver shift register, the MODEM control inputs are internally connected to the MODEM control outputs, and the outputs are forced to their inactive state. Transmit and receive interrupts operate normally but MODEM control interrupts are now controlled through the MODEM control register.

Bits OUT2, OUT1, RTS, and DTR perform identical functions on their respective outputs. When these bits are set (logic 1) in the register, the associated output is forced to a logic 0. When cleared (logic 0), the output is forced to a logic1.

OUT2 - Output 2: Controls the OUT2 output as described above.

Used for interrupt enable, see section VI.

OUT1 - Output 1:

Controls the OUT1 output as described above. OUT1 is unused on the DS-202 / DS-302.

RTS - Request To Send:

Controls the RTS output as described above. Used for output driver control, see section VII.

DTR - Data Terminal Ready:

Controls the DTR output as described above.

Used for output driver control, see section VII.

FUNCTIONAL DESCRIPTION

LINE STATUS REGISTER

FFRX - FIFO Receiver Error:

*

Always logic 0 in the 16450 and in the 16550 character mode.

FIFO mode:

*

Indicates one or more parity errors, framing errors, or break indications in the receiver FIFO. FFRX is reset by reading the line status register.

*

TEMT - Transmitter Empty:

Indicates the transmitter holding register (or FIFO) and the transmitter shift register are empty and are ready to receive new data. TEMT is reset by writing a character to the transmitter holding register.

THRE - Transmitter Holding Register Empty:

Indicates the transmitter holding register (or FIFO) is empty and it is ready to accept new data. THRE is reset by writing data to the transmitter holding register (or FIFO).

*

with optional 16550.

FUNCTIONAL DESCRIPTION

Bits BI, FE, PE, and OE are the sources of receiver line status interrupts. These bits are reset by reading the line status register. In FIFO mode*, these bits are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO.

BI - Break Interrupt:

Indicates the receive data input has been in the spacing state (logic 0) for longer than one full word transmission time.

FIFO mode:

*

Only one zero character is loaded into the FIFO and transfers are disabled until SIN goes to the mark state (logic 1) and a valid start bit is received.

FE - Framing Error:

Indicates the received character had an invalid stop bit. The stop bit following the last data or parity bit was a 0 bit (spacing level).

PE - Parity Error:

Indicates that the received data does not have the correct parity.

OE - Overrun Error:

Indicates the receive buffer was not read before the next character was received and the character is destroyed.

FIFO mode:

*

Indicates the FIFO is full and another character has been shifted in. The character in the shift register is destroyed but is not transferred to the FIFO.

DR - Data ready:

Indicates data is present in the receive buffer or FIFO. DR is reset by reading the receive buffer register or receiver FIFO.

*

with optional 16550.

FUNCTIONAL DESCRIPTION

MODEM STATUS REGISTER

DCD - Data Carrier Detect:

Complement of the DCD input.

RI - Ring Indicator:

Complement of the RI input.

DSR - Data Set Ready:

Complement of the DSR input.

CTS - Clear To Send:

Complement of the CTS input.

Bits DDCD, TERI, DDSR, and DCTS are the sources of MODEM status interrupts. These bits are reset when the MODEM status register is read.

DDCD - Delta Data Carrier Detect:

Indicates the Data Carrier Detect (DCD) input has changed state.

TERI - Trailing Edge Ring Indicator:

Indicates the Ring Indicator (RI) input has changed from a low to a high state.

DDSR - Delta Data Set Ready:

Indicates the Data Set Ready (DSR) input has changed state.

DCTS - Delta Clear To Send:

Indicates the Clear to Send (CTS) input has changed state.

FUNCTIONAL DESCRIPTION

SCRATCHPAD

REGISTER

This register is not used by the 16450/16550. It may be used by the programmer for data storage.

FIFO

INTERRUPT MODE OPERATION

*

1. The receive data interrupt is issued when the FIFO reaches the trigger level. The interrupt is cleared as soon as the FIFO falls below the trigger level.

2. The interrupt identification register's receive data available indicator is set and cleared along with the receive data interrupt above.

3. The data ready indicator is set as soon as a character is transferred into the receiver FIFO and is cleared when the FIFO is empty.

IV. BAUD

RATE SELECTION

The 16450/16550 ACE determines the baud rate of the serial output using a combination of the input clock frequency and the value written to the baud rate divisor latches. Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the DS-202 / DS-302 uses an

18.432 MHz crystal and a frequency divider circuit to produce the standard clock frequency.

Jumper block J1 is used to set the frequency input to the ACE. The jumper may be connected to divide the

18.432 MHz clock input by 1, 2, 5, or 10. For compatibility as stated above, J1 should be configured to divide by 10 as shown in figure 7(d). A table of baud rates available using the 1.8432 MHz input is given in figure 7.

*

with optional 16550.

BAUD RATE SELECTION

J1 J1 +---------+ +---------+ 4| _ +_ _ |6 4| _--_ _ |6 1| _ +_ _ |3 1| _ _--_ |3 +---------+ +---------+ (a) ÷1 input clock (b) ÷2 input clock

J1 J1 +---------+ +---------+ 4| _ _--_ |6 1| _--_ +_ |4 1| _--_ _ |3 2| _--_ +_ |5 +---------+ +---------+ (c) ÷5 input clock (d) ÷10 input clock

Figure 7. Input clock frequency options. For

compatibility, the jumper should be set to ÷10 ( 18.432 MHz ÷ 10 = 1.8432 MHz ).

+-----------+-------------+-----------------------+ | Desired | Divisor | Error Between Desired | | Baud Rate | Latch Value | and Actual Value (%) | +-----------+-------------+-----------------------+ | 50 | 2304 | - | | 75 | 1536 | - | | 110 | 1047 | 0.026 | | 150 | 768 | - | | 300 | 384 | - | | 600 | 192 | - | | 1200 | 96 | - | | 1800 | 64 | - | | 2000 | 58 | 0.69 | | 2400 | 48 | - | | 3600 | 32 | - | | 4800 | 24 | - | | 7200 | 16 | - | | 9600 | 12 | - | | 19200 | 6 | - | | 38400 | 3 | - | | 56000 | 2 | 2.86 | +-----------+-------------+-----------------------+

Figure 8. Divisor latch settings for common baud rates using a 1.8432 MHz input clock. The jumper must be set to the divide by 10 configuration (figure 7(d)).

BAUD RATE SELECTION

V. ADDRESSING

Each channel of the DS-202 / DS-302 uses eight consecutive I/O address locations in the range 0 to 07FF Hex. The base address of channel 1 is selected using dip switch SW1 while the base address of channel 2 is selected using SW2. Switch positions 1 - 8 control the selection of address lines A9 through A3 respectively. A switch set to the "ON" position requires the corresponding address bit to be "0" for channel selection while a switch set to the "OFF" position requires the address bit to be "1". Address lines A10 - A15 must be "0" for port selection. Some address selection examples are given in figure 10.

Jumper J4 is used to independently enable or disable the communication channels. Connecting J4 pins 1 and 3 enables channel 1 while connecting J4 pins 2 and 4 enables channel 2. A channel may be disabled by removing the corresponding jumper from J4. The layout of jumper J4 is shown in figure 11.

SW1 +----------------------------+ | 1 2 3 4 5 6 7 8 | |ON +-++-++-++-++-++-++-++-+ | | |_|| || || || || || || | | | | ||_||_||_||_||_||_||_| | | +-++-++-++-++-++-++-++-+ | +----------------------------+

(a) Address selection switch for channel 1. Shown is setting for base address 03F8H (COM1).

SW2 +----------------------------+ | 1 2 3 4 5 6 7 8 | |ON +-++-++-++-++-++-++-++-+ | | |_|| ||_|| || || || || | | | | ||_|| ||_||_||_||_||_| | | +-++-++-++-++-++-++-++-+ | +----------------------------+

(b) Address selection switch for channel 2. Shown is setting for base address 02F8H (COM2).

Figure 9. Address selection switches.

ADDRESSING

1 2 3 4 5 6 7 8 ON +-++-++-+ +-++-++-++-+ +-+ |_|| || | | || || || | | | | ||_||_| |_||_||_||_| |_| +-++-++-+ +-++-++-++-+ +-+ 0 2 1 8 4 2 1 8

BASE ADDRESS 3 F 8 = 03F8H

1 2 3 4 5 6 7 8 ON +-++-++-+ +-++-++-++-+ +-+ |_|| ||_| | || || || | | | | ||_|| | |_||_||_||_| |_| +-++-++-+ +-++-++-++-+ +-+ 0 2 0 8 4 2 1 8

BASE ADDRESS 2 F 8 = 02F8H

1 2 3 4 5 6 7 8 ON +-++-++-+ +-++-++-++-+ +-+ |_|| || | | || || ||_| | | | ||_||_| |_||_||_|| | |_| +-++-++-+ +-++-++-++-+ +-+ 0 2 1 8 4 2 0 8

BASE ADDRESS 3 E 8 = 03E8H

1 2 3 4 5 6 7 8 ON +-++-++-+ +-++-++-++-+ +-+ |_|| ||_| | || || ||_| |_| | ||_|| | |_||_||_|| | | | +-++-++-+ +-++-++-++-+ +-+ 0 2 0 8 4 2 0 0

BASE ADDRESS 2 E 0 = 02E0H

Figure 10. Address selection examples.

J4 +------+ 3 | _ _ | 4 1 | _ _ | 2 +------+ enable channel 1 --+ +-- enable channel 2

Figure 11. Channel enable / disable jumper.

Connecting pins 1 - 3 enables channel 1. Connecting pins 2 - 4 enables channel 2.

ADDRESSING

VI. INTERRUPTS

Each channel of the DS-202 / DS-302 may select one of six possible interrupt request levels (IRQ 2 - 7). The interrupt request level is selected using jumper J5 for channel 1 and jumper J6 for channel 2 as shown in the figure below.

J5/J6 interrupt source +----_--_--_--_--_--_ _ _ _ _ _ _ IRQ 2 --+ | | | | | IRQ 3 -----+ | | | | IRQ 4 --------+ | | | IRQ 5 -----------+ | | IRQ 6 --------------+ | IRQ 7 -----------------+

Figure 12.System interrupt connection. Use jumper J5 for channel 1, J6 for channel 2.

An additional feature of the DS-202 / DS-302 is the ability to share one interrupt level between both communication channels, or to share an interrupt level with another Quatech

adapter supporting this interrupt sharing capability. Jumper J2 controls the interrupt sharing feature for channel 1, jumper J3 for channel 2.

J2/J3 J2/J3 +---------+ +---------+ 4 | _ _--_ | 6 4 | _--_ _ | 6 1 | _ _--_ | 3 1 | _--_ _ | 3 +---------+ +---------+

(a) dedicated interrupt (b) shared interrupt level (non-sharing) capability

Figure 13. Interrupt mode selection. NOTE: To be 100% ISA compatible, jumpers must

be set to the dedicated interrupt level positions.

INTERRUPTS

VII. OUTPUT

CONFIGURATION

Four sets of jumpers are implemented on the DS-202 / DS-302 to control the auxiliary channel configuration and tri-state output drivers. Jumpers J7 and J8 and jumpers J9 and J10 perform the identical functions on channels 1 and 2 respectively.

DTR -----+ +----- RTS ___ | | ___ +------------+ TxD DTR --+ | | +-- RTS | RS-422/485 +------- + |5 |6 7| 8| | Driver +------- +_ +_ _+ _+ Enable +-----+------+ J7/J9 _--_--_--_-----------------+ 1 2 3 4 +-----+------+ AUXOUT +------+ +---------------+ RS-422/485 +------- + | XCLK +---------|--+ | Driver +------- | ___ | 4 5| 6| +------------+ | RTS +-----_ _+ _+ | ___ | +-_ _+ _+ J8/J10 +------------+ AUXIN | CTS +---+ 1 2| 3| | RS-422/485 +------ + | | +--|-------------+ Receiver +------ | RCLK +------------+ +------------+ | ___ | | DTR +-+ +------------+ RxD | ___ | | | RS-422/485 +------ + | DSR +-+ | Receiver +------ | ___ | | +------------+ | DCD +-+ | __ | | | RI +-+ +------+ 16450

Figure 14. Output control block diagram.

Auxiliary

Channel Configuration

The function of jumpers J8 and J10 is to control the source of the information exchanged on the auxiliary communication lines. The output sources are request to send (RTS), transmit clock (XCLK), and the auxiliary input (AUXIN). The inputs selections are clear to send (CTS) and receive clock (RCLK).

Transmission of RTS, when combined with reception of CTS, allows for handshaking between the ACE and a peripheral device. RTS is transmitted by connecting pins 4 and 5 of the jumper block (figure 16a). CTS is

OUTPUT CONFIGURATION

received by connecting pins 1 and 2 (figure 16a). The RTS/CTS handshake can be defeated by looping the RTS output back to the CTS input. This is accomplished by connecting pins 1 and 4 (figures 16b and 16c).

RCLK is the input to the ACE that controls the shift rate of the receiver portion of the chip. Generally, this input is provided by connecting it to the transmit clock, XCLK, output from the ACE. This is accomplished by connecting pins 3 and 6 of the jumper (figures 16a and 16c). RCLK may be received from an external source by connecting pins 2 and 3 (figure 16b).

Transmission of XCLK can be used to synchronize communications with a peripheral or to provide a shift clock to a receiver. XCLK is transmitted by connecting pins 5 and 6 of the jumper block (figure 16b).

AUXIN is the auxiliary input from a peripheral device. Connecting AUXIN to AUXOUT provides a loopback mode of operation. That is, whatever is transmitted by the peripheral will be fed back to the peripheral. This is implemented by connecting pins 2 and 5 of the jumper block (figure 16c).

AUXOUT RTS ----+ | +---- XCLK +---------+ 4 | _ _ _ | 6 1 | _ _ _ | 3 +---------+ CTS ----+ | +---- RCLK AUXIN

J8 _ channel 1 J10 _ channel 2

+-------------------------+---------+ | Function | J8/J10 | +-------------------------+---------+ | RTS/CTS loopback

*

| 1-4 | | Transmit RTS | 4-5 | | Receive CTS | 1-2 | | RCLK/XCLK loopback

*

| 3-6 | | Transmit XCLK | 5-6 | | Receive RCLK | 2-3 | | AUXOUT/AUXIN loopback

*

| 2-6 | +-------------------------+---------+ *Indicates factory jumper settings.

Figure 15. Auxiliary channel jumper definition.

OUTPUT CONFIGURATION

AUXOUT AUXOUT RTS ----+ | +---- XCLK RTS ----+ | +---- XCLK +---------+ +---------+ 4 | _--_ _+| 6 4 | _+ _--_ | 6 1 | _--_ _+| 3 1 | _+ _--_ | 3 +---------+ +---------+ CTS ----+ | +---- RCLK CTS ----+ | +---- RCLK AUXIN AUXIN

(a) RTS transmission (b) RTS/CTS loopback CTS reception XCLK transmission XCLK/RCLK loopback RCLK reception

AUXOUT RTS ----+ | +---- XCLK +---------+ 4 | _+ _+ _+| 6 1 | _+ _+ _+| 3 +---------+ CTS ----+ | +---- RCLK AUXIN

(c) RTS/CTS loopback XCLK/RCLK loopback AUXOUT/AUXIN loopback

Figure 16. Auxiliary channel configuration. Use J8 for channel 1, J10 for channel 2.

+--+--+--+----- driver enable +------------+ 5 | _ _ _ _ | 8 1 | _ _ _ _ | 4 +------------+ +DTR ----+ | | |

-DTR -------+ | | +RTS ----------+ |

-RTS -------------+

Figure 17. Half duplex control jumper. Use J7 for channel 1, J9 for channel 2.

OUTPUT CONFIGURATION

Half

Duplex Operation

The function of jumpers J7 and J9 is to configure the communication channel for half or full duplex operation. Full duplex operation requires a connection between pins 5 and 6 of the jumper block. Half duplex operation requires one jumper connected vertically across jumper J7 for channel 1 or J9 for channel 2 (see figure 17). This connection allows the transmitter to be enabled and disabled using the data terminal ready (DTR) or request to send (RTS) outputs controlled through the modem control register of the 16450/16550.

If a jumper is installed between pins 1 and 5, the output drivers are controlled by the ACE's DTR signal. Setting DTR (logic 1) enables the drivers for both the data and auxiliary channel outputs while clearing DTR (logic 0) forces both outputs to a high impedance state. If the jumper is installed between pins 2 and 6 the logical sense of DTR is inverted. That is, clearing DTR (logic 0) enables the transmitter drivers while setting DTR (logic 1) forces the outputs to a high impedance state.

If a jumper is installed between pins 3 and 7, the output drivers are controlled by the ACE's RTS signal. Setting RTS (logic 1) enables the drivers for both the data and auxiliary channel outputs while clearing RTS (logic 0) forces both outputs to a high impedance state. If the jumper is installed between pins 4 and 8 the logical sense of RTS is inverted. That is, clearing RTS (logic 0) enables the transmitter drivers while setting RTS (logic 1) forces the outputs to a high impedance state.

CAUTION: When operating in half duplex mode, the

transmitter must be disabled before receiving any information. Failure to do so will result in two output drivers being connected together which may cause damage to the adapter, the computer, and/or the peripheral equipment.

OUTPUT CONFIGURATION

VIII. EXTERNAL

CONNECTIONS

Connections to peripheral equipment are made via female D-9 connectors CN1 and CN2. A pin-out of the connectors and a description of each connector signal is given in the figures below.

+-----+----------+------------------------------------+ | PIN | SIGNAL | DESCRIPTION | +-----+----------+------------------------------------+ | 1 | AUXOUT+ | When combine with AUXOUT-, | | | | provides the auxiliary channel | | | | output defined by jumper J8 / J10. | +-----+----------+------------------------------------+ | 2 | TxD+ | When combined with TxD-, provides | | | | the serial data output. | +-----+----------+------------------------------------+ | 3 | GND | Chassis ground. | +-----+----------+------------------------------------+ | 4 | RxD+ | When combined with RxD-, provides | | | | the serial data input. | +-----+----------+------------------------------------+ | 5 | AUXIN+ | When combined with AUXIN-, | | | | provides the auxiliary channel | | | | input defined by jumper J8 / J10. | +-----+----------+------------------------------------+ | 6 | AUXOUT- | See AUXOUT+. | +-----+----------+------------------------------------+ | 7 | TxD- | See TxD+. | +-----+----------+------------------------------------+ | 8 | RxD- | See RxD+. | +-----+----------+------------------------------------+ | 9 | AUXIN- | See AUXIN+. | +-----+----------+------------------------------------+

Figure 18. Output connector definitions.

INSTALLATION / SPECIFICATIONS

IX. INSTALLATION

1. Set base address, interrupt level and output configuration jumpers on the DS-202/DS-302.

2. Turn unit off.

3. Remove system cover as instructed in the computer reference guide.

4. Insert adapter into a vacant slot following the guidelines for installation.

5. Replace system cover.

X. SPECIFICATIONS

Bus interface: ISA 8-bit bus

Controllers: 2 - 16450 Asynchronous Communication Elements (16550 optional)

Interface: 2 - D-9 female connectors

Transmit drivers: MC3487 or compatible (RS-422) TI75174 or compatible (RS-485)

Receive buffers: MC3486 or compatible (RS-422) TI75175 or compatible (RS-485)

I/O Address range: 0000H - 07FFH

Interrupt levels: IRQ 2,3,4,5,6,7

Power requirements: +--------+--------+-----------+ | I

| I

T

| Supply |

MS

+--------+--------+-----------+ | 497mA | 564mA | +5 Volts | +--------+--------+-----------+ | -- | -- | +12 Volts | +--------+--------+-----------+ | -- | -- | -12 Volts | +--------+--------+-----------+ IT - Typical adapter current I

- Maximum statistical adapter current

MS

Quatech DS-202 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual