Quatech DS-1000 Owner's Manual

WARRANTY INFORMATION

Qua Tech Inc. warrants the DS-1000 defects for one Tech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Qua Tech Inc. assumes no liability for damages resulting from errors in this document. Qua Tech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: DS-1000

PRODUCT DESCRIPTION: DUAL

(1) year from the date of purchase. Qua

CHANNEL RS-232 ASYNCHRONOUS

to be free of

COMMUNICATIONS

SERIAL NUMBER:

BOARD

IBMTM, PS/2TM, and Micro Channel are registered trademarks of International Business Machines.

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TM

FEDERAL COMMUNICATIONS COMMISSION STATEMENT

This equipment generates and uses radio frequency energy and if not installed and used properly, that is, in strict accordance with the manufacturer's instructions, may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class B computing device in accordance with the specifications in Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference in a residential installation. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

Reorient the receiving antenna. Relocate the computer with respect to the receiver. Move the computer away from the receiver. Plug the computer into a different outlet so that the computer and receiver are on different branch circuits.

If necessary, the user should consult the dealer or an experienced radio / television technician for additional suggestions. The user may find the following booklet prepared by the Federal Communications Commission helpful:

"How to Identify and Resolve Radio-TV Interference Problems"

This booklet is available from:

U.S. Government Printing Office Washington, DC 20402 Stock No. 004-000-00345-4

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TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

FEDERAL COMMUNICATIONS COMMISSION STATEMENT ii

LIST OF FIGURES . . . . . . . . . . . . . . iv

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16550 FUNCTIONAL DESCRIPTION . . . . . . . . 3

A. INTERRUPT ENABLE REGISTER . . . . . . . . 4

B. INTERRUPT IDENTIFICATION REGISTER . . . . 5

C. FIFO CONTROL REGISTER . . . . . . . . . . 7

D. LINE CONTROL REGISTER . . . . . . . . . . 8

E. MODEM CONTROL REGISTER . . . . . . . . . 10

F. LINE STATUS REGISTER . . . . . . . . . . 11

G. MODEM STATUS REGISTER . . . . . . . . . . 13

H. SCRATCHPAD REGISTER . . . . . . . . . . . 14

IV. FIFO INTERRUPT MODE OPERATION . . . . . . . 14

V. DIVISOR LATCH VALUES . . . . . . . . . . . . 14

VI. ADDRESSING . . . . . . . . . . . . . . . . . 15

VII. INTERRUPTS . . . . . . . . . . . . . . . . . 15

VIII. PROGRAMMABLE OPTION SELECT . . . . . . . . . 15

IX. OUTPUT CONFIGURATIONS . . . . . . . . . . . 18

X. INSTALLATION . . . . . . . . . . . . . . . . 22

XI. SPECIFICATIONS . . . . . . . . . . . . . . . 23

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LIST OF FIGURES

Figure 1. DS-1000 board layout . . . . . . . . . 2

Figure 2. 16550 internal registers . . . . . . . 3

Figure 3. Interrupt enable register . . . . . . 4

Figure 4. Interrupt identification register . . 5

Figure 5. Interrupt source identification . . . 6

Figure 6. FIFO control register . . . . . . . . 7

Figure 7. FIFO receiver trigger levels . . . . . 7

Figure 8. Line control register . . . . . . . . 8

Figure 9. Parity options . . . . . . . . . . . . 8

Figure 10. Word length and stop bit options . . . 9

Figure 11. MODEM control register . . . . . . . . 10

Figure 12. Line status register . . . . . . . . . 11

Figure 13. MODEM status register . . . . . . . . 13

Figure 14. Divisor latch options . . . . . . . . 14

Figure 15. POS implementation . . . . . . . . . . 16

Figure 16. Base address locations . . . . . . . . 17

Figure 17. Interrupt request levels . . . . . . . 17

Figure 18. Typical RS-232-C communications link . 18

Figure 19. RS-232-C connectors . . . . . . . . . 19

Figure 20. RS-232-C connector definitions . . . . 19

Figure 21. Typical RS-232-C cabling . . . . . . . 20

Figure 22. DTE/DCE output jumper configurations . 21

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I. INTRODUCTION

The DS-1000 is a dual channel RS-232C asynchronous serial communication adapter for the PS/2. The DS-1000 is designed to be used in the Serial 1 through Serial 8 address range as specified for the PS/2, although eight other addresses are available for applications requiring additional serial ports. The available interrupt selections (IRQ 3,4,7 and 9) can be used to reduce the number of interrupt sources on a single interrupt input. This feature can reduce software overhead in interrupt driven, high throughput applications.

The DS-1000 serial interface is accomplished through a pair of 16550 Asynchronous Communication Elements (ACEs). The 16550 is compatible with the 8250 and 16450 ACEs used in the IBM PC/XT/AT models. The 16550 also has an additional FIFO mode that reduces CPU overhead at higher data rates.

The DS-1000 address and interrupt selections are selected through the Programmable Option Select (POS) using the IBM installation utilities. In addition, jumpers are provided on the DS-1000 to configure the adapter as Data Terminal Equipment (DTE) or Data Communications Equipment (DCE). DTE/DCE selection can ease the cabling burden in local applications where MODEMS are not required.

II. BOARD

A component diagram of the DS-1000 showing the locations of the 16550 ACEs, DTE/DCE configuration jumpers, and D-9 connectors is shown in Figure 1. The first communication channel is controlled by the 16550 labeled U27, jumper J1, and is accessed through connector P1. The second channel uses the 16550 labeled U28, jumper J2, and is accessed through connector P2.

DESCRIPTION

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III. 16550 FUNCTIONAL DESCRIPTION

The 16550 is an upgrade of the standard 16450 Asynchronous Communications Element (ACE). Designed to be compatible with the 16450, the 16550 enters the character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode, can be selected to reduce CPU overhead at high data rates. The FIFO mode increases performance by providing two internal 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features include: Programmable baud rate, character length, parity, and number of stop bits Automatic addition and removal of start, stop, and parity bits Independent and prioritized transmit, receive and status interrupts Transmitter clock output to drive receiver logic

The following pages provide a brief summary of the internal registers available within the 16550 ACE. The registers are addressed as shown in Figure 2 below.

+---------------+----------------------------------------+ | DLAB A2 A1 A0 | REGISTER DESCRIPTION | +---------------+----------------------------------------+ | 0 0 0 0 | Receive buffer (read only) | | | Transmit holding register (write only) | | 0 0 0 1 | Interrupt enable | | x 0 1 0 | Interrupt identification (read only) | | | FIFO control (write only) | | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (least significant byte) | | 1 0 0 1 | Divisor latch (most significant byte) | +---------------+----------------------------------------+

Figure 2. Internal register map for 16550 ACE. DLAB is accessed through the Line Control Register.

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IIIA. INTERRUPT ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmitter holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

Figure 3. Interrupt enable register bit definitions.

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupt on overrun, parity, and framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupt on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupt on received data available or FIFO trigger level.

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IIIB. INTERRUPT IDENTIFICATION REGISTER

+------+ D7 | FFE |----- FIFO enable (FIFO only) +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

Figure 4. Interrupt identification register bit

definitions.

FFE - FIFO Enable:

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if any. See IP and Figure 5. NOTE: IID2 is always a logic 0 in character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and Figure 5.

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Quatech DS-1000 Owner's Manual

Specifications and Main Features

Frequently Asked Questions

User Manual