QUANTA ZY2, ZY6 Schematics

5

4

3

2

1

BOM MARK

ZY2 SYSTEM BLOCK DIAGRAM

X'TAL

P16

P17

14.318MHZ

P2

Dual Channel DDR2

667/800 MHz

Dual Channel DDR3

667/800 MHz

Penryn 479 uFCPGA

FSB

NB Cantiga PM965

P5,P6,P7,P8,P9,P10,P11

P3,P4

667/800/1067 Mhz

X4 DMI interface

要打

CLOCK GENERATOR

ICS: ICS9LPRS365BGLFT SELGO: SLG8SP512K05

DDRII SO-DIMM 0 SO-DIMM 1

DDRIII SO-DIMM 0 SO-DIMM 1

E@ EXT VGA

D D

C C

268@ AUDIO 268 D@ DOCK D2@ DDR2 SP@ 特殊(EXT VGA OR DDR2) LC@ LOW COST ED2@ EXT VGA & DDR2 CB@ CARDBUS NSF@ Non ASF

I@ INT VGA 888@ AUDIO 888 D3@ DDR3 ND@ NON DOCK NLC@ NON LOW COST TPM@ INT TPM ID2@ INT VGA & DDR2 ED3@ EXT VGA & DDR3 ID3@ INT VGA & DDR3 ASF@ ASF NCB@ NON CARDBUS

HDD (SATA)*2

LOW COST

1. MINI CARD 1 SLOT

2. NON DOCK

3. NON CARDBUS

4. NON ASF

5. NON HDMI

ODD (SATA)

Bluetooth

B B

USB4 P22

USB Port x 4

USB0~3

CCD

P25

P19USB7

Int MIC

P25

P27

SATA0

SATA1

SATA4

USB 2.0

Azalia

SB ICH9M

P12,P13,P14,P15

LPC

X'TAL

32.768KHZ

EC (WPC8769LDG)

Azalia Audio

SPDIF

P28

Controller ALC268 & 888

Connector

P28

P27

MDC 1.5

MIC Jack

P28

4

P27

Audio Amplifier

A A

Speaker

P27 & 28

Phone Jack Line in

5

P28P28

TPM

P23

SUBWOOFER

P28

SPI ROM

Touch Pad

K/B COON.

P32

3

CPU

Thermal Sensor

PCIE

MXM-NB8P-GS ( nVidia )

VRAM 256M VRAM 512M

LVDS

RGB

DVI Level Shift IC PI3VDP411LSZDE

Page:20

PCI-Express

PCI Bus

Cardreader Controller

OZ601T

X'TAL

32.768K

Media Card Reader

VR

P27

CIR

P32

P3

P18

P29

Fan Header

EXT_LVDS

EXT_CRT

EXT_DVI

INT_LVDS

INT_CRT

INT_DVI

BROADCOM

10/100/1G LAN

SWITCH CIRCUIT

Transformer

P31

2

5764M

RJ45

P22

CRT

Page:19

SWITCH CIRCUIT

PCIE-1

New Card

PCIE-4

PCIE-6

X'TAL 25M

P21

Page:22

P22

Size Document Number Rev

Date: Sheet

Mini Card / WLAN / TV

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

Block Diagram

LVDS

Page:19

HDMI

Page:20

DOCKING/DVI

Page: 31

USB5

P23

USB6

DOCK/LAN

Page: 33

1

140Tuesday, April 08, 2008

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Clock Generator

U25

R255 BKP1608HS181-TR255 BKP1608HS181-T

+3V +1.05V

C257

C215

C219

C216

.1U/10V_4

D D

.1U/10V_4

C219

.1U/10V_4

C215

.1U/10V_4

C257

.1U/10V_4

R254 Change from 33 to 475

SATACLKREQ#<14>

NEW_CLKREQ#<29>

PCLK_DEBUG<23>

PCLK_591<32>

PCLK_PCM<27>

PCLK_ICH<13>

CLKUSB_48<14>

14M_ICH<14>

CLK_DREFCLK<6> CLK_DREFCLK#<6>

C C

+3V

PCLK_ICH

CPU_BSEL0

MCH_BSEL1

CPU_BSEL2

CGCLK_SMB CGDAT_SMB

Clock Gen I2C

R237

R243

10K_4

R243

10K_4

CGDAT_SMB

Q26

Q26 RHU002N06

RHU002N06

PDAT_SMB<14,16,20,21,23,29>

2

3

1

+3V_CLK

C262

.1U/10V_4

R246 475/F_4R246 475/F_4 R254 475/F_4R254 475/F_4 R253 33_4R253 33_4 R252 33_4R252 33_4 R264 33_4R264 33_4 R263 33_4R263 33_4

R258 2.2K_4R258 2.2K_4 R261 33_4R261 33_4

R230 10K_4R230 10K_4

C209*30P/50V_4 C209*30P/50V_4

R229 33_4R229 33_4

RP16 I@0X2RP16 I@0X2

4 2

C260

.1U/10V_4

3 1

C263

10U/6.3V_6

CG_XOUT CG_XIN SATACLKREQ#_R NEW_CLKREQ#_R PCLK_MINI_R PCLK_591_R PCLK_PCM_R PCLK_ICH_R

FSA

DREFCLK_R DREFCLK#_R

FSC

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

39

VDD_SRC

55

VDD_CPU

61

VDD_REF

59

XTAL_OUT

60

XTAL_IN

1

PCI_0/CLKREQ_A#

3

PCI_1/CLKREQ_B#

4

PCI_2

5

PCI_3

6

^PCI_4/LCDCLK_SEL

7

PCIF_5/ITP_EN

10

USB_48MHz/FS_A

57

FS_B/TEST_MODE

62

REF/FS_C/TEST_SEL

13

SRC_0/DOT_96

14

SRC_0#/DOT_96#

64

SCL

63

SDA

8

VSS_PCI

11

VSS_48

15

VSS_I/O

19

VSS_PLL3

23

VSS_SRC_1

29

VSS_SRC_2

42

VSS_SRC_3

52

VSS_CPU

58

VSS_REF

SLG8SP512

VDD_I/O

VDD_PLL3_I/O VDD_SRC_I/O_1 VDD_SRC_I/O_2 VDD_SRC_I/O_3

VDD_CPU_I/O

CPU_STOP#

PCI_STOP#

CKPWRGD/PD#

CPU_0

CPU_0#

CPU_1_MCH

CPU_1_MCH#

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

LCDCLK/27M

LCDCLK#/27M_SS

SRC_2

SRC_2#

SRC_3/CLKREQ_C#

SRC_3#/CLKREQ_D#

SRC_7/CLKREQ_F#

SRC_7#/CLKREQ_E#

SRC_11/CLKREQ_H#

SRC_11#/CLKREQ_G#

SRC_4

SRC_4#

SRC_6

SRC_6#

SRC_9 SRC_9# SRC_10

SRC_10#

12 20 26 36 45 49

37 38 56

54 53 51 50 47 46

48

NC

17 18

21 22 24 25 27 28 41 40 44 43 30 31 34 35 33 32

C272

10U/6.3V_6

CLK_CPU_BCLK_R CLK_CPU_BCLK#_R CLK_MCH_BCLK_R CLK_MCH_BCLK#_R CLK_PCIE_CARD_R CLK_PCIE_CARD#_R

CLK_DREFSSCLK_R CLK_DREFSSCLK#_R

CLK_PCIE_SATA_R CLK_PCIE_SATA#_R CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_NEW_C_R CLK_PCIE_NEW_C#_R CLK_PCIE_ICH_R CLK_PCIE_ICH#_R PECLK_VGA_R PECLK_VGA#_R CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R CLK_PCIE_3GPLL_R CLK_PCIE_3GPLL#_R CLK_PCIE_TV_R CLK_PCIE_TV#_R

Rev:C Change C 205 & C204 P/N to CH03306JB04

QCI P/N

B B

PCLK_SMB<14,16,20,21,23,29>

Q27

Q27 RHU002N06

RHU002N06

3

+3V

2

1

CGCLK_SMB

ICS9LPRS365BGLFT

AL8SP512K05

ALPRS365K13

+1V05_CLK

C265

C213

.1U/10V_4

RP13 0X2_4RP13 0X2_4

1 3

RP12 0X2_4RP12 0X2_4

1 3

RP11 0X2_4RP11 0X2_4

1 3

RP15 I@0X2RP15 I@0X2

3 1

RP18 0X2_4RP18 0X2_4

3 1

RP17 0X2_4RP17 0X2_4

3 1

RP20 0X2_4RP20 0X2_4

3 1

RP9 0X2_4RP9 0X2_4

1 3

RP10 E@0X2RP10 E@0X2

1 3

RP19 0X2_4RP19 0X2_4

3 1

RP8 0X2_4RP8 0X2_4

3 1

RP14 0X2_4RP14 0X2_4

1 3

C205 33P/50V_4C205 33P/50V_4

C204 33P/50V_4C204 33P/50V_4

C265

.1U/10V_4

2 4 2 4 2 4

4 2

4 2 4 2 4 2 2 4 2 4 4 2 4 2 2 4

Strap table

C214

.1U/10V_4

Y8

14.318MHz

CG_XIN

CG_XOUT

C212

.1U/10V_4

PM_STPCPU# <14> PM_STPPCI# <14> CK_PWRGD <14>

CLK_CPU_BCLK <3> CLK_CPU_BCLK# <3> CLK_MCH_BCLK <5> CLK_MCH_BCLK# <5> CLK_PCIE_CARD <28> CLK_PCIE_CARD# <28>

CLK_DREFSSCLK <6> CLK_DREFSSCLK# <6>

CLK_PCIE_SATA <12> CLK_PCIE_SATA# <12> CLK_PCIE_LAN <21> CLK_PCIE_LAN# <21> CLK_PCIE_NEW_C <29> CLK_PCIE_NEW_C# <29> CLK_PCIE_ICH <13> CLK_PCIE_ICH# <13> CLK_MXM <18> CLK_MXM# <18> CLK_PCIE_MINI1 <23> CLK_PCIE_MINI1# <23> CLK_PCIE_3GPLL <6> CLK_PCIE_3GPLL# <6> CLK_PCIE_TV <23> CLK_PCIE_TV# <23>

CLK VDD power range 1.05V~3.3V

C261

.1U/10V_4

C267

.1U/10V_4

Pin 56 : It acts as a level sensitive strobe to latch the FS pins and other multiplexed inputs.

Rev:B Swap SRC9 & SRC4

SATACLKREQ#_R

NEW_CLKREQ#_R

PCLK_MINI_R

Rev:B for vendor requestSLG8SP512

R219BKP1608HS181-T R219BKP1608HS181-T

+3V

R475 10K_4R475 10K_4

R531 10K_4R531 10K_4

R532 10K_4R532 10K_4

CPU Clock select

BSEL Frequency Select Table

FSC FSB FSA Frequency

Pin 10/57/62 : For Pin CPU frequency selection

CPU_BSEL0<3>

A A

CPU_BSEL1<3>

CPU_BSEL2<3>

5

R262 0_4R262 0_4

R226 0_4R226 0_4

R231 0_4R231 0_4

MCH_BSEL0 <6>

MCH_BSEL1 <6>

CRB Rev0.7 : 110(CBA)

MCH_BSEL2 <6>

4

0

1

0

1

0

1

0

1

0

1

0

01

1

0

3

266Mhz0

133Mhz

166Mhz

200Mhz

400Mhz

Reserved

100Mhz

333Mhz

2

PCLK_PCM_R

Pin 6 : For Pin 13/14 and 17/18 selection 0 = LCDCLK & DOT96 for internal graphic controller support 1 = 27M & 27M_SS &SRC_0 for external graphic controller support

PCLK_ICH_R

R260 10K_4R260 10K_4

R259 10K_4R259 10K_4

Pin 7 : For Pin 46/47 selection 1 = CPU_ITP 0 = SRC_8

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

Size Document Number Rev

CLOCK GENERATOR CK505 W/REGULATOR

Date: Sheet

240Tuesday, April 08, 2008

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H_A#[3..16]<5>

D D

H_ADSTB#0<5>

H_REQ#[0..4]<5>

H_A#[17..35]<5>

C C

H_ADSTB#1<5>

H_A20M#<12> H_FERR#<12> H_IGNNE#<12>

H_STPCLK#<12> H_INTR<12> H_NMI<12> H_SMI#<12>

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

R494 0_4R494 0_4

AA4 AB2 AA3

D22

W6

W2 W5

W3

J4 L5

L4 K5 M3 N2

J1 N3 P5 P2

L2 P4 P1 R1 M1

K3 H2 K2

J3

L1

Y2 U5 R3

U4 Y5 U1 R4 T5 T3

Y4 U2 V4

V1

A6 A5 C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 D2

D3 F6

U40A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M# FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA

THERMDC

H CLK

BCLK[0] BCLK[1]

U40B

AD26

AF26

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24

H22 F26 K22 H23

H26 H25

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

C23 D25 C24

AF1 A26

B22 B23 C21

J24 J23

J26

C3

U40B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2]

Penryn

DATA GRP 0

MISC

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0

R500 27.4/F_6R500 27.4/F_6

COMP1

R501 54.9/F_4R501 54.9/F_4

COMP2

R144 27.4/F_6R144 27.4/F_6

COMP3

R147 54.9/F_4R147 54.9/F_4

H_D#[32..47]

H_D#[48..63]

H_DSTBN#3 <5> H_DSTBP#3 <5> H_DINV#3 <5>

ICH_DPRSTP# <6,12,35> H_DPSLP# <12> H_DPWR# <5> H_PWRGD <12> H_CPUSLP# <5> PSI# <35>

H_D#[32..47] <5>

H_DSTBN#2 <5> H_DSTBP#2 <5> H_DINV#2 <5>

H_D#[48..63] <5>

Layout note: comp0,2: Zo=27.4ohm, L<0.5" comp1,3: Zo=55ohm, L<0.5"

Layout note: DPRSTP# , Daisy Chain (SB>Power>NB>CPU)

H1 E2 G5

H5 F21 E1

F1

H_IERR#

D20 B3

H4

C1 F3 F4 G3 G2

G6 E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM#4

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3 AB5 AB6 C20

D21 A24 B25

C7

A22 A21

XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_PROCHOT#_D H_THERMDA H_THERMDC

PM_THRMTRIP#

R162 56.2/F_4R162 56.2/F_4

H_RS#0 H_RS#1 H_RS#2

R491 0_4R491 0_4

H_ADS# <5> H_BNR# <5> H_BPRI# <5>

H_DEFER# <5> H_DRDY# <5> H_DBSY# <5>

H_BREQ# <5>

H_INIT# <12> H_LOCK# <5>

T16T16

H_CPURST# <5> H_RS#[0..2] <5>

H_TRDY# <5>

H_HIT# <5> H_HITM# <5>

T10T10 T15T15 T13T13 T11T11 T14T14

Connect it to CPU DBR# is for ITP debug port or CPU interposer (like ICE) to reset the system

+1.05V

SYS_RST# <14>

CLK_CPU_BCLK <2> CLK_CPU_BCLK# <2>

+1.05V

R113

R113 1K/F_4

1K/F_4

R115

R115 2K/F_6

2K/F_6

H_D#[0..15]<5>

H_DSTBN#0<5> H_DSTBP#0<5> H_DINV#0<5>

H_D#[16..31]<5>

H_DSTBN#1<5> H_DSTBP#1<5> H_DINV#1<5>

Layout note: H_GTLREF: Zo=55 ohm L<0.5", 2/3*VCCP+-2%

CPU_BSEL0<2> CPU_BSEL1<2> CPU_BSEL2<2>

H_D#[0..15]

H_D#[16..31]

T18T18 T17T17 T19T19 T72T72 T12T12 T70T70 T71T71

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

H_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7

Penryn

Thermal Trip

B B

DELAY_VR_PWRGOOD<6,14,32,35>

+1.05V

R495

56.2/F_4

+1.05V

56.2/F_4

R163

56_4

5

PM_THRMTRIP#

A A

Processor hot

H_PROCHOT#_D

+1.05V

3

Q41

2

FDV301N

1

2

Q40

Q40 MMBT3904

MMBT3904

1 3

No use Thermal trip CPU side still PU 56ohm. Use Thermal trip can share PU at SB side

No use PROCHOT CPU side still PU 56ohm. Use PROCHOT to optional receiver CPU side PU 68ohm and through isolat 2.2K ohm to receiver side

R164 *0_4R164 *0_4

SYS_SHDN# <34,38>

PM_THRMTRIP# <6,12>

H_PROCHOT# <35>

CPU Thermal monitor

2ND_MBCLK<32>

2ND_MBDATA<32>

THERM_ALERT#<14,18>

CPUFAN#_ON<31>

4

R540

10K_4

+3V

U39

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

G780

ADDRESS: 98H

R490

200_6

VCC

DXP

DXN

GND

LM86VCC

1

2

3

5

C552

.1U/10V_4

H_THERMDA

C551

100P/X7R/50V_4

H_THERMDC

2

Rev:B Add R540

+3V

Q39

2

RHU002N06

3

R465 *0_4R465 *0_4

+5V

R493 *10K_4R493 *10K_4

1

+3V

Q38

2

RHU002N06

1

R466

10K_4

CPUFAN#_ON

3

R467

10K_4

XDP PU/PD

XDP_DBRESET#

XDP_TDO

XDP_TDI

XDP_TMS

XDP_BPM#5

XDP_TCK

XDP_TRST#

Size Document Number Rev

CPU Host Bus

Date: Sheet

R492 *1K_4R492 *1K_4

XDP_DBRESET# and XDP_TDO reserve for XDP

R128 *54.9/F_4R128 *54.9/F_4

R149 54.9/F_4R149 54.9/F_4

R131 54.9/F_4R131 54.9/F_4

R121 54.9/F_4R121 54.9/F_4

R127 54.9/F_4R127 54.9/F_4

R124 54.9/F_4R124 54.9/F_4

Quanta Computer Inc.

PROJECT :

1

+3V

+1.05V

ZY2 & ZY6

340Tuesday, April 08, 2008

of

1A

5

4

3

2

1

U40D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

D D

C C

B B

A A

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn

5

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

.

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

C557

*10U/6.3V_8

C565

10U/6.3V_8

C156

10U/6.3V_8

C573

*10U/6.3V_8

C154

10U/6.3V_8

C572

10U/6.3V_8

C140

*10U/6.3V_8

Layout Note: Place these parts reference to Intel demo board.

C158

*10U/6.3V_8

C563

10U/6.3V_8

10/12 :Modify BOM

4

C558

C155

*10U/6.3V_8

C571

*10U/6.3V_8

C153

*10U/6.3V_8

C574

10U/6.3V_8

C558

10U/6.3V_8

C553

*10U/6.3V_8

C141

*10U/6.3V_8

C152

10U/6.3V_8

C570

10U/6.3V_8

C80

+

*330U/2V_7343

Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0 stuff 22U*34, NC 22U*2 stuff 330U*2, NC330U*2

C568

*10U/6.3V_8

C556

10U/6.3V_8

C139

*10U/6.3V_8

C142

*10U/6.3V_8

C151

*10U/6.3V_8

C569

*10U/6.3V_8

C576

+

330U/2V_7343

C566

*10U/6.3V_8

C119

*10U/6.3V_8

C560

10U/6.3V_8

C120

*10U/6.3V_8

C567

10U/6.3V_8

C554

10U/6.3V_8

C81

+

330U/2V_7343

3

+

VCC_CORE VCC_CORE

U40C

A7

C157

*10U/6.3V_8

C559

*10U/6.3V_8

C118

10U/6.3V_8

C121

10U/6.3V_8

C564

*10U/6.3V_8

C555

*10U/6.3V_8

C577

*330U/2V_7343

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A9

B7 B9

C9

D9

E7 E9

F7 F9

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

.

VCCA : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)

2

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

Size Document Number Rev

Date: Sheet

VCC:38A

VCCP:130mA

H_VID0 <35> H_VID1 <35> H_VID2 <35> H_VID3 <35> H_VID4 <35> H_VID5 <35> H_VID6 <35>

CPU Power

Layout Note: Inside CPU center cavity in 2 rows

C129

.1U/16V_6

C128

.1U/16V_6

+

C575

330U/2.5V_7

Layout Note: VCCA CAP closr to Pin VCCA : 2.5A(Supply after VCC Stable)

4.5A(Supply before VCC Stable)

R84 100/F_6R84 100/F_6

R77

100/F_6

Quanta Computer Inc.

PROJECT :

C135

.1U/16V_6

C136

.1U/16V_6

C562

.01U/16V_4

Layout Note: Z0=27.4,PU/PD L<1"

ZY2 & ZY6

1

+1.05V

C561

10U/6.3V_8

VCC_CORE

VCCSENSE <35>

VSSSENSE <35>

of

440Tuesday, April 08, 2008

C147

.1U/16V_6

C148

.1U/16V_6

+1.5V

1A

5

4

3

2

1

U38A

H_D#[0..63]<3>

D D

QCI P/N

Intel Cantiga (G)M

Intel Cantiga (P)M

+1.05V

C C

B B

A A

0.3125*VCCP WIDE(10):SPACING(20) ,

R177

L<0.5"

221/F_4

H_SWING

R175

100/F_4

R464

24.9/F_4

2/3*VCCP WIDE(10):SPACING(20), L<0.5"

5

AJ0QT620T01

AJ0QT780T03

Capacitor close

C178

to the pin

0.1U/10V_4

H_RCOMP

WIDE(10):SPACING(20) , L<0.5"

+1.05V

R484

1K/F_4

R482

2K/F_4

H_CPURST#<3>

4

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_AVREF

U38A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

SP@CANTIGA_1p2

3

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

B15 K13 F13 B13 B14

B6 F12 C8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3

H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_RS#0 H_RS#1 H_RS#2

2

H_A#[3..35] <3>

H_ADS# <3>

H_ADSTB#0 <3>

H_ADSTB#1 <3> H_BNR# <3> H_BPRI# <3> H_BREQ# <3> H_DEFER# <3> H_DBSY# <3> CLK_MCH_BCLK <2> CLK_MCH_BCLK# <2> H_DPWR# <3> H_DRDY# <3> H_HIT# <3> H_HITM# <3> H_LOCK# <3> H_TRDY# <3>

H_DINV#[3..0] <3>

H_DSTBN#[3..0] <3>

H_DSTBP#[3..0] <3>

H_REQ#[0..4] <3>

H_RS#[0..2] <3>H_CPUSLP#<3>

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GMCH HOST

Date: Sheet

PROJECT :

ZY2 & ZY6

of

540Tuesday, April 08, 2008

1

1A

5

4

3

2

1

Strap table

Pin Name Strap description

CFG[2:0]

CFG[4:3]

CFG5

CFG6

D D

CFG7

CFG8

CFG9

CFG10

FSB Frequency Select

Reserved

DMI X2 Select

iTPM Host Interface

ME TLS Confidentiality

Reserved

PCIE Graphics Lane Reversal

PCIE Loopback enable

ReservedCFG11

CFG12

CFG13

CFG[15:14]

CFG16

CFG[18:17]

CFG19

C C

CFG20

ALLZ

XOR

Reserved

FSB Dynamic ODT

Reserved

DMI Lane Reversal

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIE

SDVO_CTRLDATA SDVO Present

DDPC_CTRLDATA Digital Display Present

Strap pin

+3V

R477 *4.02K/F_4R477 *4.02K/F_4 R478 *4.02K/F_4R478 *4.02K/F_4

B B

A A

R207 TPM@2.21K/F_4R207 TPM@2.21K/F_4 R479 *4.02K/F_4R479 *4.02K/F_4 R196 *4.02K/F_4R196 *4.02K/F_4 R487 *4.02K/F_4R487 *4.02K/F_4 R488 *4.02K/F_4R488 *4.02K/F_4 R222 *4.02K/F_4R222 *4.02K/F_4 R216 *4.02K/F_4R216 *4.02K/F_4 R200 *4.02K/F_4R200 *4.02K/F_4

REV: E Modify TPM (R207)

+3V

R184 I@2.21K/F_4R184 I@2.21K/F_4 R188 I@2.21K/F_4R188 I@2.21K/F_4 R206 *2.21K/F_4R206 *2.21K/F_4 R217 *2.21K/F_4R217 *2.21K/F_4 R481 10K_4R481 10K_4 R485 10K_4R485 10K_4 R209 10K_4R209 10K_4

5

Configuration

000= FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz

0 = DMI X2 1 = DMI X4(Default)

0 = iTPM Host Interface is enabled 1 = iTPM Host Interface is disabled(Default)

0 = AMT Firmware will use TLS cipher suite with no confidentiality 1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)

0 = Reverse Lanes 1 = Normal operation(Default)

0 = Enabled 1 = Disabled (Default)

0 = ALLZ mode enable 1 = disable(Default)

0 = XOR mode enable 1 = disable(Default)

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

0 = Normal (Default) 1 = Lanes Reversed

0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is operational (Default) 1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

0 = No SDVO/HDMI Device Present(Default) 1 = SDVO/HDMI Device present

0 = Digital display(HDMI/DP) device absent(Default) 1 = Digital display(HDMI/DP) device present

MCH_CFG_19 MCH_CFG_20

MCH_CFG_5 MCH_CFG_7

MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16

MCH_CFG_6_R <13>

SDVO_CTRLDATA SDVO_CTRLCLK

DDPC_DDCDATA DDPC_CTRLCLK CLK_MCH_OE# PM_EXTTS#0 PM_EXTTS#1

MCH_CFG_6<13>

PM_SYNC#<14>

ICH_DPRSTP#<3,12,35> PM_EXTTS#0<16,17>

PM_EXTTS#1<16,17>

DELAY_VR_PWRGOOD<3,14,32,35>

PLT_RST#<13>

PM_THRMTRIP#<3,12>

PM_DPRSLPVR<14,35>

No use Thermal trip NB side can NC.(NB has ODT)

PM_DPRSTP# The Daisy chain topology should be routed from ICH9M to IMVP , then to (G)MCH and CPU, in that order.

4

T30T30

T28T28

T31T31

T29T29

MCH_BSEL0<2> MCH_BSEL1<2> MCH_BSEL2<2>

T25T25 T27T27

T21T21

T24T24

T26T26 T20T20

T22T22 T23T23

R213 0_4R213 0_4 R483 0_4R483 0_4 R470 0_4R470 0_4 R212 0_4R212 0_4

R247 100/F_4R247 100/F_4 R221 *0_4R221 *0_4 R218 0_4R218 0_4

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20

PM_SYNC#_R ICH_DPRSTP#_R

PM_EXTTS#0_1_EC_R

TS#DIMM0_1_R

RST_IN#_MCH THRMTRIP#_R DPRSLPVR_R

U38B

M36

RSVD1

N36

RSVD2

R33

RSVD3

T33

RSVD4

AH9

RSVD5

AH10

RSVD6

AH12

RSVD7

AH13

RSVD8

K12

RSVD9

T24

RSVD14

B31

RSVD15

M1

RSVD17

AY21

RSVD20

B2

RSVD21

BG23

RSVD22

BF23

RSVD23

BH18

RSVD24

BF18

RSVD25

AL34

ME_JTAG_TCK

AK34

ME_JTAG_TDI

AN35

ME_JTAG_TDO

AM35

ME_JTAG_TMS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC_1

BF48

NC_2

BD48

NC_3

BC48

NC_4

BH47

NC_5

BG47

NC_6

BE47

NC_7

BH46

NC_8

BF46

NC_9

BG45

NC_10

BH44

NC_11

BH43

NC_12

BH6

NC_13

BH5

NC_14

BG4

NC_15

BH3

NC_16

BF3

NC_17

BH2

NC_18

BG2

NC_19

BE2

NC_20

BG1

NC_21

BF1

NC_22

BD1

NC_23

BC1

NC_24

F1

NC_25

SP@CANTIGA_1p2

3

CFG

PM

NC

SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

RSVD

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_DRAMRST#

DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

ME JTAG

CLK

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BB36

BA17 AY16 AV16 AR13

BD17 AY17 BF15 AY13

BG22 BH21

BF28 BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

AE35 AE43 AE46 AH42

AD35 AE44 AF46 AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35 AH34

N28 M28 G36 E36 K36 H36

B12

B28 B30 B29 C29 A28

M_CLK0 M_CLK1 M_CLK2 M_CLK3

M_CLK#0 M_CLK#1 M_CLK#2 M_CLK#3

M_RCOMP M_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF SM_PWROK SM_REXT

R256 499/F_4R256 499/F_4 R257 D3@0_4R257 D3@0_4

CLK_DREFCLK CLK_DREFCLK# CLK_DREFSSCLK CLK_DREFSSCLK#

CLK_PCIE_3GPLL CLK_PCIE_3GPLL#

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

MCH_CLVREF_R

DDPC_CTRLCLK DDPC_DDCDATA

CLK_MCH_OE#

TSATN#

R180 56_4R180 56_4

HDA_BIT_CLK_HDMI HDA_RST#_HDMI HDA_SDIN_HDMI HDA_SDOUT_HDMI HDA_SYNC_HDMI

Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V

NOTE: If (G)MCH's HD Audio signals are connected to ICH9M for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be only on 1.5V. These power pins on ICH9M can be supplied with 3.3V if and only if (G)MCH's HDA is not connected to ICH9M. Consequently, only 1.5V audio/modem codecs can be used on the platform.

M_CLK0 <16,17> M_CLK1 <16,17> M_CLK2 <16,17> M_CLK3 <16,17>

M_CLK#0 <16,17> M_CLK#1 <16,17> M_CLK#2 <16,17> M_CLK#3 <16,17>

M_CKE0 <16,17> M_CKE1 <16,17> M_CKE2 <16,17> M_CKE3 <16,17>

M_CS#0 <16,17> M_CS#1 <16,17> M_CS#2 <16,17> M_CS#3 <16,17>

M_ODT0 <16,17> M_ODT1 <16,17> M_ODT2 <16,17> M_ODT3 <16,17>

SM_VREF=0.5*VCC_SM

SM_PWROK only for DDR3.DDR2 PD only

SM_DRAMRST# only for DDR3.DDR2 NC.

DDR3_DRAMRST# <17>

CLK_DREFCLK <2> CLK_DREFCLK# <2> CLK_DREFSSCLK <2> CLK_DREFSSCLK# <2>

CLK_PCIE_3GPLL <2> CLK_PCIE_3GPLL# <2>

DMI_TXN[3:0] <13>

DMI_TXP[3:0] <13>

DMI_RXN[3:0] <13>

DMI_RXP[3:0] <13>

CL_CLK0 <14>

CL_DATA0 <14> MPWROK <14,32> CL_RST#0 <14>

SDVO_CTRLCLK <20>

SDVO_CTRLDATA <20>

MCH_ICH_SYNC# <14>

HDA_BIT_CLK_HDMI <12> HDA_RST#_HDMI <12> HDA_SDIN_HDMI <12> HDA_SDOUT_HDMI <12> HDA_SYNC_HDMI <12>

2

Check list note : CL_REF=0.35VNB Thermal trip pin

+1.05V

C207

0.1U/10V_4

DDPC_CTRL for HDMI port C SDVO_CTRL for HDMI port B

If HDMI not support HDA --> NC VCC_HDA-->GND Differential signal-->NC

M_RCOMP

R458 80.6/F_4R458 80.6/F_4

M_RCOMP#

R457 80.6/F_4R457 80.6/F_4

SM_VREF

SM_PWROK

R251 D3@10K/F_4R251 D3@10K/F_4 R248 10K/F_4R248 10K/F_4

INTEL FAE Suggest PD for Ext graphics

CLK_DREFCLK# CLK_DREFCLK CLK_DREFSSCLK# CLK_DREFSSCLK

SM_RCOMP_VOH

C516

2.2U/6V_6

SM_RCOMP_VOL

C514

2.2U/6V_6

+1.05V

R224

1K/F_4

R233

511/F_4

<Checklist ver0.8> If TSATN# is not used, then it must be terminated with a 56-Ω pull-up resistor to VCCP.

<Pin out check issue> Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN

Size Document Number Rev

GMCH DMI

Date: Sheet of

+VDR_SUS

R250 10K/F_4R250 10K/F_4 R249 10K/F_4R249 10K/F_4

+VDR_SUS

HWPG_VDR <32,37>

R174 E@0_4R174 E@0_4 R182 E@0_4R182 E@0_4 R193 E@0_4R193 E@0_4 R183 E@0_4R183 E@0_4

C517

R453

0.01U/16V_4

3.01K/F_4

R452

C515

1K/F_4

0.01U/16V_4

Quanta Computer Inc.

PROJECT :

1

+VDR_SUS

R4541K/F_4 R4541K/F_4

ZY2 & ZY6

1A

640Tuesday, April 08, 2008

1A

5

4

3

2

1

U38C

IV&EV Dis/Enable setting

If LVDS no use,all signal can NC

L_BKLT_CTRL<19>

D D

INT_LVDS_BLON<19>

+3V

INT_LVDS_EDIDCLK<19> INT_LVDS_EDIDDATA<19>

INT_LVDS_DIGON<19>

10/15: R178 Change to I@

INT_TXLCLKOUT-<18>

INT_TXLCLKOUT+<18>

INT_TXUCLKOUT-<18>

INT_TXUCLKOUT+<18>

INT_TXLOUT0-<18>

INT_TXLOUT1-<18>

INT_TXLOUT2-<18>

INT_TXLOUT0+<18>

INT_TXLOUT1+<18>

C C

INT_TXLOUT2+<18>

INT_TXUOUT0-<18>

INT_TXUOUT1-<18> INT_TXUOUT2-<18>

INT_TXUOUT0+<18>

INT_TXUOUT1+<18>

INT_TXUOUT2+<18>

IV&EV Dis/Enable setting

Note :REV B: remove R475 & R471 short to GND

B B

INT_CRT_DDCCLK<18> INT_CRT_DDCDAT<18>

INT_HSYNC<18>

HSYNC/VSYNC serial R place close to NB

A A

INT_VSYNC<18>

R203 I@10K_4R203 I@10K_4

R469 I@10K_4R469 I@10K_4

R178 I@2.37K/F_4R178 I@2.37K/F_4

INT_TXLCLKOUTINT_TXLCLKOUT+ INT_TXUCLKOUTINT_TXUCLKOUT+

INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2-

INT_TXLOUT0+ INT_TXLOUT1+ INT_TXLOUT2+

INT_TXUOUT0INT_TXUOUT1INT_TXUOUT2-

INT_TXUOUT0+ INT_TXUOUT1+ INT_TXUOUT2+

R189 75_4R189 75_4 R195 75_4R195 75_4 R205 75_4R205 75_4

INT_CRT_BLU<18>

INT_CRT_GRN<18>

INT_CRT_RED<18>

R473 I@30.1_4R473 I@30.1_4

R474 I@30.1_4R474 I@30.1_4

CRTIREF pull down for Teenah 1.3k ohm/F for cantiga 1.02k ohm/F

L_CTRL_CLK

L_CTRL_DATA

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

INT_CRT_BLU

INT_CRT_GRN

INT_CRT_RED

HSYNC_G CRTIREF VSYNC_G

U38C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

SP@CANTIGA_1p2

L<0.5" , If PCIE not support still connect to +VCC_PEG

EXP_A_COMPX

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6

LVDS

TV

VGA

PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12

PCI-EXPRESS GRAPHICS

PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8

PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8

PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

C_PEG_TXN0 C_PEG_TXN1 C_PEG_TXN2 C_PEG_TXN3 C_PEG_TXN4 C_PEG_TXN5 C_PEG_TXN6 C_PEG_TXN7 C_PEG_TXN8 C_PEG_TXN9 C_PEG_TXN10 C_PEG_TXN11 C_PEG_TXN12 C_PEG_TXN13 C_PEG_TXN14 C_PEG_TXN15

C_PEG_TXP0 C_PEG_TXP1 C_PEG_TXP2 C_PEG_TXP3 C_PEG_TXP4 C_PEG_TXP5 C_PEG_TXP6 C_PEG_TXP7 C_PEG_TXP8 C_PEG_TXP9 C_PEG_TXP10 C_PEG_TXP11 C_PEG_TXP12 C_PEG_TXP13 C_PEG_TXP14 C_PEG_TXP15

R215 49.9/F_4R215 49.9/F_4

C189 .1U/10V_4C189 .1U/10V_4 C196 .1U/10V_4C196 .1U/10V_4 C197 .1U/10V_4C197 .1U/10V_4 C208 .1U/10V_4C208 .1U/10V_4 C218 E@.1U/10V_4C218 E@.1U/10V_4 C228 E@.1U/10V_4C228 E@.1U/10V_4 C233 E@.1U/10V_4C233 E@.1U/10V_4 C242 E@.1U/10V_4C242 E@.1U/10V_4 C249 E@.1U/10V_4C249 E@.1U/10V_4 C250 E@.1U/10V_4C250 E@.1U/10V_4 C252 E@.1U/10V_4C252 E@.1U/10V_4 C264 E@.1U/10V_4C264 E@.1U/10V_4 C269 E@.1U/10V_4C269 E@.1U/10V_4 C270 E@.1U/10V_4C270 E@.1U/10V_4 C274 E@.1U/10V_4C274 E@.1U/10V_4 C276 E@.1U/10V_4C276 E@.1U/10V_4

C188 .1U/10V_4C188 .1U/10V_4 C194 .1U/10V_4C194 .1U/10V_4 C195 .1U/10V_4C195 .1U/10V_4 C206 .1U/10V_4C206 .1U/10V_4 C220 E@.1U/10V_4C220 E@.1U/10V_4 C224 E@.1U/10V_4C224 E@.1U/10V_4 C230 E@.1U/10V_4C230 E@.1U/10V_4 C236 E@.1U/10V_4C236 E@.1U/10V_4 C245 E@.1U/10V_4C245 E@.1U/10V_4 C251 E@.1U/10V_4C251 E@.1U/10V_4 C254 E@.1U/10V_4C254 E@.1U/10V_4 C256 E@.1U/10V_4C256 E@.1U/10V_4 C259 E@.1U/10V_4C259 E@.1U/10V_4 C271 E@.1U/10V_4C271 E@.1U/10V_4 C275 E@.1U/10V_4C275 E@.1U/10V_4 C277 E@.1U/10V_4C277 E@.1U/10V_4

PEG_RXN[15:0] <18>

Can support reversal routing.If CFG9=1, PCI Express is normal operation. If CFG9=0, then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1 becomes PEG_TXP14, PEG_TXP2 becomes PEG_TXP13, etc. similarly for PEG_RXP[15:0] and PEG_RXN[15:0]

PEG_RXP[15:0] <18>

Rev: B Change P/N

+1.05V

PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15

PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15

IV&EV Dis/Enable setting

<5/31>Montevina_Schematics_Checklist_Rev0_8 a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But design guide Rev0.7 show NC.What is correct. b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA . CRT_HSYNC, CRT_VSYNCThese signals should be connected to GND. But design guide Rev0.7 show NC, Intel suggest follow Design guide.

PEG_TXN[15:0] <18>

PEG_TXP[15:0] <18>

<check list> For EV@ Connect to GND CRT R/G/B HSYNC/VSYNC CRTIREF

R181 SP@0 & 1.02K/F_4R181 SP@0 & 1.02K/F_4

<check list> For IV@ Connect to 150ohm CRT R/G/B Connect to 1.02Kohm CRTIREF

CRTIREF

11/28: Change R181 1.02K ohm P/N

R472 E@0_4R472 E@0_4

R468 E@0_4R468 E@0_4

R186 SP@150_4R186 SP@150_4

R190 SP@150_4R190 SP@150_4

R197 SP@150_4R197 SP@150_4

HSYNC_G

VSYNC_G

INT_CRT_BLU

INT_CRT_GRN

INT_CRT_RED

10/15: Change to SP@

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GMCH VGA

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

of

740Tuesday, April 08, 2008

1

1A

5

4

3

2

1

M_A_DQ[63:0]<16,17>

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U38D

AJ38 AJ41 AN38

AM38

AJ36

AJ40 AM44 AM42 AN43 AN44

AU40

AT38

AN41

AN39

AU44

AU42

AV39

AY44

BA40

BD43

AV41

AY43

BB41

BC40

AY37

BD38

AV37

AT36

AY38

BB38

AV36

AW36

BD13 AU11 BC11

BA12 AU13

AV13 BD12 BC12

BB9 BA9

AU10

AV9

BA11

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6

AT5 AN10 AM11

AM5

AJ9

AJ8 AN12 AM13

AJ11 AJ12

SP@CANTIGA_1p2

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

AM37

SA_DM_0

AT41

SA_DM_1

AY41

SA_DM_2

AU39

SA_DM_3

BB12

SA_DM_4

AY6

SA_DM_5

AT7

SA_DM_6

AJ5

SA_DM_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_10

SA_MA_11

SA_MA_12

SA_MA_13

SA_MA_14

DDR SYSTEM MEMORY A

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS0 <16,17> M_A_BS1 <16,17> M_A_BS2 <16,17>

M_A_RAS# <16,17> M_A_CAS# <16,17> M_A_WE# <16,17>

M_A_DM[7:0] <16,17>

M_A_DQS[7:0] <16,17>

M_A_DQS#[7:0] <16,17>

M_A_A[14:0] <16,17>

M_B_DQ[63:0]<16,17>

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U38E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_10

AY48

SB_DQ_11

AT47

SB_DQ_12

AR47

SB_DQ_13

BA47

SB_DQ_14

BC47

SB_DQ_15

BC46

SB_DQ_16

BC44

SB_DQ_17

BG43

SB_DQ_18

BF43

SB_DQ_19

BE45

SB_DQ_20

BC41

SB_DQ_21

BF40

SB_DQ_22

BF41

SB_DQ_23

BG38

SB_DQ_24

BF38

SB_DQ_25

BH35

SB_DQ_26

BG35

SB_DQ_27

BH40

SB_DQ_28

BG39

SB_DQ_29

BG34

SB_DQ_30

BH34

SB_DQ_31

BH14

SB_DQ_32

BG12

SB_DQ_33

BH11

SB_DQ_34

BG8

SB_DQ_35

BH12

SB_DQ_36

BF11

SB_DQ_37

BF8

SB_DQ_38

BG7

SB_DQ_39

BC5

SB_DQ_40

BC6

SB_DQ_41

AY3

SB_DQ_42

AY1

SB_DQ_43

BF6

SB_DQ_44

BF5

SB_DQ_45

BA1

SB_DQ_46

BD3

SB_DQ_47

AV2

SB_DQ_48

AU3

SB_DQ_49

AR3

SB_DQ_50

AN2

SB_DQ_51

AY2

SB_DQ_52

AV1

SB_DQ_53

AP3

SB_DQ_54

AR1

SB_DQ_55

AL1

SB_DQ_56

AL2

SB_DQ_57

AJ1

SB_DQ_58

AH1

SB_DQ_59

AM2

SB_DQ_60

AM3

SB_DQ_61

AH3

SB_DQ_62

AJ3

SB_DQ_63

SP@CANTIGA_1p2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

AM47

SB_DM_0

AY47

SB_DM_1

BD40

SB_DM_2

BF35

SB_DM_3

BG11

SB_DM_4

BA3

SB_DM_5

AP1

SB_DM_6

AK2

SB_DM_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_10

SB_MA_11

SB_MA_12

SB_MA_13

SB_MA_14

DDR SYSTEM MEMORY B

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6

M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS0 <16,17> M_B_BS1 <16,17> M_B_BS2 <16,17>

M_B_RAS# <16,17> M_B_CAS# <16,17> M_B_WE# <16,17>

M_B_DM[7:0] <16,17>

M_B_DQS[7:0] <16,17>

M_B_DQS#[7:0] <16,17>

M_B_A[14:0] <16,17>

A A

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GMCH DDRII

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

840Tuesday, April 08, 2008

1

1A

of

5

Power consumption reference to Intel 644135 Cantiga chipset EDS Volume1. Section 10

GM TDP 10.5~12W GS TDP 7~8W PM TDP 7W

D D

U38G

+VDR_SUS

+

C244

C519

22U/6V_8

Place on the edga

VCC_SM(1.8V) DDR2(800M) 3000mA_S0 , 1mA_S3 DDR2(667M) : 2600mA_S0 DDR3(1067M) : 4140mA_S0

C C

B B

C244

C521

0.1U/10V_4

22U/6V_8

1.05V Graphics core VCC_AXG VCC_AXG_NCTF

6326.84mA

Voltage regulator is shared between the Graphics Core Rail, VCCA_HPLL, VCCA_MPLL, VCCA_PEG_PLLVCCD_PEG_PLL, VCCA_SM_CK, VCCA_DPLLA, VCCA_DPLLB, VCCD_HPLL, VCCA_SM, VCC_AXF

C518

330U/2.5V_7

+1.05V_AXG

R242 I@10/F_4R242 I@10/F_4 R238 I@10/F_4R238 I@10/F_4

+1.05V_AXG

AP33 AN33 BH32

BG32

BF32 BD32 BC32 BB32 BA32 AY32

AW32

AV32 AU32 AT32 AR32 AP32 AN32 BH31

BG31

BF31

BG30

BH29

BG29

BF29 BD29 BC29 BB29 BA29 AY29

AW29

AV29 AU29 AT29 AR29 AP29

BA36 BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21 AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15 AG15

AF15

AB15

AA15

AN14 AM14

AJ14

AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

U38G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

VCC SMVCC GFX

4

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22

POWER

VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56

VCC GFX NCTF

VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

+1.05V_AXG

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

1.8V Internal connect to power

VCC_SM_LF1

AV44

VCC_SM_LF2

BA37

VCC_SM_LF3

AM40

VCC_SM_LF4

AV21

VCC_SM_LF5

AY5

VCC_SM_LF6

AM10

VCC_SM_LF7

BB13

C268

.1U/10V_4

3

Intel check list(Rev 0.8) 270U*1 near to power(+V1.05M). 270U*2 near to NB Intel CRB(Rev 0.7)

+1.05V

C217

I@10U/10V_8

C258

1U/6V_4

C231

.1U/10V_4

270U*3 near to power(+V1.05M). 270U*1 near to NB ESR=12m ohm

C225

.22U/6V_4

C201

I@22U/6V_8

Intel check list(Rev 0.8) No description for VCC_SM bulk CAP Intel CRB(Rev 0.7) 330U*1 Reserve near to power 330U*1 near to NB

+1.05V +1.05V_AXG

R227 I@0_8R227 I@0_8

R228 I@0_8R228 I@0_8

C200

I@.47U/6V_4

C238

.47U/6V_4

SP@:INT 上 1 U EXT

上

0 ohm

C237

SP@0_6

C266

1U/6V_4

+1.05V_AXG

+

C191

I@330U/2.5V_7343

IV&EV Dis/Enable setting

Design guide(Table 72) For INT VGA diasble.VCC_AXG power can connect to GND

+

C192

I@330U/2.5V_7343

Place close to the GMCH Cavity Capacitors

Intel check list(Rev 0.8) 220U*2 near to NB(ESR=15m ohm) Intel CRB(Rev 0.7) 270U*4 near to power(+V1.05S). 330U*2 near to NB

C239

.1U/10V_4

C255

.22U/6V_4

C253

.22U/6V_4

C226

.22U/6V_4

C210

22U/6V_8

C247

I@.1U/10V_4

2

+

C524

330U/2.5V_7

Place close to the GMCH

C203

I@.1U/10V_4

VCC VCC_NCTF

1210.34mA_EV

1930.4mA_IV ME Engine

508.12mA Total Max=2438.52mA

AG34 AC34 AB34 AA34

Y34 V34

U34 AM33 AK33 AJ33 AG33 AF33

AE33 AC33 AA33

Y33

W33

V33

U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23

T32

U38F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35

SP@CANTIGA_1p2

VCC CORE

POWER

1

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

+1.05V

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm

A A

and VSS_AXG_SENSE PD with 10ohm for Intel suggest

5

SP@CANTIGA_1p2

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GMCH VCC,NCTF

Date: Sheet

4

3

2

Date: Sheet

PROJECT :

ZY2 & ZY6

940Tuesday, April 08, 2008

1

940Tuesday, April 08, 2008

1A

of

5

Power consumption reference to Intel 644135 Cantiga chipset EDS Volume1. Section 10

1210 10UH, 10%

0.45A DCR_max = 0.39

D D

C C

B B

A A

L48 I@10UH_8L48 I@10UH_8

+1.05V

SP@:INT

上

EXT

上

L44 I@10UH_8L44 I@10UH_8

+1.05V

R245 0_6R245 0_6

+1.05V

+3V

CRB no 10U Check list need min 10U~100U for VCCA_TV_DAC

1.05V 50mA

L47 I@BLM18PG181SN1D_6L47 I@BLM18PG181SN1D_6

C549

I@10U/6.3V_8

+1.5V

1.5V 50mA

Design guide table 72 VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V

+1.5V

+1.05V

R244 0_6R244 0_6

1.05V 24mA

+1.05VM_MCH_PLL2

L29 BLM18PG181SN1D_6L29 BLM18PG181SN1D_6

+1.05VM_MPLL_RC

C227

22U/6V_8

FB 180@100 MHz, 25% 1.5A DCR_max=90 m

3.3V

24.15mA for VCCA_TVA_DAC

39.48mA for VCCA_TVB_DAC

24.15mA for VCCA_TVC_DAC Total 87.78mA

R486 I@0_6R486 I@0_6

R179 0_6R179 0_6

L49 I@BLM18PG181SN1D_6L49 I@BLM18PG181SN1D_6

FB 180@100 MHz, 25% 1.5A

C548

DCR_max=90 m

10U/6.3V_8

CRB no 10U Check list need min 10U~100U for VCCA_QDAC

L43 BLM18PG181SN1D_6L43 BLM18PG181SN1D_6

+1.05VM_PEGPLL_RC

C527

10U/10V_8

ESR=60m ohm

5

+

C550

220U/2.5V_7343

ESR=15 m

0.1U 0 ohm

C229

4.7U/10V_6

1210 0.1uH, 20%, 1A, DCR_max=0.078Ω

R234 0.5/F_6R234 0.5/F_6

SP@:INT EXT

1.5V

48.363mA for CRT 5mA for TV

IV&EV Dis/Enable setting

C546

SP@0_4

1210 10UH, 10%

0.45A DCR_max = 0.39

+

C535

220U/2.5V_7343

ESR=15 m

C223

.1U/10V_4

1.05V DDR2-800 26mA

IV&EV Dis/Enable setting

上

0.1U

上

0 ohm

1.5V

58.67mA

FB 220 @100 MHz, 25%, 2A

R463 1/F_4R463 1/F_4

+3V

1.05V

139.2mA

C221

.1U/10V_4

+1.05V

C544

I@.1U/10V_4

C185

.1U/10V_4

C184

I@.1U/10V_4

R480 I@0_6R480 I@0_6

R476 I@0_6R476 I@0_6

1.05V

64.8mA for A/B

Design guide table 72 VCCA_DPLLA/B always keep to +1.05V(If no use IV dynamic core power)

C533

SP@.1U/10V_4

1.05V DDR2-800 720mA

R241 0_6R241 0_6

C541

SP@0_4

C175

SP@0_4

C183

.01U/16V_4

C181

SP@0_4

SP@:INT EXT

Design guide Table 72

1.5V 414uA

3.9 nH, 0.2 nH, 1A , DCR_max=32 m

+1.05V

SP@:INT EXT

上

0.01U

上

0 ohm

C529

.1U/10V_4

4

+3V_A_CRT_DAC

C542

I@.1U/10V_4

+3V_A_DAC_BG

C543

I@.1U/10V_4

IV&EV Dis/Enable setting

R462 0_8R462 0_8

+1.5V

R240 0_6R240 0_6

CRB : 0 ohm Check list : 2.2nH

上

0.01U

上

0 ohm

IV&EV Dis/Enable setting

+1.8V

1.8V

60.31mA

4

C540

SP@0_4

SP@:INT 上 0.01U EXT

上

0 ohm

C179

SP@0_4

3.3V

2.68mA

+1.05VM_DPLLA

+1.05VM_DPLLB

+1.05VM_HPLL

+1.05VM_MPLL

+1.8VSUS_TXLVDS

C538

C528

.1U/10V_4

C248

22U/6V_8

+1.05VM_A_SM_CK

C241

*2.2U/10V_6

C234

.1U/10V_4

R176 I@0_6R176 I@0_6

C538

I@1000P/50V_4

+VCCA_PEG_BG

+1.05VM_PEGPLL

VCCA_PEG_PLL +1.25V for Teenah use(100mA)

C240

C246

1U/6V_4

4.7U/10V_6

C243

C235

.1U/10V_4

22U/6V_8

+3V_TV_DAC

+VCC_HDA

+1.5V_TVDAC

+1.5V_QDAC

+1.05VM_MCH_PLL2

+1.05VM_PEGPLL

C531

.1U/10V_4

+1.8VSUS_DLVDS

上

1 U

SP@:INT EXT

上

0 ohm

1.8V

13.2mA

+1.05VM_A_SM

VCCD_QDAC share to TV and CRT

1.05V

157.2mA

1.05V 50mA

C187

SP@0_4

3.3V 73mA

AD48

AR20

AN20 AR17

AN17

AR16

AN28

AN25 AN24 AM28 AM26 AM25

AM24

AM23

AA48

AP20

AP17

AT16

AP16

AP28

AP25

AL25

AL24

AL23

AA47

AD1

AE1

M25

AF1

M38

3

U38H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

VCCA_HPLL

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

VCCA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9

VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

VCCD_TVDAC

L28

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1

L37

VCCD_LVDS_2

SP@CANTIGA_1p2

3

U13

VTT_1

T13

VTT_2

U12

VTT_3

T12

VTT_4

U11

VTT_5

T11

VTT_6

U10

VTT_7

T10

VTT_8

U9

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

Power Rail Differences between the Teenah and Cantiga Chipset Family

Power Net Name

VCC_AXG_# VCC_AXG_NCTF_#

VCCA_PEG_BG

VCCA_DPLLA

VCCA_DPLLB

VCCA_SM_#

VCCA_HPLL

VCCA_MPLL

VCCA_SM_CK_#

VCCA_PEG_PLL

VCC_AXF_#

VCCD_HPLL

VCCD_PEG_PLL

VTT_9

T9

VTT_10

U8

VTT_11

T8

VTT_12

U7

VTT_13

T7

VTT_14

U6

VTT_15

VTT

T6

VTT_16

U5

VTT_17

T5

VTT_18

V3

VTT_19

U3

VTT_20

V2

VTT_21

U2

VTT_22

T2

VTT_23

V1

VTT_24

U1

VTT_25

B22

VCC_AXF_1

B21

VCC_AXF_2

A21

VCC_AXF_3

AXF

BF21

VCC_SM_CK_1

BH20

VCC_SM_CK_2

BG20

VCC_SM_CK_3

BF20

VCC_SM_CK_4

SM CK

DMI

K47

VCC_TX_LVDS

C35

VCC_HV_1

B35

VCC_HV_2

A35

VCC_HV_3

HV

V48

VCC_PEG_1

U48

VCC_PEG_2

V47

VCC_PEG_3

U47

VCC_PEG_4

U46

VCC_PEG_5

PEG

AH48

VCC_DMI_1

AF48

VCC_DMI_2

AH47

VCC_DMI_3

AG47

VCC_DMI_4

A8

VTTLF1

L1

VTTLF2

AB2

VTTLF3

VTTLF

Cantiga(V)

1.05V 1.25V 6326.84mA

1.5V

1.05V

Tennah(V)

3.3V

1.25V

C198

.47U/6V_4

+1.05VM_AXF

+1.8VSUS_VCC_SM_CK

+1.8VSUS_TXLVDS

3.3V

105.3mA

C211

.47U/6V_4

Tennah Current

Cantiga use

400uA

100mA

1065mA

50mA

150mA

35mA

100mA

495mA

250mA

100mA

2

C193

2.2U/6V_6

Check list : 0.1UH CRB : 0 ohm 1210 0.1 ?H, 20% 1A DCR max = 78 m

C545

1U/6V_4

C522

.1U/10V_4

SP@:INT EXT

C534

.47U/6V_4

2

C199

4.7U/10V_6

C547

*10U/10V_8

ESR = 60 m

R4551/F_4 R4551/F_4

IV&EV Dis/Enable setting

上

1000 P

上

0 ohm

+3V

C182

.1U/10V_4

C526

.1U/10V_4

C539

.47U/6V_4

+

C190

C180

4.7U/10V_6

330U/2.5V_7

ESR= 12m ohm

L46 1UH_8L46 1UH_8

1.05V

321.35mA

+1.8VSUS_SMCK_RC

C537

SP@1000P/50V_4

R489 10_4R489 10_4

C530

4.7U/10V_6

1

External Graphics (GMCH Integrated Graphics Disable)

VCCSYNC_CRT

VCCA_CRT_DAC

VCCD_LVDS

VCC_TX_LVDS

VCCA_LVDS

VCCA_TVDAC

VCCD_QDAC

+1.05V

1.05V FSB-1067 852mA

+1.05V

0805 1UH , Rdc = 0.14 - 0.26. Max rated current = 220 mA

L42 1UH_8L42 1UH_8

C520 10U/10V_8C520 10U/10V_8

0805 100 nH, DCR=160 m

L45 I@0.1UH_1.5L45 I@0.1UH_1.5

C536

I@22U/6V_8

+1.05V_SD

+1.05V

+

C532

C525

220U/6_7343

22U/6V_8

Size Document Number Rev

GMCH POWER

Date: Sheet

VCCA_DAC_BG

VCC_AXG

VCC_AXG_NCTF

+VDR_SUS

1.8V DDR2-800 124mA

1.8V

118.8mA

D38 BAT54D38 BAT54

21

1.05V 1782mA

1.05V Internal connect to power

Quanta Computer Inc.

PROJECT :

1

GND

+1.8V

+1.05V

ESL=2.4 nH ESR =15 m

1.05V 456mA

ZY2 & ZY6

10 40Tuesday, April 08, 2008

of

1A

5

U38I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

D D

C C

B B

A A

5

AD47 AB47

G47 BD46 BA46 AY46 AV46 AR46

AM46

BF44 AH44 AD44 AA44

M44

BC43 AV43 AU43

AM43

BG42

AY42 AT42 AN42

AJ42

AE42

BD41 AU41

AM41

AH41 AD41 AA41

M41

G41

BG40

BB40 AV40 AN40

AT39

AM39

AJ39

AE39

BH38 BC38 BA38 AU38 AH38 AD38 AA38

BF37 BB37

AW37

AT37 AN37

AJ37

BG36

BD36 AK15 AU36

Y47 T47 N47 L47

V46 R46 P46 H46 F46

Y44 U44 T44

F44

C43

N42 L42

Y41 U41 T41

B41

H40 E40

N39 L39 B39

Y38 U38 T38

F38 C38

H37 C37

J43

J38

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

SP@CANTIGA_1p2

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

4

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

4

3

U38J

BG21

VSS_199

L12

VSS_200

AW21

VSS_201

AU21

VSS_202

AP21

VSS_203

AN21

VSS_204

AH21

VSS_205

AF21

VSS_206

AB21

VSS_207

R21

VSS_208

M21

VSS_209

J21

VSS_210

G21

VSS_211

BC20

VSS_212

BA20

VSS_213

AW20

VSS_214

AT20

VSS_215

AJ20

VSS_216

AG20

VSS_217

Y20

VSS_218

N20

VSS_219

K20

VSS_220

F20

VSS_221

C20

VSS_222

A20

VSS_223

BG19

VSS_224

A18

VSS_225

BG17

VSS_226

BC17

VSS_227

AW17

VSS_228

AT17

VSS_229

R17

M17

H17 C17

BA16

AU16 AN16

N16 K16 G16

E16 BG15 AC15

W15

A15 BG14 AA14

C14 BG13 BC13 BA13

AN13

AJ13

AE13

N13

L13 G13 E13

BF12 AV12 AT12

AM12

AA12

J12 A12

BD11 BB11 AY11 AN11 AH11

Y11 N11 G11 C11

BG10 AV10 AT10

AJ10 AE10 AA10

M10

BF9 BC9 AN9 AM9 AD9

G9 B9

BH8

BB8

AV8

AT8

3

VSS

VSS_230 VSS_231 VSS_232 VSS_233

VSS_235

VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

SP@CANTIGA_1p2

VSS NCTF

VSS SCB

NC

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354 VSS_355

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4

VSS_SCB_6

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43

2

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29 AJ6

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1

A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GMCH VSS

Date: Sheet

2

Date: Sheet

PROJECT :

1

ZY2 & ZY6

of

11 40Tuesday, April 08, 2008

1A

5

C410 15P/50V_4C410 15P/50V_4

C409 15P/50V_4C409 15P/50V_4

+VCCRTC

D D

24.9 Ohm pull up to 1.5V for GLAN_COMPI/O is required, no matter intel LAN is used or not.

Internal pull-down resistors that are always enabled

ACZ_SDIN0<25> ACZ_SDIN1<25>

C C

OC Pin need PU, ZS2 PU at LED side.

SATA_LED#<31>

SATA_RXN0<24> SATA_RXP0<24>

SATA_TXN0<24> SATA_TXP0<24>

SATA_RXN1<24> SATA_RXP1<24>

SATA_TXN1<24> SATA_TXP1<24>

23

Y9

32.768KHZ

4 1

R360 1M/F_6R360 1M/F_6

R393 332K/F_4R393 332K/F_4

Internal VRM enabled for VccSus1_05, VccSus1_5, VccCL1_5, VccLAN1_05 and VccCL1_05.

+3V_S5

R376 10K_4R376 10K_4

R351 24.9/F_4R351 24.9/F_4

+1.5V

T38T38 T40T40

11/8 REV:B Y9 change footprint 11/26 REV:B C410 &C409 change to 15p 97/03/25 REV: C Change to NPO

R368

CLK_32KX1

10M_6

CLK_32KX2

RTC_RST# SRTC_RST#

SM_INTRUDER#

ICH_INTVRMEN

ICH_GPIO56

HDA_BIT_CLK_R HDA_SYNC_R

HDA_RST#_R

HDA_SDIN2 HDA_SDIN3

HDA_SDOUT_R

4

U35A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GLAN_DOCK#/GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M REV 1.0

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

RCIN#

STPCLK#

THRMTRIP#

SATA4RXN

IHDA

SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATA_CLKN SATA_CLKP

SATA

SATARBIAS#

SATARBIAS

INTR

SMI#

NMI

TP8

K5 K4 L6 K2

K3

J3 J1

N7 AJ27

AJ25 AE23

AJ26

AD22

AF25

AE22 AG25 L3

AF23 AF24

AH27

AG26

AG27

AH11 AJ11 AG12 AF12

AH9 AJ9 AE10 AF10

AH18 AJ18

AJ7 AH7

T44T44 T65T65

H_DPRSTP#_R H_DPSLP#_R

H_FERR#_R

H_SMI#_R

H_THERMTRIP_R

SATA_RBIAS_PN

3

LDRQ0/1# : Internal PU

R326 8.2K_4R326 8.2K_4

R435 0_4R435 0_4 R312 0_4R312 0_4

R432 56_4R432 56_4

R343 10K_4R343 10K_4

R299 0_4R299 0_4

R311 54.9/F_4R311 54.9/F_4

T39T39

SATABIAS L<0.5"

R426

24.9/F_4

+3V

H_THERMTRIP_RR

LAD0 <23,32> LAD1 <23,32> LAD2 <23,32> LAD3 <23,32>

LFRAME# <23,32>

GATEA20 <32> H_A20M# <3>

H_PWRGD <3>

H_IGNNE# <3>

H_INIT# <3> H_INTR <3>

RCIN# <32> H_NMI <3> H_SMI# <3>

H_STPCLK# <3>

SATA_RXN4 <24> SATA_RXP4 <24> SATA_TXN4 <24> SATA_TXP4 <24>

CLK_PCIE_SATA# <2>

CLK_PCIE_SATA <2>

2

+1.05V

R298

R434

*56_4

R297 56.2/F_4R297 56.2/F_4

R296 *0_4R296 *0_4

No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm) Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm) PU L<2"

Layout note: DPRSTP# , Daisy Chain

*56_4

(SB>Power>NB>CPU)

ICH_DPRSTP# <3,6,35> H_DPSLP# <3>

+1.05V

PM_THRMTRIP# <3,6>

+1.05V

R433

56_4

H_FERR# <3>

1

HD Audio

R513 E@33_4R513 E@33_4 R279 I@33_4R279 I@33_4

B B

HDA_SDOUT_R

Weak integrated PD on the HDA_SDOUT pin.

HDA_SYNC_R

Weak integrated PD on the HDA_SYNC pins

R295 33_4R295 33_4 R294 33_4R294 33_4

R514 E@33_4R514 E@33_4 R427 I@33_4R427 I@33_4 R429 33_4R429 33_4 R428 33_4R428 33_4

MXM_SDOUT_HDMI <18> HDA_SDOUT_HDMI <6> ACZ_SDOUT_MDC <25> ACZ_SDOUT_AUDIO <25>

C344

*10P/50V_4

MXM_SYNC_HDMI <18> HDA_SYNC_HDMI <6> ACZ_SYNC_MDC <25>

ACZ_SYNC_AUDIO <25> ACZ_RST#_AUDIO <25>

C479

*10P/50V_4

HDA_BIT_CLK_R

24.000 MHz is output from the ICH9M.

HDA_RST#_R

HDA_SDIN3 HDA_SDIN2

R517 E@33_4R517 E@33_4 R285 I@33_4R285 I@33_4 R282 33_4R282 33_4 R309 33_4R309 33_4

R516 E@33_4R516 E@33_4 R308 I@33_4R308 I@33_4 R307 33_4R307 33_4 R306 33_4R306 33_4

R515 E@0_4R515 E@0_4 R289 I@0_4R289 I@0_4

South Bridge Strap Pin (1/3)

Pin Name

HDA_DOCK_EN/ GPIO33

A A

SATALED#

TP3

HDA_SDOUT

Strap description

Flash Descriptor Security Override Strap

PCI Express Lane Reversal (Lanes 1-4)

XOR Chain Entrance

XOR Chain Entrance /PCI Express* Port Config 1 bit 1(Port 1-4)

5

Sampled

PWROK

Configuration PU/PD

0 = The Flash Descriptor Security will be overridden. 1 = The security measures defined in the Flash Descriptor will be in effect

Internal PU

ICH_TP3

HDA_SDOUT

0

11

4

RSVD

Enter XOR Chain

1

Normal opration(Default)

01

Set PCIE port config bit 1

Description

10/16: R517 Change to E@

C354

*10P/50V_4

C402

*10P/50V_4

MXM_RST#_HDMI <18> HDA_RST#_HDMI <6> ACZ_RST#_MDC <25>

MXM_SDIN_HDMI <18> HDA_SDIN_HDMI <6>

This strap should only be enabled in manufacturing environments using an external pull-up resistor.

ICH_TP3<14>

HDA_SDOUT_R

ICH_TP3

3

MXM_BIT_CLK_HDMI <18> HDA_BIT_CLK_HDMI <6> BIT_CLK_MDC <25> BIT_CLK_AUDIO <25>

C330

*10P/50V_4

R406 *1K_4R406 *1K_4

R310 *1K_4R310 *1K_4

+3V

RTC

+3VPCU

VCCRTC_1

20MIL

R272

1K_4

VCCRTC_2

20MIL

12

D19 CH500HD19 CH500H

D20 CH500HD20 CH500H

1 3

CN26

RTC_CONN

2

RTC_N01

Q28

MMBT3904

RTC_N03

+VCCRTC

20MIL

1

C391

1U/6V_4

C458

1U/6V_4

SRTC_RST#

12

RTC_RST#

12

ZY2 & ZY6

12 40Tuesday, April 08, 2008

R440 20K_6R440 20K_6

C314

1U/10V_4

R439 20K_6R439 20K_6

R271 16K_6R271 16K_6

Size Document Number Rev

Date: Sheet

+5VPCU

R270

68.1K/F_4

R268

150K/F_6

ICH9M HOST

Quanta Computer Inc.

PROJECT :

G8

*SHORT_ PAD

G7

*SHORT_ PAD

of

1A

5

AD[0..31]<27>

D D

PLT_RST-R#

INTA#<27>

+3V

2

1

3 5

4

U30

TC7SH08FU

C C

B B

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

INTA# INTB# INTC# INTD#

C408

.1U/50V_6

R357

100K_6

D11

E12

E10

G11

F11

F10

D10

U35B

AD0

C8

PCI

AD1

D9

AD2 AD3

E9

AD4

C9

AD5 AD6

B7

AD7

C7

AD8

C5

AD9 AD10

F8

AD11 AD12

E7

AD13

A3

AD14

D2

AD15 AD16

D5

AD17 AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC# PIRQD#C4PIRQH#/GPIO5

ICH9M REV 1.0

PLTRST# <18,21,23,28,29,32>

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1# C/BE2# C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4

F1 G4 B6 A7 F13 F12 E6 F6

D8 B4 D6 A5

D3 E3 R1 C6 E4 C2 J4 A4 F5 D7

C14 D4 R2

H4 K6 F2 G2

REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#

IRDY# PAR PCIRST# DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME#

PLT_RST-R#

PCI_PME#

INTE# INTF# INTG# INTH#

South Bridge Strap Pin (2/3)

Pin Name Strap description

HDA_SYNC

GNT2# / GPIO53

GNT1# / GPIO51

GNT3# / GPIO55

A A

SPI_MOSI

GNT0#

SPI_CS1# / GPIO58 / CLGPIO6

PCI Express Port Config 1 bit 0 (Port 1-4)

PCI Express Port Config 2 bit 2 (Port 5-6)

ESI Strap(Server Only)

Top-Block Swap Override

Integrated TPM Enable

Boot BIOS Selection 0

5

Sampled

PWROK

CLPWROK

PWROK

CLPWROKBoot BIOS Selection 1

0 = Default 1 = Setting bit 0

0 = Setting bit 2 1 = Default

0 = DMI for ESI-compatible 1 = Default

0 = "top-block swap" mode 1 = Default

0 = INT TPM disable(Default) 1 = INT TPM enable

4

REQ0# <27> GNT0# <27>

T59T59

T46T46

GNT3#

CBE0# <27> CBE1# <27> CBE2# <27>

CBE3# <27>

IRDY# <27> PAR <27> PCIRST# <23,27> DEVSEL# <27>

STOP# <27> TRDY# <27>

R367 0_4R367 0_4

FRAME# <27>

PLT_RST# <6>

PCLK_ICH <2>

PCI_PME# <27>

PME# internal PU 18K~42K

TM & AS

LOW COST

Y

N

TPM SPI FLASH

U31

SPI_MOSO

R370 SP@15_4R370 SP@15_4

SPI_MOSO_R

SPI_MOSI_R

SPI_CLK_R

SPI_CS0#_R

Configuration PU/PD

GNT3#

SPI_MOSI_H

Boot Location

SPI_CS#1PCI_GNT#0

SPI(Default)

10

PCI

01

LPC

11

4

GNT0#

SPI_CS1#

U31

2

SO

5

SI

6

SCK

1

CE

SP@W25X16VSSIG

R347 *1K_4R347 *1K_4

R329 TPM@10K_4R329 TPM@10K_4

R344 *1K_4R344 *1K_4

R340 *1K_4R340 *1K_4

HOLD

VDD

WP

VSS

NEW CARD

CARD READER

Wireless

+3V_S5

8

7

3

4

+3V_S5

TV CARD

C411

SP@.1U/16V_4

3

PCIE_RXN1<29>

PCIE_RXN2<23> PCIE_RXP2<23> PCIE_TXN2<23> PCIE_TXP2<23>

JMB_RXN<28> JMB_RXP<28> JMB_TXN<28> JMB_TXP<28>

GLAN_RXN<21> GLAN_RXP<21> GLAN_TXN<21> GLAN_TXP<21>

PCIE_RXP1<29>

PCIE_TXN1<29> PCIE_TXP1<29>

PCIE_RXN4<23> PCIE_RXP4<23>

PCIE_TXN4<23> PCIE_TXP4<23>

SPI_CLK_R SPI_CS0#_R

SPI_MOSI_R

C378 .1U/10V_4C378 .1U/10V_4 C376 .1U/10V_4C376 .1U/10V_4

C385 .1U/10V_4C385 .1U/10V_4 C387 .1U/10V_4C387 .1U/10V_4

C386 .1U/10V_4C386 .1U/10V_4 C392 .1U/10V_4C392 .1U/10V_4

C393 .1U/10V_4C393 .1U/10V_4 C397 .1U/10V_4C397 .1U/10V_4

C464 .1U/10V_4C464 .1U/10V_4 C463 .1U/10V_4C463 .1U/10V_4

R369 SP@15_4R369 SP@15_4 R350 SP@15_4R350 SP@15_4

R348 SP@15_4R348 SP@15_4

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

GLAN_TXN_SB GLAN_TXP_SB

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MOSO

USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9 USBOC#10 USBOC#11

SB_USBBIAS

R301

22.6/F_4

L<0.5",Avoid routing next to clock/high speed signals.

TPM SW

MCH_CFG_6<6>

3

MCH_CFG_6 MCH_CFG_6_R

TPM@DHN-02F-T-V-T/R

USBOC#6

USBOC#2 USBOC#4 USBOC#1

+3V_S5

USBOC#8 USBOC#9 USBOC#10 USBOC#11

U35D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M REV 1.0

R564 *0_4R564 *0_4

U44

1

OFF

ON

2

ON3OFF

R563 *0_4R563 *0_4

RN22

6 7 8 9

10

10K_10P8R

RN21

6 4 2

10K_8P4R

2

4

5 4 3 2 1

78 5 3 1

2

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB27

DMI2RXN

AB26

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

PCI-Express

USB

USBOC#0USBOC#3 USBOC#7

USBOC#5

T25

DMI_CLKP

Direct Media Interface

AF29

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N

SPI

USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

PCI ROUTING TABLE

REQ0# / GNT0# OZ601T

MCH_CFG_6_R <6>

SPI_MOSISPI_MOSI_H

+3V_S5

AF28

AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

DMI_IRCOMP_R

USBP8USBP8+ USBP9USBP9+

R423 24.9/F_4R423 24.9/F_4

INTERUPT

IDSEL

AD20

INTA#

STOP# REQ2# FRAME# REQ1#

+3V

SERR# INTA# INTE# INTC#

+3V

INTH#

REQ0#

+3V

Size Document Number Rev

ICH9M PCIE / PCI / USB

Date: Sheet

1

DMI_RXN0 <6> DMI_RXP0 <6> DMI_TXN0 <6> DMI_TXP0 <6>

DMI_RXN1 <6> DMI_RXP1 <6> DMI_TXN1 <6> DMI_TXP1 <6>

DMI_RXN2 <6> DMI_RXP2 <6> DMI_TXN2 <6> DMI_TXP2 <6>

DMI_RXN3 <6> DMI_RXP3 <6> DMI_TXN3 <6> DMI_TXP3 <6>

CLK_PCIE_ICH# <2> CLK_PCIE_ICH <2>

+1.5V

USBP0- <30> USBP0+ <30>

USBP1- <30> USBP1+ <30> USBP2- <23>

USBP2+ <23>

USBP3- <23>

USBP3+ <23>

USBP5- <22>

USBP5+ <22> USBP6- <29> USBP6+ <29>

USBP7- <29>

USBP7+ <29>

USBP8- <29>

USBP8+ <29>

USBP9- <30>

USBP9+ <30> USBP10- <31> USBP10+ <31>

USBP11- <19>

USBP11+ <19>

M/B USB PortGLAN M/B USB Port Wireless MINI_TV

BLUETOOTH NEW CARD D/B USB Port D/B USB Port Finger Printer DOCKING CCD

DEVICE

RN25

6 7 8 9

10

8.2K_10P8R

RN23

6 7 8 9

10

8.2K_10P8R

RN24

6 7 8 9

10

8.2K_10P8R

Quanta Computer Inc.

PROJECT :

+3V

5 4 3 2 1

+3V

5 4 3 2 1

+3V

5 4 3 2 1

1

REQ3# INTD# DEVSEL# TRDY#

INTG# INTF#

IRDY# PERR# INTB# LOCK#

ZY2 & ZY6

13 40Wednesday, April 09, 2008

of

1A

3

+3V_S5

I

T

R397 2.2K_4R397 2.2K_4

R398 2.2K_4R398 2.2K_4

R336 2.2K_4R336 2.2K_4

R401 2.2K_4R401 2.2K_4

R332 10K_4R332 10K_4

R338 10K_4R338 10K_4

D D

C C

R331 10K_4R331 10K_4

R399 10K_4R399 10K_4

R342 10K_4R342 10K_4

R395 8.2K_4R395 8.2K_4

PWRBTN : 16 ms of internal debounce logic on this pin and internal PU 24K

R323 *10K_4R323 *10K_4

+3V

R337 8.2K_4R337 8.2K_4

R325 10K_4R325 10K_4

R430 8.2K_4R430 8.2K_4

R394 10K_4R394 10K_4

R431 10K_4R431 10K_4

R328 10K_4R328 10K_4

R438 *10K_4R438 *10K_4

R288 10K_4R288 10K_4

R287 10K_4R287 10K_4

R402 *10K_4R402 *10K_4

R362 *10K_4R362 *10K_4

+3V_S5

R403 10K_4R403 10K_4

R404 *100/F_4R404 *100/F_4

5

D3A:(1/31) ASF issue:when iAMT is not implemented,

SMB_CLK_ME

SMB_DATA_ME

PCLK_SMB

PDAT_SMB

RI#

ICH_GPIO60 RI#

SYS_RST#

SMB_ALERT#

PCIE_WAKE#

PM_BATLOW#

DNBSWON#

CLKRUN#

SERIRQ

THERM_ALERT#

EC_SCI#

ICH_GPIO22

SATACLKREQ#

MCH_ICH_SYNC#_R

KBSMI#_ICH

LID591#_ICH

PM_STPPCI#

PM_STPCPU#

TPM Physical Presence for iTPM.

ICH_GPIO57

ICH8M SMBus and SMLink should be connected together to support slave mode Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use)

A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME

OC Pin need PU

PCLK_SMB<2,16,20,21,23,29> PDAT_SMB<2,16,20,21,23,29>

SYS_RST#<3>

PM_SYNC#<6>

PM_STPPCI#<2> PM_STPCPU#<2>

CLKRUN#<27,32>

PCIE_WAKE#<21,23,32>

SERIRQ<27,32>

THERM_ALERT#<3,18>

KBSMI#<32> LID591#<19,29,32>

EC_SCI#<32>

Rev:B ,support Intel low power ECR solution

LP_ECR<25>

SATACLKREQ#<2>

CR_WAKE#<28>

Rev: B new ADD. CR_WAKE#

PCSPK<25>

MCH_ICH_SYNC#<6>

ICH_TP3<12>

4

PCLK_SMB

R384 *0_4R384 *0_4

PDAT_SMB

R385 *0_4R385 *0_4

D24 BAS316D24 BAS316 D23 BAS316D23 BAS316

R535 *0_4R535 *0_4

R436 0_4R436 0_4

T43T43

PCIE_WAKE#

THERM_ALERT#

VR_PWRGD_CLKEN

T62T62

T34T34

T49T49 T52T52

T60T60

T36T36 T37T37

MCH_ICH_SYNC#_R ICH_TP3

T69T69 T67T67 T68T68

PCLK_SMB PDAT_SMB ICH_GPIO60 SMB_CLK_ME SMB_DATA_ME

SYS_RST#

SMB_ALERT#

KBSMI#_ICH LID591#_ICH

BOARD_ID0 BOARD_ID1 BOARD_ID3 ICH_GPIO22

SATACLKREQ# CR_WAKE#

DMI_TERM_SEL ICH_GPIO57

+3V

U35C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP12

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

LAN_PHY_PWR_CTRL/GPIO12

C21

ENERGY_DETECT/GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP9

AJ20

TP10

AJ21

TP11

ICH9M REV 1.0

3

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

SATA

GPIO

SATA

GPIO

SMB

Clocks

SYS GPIO

Power MGTController Link

GPIO

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

MISC

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

SATA[x]GP pins if unused require

8.2-k to 10-k pull-up to Vcc3_3 or

8.2-k to 10-k pull-down to ground

ICH_GPIO21

AH23

BOARD_ID2

AF19

ICH_GPIO36

AE21

ICH_GPIO37

AD20

H1 AF3

P1

SUSBR#

C16

SUSCR#

E16 G17

C10

G20

M2

B13

R3

D20

D22

R5

R6

B16

F24 B19

F22 C19

C25 A19

F21 D18

A16 C18 C11 C20

ICH_PWROK

PM_DPRSLPVR_R

PM_BATLOW#

PM_LAN_ENABLE_R

PM_RSMRST#_R

CL_VREF0_SB CL_VREF1_SB

ICH_GPIO10 ICH_GPIO14 ICH_GPIO9

ZS2 Default not support IAMT. So this interface follow CRB/Checklist PU only

T66T66

T47T47

T48T48

R421 0_4R421 0_4

T53T53

T58T58

T51T51

T50T50

T61T61

R335 10K_4R335 10K_4 R334 10K_4R334 10K_4 R324 10K_4R324 10K_4

R437 10K_4R437 10K_4

R316 10K_4R316 10K_4 R318 10K_4R318 10K_4

R349 0_4R349 0_4 R366 0_4R366 0_4

R327 0_4R327 0_4

R364 0_4R364 0_4

R361 *0_4R361 *0_4

2

+3V

14M_ICH <2> CLKUSB_48 <2>

SUSB# <32> SUSC# <32>

PM_DPRSLPVR <6,35>

DNBSWON# <32>

PM_RSMRST#_R

CK_PWRGD <2>

MPWROK <6,32>

CL_CLK0 <6>

CL_DATA0 <6>

CL_RST#0 <6>

+3V_S5

ICH_PWROK

f integrated LAN is not used LAN_RST# tie it to GND.NC serial R from RSMRS

If Intel LAN is used with Wake On LAN, tie LAN_RST# to RSMRST# and NC 0ohm.

CL_PWROK must not assert after PWROK asserts for IAMT. CL_PWROK to the NB and SB should be connected to existing PWROK inputs on the NB and SB on a platform with no IAMT

VREF1 CRB connect to +3V_S5 Checklist connect to +3V(ZS2 follow)

R389

*453/F_4

.1U/16V_4C472 .1U/16V_4C472

U36

TC7SH08FU

+3V_S5

DELAY_VR_PWRGOOD need PU 2K to +3V. ZS2 PU at power side

53

1

4

R355

*3.24K/F_6

C456

*.1U/10V_4

PWROK_EC

2

R420 100K_4R420 100K_4

<Checklist ver0.8> The ICH9M Controller Link 1 VREF circuit is required only if Intel AMT is to be supported.

CL_VREF0_SBCL_VREF1_SB

1

DELAY_VR_PWRGOOD <3,6,32,

PWROK_EC <32>

+3V+3V

R363

3.24K/F_6

C405

R359

.1U/10V_4

453/F_4

C406

.1U/10V_4

R320 10K_4R320 10K_4

R341 10K_4R341 10K_4

B B

CR_WAKE#

ICH_PWROK

U29

1

VR_PWRGD_CK410#<35>

2

NC7SZ04

5

VR_PWRGD_CLKEN

43

.1U/10V_4

R356

100K_4

PM_RSMRST#_R

South Bridge Strap Pin (3/3)

Pin Name Strap description

A A

GPIO20

SPKR

GPIO49

Reserved PWROK

No Reboot PWROK

DMI Termination Voltage

Sampled

PWROK

5

Configuration PU/PD

0 = Default 1 = No Reboot mode

0 = for desktop applications 1 = for mobile applications Internal PU

PCSPK

DMI_TERM_SEL

4

R346 *1K_4R346 *1K_4

R400 *1K_4R400 *1K_4

+3V

3

ICH9M CRB connect to EC directly

R388 *0_4R388 *0_4

3 1

Q33

R396

10K_4

R352

2.2K_4

Q33

MMBT3906

2

R382 4.7K_4R382 4.7K_4

2

D27

3

BAV99

1

ZD1 INTEL FAE (08/17)

2

"Add RSMRST# isolation (important!!! See

D26

ww22 Santa Rosa MoW)"

3

Default stuff for Teenah(Interposer)

BAV99

chipset ZS2 Intel FAE suggestion to add for to protect RTC/CMOS data from corruption

1

when system encounters an abnormal power down sequence

RSMRST# <32>

+3VSUS

2

+3V+3V +3V+3V

R303

R283

*10K_4

R284

10K_4

R303

*10K_4

BOARD_ID2BOARD_ID3 BOARD_ID0BOARD_ID1

R302

10K_4

ZY2

LOW COST

ZY6

Size Document Number Rev

ICH9M GPIO

Date: Sheet

R333

SP@10K_4

R330

SP@10K_4

R304

SP@10K_4

R305

SP@10K_4

ID2ID3

0000

000

00

1

00

1

000

1

Quanta Computer Inc.

PROJECT :

1

ZY2 & ZY6

14 40Tuesday, April 08, 2008

of

ID0ID1Board ID

1

0

1

1A

5

Power consumption reference to Intel 642879 ICH9 Family EDS Rev 1.5

2~3.456v

+VCCRTC

3.6uA_G3

D D

5V 2mA

5V 2mA_S0 1mA_S3/S4/S5

C C

B B

D29 BAT54D29 BAT54

+3V

R405 10_6R405 10_6

+5V

D25 BAT54D25 BAT54

+3V_S5

+5V_S5

+1.5V

R315 10_6R315 10_6

L39 BLM21PG331SN1DL39 BLM21PG331SN1D

+1.5V

1.5V 646mA

2 1

330 Ohms@ 100 MHz , 0805

1 2

+

C473

220U/6_7343

C365

22U/6V_8

L40 10UH_8L40 10UH_8

VCC1_5_A

1.5V 1342mA

1.05V , Powered by VCC1_05 in S0

C400 .1U/10V_4C400 .1U/10V_4

R392 0_6R392 0_6

+3V

3.3V 19mA_S0 , 78mA_S3/S4/S5

1.5V 23mA

L35 1UH_6L35 1UH_6

+1.5V

A A

If use SB MAC for LAN function. And support wake up need connect to relation power.

+1.5V

1.5V 80mA

C455

C460

.1U/10V_4

SB_V5REF

C454

.1U/10V_4

+5VPCU_ICH_V5REF_SUS

C361

.1U/10V_4

C377

22U/6V_8

1.5V 47mA

C480

10U/10V_8

VCCLAN1_05_INT_ICH

+3VM_VCCPAUX

+1.5V_ICH_GLANPLL_R

C407

10U/10V_8

C389

2.2U/10V_6

+1.5V_APLL_ICH +3V_VCCSUSHDA

C478

1U/6V_4

C362

1U/6V_4

C363

1U/6V_4

1.5V 11mA

C364

.1U/10V_4

C388

.1U/10V_4

C459

.1U/10V_4

C404

2.2U/10V_6

C465

4.7U/10V_6

AG15

AG10 AG11

AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29

AJ19

AC16 AD15 AD16 AE15 AF15

AH15 AJ15

AC11 AD11 AE11 AF11

AH10 AJ10

AC18 AC19

AC21

AC12 AC13 AC14

A23

AE1

F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25

U23 W24 W25

K23

Y24

Y25

AC9

G10

AJ5

AA7

AB6

AB7 AC6 AC7

A10

A11

A12

B12

A27

D28

D29

E26

E27

A26

4

U35F

A6

G9

ICH9M REV 1.0

VCCRTC

V5REF

V5REF_SUS

VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49]

VCCSATAPLL

VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08]

VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]

VCC1_5_A[17]

VCC1_5_A[18] VCC1_5_A[19]

VCC1_5_A[20]

VCC1_5_A[21] VCC1_5_A[22]

VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25]

VCCUSBPLL

VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]

VCCLAN1_05[1] VCCLAN1_05[2]

VCCLAN3_3[1] VCCLAN3_3[2]

VCCGLANPLL

VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4]

VCCGLAN3_3

CORE

VCCA3GP ATXARX USB CORE

VCCP_CORE

PCI

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]

VCCPSUSVCCPUSB

VCCSUS3_3[05]

VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]

GLAN POWER

VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[01]

VCC3_3[02]

VCC3_3[07]

VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]

VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29

W23 Y23

AB23 AC23

AG29

AJ6

AC10

AD19 AF20 AG24 AC20

B9 F9 G3 G6 J2 J7 K7

AJ4

AJ3

AC8 F17

AD8

F18

A18 D16 D17 E22

AF1

T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

G22

G23

A24 B24

VCCCL1_05_INT_ICH

VCCCL1_5_INT_ICH

+1.5V_ICH_VCCDMIPLL

+1.05V_ICH_DMI

C371

4.7U/10V_6

C350

.1U/10V_4

+3V_HDA_IO_ICH

TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2

TP_VCCSUS1_5_ICH_1

VCCSUS1_5_INT_ICH

C375

.1U/10V_4

C471

.01U/16V_4

C401

.1U/10V_4

C383

*1U/10V_4

3

C373

.1U/10V_4

C368

.1U/10V_4

C380

.1U/10V_4

C370

.022U/10V_4

L38 1UH_6L38 1UH_6

C470

10U/10V_8

L31 NBQ160808T-100Y-NL31 NBQ160808T-100Y-N

C374

Checklist stuff 22U,but CRB no

22U/6V_8

+1.05V

C366

.1U/10V_4

C476

.1U/10V_4

C381

C395

.1U/10V_4

T42T42 T45T45

T41T41

C372

.022U/16V_4

C390

C382

.1U/10V_4

*.1U/10V_4

+1.05V

1.05V 1634mA

+1.5V

500 mA, 20%

5 Ohms @ 100 MHz , 0.7A

C367

4.7U/10V_6

C474

.1U/10V_4

C352

.1U/10V_4

C369

.1U/10V_4

VCCCL1_05 power by VCC1_05_A in S0 VCCCL1_5 power by VCC1_5_A in S0

+3V

1.5V 23mA

+1.05V

R290 E@0_6R290 E@0_6

C351

R291 I@0_6R291 I@0_6

.1U/10V_4

R292 E@0_6R292 E@0_6

R293 I@0_6R293 I@0_6

1.5V / 3.3V 11mA_S0 , 1mA_S3/S4/S5

VCCSUS1_05 power by VCC1_05 in S0 / VCCSUS3_3 in S3/S4/S5 VCCSUS1_5 power by VCC1_5_A in S0 / VCCSUS3_3 in S3/S4/S5

+3V_S5

Check list:

0.1U for Pin AF1

3.3V 19mA_S0 , 73mA_S3/S4/S5

If use SB MAC for LAN function. And support wake up need connect to relation power.

+3V_S5

+1.5V_S5

2

1.05V 50mA

VCCP 2mA

+3V

+1.5V

+3V

VCC3_3

3.3V 308mA

1.5V / 3.3V 11mA

NOTE: If (G)MCH's HD Audio signals are connected to ICH9M for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be only on 1.5V. These power pins on ICH9M can be supplied with 3.3V if and only if (G)MCH's HDA is not connected to ICH9M. Consequently, only 1.5V audio/modem codecs can be used on the platform.

3.3V 212mA_S0 , 53mA_S3/S4/S5

ZS2 Default not support INT HDMI interface

Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V

Support INT HDMI HDA interface. These power only support 1.5V.Device must to meet.

AA26 AA27

AA23 AB28 AB29

AC17 AC26 AC27

AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29

AE12 AE13 AE14 AE16 AE17

AE20 AE24

AF13 AF16 AF18 AF22

AH26

AF26 AF27

AG13 AG16 AG18 AG20 AG23

AH12 AH14 AH17 AH19

AH22 AH25 AH28

AJ12 AJ14 AJ17

AA3 AA6 AB1

AB4 AB5

AC3 AD1

AD4 AD5 AD6 AD7 AD9

AE2

AE3 AE4 AE6 AE9

AF5 AF7 AF9

AG3 AG6 AG9

AH2

AH5 AH8

AJ8 B11 B14 B17

B20 B23

C26 C27 E11 E14 E18

E21 E24

F16 F28 F29 G12 G14 G18 G21 G24 G26 G27

G8

H2 H23 H28 H29

U35E

VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076]

B2

VSS[077] VSS[078] VSS[079]

B5

VSS[080]

B8

VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086]

E2

VSS[087] VSS[088] VSS[089]

E5

VSS[090]

E8

VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]

ICH9M REV 1.0

1

VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]

VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

+3V

3.3V 1mA

Size Document Number Rev

ICH9 POWER

Date: Sheet

5

4

3

2

Date: Sheet

Quanta Computer Inc.

PROJECT :

ZY2 & ZY6

15 40Tuesday, April 08, 2008

of

1

of

1A

5

+VDR_SUS +VDR_SUS +VDR_SUS +VDR_SUS

CN24

1

VREF

3

M_A_DQ0 M_A_DQ1

M_A_DQS#0 M_A_DQS0

M_A_DQ2

D D

C C

B B

A A

M_A_DQ3

M_A_DQ8 M_A_DQ9

M_A_DQS#1 M_A_DQS1

M_A_DQ10 M_A_DQ11

M_A_DQ16 M_A_DQ17

M_A_DQS#2 M_A_DQS2

M_A_DQ18 M_A_DQ19

M_A_DQ24 M_A_DQ25

M_A_DM3

M_A_DQ26 M_A_DQ27

M_CKE0

M_A_BS2

M_A_A12 M_A_A9 M_A_A8

M_A_A5 M_A_A3 M_A_A1

M_A_A10 M_A_BS0 M_A_WE#

M_A_CAS# M_CS#1

M_ODT1

M_A_DQ32 M_A_DQ33

M_A_DQS#4 M_A_DQS4

M_A_DQ34 M_A_DQ35

M_A_DQ40 M_A_DQ41

M_A_DM5

M_A_DQ42 M_A_DQ43

M_A_DQ48 M_A_DQ49

M_A_DQS#6 M_A_DQS6

M_A_DQ50 M_A_DQ51

M_A_DQ56 M_A_DQ57

M_A_DM7

M_A_DQ58 M_A_DQ59

SDA_DDR SCL_DDR

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

D2@DDR2_DIMM_H5.2_Stand

SO-DIMM0 SO-DIMM1

A_SA0<17> A_SA1<17>

Close to DIMM0

5

2

VSS46

DQ4 DQ5

VSS15

DM0

VSS5

DQ6 DQ7

VSS16

DQ12 DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14 DQ15

VSS54

VSS20

DQ20 DQ21 VSS6

NC3 DM2

VSS21

DQ22 DQ23

VSS24

DQ28 DQ29

VSS25

DQS#3

DQS3

VSS10

DQ30 DQ31 VSS8 CKE1 VDD8

A15 A14

VDD11

A11

A7 A6

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

VDD4

A4 A2 A0

VDD12

BA1

RAS#

S0# VDD1 ODT0

A13 VDD6

NC2

VSS12

DQ36 DQ37

VSS28

DM4

VSS42

DQ38 DQ39

VSS55

DQ44 DQ45

VSS43

DQS#5

DQS5

VSS56

DQ46 DQ47

VSS44

DQ52 DQ53

VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54 DQ55

VSS35

DQ60 DQ61 VSS7

DQS#7

DQS7

VSS36

DQ62 DQ63

VSS13

SA0 SA1

M_A_DQ4

4

M_A_DQ5

6 8

M_A_DM0

10 12

M_A_DQ6

14

M_A_DQ7

16 18

M_A_DQ12

20

M_A_DQ13

22 24

M_A_DM1

26 28

M2_CLK0

30

M2_CLK#0

32 34

M_A_DQ14

36

M_A_DQ15

38 40

42

M_A_DQ20

44

M_A_DQ21

46 48

PM_EXTTS#0

50

M_A_DM2

52 54

M_A_DQ22

56

M_A_DQ23

58 60

M_A_DQ28

62

M_A_DQ29

64 66

M_A_DQS#3

68

M_A_DQS3

70 72

M_A_DQ30

74

M_A_DQ31

76 78

M_CKE1

80 82 84

M_A_A14

86 88

M_A_A11

90

M_A_A7

92

M_A_A6

94 96

M_A_A4

98

M_A_A2

100

M_A_A0

102 104

M_A_BS1

106

M_A_RAS#

108 110 112

M_ODT0

114

M_A_A13

116 118 120 122

M_A_DQ36

124

M_A_DQ37

126 128

M_A_DM4

130 132

M_A_DQ38

134 136 138

M_A_DQ44

140

M_A_DQ45

142 144

M_A_DQS#5

146

M_A_DQS5

148 150

M_A_DQ46

152

M_A_DQ47

154 156

M_A_DQ52

158

M_A_DQ53

160 162

M2_CLK1

164

M2_CLK#1

166 168

M_A_DM6

170 172

M_A_DQ54

174

M_A_DQ55

176 178

M_A_DQ60

180

M_A_DQ61

182 184

M_A_DQS#7

186

M_A_DQS7

188 190

M_A_DQ62

192

M_A_DQ63

194 196

A_SA0

198

A_SA1

200

SMbus address A0

terminated to +SMDDR_VTERM

R522 D2@10K_4R522 D2@10K_4 R521 D2@10K_4R521 D2@10K_4

10/16: Change to D2@

NOTE:Place one cap close to every 2 pull-up resistors

4

M_A_BS0

RP43 D2@56X2_4RP43 D2@56X2_4

M_A_A10

M_A_A2 M_A_A4

M_A_A5 M_A_A8

M_A_A6 M_A_A7

M_A_A1 M_A_A3

M_A_A9 M_A_A12

M_ODT0 M_ODT1

M_A_RAS# M_CS#0

M_A_BS2 M_CKE0

M_A_CAS# M_A_WE#

M_A_BS1 M_A_A0

M_CKE1 M_A_A14

M_CS#1 M_A_A13

M_A_A11

132

RP40 D2@56X2_4RP40 D2@56X2_4

132

RP45 D2@56X2_4RP45 D2@56X2_4

132

RP38 D2@56X2_4RP38 D2@56X2_4

132

RP44 D2@56X2_4RP44 D2@56X2_4

132

RP46 D2@56X2_4RP46 D2@56X2_4

132

RP36 D2@56X2_4RP36 D2@56X2_4

132

RP37 D2@56X2_4RP37 D2@56X2_4

132

RP47 D2@56X2_4RP47 D2@56X2_4

132

RP42 D2@56X2_4RP42 D2@56X2_4

132

RP39 D2@56X2_4RP39 D2@56X2_4

132

RP35 D2@56X2_4RP35 D2@56X2_4

132

RP41 D2@56X2_4RP41 D2@56X2_4

132

R275 D2@56_4R275 D2@56_4

D2@.1U/16V_4C318 D2@.1U/16V_4C318 D2@.1U/16V_4C335 D2@.1U/16V_4C335 D2@.1U/16V_4C319 D2@.1U/16V_4C319 D2@.1U/16V_4C341 D2@.1U/16V_4C341 D2@.1U/16V_4C340 D2@.1U/16V_4C340 D2@.1U/16V_4C339 D2@.1U/16V_4C339 D2@.1U/16V_4C337 D2@.1U/16V_4C337 D2@.1U/16V_4C342 D2@.1U/16V_4C342 D2@.1U/16V_4C332 D2@.1U/16V_4C332 D2@.1U/16V_4C333 D2@.1U/16V_4C333 D2@.1U/16V_4C334 D2@.1U/16V_4C334 D2@.1U/16V_4C338 D2@.1U/16V_4C338 D2@.1U/16V_4C331 D2@.1U/16V_4C331 D2@.1U/16V_4C336 D2@.1U/16V_4C336

D2@.1U/16V_4C316 D2@.1U/16V_4C316

2.2U/10V_6C504 2.2U/10V_6C504

C357 D2@330U/2.5V_7

+

D2@2.2U/10V_6C323 D2@2.2U/10V_6C323 D2@2.2U/10V_6C324 D2@2.2U/10V_6C324 D2@2.2U/10V_6C321 D2@2.2U/10V_6C321 D2@2.2U/10V_6C322 D2@2.2U/10V_6C322 SP@2.2U/10V_6C509 SP@2.2U/10V_6C509

SP@:DDR2 上 2.2U DDR3

上

4

10U

4

+VDR_VTT

+VDR_VREF

+VDR_VTT

+VDR_SUS

3

+VDR_VREF+VDR_VREF

M_B_DQ0 M_B_DQ1

M_B_DQS#0 M_B_DQS0

M_B_DQ2 M_B_DQ3

M_B_DQ8 M_B_DQ9

M_B_DQS#1 M_B_DQS1

M_B_DQ10 M_B_DQ11

M_B_DQ16 M_B_DQ17

M_B_DQS#2 M_B_DQS2

M_B_DQ18 M_B_DQ19

M_B_DQ24 M_B_DQ25

M_B_DM3

M_B_DQ26 M_B_DQ27

M_CKE2

M_B_BS2

M_B_A12 M_B_A9 M_B_A8

M_B_A5 M_B_A3 M_B_A1

M_B_A10 M_B_BS0 M_B_WE#M_CS#0

M_B_CAS# M_CS#3

M_ODT3

M_B_DQ32 M_B_DQ33

M_B_DQS#4 M_B_DQS4

M_B_DQ34 M_B_DQ35

M_B_DQ40 M_B_DQ41

M_B_DM5

M_B_DQ42 M_B_DQ43

M_B_DQ48 M_B_DQ49

M_B_DQS#6 M_B_DQS6

M_B_DQ50 M_B_DQ51

M_B_DQ56 M_B_DQ57

M_B_DM7

M_B_DQ58 M_B_DQ59

SDA_DDR SCL_DDR

+3V+3V

CN25

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

D2@DDR2_DIMM_H9.2_Stand

PC4800 DDR2 SDRAM

VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)

2

VSS46

DQ4 DQ5

VSS15

DM0

VSS5

DQ6 DQ7

VSS16

DQ12 DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14 DQ15

VSS54

VSS20

DQ20 DQ21 VSS6

NC3 DM2

VSS21

DQ22 DQ23

VSS24

DQ28

DQ29 VSS25 DQS#3

DQS3

VSS10

DQ30

DQ31

VSS8

CKE1

VDD8

A15 A14

VDD11

A11

A7 A6

SO-DIMM (200P)

VDD4

A4 A2 A0

VDD12

BA1

RAS#

S0# VDD1 ODT0

A13 VDD6

NC2

VSS12

DQ36 DQ37

VSS28

DM4

VSS42

DQ38 DQ39

VSS55

DQ44

DQ45 VSS43 DQS#5

DQS5

VSS56

DQ46

DQ47 VSS44

DQ52

DQ53 VSS57

CK1

CK1# VSS45

DM6

VSS32

DQ54

DQ55 VSS35

DQ60

DQ61

VSS7 DQS#7

DQS7

VSS36

DQ62

DQ63 VSS13

SA0 SA1

M_B_DQ4

4

M_B_DQ5

6 8

M_B_DM0

10 12

M_B_DQ6

14

M_B_DQ7

16 18

M_B_DQ12

20

M_B_DQ13

22 24

M_B_DM1

26 28

M2_CLK2

30

M2_CLK#2

32 34

M_B_DQ14

36

M_B_DQ15

38 40

42

M_B_DQ20

44

M_B_DQ21

46 48

PM_EXTTS#1

50

M_B_DM2

52 54

M_B_DQ22

56

M_B_DQ23

58 60

M_B_DQ28

62

M_B_DQ29

64 66

M_B_DQS#3

68

M_B_DQS3

70 72

M_B_DQ30

74

M_B_DQ31

76 78

M_CKE3

80 82 84

M_B_A14

86 88

M_B_A11

90

M_B_A7

92

M_B_A6

94 96

M_B_A4

98

M_B_A2

100

M_B_A0

102 104

M_B_BS1

106

M_B_RAS#

108

M_CS#2

110 112

M_ODT2

114

M_B_A13

116 118 120 122

M_B_DQ36

124

M_B_DQ37

126 128

M_B_DM4

130 132

M_B_DQ38

134

M_B_DQ39M_A_DQ39

136 138

M_B_DQ44

140

M_B_DQ45

142 144

M_B_DQS#5

146

M_B_DQS5

148 150

M_B_DQ46

152

M_B_DQ47

154 156

M_B_DQ52

158

M_B_DQ53

160 162

M2_CLK3

164

M2_CLK#3

166 168

M_B_DM6

170 172

M_B_DQ54

174

M_B_DQ55

176 178

M_B_DQ60

180

M_B_DQ61

182 184

M_B_DQS#7

186

M_B_DQS7

188 190

M_B_DQ62

192

M_B_DQ63

194 196

B_SA0

198

B_SA1

200

M_CS#2 M_ODT2

M_B_A8 M_B_A5

M_B_A6 M_B_A4

M_B_A11 M_B_A7

M_B_A12 M_B_A9

M_B_A2 M_B_A0

M_B_A3 M_B_A1

M_B_A10 M_B_BS0

M_B_BS2 M_CKE2

M_B_A13 M_CS#3

M_B_BS1 M_B_RAS#

M_CKE3 M_B_A14

M_B_CAS# M_B_WE#

M_ODT3

SMbus address A2

+3V

B_SA1<17> B_SA0<17>

R273 D2@10K_4R273 D2@10K_4 R274 D2@10K_4R274 D2@10K_4

Close to DIMM1

3

2

RP21 D2@56X2_4RP21 D2@56X2_4

132

上上

SP@2.2U/10V_6C511 SP@2.2U/10V_6C511 .1U/16V_4C506 .1U/16V_4C506 .1U/16V_4C507 .1U/16V_4C507 .1U/16V_4C508 .1U/16V_4C508 .1U/16V_4C503 .1U/16V_4C503

2

4

D2@.1U/16V_4C309 D2@.1U/16V_4C309 D2@.1U/16V_4C301 D2@.1U/16V_4C301 D2@.1U/16V_4C303 D2@.1U/16V_4C303 D2@.1U/16V_4C311 D2@.1U/16V_4C311 D2@.1U/16V_4C302 D2@.1U/16V_4C302 D2@.1U/16V_4C306 D2@.1U/16V_4C306 D2@.1U/16V_4C307 D2@.1U/16V_4C307 D2@.1U/16V_4C315 D2@.1U/16V_4C315 D2@.1U/16V_4C312 D2@.1U/16V_4C312 D2@.1U/16V_4C304 D2@.1U/16V_4C304 D2@.1U/16V_4C313 D2@.1U/16V_4C313 D2@.1U/16V_4C305 D2@.1U/16V_4C305 D2@.1U/16V_4C310 D2@.1U/16V_4C310 D2@.1U/16V_4C308 D2@.1U/16V_4C308

2.2U 10U

.1U/16V_4C502 .1U/16V_4C502

1U/10V_4C505 1U/10V_4C505

RP28 D2@56X2_4RP28 D2@56X2_4

RP24 D2@56X2_4RP24 D2@56X2_4

RP25 D2@56X2_4RP25 D2@56X2_4

RP29 D2@56X2_4RP29 D2@56X2_4

RP23 D2@56X2_4RP23 D2@56X2_4

RP32 D2@56X2_4RP32 D2@56X2_4

RP31 D2@56X2_4RP31 D2@56X2_4

RP34 D2@56X2_4RP34 D2@56X2_4

RP30 D2@56X2_4RP30 D2@56X2_4

RP22 D2@56X2_4RP22 D2@56X2_4

RP26 D2@56X2_4RP26 D2@56X2_4

RP33 D2@56X2_4RP33 D2@56X2_4

R269 D2@56_4R269 D2@56_4

SP@:DDR2 DDR3

+VDR_VTT

+VDR_SUS

+3V

1

FOR DDR2

M2_CLK#0 M2_CLK0 M2_CLK#1 M2_CLK1

M2_CLK#2 M2_CLK2 M2_CLK#3 M2_CLK3

PDAT_SMB<2,14,20,21,23,29>

PCLK_SMB<2,14,20,21,23,29>

Size Document Number Rev

Date: Sheet

RN31 D2@0_4P2RRN31 D2@0_4P2R

4 3

RN29 D2@0_4P2RRN29 D2@0_4P2R

4 3

RN20 D2@0_4P2RRN20 D2@0_4P2R

4 3

RN19 D2@0_4P2RRN19 D2@0_4P2R

4 3

PM_EXTTS#1<6,17>

PM_EXTTS#0<6,17>

M_CS#[3:0]<6,17>

M_ODT[3:0]<6,17>

M_CKE[3:0]<6,17>

M_CLK#[3:0]<6,17>

M_CLK[3:0]<6,17>

M_A_CAS#<8,17>

M_A_RAS#<8,17>

M_A_WE#<8,17>

M_A_BS[2:0]<8,17>

M_A_DM[7:0]<8,17>

M_A_DQS#[7:0]<8,17>

M_A_DQS[7:0]<8,17>

M_A_A[14:0]<8,17>

M_A_DQ[63:0]<8,17>

M_B_CAS#<8,17>

M_B_RAS#<8,17>

M_B_WE#<8,17>

M_B_BS[2:0]<8,17>

M_B_DM[7:0]<8,17>

M_B_DQS#[7:0]<8,17>

M_B_DQS[7:0]<8,17>

M_B_A[14:0]<8,17>

M_B_DQ[63:0]<8,17>

+3V

2

3

Q31

+3V

RHU002N06

2

3

Q30

RHU002N06

Quanta Computer Inc.

PROJECT :

DDRII SO-DIMM

12

R353

10K_4

1

PM_EXTTS#1

PM_EXTTS#0

M_A_CAS#

M_A_RAS#

M_A_WE#

M_B_CAS#

M_B_RAS#

M_B_WE#

M_CS#[3:0]

M_ODT[3:0]

M_CKE[3:0]

M_CLK#[3:0]

M_CLK[3:0]

M_A_BS[2:0]

M_A_DM[7:0]

M_A_DQS#[7:0]

M_A_DQS[7:0]

M_A_A[14:0]

M_A_DQ[63:0]

M_B_BS[2:0]

M_B_DM[7:0]

M_B_DQS#[7:0]

M_B_DQS[7:0]

M_B_A[14:0]

M_B_DQ[63:0]

R354

10K_4

1

M_CLK#0

M_CLK0

M_CLK#1

M_CLK1

M_CLK#2

M_CLK2

M_CLK#3

M_CLK3

SDA_DDR <17>

SCL_DDR <17>

ZY2 & ZY6

of

16 40Tuesday, April 08, 2008

1A

5

CN13

75

VDD1

81

VDD3

87

VDD5

93

+VDR_VREF

+3V

+VDR_VTT

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DM0

M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQS#1 M_A_DQS1

M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQS#2 M_A_DQS2

M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DM3

M_CKE0

M_A_BS2 M_A_BS0

M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10 M_A_A13

M3_CLK0 M3_CLK#0

M_CS#1

M_A_WE# M_A_CAS#

M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQS#4 M_A_DQS4

M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DM5

M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQS#6 M_A_DQS6

M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DM7

PM_EXTTS#0

A_SA0 A_SA1

C490

D3@2.2U/10V_6

D D

C C

B B

10/16: Change to D3@

A A

5

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

1

VREF_DQ

199

VDD(SPD)

5

DQ0

7

DQ1

15

DQ2

17

DQ3

11

DM0

21

DQ8

23

DQ9

33

DQ10

35

DQ11

27

DQS#1

29

DQS1

39

DQ16

41

DQ17

51

DQ18

53

DQ19

45

DQS#2

47

DQS2

57

DQ24

59

DQ25

67

DQ26

69

DQ27

63

DM3

73

CKE0

79

BA2

109

BA0

83

A12/BC#

85

A9

89

A8

91

A5

95

A3

97

A1

107

A10/AP

119

A13

101

CK0

103

CK0#

121

CS1#

113

WE#

115

CAS#

129

DQ32

131

DQ33

141

DQ34

143

DQ35

135

DQS#4

137

DQS4

147

DQ40

149 157 159 153

163 165 175 177 169 171

181 183 191 193 187

198

197 201

77

125

203

3

9 13 19 25 31 37 43 49 55 61 65 71

127 133 139 145 151 155 161 167 173 179 185 189 195

SMbus address A0

DDR3 SDRAM

DQ41 DQ42 DQ43 DM5

DQ48 DQ49 DQ50 DQ51 DQS#6 DQS6

DQ56 DQ57 DQ58 DQ59 DM7

EVENT#

SA0 SA1

NC1 NCTEST

VTT1

VSS2 VSS4 VSS5 VSS7 VSS9 VSS11 VSS13 VSS15 VSS18 VSS20 VSS22 VSS23 VSS25 VSS27 VSS29 VSS32 VSS34 VSS36 VSS37 VSS39 VSS41 VSS44 VSS46 VSS48 VSS49 VSS51

D3@DDR3_SODIMM_H4_RVS

SO-DIMM0

+VDR_SUS+VDR_SUS

76

VDD2

82

VDD4

88

VDD6

94

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VREF_CA

DQ4 DQ5 DQ6 DQ7

DQS#0

DQS0

DQ12

DQ13

DQ14

DQ15

DM1

DQ20

DQ21

DQ22

DQ23

DM2

DQ28

DQ29

DQ30

DQ31 DQS#3

DQS3

CKE1

BA1

RESET#

CK1

CK1#

CS#0

RAS#

ODT0

ODT1

DQ36

DQ37

DQ38

DQ39

DM4

SO-DIMM (204P)

DQ44

DQ45

DQ46

DQ47 DQS#5

DQS5

DQ52

DQ53

DQ54

DQ55

DM6

DQ60

DQ61

DQ62

DQ63 DQS#7

DQS7

SDA SCL

NC2

VTT2

VSS1

VSS3

VSS6

VSS8

VSS10 VSS12 VSS14 VSS16 VSS17 VSS19 VSS21 VSS24 VSS26 VSS28 VSS30 VSS31 VSS33 VSS35 VSS38 VSS40 VSS42 VSS43 VSS45 VSS47 VSS50 VSS52

+VDR_VREF

100 106 112 118 124 126

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

16

M_A_DQ7

18

M_A_DQS#0

10

M_A_DQS0

12

M_A_DQ12

22

M_A_DQ13

24

M_A_DQ14

34

M_A_DQ15

36

M_A_DM1

28

M_A_DQ20

40

M_A_DQ21

42

M_A_DQ22

50

M_A_DQ23

52

M_A_DM2

46

M_A_DQ28

56

M_A_DQ29

58

M_A_DQ30

68

M_A_DQ31

70

M_A_DQS#3

62

M_A_DQS3

64

M_CKE1

74

M_A_BS1

108

M_A_A14

80

A14 A11

A7 A6 A4 A2 A0

A15

84 86 90 92 96 98

30

102 104

114

110

116 120

130 132 140 142 136

146 148 158 160 152 154

164 166 174 176 170

180 182 192 194 186 188

200 202

78 122

204

2 8 14 20 26 32 38 44 48 54 60 66 72 128 134 138 144 150 156 162 168 172 178 184 190 196

M_A_A11 M_A_A7 M_A_A6 M_A_A4 M_A_A2 M_A_A0

DDR3_DRAMRST#

M3_CLK1 M3_CLK#1

M_CS#0

M_A_RAS#

M_ODT0 M_ODT1

M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DM4

M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQS#5 M_A_DQS5

M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DM6

M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#7 M_A_DQS7

SDA_DDR SCL_DDR

+VDR_VTT

4

C492

D3@2.2U/10V_6

4

10/16: ADD

D3@.1U/16V_4C489 D3@.1U/16V_4C489 D3@.1U/16V_4C488 D3@.1U/16V_4C488 D3@.1U/16V_4C487 D3@.1U/16V_4C487 D3@.1U/16V_4C486 D3@.1U/16V_4C486

C475 D3@330U/2.5V_7

+

D3@2.2U/16V_6C482 D3@2.2U/16V_6C482 D3@2.2U/16V_6C481 D3@2.2U/16V_6C481 D3@2.2U/16V_6C484 D3@2.2U/16V_6C484 D3@2.2U/16V_6C485 D3@2.2U/16V_6C485

.1U/16V_4C496 .1U/16V_4C496

1U/10V_4C495 1U/10V_4C495

+VDR_VREF

D3@.1U/16V_4C483 D3@.1U/16V_4C483

D3@2.2U/10V_6C477 D3@2.2U/10V_6C477

+VDR_SUS

+3V

3

CN11

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

+3V

M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DM0

M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQS#1 M_B_DQS1

M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQS#2 M_B_DM2 M_B_DQS2

M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DM3

M_CKE2 M_CKE3

M_B_BS2 M_B_BS0

M_B_A12 M_B_A9 M_B_A8 M_B_A5 M_B_A3

M_B_A10 M_B_A13

M3_CLK2 M3_CLK#2 M3_CLK#3

M_CS#3

M_B_WE# M_B_CAS#

M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQS#4 M_B_DQS4

M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DM5

M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQS#6 M_B_DQS6

M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DM7

B_SA0

+VDR_VTT +VDR_VTT

C497

D3@2.2U/10V_6

3

VDD13

117

VDD15

123

VDD17

1

VREF_DQ

199

VDD(SPD)

5

DQ0

7

DQ1

15

DQ2

17

DQ3

11

DM0

21

DQ8

23

DQ9

33

DQ10

35

DQ11

27

DQS#1

29

DQS1

39

DQ16

41

DQ17

51

DQ18

53

DQ19

45

DQS#2

47

DQS2

57

DQ24

59

DQ25

67

DQ26

69

DQ27

63

DM3

73

CKE0

79

BA2

109

BA0

83

A12/BC#

85

A9

89

A8

91

A5

95

A3

97

A1

107

A10/AP

119

A13

101

CK0

103

CK0#

121

CS1#

113

WE#

115

CAS#

129

DQ32

131

DQ33

141

DQ34

143

DQ35

135

DQS#4

137

DQS4

147

DQ40

149

DQ41

157

DQ42

159

DQ43

153

DM5

163

DQ48

165

DQ49

175

DQ50

177

DQ51

169

DQS#6

171

DQS6

181

DQ56

183

DQ57

191

DQ58

193

DQ59

187

DM7

198

EVENT#

197

SA0

201

SA1

77

NC1

125

NCTEST

203

VTT1

3

VSS2

9

VSS4

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

49

VSS18

55

VSS20

61

VSS22

65

VSS23

71

VSS25

127

VSS27

133

VSS29

139

VSS32

145

VSS34

151

VSS36

155

VSS37

161

VSS39

167

VSS41

173

VSS44

179

VSS46

185

VSS48

189

VSS49

195

VSS51

D3@DDR3_SODIMM_H5.2_RVS

SO-DIMM1

SMbus address A2

VDD2 VDD4 VDD6

VDD8 VDD10 VDD12 VDD14 VDD16 VDD18

VREF_CA

DQ4 DQ5 DQ6 DQ7

DQS#0

DQS0

DQ12

DQ13

DQ14

DQ15

DM1

DQ20

DQ21

DQ22

DQ23

DM2

DQ28

DQ29

DQ30

DQ31 DQS#3

DQS3

CKE1

BA1

A14 A11

A7 A6 A4 A2 A0

RESET#

CK1

CK1#

CS#0

RAS#

ODT0

ODT1

DQ36

DQ37

DQ38

DQ39

DM4

DDR3 SDRAM

SO-DIMM (204P)

DDR3 SDRAM

SO-DIMM (204P)

DQ44

DQ45

DQ46

DQ47 DQS#5

DQS5

DQ52

DQ53

DQ54

DQ55

DM6

DQ60

DQ61

DQ62

DQ63 DQS#7

DQS7

SDA SCL

A15

NC2

VTT2

VSS1

VSS3

VSS6

VSS8 VSS10 VSS12 VSS14 VSS16 VSS17 VSS19 VSS21 VSS24 VSS26 VSS28 VSS30 VSS31 VSS33 VSS35 VSS38 VSS40 VSS42 VSS43 VSS45 VSS47 VSS50 VSS52

2

+VDR_SUS+VDR_SUS

76 82 88 94

+VDR_VREF+VDR_VREF

100 106 112 118 124 126

M_B_DQ4M_B_DQ0

4

M_B_DQ5

6

M_B_DQ6

16

M_B_DQ7

18

M_B_DQS#0

10

M_B_DQS0

12

M_B_DQ12

22

M_B_DQ13

24

M_B_DQ14

34

M_B_DQ15

36

M_B_DM1

28

M_B_DQ20

40

M_B_DQ21

42

M_B_DQ22

50

M_B_DQ23

52 46

M_B_DQ28

56

M_B_DQ29

58

M_B_DQ30

68

M_B_DQ31

70

M_B_DQS#3

62

M_B_DQS3

64

74

M_B_BS1

108

M_B_A14

80

M_B_A11

84

M_B_A7

86

M_B_A6

90

M_B_A4

92

M_B_A2

96

M_B_A0M_B_A1

98

30

M3_CLK3

102 104

M_CS#2

114

M_B_RAS#

110

M_ODT2

116

M_ODT3

120

M_B_DQ36

130

M_B_DQ37

132

M_B_DQ38

140

M_B_DQ39

142

M_B_DM4

136

M_B_DQ44

146

M_B_DQ45

148

M_B_DQ46

158

M_B_DQ47

160

M_B_DQS#5

152

M_B_DQS5M_B_DQ48

154

M_B_DQ52

164

M_B_DQ53

166

M_B_DQ54

174

M_B_DQ55

176

M_B_DM6

170

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194

M_B_DQS#7

186

M_B_DQS7PM_EXTTS#1

188

SDA_DDR

200

SCL_DDRB_SA1

202

78 122

204

2 8 14 20 26 32 38 44 48 54 60 66 72 128 134 138 144 150 156 162 168 172 178 184 190 196

2

DDR3_DRAMRST# <6>

SDA_DDR <16> SCL_DDR <16>

C501

D3@2.2U/10V_6

1

FOR DDR3

M3_CLK0

M3_CLK#0

M3_CLK1 M_CLK1

M3_CLK#1

M3_CLK2

M3_CLK#2

M3_CLK3

M3_CLK#3

RN28 D3@0_4P2RRN28 D3@0_4P2R

RN30 D3@0_4P2RRN30 D3@0_4P2R

RN26 D3@0_4P2RRN26 D3@0_4P2R

RN27 D3@0_4P2RRN27 D3@0_4P2R

PM_EXTTS#1<6,16>

PM_EXTTS#0<6,16>

M_CS#[3:0]<6,16>

M_ODT[3:0]<6,16>

M_CKE[3:0]<6,16>

M_CLK#[3:0]<6,16>

M_CLK[3:0]<6,16>

M_A_DQS#[7:0]<8,16>

M_A_DQS[7:0]<8,16>

M_A_DQ[63:0]<8,16>

B_SA1<16> B_SA0<16>

12

4 3

12

4 3

12

4 3

12

4 3

M_A_CAS#<8,16>

M_A_RAS#<8,16>

M_A_WE#<8,16>

M_A_BS[2:0]<8,16>

M_A_DM[7:0]<8,16>

M_A_A[14:0]<8,16>

M_B_CAS#<8,16>

M_B_RAS#<8,16>

M_B_WE#<8,16>

M_B_BS[2:0]<8,16>

M_B_DM[7:0]<8,16>

M_B_DQS#[7:0]<8,16>

M_B_DQS[7:0]<8,16>

M_B_A[14:0]<8,16>

M_B_DQ[63:0]<8,16>

R524 D3@10K_4R524 D3@10K_4 R523 D3@10K_4R523 D3@10K_4

Close to DIMM1

A_SA0<16> A_SA1<16>

R425 D3@10K_4R425 D3@10K_4 R424 D3@10K_4R424 D3@10K_4

Close to DIMM0

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

DDRIII SO-DIMM

Date: Sheet

PROJECT :

1

M_CLK#0

M_CLK#1

M_CLK#2

M_CLK#3

PM_EXTTS#1

PM_EXTTS#0

M_CS#[3:0]

M_ODT[3:0]

M_CKE[3:0]

M_CLK#[3:0]

M_CLK[3:0]

M_A_CAS#

M_A_RAS#

M_A_WE#

M_A_BS[2:0]

M_A_DM[7:0]

M_A_DQS#[7:0]

M_A_DQS[7:0]

M_A_A[14:0]

M_A_DQ[63:0]

M_B_CAS#

M_B_RAS#

M_B_WE#

M_B_BS[2:0]

M_B_DM[7:0]

M_B_DQS#[7:0]

M_B_DQS[7:0]

M_B_A[14:0]

M_B_DQ[63:0]

ZY2 & ZY6

17 40Tuesday, April 08, 2008

M_CLK0

M_CLK2

M_CLK3

of

+3V

1A

5

0C Change footprint 0103

CN29A

VIN

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

+5V

+3V

+2.5V

+1.8V

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

18

5VRUN

226

3V3RUN

228

3V3RUN

230

3V3RUN

222

2V5RUN

2

1V8RUN

4

1V8RUN

6

1V8RUN

8

1V8RUN

10

1V8RUN

12

1V8RUN

14

1V8RUN

17

GND

19

GND

20

GND

21

GND

22

GND

23

GND

24

GND

29

GND

32

GND

35

GND

38

GND

41

GND

44

GND

47

GND

50

GND

53

GND

56

GND

59

GND

62

GND

65

GND

68

GND

71

GND

74

GND

77

GND

80

GND

83

GND

86

GND

89

GND

92

GND

95

GND

98

GND

101

GND

104

GND

107

GND

110

GND

113

GND

116

GND

119

GND

126

GND

130

GND

138

GND

142

GND

146

GND

152

GND

164

GND

170

GND

175

GND

176

GND

182

GND

187

GND

188

GND

193

GND

194

GND

199

GND

200

GND

206

GND

211

GND

217

GND

223

GND

224

GND

229

GND

231

GND

232

GND

E@MXM CONNECTOR_2

MXM_SPDIF_OUT

C298

E@4.7U/25V_8

C284

4.7U/25V_8

PEX_REFCLK#

4Amp

0.5Amp

D D

1.5Amp

0.5Amp

3.5Amp

0C Change power name from +1.8V to +1.8V_MXM 0108

C C

B B

MXM_SPDIF_OUT<25>

A A

VIN

C299

E@4.7U/25V_8

125

CLK_REQ#

PLTRST#

127

PEX_RST#

CLK_MXM#

121

CLK_MXM

123

PEX_REFCLK

PEG_RXN0

115

PEX_RX0# PEX_RX1# PEX_RX2# PEX_RX3# PEX_RX4# PEX_RX5# PEX_RX6# PEX_RX7# PEX_RX8#

PEX_RX9# PEX_RX10# PEX_RX11# PEX_RX12# PEX_RX13# PEX_RX14# PEX_RX15#

PEX_RX0 PEX_RX1 PEX_RX2 PEX_RX3 PEX_RX4 PEX_RX5 PEX_RX6 PEX_RX7 PEX_RX8

PEX_RX9 PEX_RX10 PEX_RX11 PEX_RX12 PEX_RX13 PEX_RX14 PEX_RX15

PEX_TX0# PEX_TX1# PEX_TX2# PEX_TX3# PEX_TX4# PEX_TX5# PEX_TX6# PEX_TX7# PEX_TX8# PEX_TX9#

PEX_TX10# PEX_TX11# PEX_TX12# PEX_TX13# PEX_TX14# PEX_TX15#

PEX_TX0

PEX_TX1

PEX_TX2

PEX_TX3

PEX_TX4

PEX_TX5

PEX_TX6

PEX_TX7

PEX_TX8

PEX_TX9 PEX_TX10 PEX_TX11 PEX_TX12 PEX_TX13 PEX_TX14 PEX_TX15

PRSNT1#

PRSNT2#

C282

.1U/25V_4

PEG_RXN1

109

PEG_RXN2

103

PEG_RXN3

97

PEG_RXN4

91

PEG_RXN5

85

PEG_RXN6

79

PEG_RXN7

73

PEG_RXN8

67

PEG_RXN9

61

PEG_RXN10

55

PEG_RXN11

49

PEG_RXN12

43

PEG_RXN13

37

PEG_RXN14

31

PEG_RXN15

25

PEG_RXP0

117

PEG_RXP1

111

PEG_RXP2

105

PEG_RXP3

99

PEG_RXP4

93

PEG_RXP5

87

PEG_RXP6

81

PEG_RXP7

75

PEG_RXP8

69

PEG_RXP9

63

PEG_RXP10

57

PEG_RXP11

51

PEG_RXP12

45

PEG_RXP13

39

PEG_RXP14

33

PEG_RXP15

27

PEG_TXN0

118

PEG_TXN1

112

PEG_TXN2

106

PEG_TXN3

100

PEG_TXN4

94

PEG_TXN5

88

PEG_TXN6

82

PEG_TXN7

76

PEG_TXN8

70

PEG_TXN9

64

PEG_TXN10

58

PEG_TXN11

52

PEG_TXN12

46

PEG_TXN13

40

PEG_TXN14

34

PEG_TXN15

28

PEG_TXP0

120

PEG_TXP1

114

PEG_TXP2

108

PEG_TXP3

102

PEG_TXP4

96

PEG_TXP5

90

PEG_TXP6

84

PEG_TXP7

78

PEG_TXP8

72

PEG_TXP9

66

PEG_TXP10

60

PEG_TXP11

54

PEG_TXP12

48

PEG_TXP13

42

PEG_TXP14

36

PEG_TXP15

30

MXM_SPDIF_OUT

158

SPDIF

EVPRSNT1#

122 26

+1.8V

+

C300

E@330U/2.5V_7

0C Change power name from +1.8V to +1.8V_MXM 0108

C281

E@.1U/25V_4

PEG_RXN[15:0]

PEG_RXP[15:0]

PEG_TXN[15:0]

PEG_TXP[15:0]

R220 E@0_4R220 E@0_4

C283

E@10U/10V_8

C279

E@.1U/25V_4

C280

E@.1U/16V_4

Rev: B New add.

4

PLTRST# <13,21,23,28,29,32>

CLK_MXM# <2> CLK_MXM <2>

PEG_RXN[15:0] <7>

PEG_RXP[15:0] <7>

PEG_TXN[15:0] <7>

PEG_TXP[15:0] <7>

C604

*10U/25V_1206

+2.5V

+3V

C162

E@10U/10V_8

EV_LVDS_VDDEN<19>

EV_LVDS_BLON<19>

EV_LVDS_BL_BRGHT<19>

EV_LVDS_DDCCLK<19> EV_LVDS_DDCDAT<19>

THERM_ALERT#<3,14>

C170

E@1U/10V_4

+5V

C167

E@.1U/16V_4

TXUCLKOUTTXUCLKOUT+

TXUOUT0TXUOUT1TXUOUT2-

TXUOUT0+ TXUOUT1+ TXUOUT2+

TXLCLKOUTTXLCLKOUT+

TXLOUT0TXLOUT1TXLOUT2-

TXLOUT0+ TXLOUT1+ TXLOUT2+

EV_LVDS_VDDEN EV_LVDS_BLON EV_LVDS_BL_BRGHT

EV_LVDS_DDCCLK EV_LVDS_DDCDAT

HSYNC VSYNC

VGA_RED VGA_GRN VGA_BLU

CRTDCLK CRTDDAT

R210 E@0_4R210 E@0_4

MXMDATA MXMCLK

C278

E@1U/10V_4

C165

*.1U/16V_4

THERM#

3

CN29B

148

LVDS_UCLK#

150

LVDS_UCLK

172

LVDS_UTX0#

166

LVDS_UTX1#

160

LVDS_UTX2#

154

LVDS_UTX3#

174

LVDS_UTX0

168

LVDS_UTX1

162

LVDS_UTX2

156

LVDS_UTX3

178

LVDS_LCLK#

180

LVDS_LCLK

202

LVDS_LTX0#

196

LVDS_LTX1#

190

LVDS_LTX2#

184

LVDS_LTX3#

204

LVDS_LTX0

198

LVDS_LTX1

192

LVDS_LTX2

186

LVDS_LTX3

212

LVDS_PPEN

216

LVDS_BLEN

214

LVDS_BL_BRGHT

210

DDCC_CLK

208

DDCC_DAT

139

VGA_HSYNC

141

VGA_VSYNC

136

VGA_RED

140

VGA_GREEN

144

VGA_BLUE

143

DDCA_CLK

145

DDCA_DAT

128

TV_Y/HDTV_Y/TV_CVBS

124

TV_C/HDTV_Pr

132

TV_CVBS/HDTV_Pb

137

THERM#

133

SMB_DAT

135

SMB_CLK

E@MXM CONNECTOR_2

LVDS

2

HDMI_CLK-

207

DVI_A_CLK#

DVI_A_CLK

DVI_A_TX0# DVI_A_TX1# DVI_A_TX2#

DVI_A_TX0 DVI_A_TX1

DVI-ADVI-B

DVI_A_TX2

DVI

+3V

2

+3V

2

DVI_A_HPD

DDCB_CLK DDCB_DAT

DP_AUX#

DP_AUX

DP_L0#

DP_L1# DP_L2# DP_L3#

DP_HPD

HDA_SYNC HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

RUNPWROK

AC/BATT#

R191

E@4.7K_4

1

Q24

E@RHU002N06

1

DP_L0

DP_L1 DP_L2 DP_L3

RSVD RSVD

LVDS

TVCRT

Q22

E@RHU002N06

MXM_SMCLK<20,32>

MXM_SMDATA<20,32>

3

HDMI_CLK+

209

HDMI_TX0N

225

HDMI_TX1N

219

HDMI_TX2N

213

HDMI_TX0P

227

HDMI_TX1P

221

HDMI_TX2P

215

HDMI_HP_A

205

MXM_DDCCK

220

MXM_DDCDAT

218

159 161

177 179

201 195 189

203 197 191

181

183 185

151

IGP

153

IGP

155

IGP

163

IGP

165

IGP

167

IGP

169

IGP

171

IGP IGP

HDA_RST# PIN change from 151 to 134

173

129 131 134 147 149

16

157

MXM_PWROK

MXM_ACIN

R199

E@4.7K_4

MXMCLK

MXMDATA

R520 E@0_4R520 E@0_4

R265 E@0_4R265 E@0_4

CRT

HDMI_CLK- <20> HDMI_CLK+ <20>

HDMI_TX0N <20> HDMI_TX1N <20> HDMI_TX2N <20>

HDMI_TX0P <20> HDMI_TX1P <20> HDMI_TX2P <20>

HDMI_HP_A <20,31>

MXM_SYNC_HDMI <12> MXM_BIT_CLK_HDMI <12> MXM_RST#_HDMI <12>

MXM_SDIN_HDMI <12>

MXM_SDOUT_HDMI <12>

PWROK_MXM <32>

VGA_RED<19>

VGA_GRN<19>

HSYNC<19>

VSYNC<19>

CRTDCLK<19>

CRTDDAT<19>

VGA_RED

VGA_GRN

VGA_BLU

HSYNC

VSYNC

CRTDCLK

CRTDDAT

MXM_DDCCK

MXM_DDCDAT

MXM_ACIN

R202 I@0_4R202 I@0_4

R185 I@0_4R185 I@0_4

R187 I@0_4R187 I@0_4

R208 I@0_4R208 I@0_4

R204 I@0_4R204 I@0_4

R198 I@0_4R198 I@0_4

R194 I@0_4R194 I@0_4

+3V

R498

E@4.7K_4

1

Q43

E@RHU002N06

R499 *0_4R499 *0_4

+3V

R496

E@4.7K_4

1

Q42

E@RHU002N06

R497 *0_4R497 *0_4

+3V

R201

*10K_4

Q25

E@DTA114YUA

Rev: B Net:TX0 &TX2

TXLCLKOUT-

RN36 I@0_4P2RRN36 I@0_4P2R

TXLCLKOUT-<19>

TXLCLKOUT+<19>

TXLOUT0-<19>

TXLOUT0+<19>

TXLOUT1-<19>

TXLOUT1+<19>

TXLOUT2-<19>

TXLOUT2+<19>

TXUCLKOUT-<19>

TXUCLKOUT+<19>

TXUOUT0-<19>

TXUOUT0+<19>

TXUOUT1-<19>

TXUOUT1+<19>

TXUOUT2-<19>

TXUOUT2+<19>

TXLCLKOUT+

TXLOUT0TXLOUT0+

TXLOUT1TXLOUT1+

TXLOUT2TXLOUT2+

TXUCLKOUT+

TXUOUT0-

TXUOUT0+

TXUOUT1-

TXUOUT1+

TXUOUT2-

TXUOUT2+

1 2

RN39 I@0_4P2RRN39 I@0_4P2R

1 2

RN38 I@0_4P2RRN38 I@0_4P2R

1 2

RN37 I@0_4P2RRN37 I@0_4P2R

1 2

RN32 I@0_4P2RRN32 I@0_4P2R

1 2

RN35 I@0_4P2RRN35 I@0_4P2R

1 2

RN34 I@0_4P2RRN34 I@0_4P2R

1 2

RN33 I@0_4P2RRN33 I@0_4P2R

1 2

INT_TXLCLKOUT-INT_TXLCLKOUT-

INT_TXLCLKOUT+

43

INT_TXLOUT0INT_TXLOUT0+

43

INT_TXLOUT1INT_TXLOUT1+

43

INT_TXLOUT2INT_TXLOUT2+

43

INT_TXUCLKOUT-TXUCLKOUT-

INT_TXUCLKOUT+

43

INT_TXUOUT0INT_TXUOUT0+

43

INT_TXUOUT1INT_TXUOUT1+

43

INT_TXUOUT2INT_TXUOUT2+

43

INT_TXLCLKOUT- <7> INT_TXLCLKOUT+ <7>

INT_TXLOUT0- <7> INT_TXLOUT0+ <7>

INT_TXLOUT1- <7> INT_TXLOUT1+ <7>

INT_TXLOUT2- <7> INT_TXLOUT2+ <7>

INT_TXUCLKOUT- <7> INT_TXUCLKOUT+ <7>

INT_TXUOUT0- <7>

INT_TXUOUT0+ <7>

INT_TXUOUT1- <7>

INT_TXUOUT1+ <7>

INT_TXUOUT2- <7> INT_TXUOUT2+ <7>

HDMI

PEG_RXP3

R235 I@0_4R235 I@0_4

PEG_TXN2

RN15 I@0_4P2RRN15 I@0_4P2R

PEG_TXP2 PEG_TXN1 PEG_TXP1 PEG_TXN0 PEG_TXP0 PEG_TXN3 PEG_TXP3

Size Document Number Rev

Date: Sheet

1 2

43

RN16 I@0_4P2RRN16 I@0_4P2R

1 2

43

RN17 I@0_4P2RRN17 I@0_4P2R

1 2

43

RN18 I@0_4P2RRN18 I@0_4P2R

1 2

43

MXM

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

+3V

2

+3V

2

10K

2

1

3

+3V

47K

13

INT_CRT_RED <7>

INT_CRT_GRN <7>

INT_CRT_BLU <7>VGA_BLU<19>

INT_HSYNC <7>

INT_VSYNC <7>

INT_CRT_DDCCLK <7>

INT_CRT_DDCDAT <7>

對調

TMDS_HPD <20>

INT_HDMITXN0 <20> INT_HDMITXP0 <20> INT_HDMITXN1 <20> INT_HDMITXP1 <20> INT_HDMITXN2 <20> INT_HDMITXP2 <20> INT_HDMITXN3 <20> INT_HDMITXP3 <20>

HDMI_DDCCLK <20,31>

HDMI_DDCDATA <20,31>

R192

*10K_4

3

2

Q23

E@2N7002E

1

of

18 40Tuesday, April 08, 2008

ACIN <32,33>

1A

Rev: B New add.

5

4

3

2

1

CRT Select

2

3

4

5

6

7

8

CRT CONNECTOR AND ESD

10/15 :Rev: C CN40 Change footprint same as ZY5

D42 SSM14D42 SSM14

+5V

L12 BLM18BA750SN1DL12 BLM18BA750SN1D

L11 BLM18BA750SN1DL11 BLM18BA750SN1D

L10 BLM18BA750SN1DL10 BLM18BA750SN1D

C10

C16

10P/50V_4

L52 BLM18BA220SN1L52 BLM18BA220SN1 L53 BLM18BA220SN1L53 BLM18BA220SN1

INT_LVDS_DIGON<7>

EV_LVDS_VDDEN<18>

C10

10P/50V_4

CRT_VSYNC1 <31>

CRT_HSYNC1 <31>

VSYNC <18>

HSYNC <18>

CRTDCLK <18> CRTDDAT <18>

R168 I@0_4R168 I@0_4

R169 E@0_4R169 E@0_4

<Check list ver:0.8> UMA: 100K pull-down to GND

CRTVDD3

R14

150/F_4

SYNC_OUT2 SYNC_OUT1

SYNC_IN2 SYNC_IN1

DDC_OUT1 DDC_OUT2

10/15 :Change BOM

C18

10P/50V_4

16 14

15 13

10

DDC_IN1

11

DDC_IN2

9 12

C17

10P/50V_4

CRT_VSYNC1 CRT_HSYNC1

VSYNC HSYNC

CRTDCLK CRTDDAT

DDCCLK_1 DDCDAT_1

CRT SWITCH

U42

A A

B B

VGA_RED<18>

VGA_GRN<18>

VGA_BLU<18>

PR_INSERT_5V<20,31>

VGA_RED

VGA_GRN

VGA_BLU

LVDS

TXLCLKOUT+<18>

TXLCLKOUT-<18>

TXLOUT0+<18>

TXLOUT0-<18>

TXLOUT1+<18>

TXLOUT1-<18>

TXLOUT2+<18>

C C

TXLOUT2-<18>

Rev:B, Modify QCI P/N.

VGA_RED

VGA_GRN

7

VGA_BLU

9

12

1

15

D@SN74CBTLV3257PWR

VIN

R167 0_8R167 0_8

CCD_POWER

BL_ON

U42

C_A4A0

C_B

C_C

C_D

SE EN#

R34 ND@0_4R34 ND@0_4

R35 ND@0_4R35 ND@0_4

R29 ND@0_4R29 ND@0_4

16

VCC

VGA_RED_SYS

2

VGA_RED_PR

3

A1

VGA_GRN_SYS

5

B0

VGA_GRN_PR

6

B1

VGA_BLU_SYS

11

C0

VGA_BLU_PR

10

C1

14

D0

13

D1

8

GND

VGA_RED_SYS

VGA_GRN_SYS

VGA_BLU_SYS

INVCC0

CN7

INVCC0

+3V

TXLCLKOUT+ TXLCLKOUT-

TXLOUT0+ TXUOUT0+ TXLOUT0-

TXLOUT1+

TXLOUT1-

TXLOUT2+ TXLOUT2-

CN7

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 42

ACES_88242-40XX_LVDS

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

+5V

VGA_RED_PR <31>

VGA_GRN_PR <31>

VGA_BLU_PR <31>

LCDVCC

LCD_EDIDDATA LCD_EDIDCLK LVDS_VADJ

USBP11+_R USBP11-_R

+5V

+3V

R123 *0_4R123 *0_4 R130 I@0_4R130 I@0_4 R129 E@0_4R129 E@0_4

RP7 0X2_4RP7 0X2_4

3 1

TXUCLKOUT+ TXUCLKOUT-

TXUOUT0-

TXUOUT1+ TXUOUT1-

TXUOUT2+ TXUOUT2-

VGA_RED_SYS CRT_11

VGA_GRN_SYS

VGA_BLU_SYS

R15

R16

150/F_4

C19

.1U/10V_4

C600

.1U/10V_4

4 2

C15 .22U/25V_6C15 .22U/25V_6

CRTVDD3

CRT_BYP

CRT_R1 CRT_G1 CRT_B1

EV_LVDS_BL_BRGHT <18> L_BKLT_CTRL <7> CONTRAST <32>

USBP11+ <13> USBP11- <13>

TXUCLKOUT+ <18> TXUCLKOUT- <18>

TXUOUT0+ <18> TXUOUT0- <18>

TXUOUT1+ <18> TXUOUT1- <18>

TXUOUT2+ <18> TXUOUT2- <18>

U10

1

VCC_SYNC

7

VCC_DDC

8

BYP

2

VCC_VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

IP4772

CRTVDD3

R166

I@100K_4

6

7 2 8 3 9 4

10

5

D10 MTW355D10 MTW355

U22

6

IN

4

IN

3

ON/OFF

AAT4280

CRT_R1

CRT_G1

CRT_B1 CRTHSYNC

C12

C11

10P/50V_4

CRTVSYNC CRTHSYNC

R506

R507

2.7K_4

+3V

C146

.1U/10V_4

DISP_ONDISP_ONDISP_ONDISP_ON

CN40

1617

CRT

111

12

13

14

15

OUT

GND

DDCDAT_1

CRTVSYNC

DDCCLK_1

CRT_SENSE# <31,32>

CRTDCLK CRTDDAT

LCDVCC_1

1

2

5

T7T7

DDCDAT_1 <31>

DDCCLK_1 <31>

C599 .1U/10V_4C599 .1U/10V_4

C589 *10P/50V_4C589 *10P/50V_4

C590 *10P/50V_4C590 *10P/50V_4

C584 10P/50V_4C584 10P/50V_4

C583 10P/50V_4C583 10P/50V_4

R505 2.7K_4R505 2.7K_4 R504 2.7K_4R504 2.7K_4

R165 0_8R165 0_8

C166

C161

.1U/10V_4

2.2U/10V_8

CRTVDD3

CRTVSYNC

CRTHSYNC

DDCCLK_1

DDCDAT_1

C163

.1U/10V_4

+3V

CRT_SENSE#

C164

.01U/16V_4

+3V

3

LCDVCC

C160

2.2U/10V_1206

1

D11

DA204U

2

Rev:C, Change to 4.7U 0805

+3V

R145

2.2K_4

EV_LVDS_DDCCLK<18>

INT_LVDS_EDIDCLK<7>

EV_LVDS_DDCDAT<18>

INT_LVDS_EDIDDATA<7>

D D

1

R172 E@0_4R172 E@0_4

R173 I@0_4R173 I@0_4

R171 E@0_4R171 E@0_4

R170 I@0_4R170 I@0_4

LCD_EDIDCLK

+3V

R146

2.2K_4

LCD_EDIDDATA

CAMERA MODULE CONNECTOR

2

C39

1000P/50V_4

+3V

1

3

C159

1000P/50V_4

CCD_POWER

3

Q21

2

AO3413

+

C149 2.2U/10V_8

C145 1000P/50V_4C145 1000P/50V_4

VIN+3V+5V

C169

4.7U/25V_8

4

C168

1000P/X7R/50V_4

+3V

R160

4.7K_4

Q19

1 3

DTC144EU

2

CCD_POWERON <32>

5

Backlight Control

INT_LVDS_BLON<7>

EV_LVDS_BLON<18>

<Check list ver:0.8> UMA: 100K pull-down to GND

6

+3V

R116

10K_4

BL#

3

R122I@0_4 R122I@0_4

R125E@0_4 R125E@0_4

R112

I@100K/F_6

2

1

Size Document Number Rev

Date: Sheet

Q16

2N7002

Q17

2N7002

R117

10K_4

BL_ON

D17 BAS316D17 BAS316

3

2

1

CRT

7

2 1

2

Q14

1 3

DTC144EUA

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

LID591# <14,29,32>

EC_FPBACK# <32>

19 40Tuesday, April 08, 2008

of

8

1A

5

DVI-I CONNECTOR (DVI-D)

QCI P/N

PI3VDP411LS

Ch7318A

D D

ALP411LS000

AL007318000

PS8101

+3V

R161

R161 I@20K/F

I@20K/F

TMDS_HPD<18>

C C

HDMI_DDCCLK<18,31>

HDMI_DDCDATA<18,31>

PR_INSERT_5V<19,31>

B B

A A

TMDS_HPD

R158

I@7.5K/F_4

HDMI_DDCCLK

HDMI_DDCDATA

HDMI_HP_A<18,31>

NV suggestion near HDMI connector

HDMI_HP_A

HDMI_DDCCLK HDMI_MBCLK

HDMI_DDCDATA

HDMI_HP_A

HDMI_MBCLK

5

3

1

Q20

I@2N7002

2

TMDS_HPD_1

R159

I@100K_4

U43

C_A4A0

7

C_B

9

C_C

12

C_D

1

SE

15

EN#

D@SN74CBTLV3257PWR

R32 ND@0_4R32 ND@0_4

R33 ND@0_4R33 ND@0_4

R19 ND@0_4R19 ND@0_4

+5V

R10

*2K_4

INT_HDMITXP0<18> INT_HDMITXN0<18>

INT_HDMITXP1<18> INT_HDMITXN1<18>

INT_HDMITXP2<18> INT_HDMITXN2<18>

INT_HDMITXP3<18> INT_HDMITXN3<18>

SDVO_CTRLCLK<6>

SDVO_CTRLDATA<6>

+3V

Rev:B Add PU

+3V

R527 *0_4R527 *0_4 R528 *0_4R528 *0_4 R529 *0_4R529 *0_4 R530 *0_4R530 *0_4 R539 *0_4R539 *0_4

R148 0_4R148 0_4 R153 0_4R153 0_4 R152 0_4R152 0_4 R104 0_4R104 0_4 R105 0_4R105 0_4

16

VCC

GND

HDMI_MBCLK

2 3

A1

HDMI_MBDATA

5

B0

6

B1

HDMI_MB_A

11

C0

10

C1

14

D0

13

D1

8

HDMI_MBDATA

HDMI_MB_A

R11

*2K_4

L7 220R_100MHZ_6L7 220R_100MHZ_6

L8 220R_100MHZ_6L8 220R_100MHZ_6

R107 I@10K_4R107 I@10K_4

R109 I@0_4R109 I@0_4

R151 I@499/F_4R151 I@499/F_4

C7

*.1U/10V_4

C8

*.1U/10V_4

4

TMDS_HPD_1

PC0

PC1 TEST1 TEST2

RT_EN#

PC0

PC1 TEST1 TEST2

+5V

MB_HDMI_DDCCLK

MB_HDMI_DDCDATAHDMI_MBDATA

4

39 38

42 41

45 44

48 47

9 8

7

32

25

6

27

RT_EN#

10

PC0

3

PC1

4

TEST1

34

TEST2

35

SP@PERICOM_PI3VDP411LS

U21

IN_D1+

OUT_D1+

IN_D1-

OUT_D1-

IN_D2+

OUT_D2+

IN_D2-

OUT_D2-

IN_D3+

OUT_D3+

IN_D3-

OUT_D3-

IN_D4+

OUT_D4+

IN_D4-

OUT_D4-

SCL

SCL_SINK

SDA

SDA_SINK

HPD

HPD_SINK

VCC[1] VCC[2]

I2C_EN#

VCC[3] VCC[4] VCC[5]

OE#

VCC[6] VCC[7] VCC[8]

REXT

GND[1]

PRE

GND[2] GND[3] GND[4]

RT_EN#

GND[5]

PC0

GND[6]

PC1

GND[7]

TEST1

GND[8]

TEST2

GND[9]

GND[10]

HDMI_TX0P<18>

HDMI_TX0N<18>

HDMI_TX1P<18>

HDMI_TX1N<18>

HDMI_TX2P<18>

HDMI_TX2N<18>

HDMI_CLK-<18>

HDMI_CLK+<18>

HDMI monitor default have PU to 5V.So ZY3 PD for level change.And serial R for current limited

22 23

19 20

16 17

13 14

28 29

30

2 11 15 21 26 33 40 46

1 5 12 18 24 31 36 37 43 49

HDMI_DDCCLK HDMI_DDCDATA

C127

I@.1U/10V_4

I@

E@

LOW COST

TM & AS

HDMI_TX0P HDMI_TX0N

HDMI_TX1P HDMI_TX1N

HDMI_TX2P HDMI_TX2N

HDMI_CLKHDMI_CLK+

HDMICLK+ HDMICLK-

HDMITX0P HDMITX0N

HDMITX1P HDMITX1N

HDMITX2P HDMITX2N

3

HDMITX0P HDMITX0N

HDMITX1P HDMITX1N

HDMITX2P HDMITX2N

HDMICLK+ HDMICLK-

R102 10K_4R102 10K_4 R103 10K_4R103 10K_4

HDMI_HP_A

C117

I@.1U/10V_4

+5V

C107

I@.1U/10V_4

N

Y

N

Y

RN11 E@0_4P2RRN11 E@0_4P2R

1 2

4 2

2 4

R512 SP@1K_4R512 SP@1K_4

R511

E@10K_4

43

3 1

1 3

<check list> R497 For EV@ Connect to 1K For IV@ Connect to 0ohm

3

RN12 E@0_4P2RRN12 E@0_4P2R

RN13 E@0_4P2RRN13 E@0_4P2R

RN14 E@0_4P2RRN14 E@0_4P2R

RP51 ND@0_4P2R_SRP51 ND@0_4P2R_S

RP52 ND@0_4P2R_SRP52 ND@0_4P2R_S

RP53 ND@0_4P2R_SRP53 ND@0_4P2R_S

RP54 ND@0_4P2R_SRP54 ND@0_4P2R_S

MB_HDMITX2P

MB_HDMITX2N MB_HDMITX1P

MB_HDMITX1N MB_HDMITX0P

MB_HDMITX0N MB_HDMICLK+

MB_HDMICLK-

MB_HDMI_DDCCLK MB_HDMI_DDCDATA

+3V

C134

I@.1U/10V_4

HDMITX0P HDMITX0N

HDMITX1P HDMITX1N

HDMITX2P HDMITX2N

HDMICLKHDMICLK+

MB_HDMICLK+ MB_HDMICLK-

MB_HDMITX0P MB_HDMITX0N

MB_HDMITX1P MB_HDMITX1N

MB_HDMITX2P MB_HDMITX2N

+5V

HP_DETHDMI_MB_A

R555

*0_6

Rev:B ,change IC

CN36

19

D2+

18

D2 Shield

17

D2-

16

D1+

15

D1 Shield

14

D1-

13

D0+

12

D0 Shield

11

D0-

10

CK+

9

CK Shield

8

CK-

7

CE Remote

6

NC

5

DDC CLK

4

DDC DATA

3

GND

2

+5V

1

HP DET

SP@HDMI CON

+3V

21

D1

D@B0520LW

C585

D@.1U/10V_4

+3V

R3 *4.7K_4R3 *4.7K_4 R4 *4.7K_4R4 *4.7K_4 R5 *4.7K_4R5 *4.7K_4 R6 *4.7K_4R6 *4.7K_4

R549 D@0_4R549 D@0_4 R546 D@0_4R546 D@0_4 R547 D@0_4R547 D@0_4 R548 D@0_4R548 D@0_4

+3V

R95 D@4.7K_4R95 D@4.7K_4 R550 *0_4R550 *0_4

FUNMS

I2C CONTROLH

L DOCK (port A)

PR_INSERT_5V<19,31>

0C Change footprint 0103

20

SHELL1

23

GND

22

GND

21

SHELL2

2

C586

D@.1U/10V_4

HS_A0/S4 HS_A1/S5 HS_A2/S6 HS_A3/S7

HS_A0/S4 HS_A1/S5

HS_A3/S7

HS_MS

D13 *BAS316D13 *BAS316

R97 0_4R97 0_4

H

L

2

C29

D@.22U/25V_6

HDMICLK+ HDMICLK-

HDMICLK HDMIDATA

+3V

R41

*4.7K_4

HS_SEL_IN

21

FUNSEL_IN

DOCK (port B)

MB (port A)

PDAT_SMB<2,14,16,21,23,29>

MXM_SMCLK<18,32>

PCLK_SMB<2,14,16,21,23,29>

MXM_SMDATA<18,32>

+5V

C30

D@.1U/10V_4

HDMITX2P

HDMITX2N

HDMITX1P

HDMITX1N

HDMITX0P

HDMITX0N

HS_MSHS_A2/S6

HS_A0/S4 HS_A1/S5 HS_A2/S6 HS_A3/S7

HS_SEL_IN

C601

.1U/16V_4

1

U9

PN

2

VDD

D0+A

6

VDD

11 15 24 36 48 22

4 5 7 8

9 10 12 13

19 20

1

49 50 51

17 16 18

55

D@PI3HDMI412AD

R552 *0_4R552 *0_4 R551 D@0_4R551 D@0_4

R554 *0_4R554 *0_4 R553 D@0_4R553 D@0_4

D0-A

VDD

D1+A

VDD

D1-A

VDD

D2+A

VDD

D2-A

CLK+A

VDD AVDD

CLK-A

D0+

D0+B

D0-

D0-B

D1+

D1+B

D1-

D1-B

D2+

D2+B

D2-

D2-B

CLK+

CLK+B

CLK-

CLK-B

GND

SCL/S3

GND

SDA/S2

GND

MS

GND GND GND

A0/S4

GND

A1/S5

GND

A2/S6 A3/S752GND

GND

TEST_OUT

GND

SEL_OUT

AGND

NC

TEST_IN

SEL_IN

OE

D_DVICLK+ D_DVICLK-

D_DVITX0+

D_DVITX1+

+3V

2

3

+3V

2

3

LOW COST

TM & AS

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

Size Document Number Rev

LVDS/HDMI/CAMERA/LID

Date: Sheet

PROJECT : ZY2 & ZY6

MB_HDMICLK+

47

MB_HDMICLK-

46

MB_HDMITX2P

44

MB_HDMITX2N

43

MB_HDMITX1P

41

MB_HDMITX1N

40

MB_HDMITX0P

38

MB_HDMITX0N

37

35 34 32 31 29 28 26 25

3 14 27 30 33 39 42 45 53 57 21 23 54

D2 D@BAS316D2 D@BAS316

56

R81 D@4.7K_4R81 D@4.7K_4

R566 100/F_4R566 100/F_4

2.2P/50V_6C612 2.2P/50V_6C612

R567 100/F_4R567 100/F_4

2.2P/50V_6C616 2.2P/50V_6C616

R568 100/F_4R568 100/F_4

2.2P/50V_6C617 2.2P/50V_6C617

R569 100/F_4R569 100/F_4

2.2P/50V_6C618 2.2P/50V_6C618

R544

D@4.7K_4

1

Q45

D@RHU002N06

Q44

D@RHU002N06

1

N

Y

1

D_DVITX0-

D_DVITX1-

D_DVITX2-D_DVITX2+

R545

D@4.7K_4

HDMICLK

HDMIDATA

D_DVICLK+ <31> D_DVICLK- <31> D_DVITX2+ <31> D_DVITX2- <31> D_DVITX1+ <31> D_DVITX1- <31> D_DVITX0+ <31> D_DVITX0- <31>

+3V

21

of

20 40Wednesday, April 09, 2008

1A

5

4

3

2

1

+3V_S5

Q13

LAN

D D

VAUX_12

PCIE_WAKE#<14,23,32>

Rev:B ,Add

2

DTC144EUA

20mil

L26 BLM11A601SL26 BLM11A601S

L25 BLM11A601SL25 BLM11A601S

Rev:B ,change to 0603

L24 BLM11A601SL24 BLM11A601S

C C

L23 BLM11A601SL23 BLM11A601S

B B

LAN_AVDDL

C610

.1U/16V_4

GPHY_PLLVDD

PCIE_PLLVDD

C104

4.7u/6.3V_6

PCIE_SDS_VDD

C92

4.7U/10V_8

CLK_PCIE_LAN<2> CLK_PCIE_LAN#<2>

C69 27P/50V_4C69 27P/50V_4

C68 27P/50V_4C68 27P/50V_4

GLAN_RXP<13> GLAN_RXN<13>

GLAN_TXP<13> GLAN_TXN<13>

PCLK_SMB<2,14,16,20,23,29> PDAT_SMB<2,14,16,20,23,29>

C99

.1U/16V_4

PLTRST#<13,18,23,28,29,32>

1 2

R68 200_4R68 200_4

C125

4.7u/6.3V_6

C130

4.7u/6.3V_6

C110

.1U/16V_4

PCIE_WAKE_R#

+3V +3V_S5

PCLK_SMB PDAT_SMB

Y7

25MHZY725MHZ

C123

.1U/16V_4

C132

.1U/16V_4

C96 .1U/16V_4C96 .1U/16V_4 C93 .1U/16V_4C93 .1U/16V_4

R74 0_4R74 0_4

CLK_LAN_X1

CLK_LAN_X2

R114 1K_4R114 1K_4 R120 1K_4R120 1K_4 R72 4.7K_4R72 4.7K_4

R61

4.7K_4

PCIE_WAKE_R#

13

VDDCIO_12VAUX_12

R99 0_4R99 0_4 R101 0_4R101 0_4

Rev:B Change to 1.21K

GLAN_TXP_5787 GLAN_TXN_5787

CLK_LAN_X2 CLK_LAN_X1

RDAC

R150

1.2K/F_6

-LAN_RST

AUX_PRES VMA_PRES

U19

5

VDDC/VDDCIO

55

VDDC/VDDCIO

13

VDDC

20

VDDC

34

VDDC

60

VDDC

39

AVDDL

45

AVDD

51

AVDDL

35

GPHY_PLLVDD

30

PCIE_PLLVDD/PCIE_PLLVDDL

27

PCIE_VDD/PCIE_PLLVDDL

33

PCIE_VDD/PCIE_VDDL

24

PCIE_GND/PCIE_VDDL

26

PCIE_TXDP

25

PCIE_TXDN

31

PCIE_RXDP

32

PCIE_RXDN

12

WAKE#

10

PERST#

29

REFCLK+

28

REFCLK-

54

VAUXPRSNT

53

VMAINPRSNT

3

LOW_PWR

58

SMB_CLK

57

SMB_DATA

22

XTALO

21

XTALI

37

RDAC

11

NC(CLK_REQ#)

Rev:B R68 change to CLK_LAN_X2

VAUX_12 +3V_S5

A A

C98

.1U/16V_4

C108

.1U/16V_4

5

C122

.1U/16V_4

C111

.1U/16V_4

C95

.1U/16V_4

C116

.1U/16V_4

C74

.1U/16V_4

C75

.1U/16V_4

4

C109

4.7U/10V_8

VDDCIO_12 +PWR_TRANSF

L21 *BLM11A601SL21 *BLM11A601S

FOR DOCK

+3V_S5

61

VDDIO6VDDIO15VDDIO19VDDIO56VDDIO

BCM5764M

10mm X 10mm

10mm X 10mm 68-Pin QFN

68-Pin QFN

C76

C144

.1U/16V_4

38

52

AVDD/DC

GPIO1_SERIALDI

GPIO0_SERIALDO

NC/(ENERGY_DET)

REGCTL25/REGOUT12IO

REG_GND/SUPER_IDDQ

GND

69

BCM5764MA0KMLG

C94

.1U/16V_4

68

AVDD/DC

VDDP/DC

SPD100LED#

SPD1000LED#

TRAFFICLED#

UART_MODE

VDDP/VDDCIO

BIASVDD

XTALVDD

AVDDH

TRD3+

TRD3-

TRD2N TRD2P

TRD1P TRD1N

TRD0-

TRD0+

LINKLED#

GPIO2

SCLK

CS#

REGCTL12

C113

.1U/16V_4

3

20mil

BIASVDD

36

23

48

42

50 49

47 46

44 43

41 40

2 1 67 66

8

9 7 4

65 63

SI

64

SO

62

59

17

18

14

16

C67

4.7U/10V_8

XTALVDD

AVDDH

LAN_TRD3P LAN_TRD3N

LAN_TRD2N LAN_TRD2P

LAN_TRD1P LAN_TRD1N

LAN_TRD0N LAN_TRD0P

LINKLED#

R71 0_4R71 0_4

100#

R70 0_4R70 0_4

1000#

R82 0_4R82 0_4

LAN_ACTLED#

SI

CS#

SI,SO,CS#,SCLK have internal pull up

R91 0_4R91 0_4

VDDCIO_12

LAN REGCTL12

R60 39K_6R60 39K_6

LAN_LINKLED#

LAN_ACTLED# <22>

T8T8

T9T9

BCM_SCL

BCM_SDA

ENERGY_DET

R51 1.5_12R51 1.5_12

1

2 3

Low is normal, H->Turn Off 1.2V, H(>0.7V <2.5V)->L will internal reset

VDDCIO_12

C83

.1U/16V_4

LAN_TRD3P <22> LAN_TRD3N <22>

LAN_TRD2N <22> LAN_TRD2P <22>

LAN_TRD1P <22> LAN_TRD1N <22>

LAN_TRD0N <22> LAN_TRD0P <22>

LAN_LINKLED# <22>

BCM_WP

Q12

MMJT9435

4

C44

.1U/16V_4

C143

.1U/16V_4

C131

.1U/16V_4

C89

.1U/16V_4

C115

.1U/16V_4

ENERGY_DET <32>

+3V_S5

C46

C47

.1U/16V_4

4.7U/10V_8

VAUX_12

C48

10U/6.3V_8

20mil

2

L28 BLM11A601SL28 BLM11A601S

L20 BLM11A601SL20 BLM11A601S

L27 BLM11A601SL27 BLM11A601S

C124

.1U/16V_4

Rev: B remove

R63

R62

*4.7K_4

4.7K_4

BCM_SDA BCM_SCL BCM_RESET#

+3V_S5

EEPROM Strapping

SO SI CS# SCLK

1101

24c64

AT45DB011B

+3V_S5

R64

4.7K_4

8 7 6 5

FAE:When 24C64 is used,Stuff R204,R88,R212,R215 not stuff R85 ,R84

AT45DB011B-SC(LAN FLASH): Stuff U6,R46,R45

U17

1

SI

2

SCK

3

RESET#

4

CS#

ASF@AT45DB011B-SC(LAN FLASH)

BCM_SCL

SI

CS#

Size Document Number Rev

BCM5787 & 5764 LAN

Date: Sheet

1

C87

R73

.1U/16V_4

ASF@4.7K_4

U15

VCC WP SCL SDA

NASF@AT24C64

SO

GND

VCC

WP#

R85 *4.7K_4R85 *4.7K_4

R106 ASF@4.7K_4R106 ASF@4.7K_4

R80 NASF@4.7K_4R80 NASF@4.7K_4

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

BCM_RESET#

1

A0

2

A1

3

NC

4

GND

SI

8 7 6

WPCS#

5

1

110

R66

ASF@4.7K_4

WP

+3V_S5

C114

ASF@.1U/16V_4

21 40Tuesday, April 08, 2008

of

1A

1

2

3

4

5

6

7

8

LAN SWITCH

+3V_S5

C91

C103

A A

DOCKIN#<25,31,32>

B B

C103

D@.1U/16V_4

D@10U_8

+3V_S5

R118

D@10K_4

D18 D@BAS316D18 D@BAS316

LAN_TRD0P<21>

LAN_TRD0N<21>

LAN_TRD1P<21>

LAN_TRD1N<21>

LAN_TRD2P<21>

LAN_TRD2N<21>

LAN_TRD3P<21>

LAN_TRD3N<21>

LAN_ACTLED#<21>

LAN_LINKLED#<21>

LAN_DOCKIN#

LAN_TRD0P

LAN_TRD0N

LAN_TRD1P

LAN_TRD1N

LAN_TRD2P

LAN_TRD2N

LAN_TRD3P

LAN_TRD3N

LAN_ACTLED#

LAN_LINKLED#

0: A to B1 1: A to B2

LAN_TRD0N LAN_TRD0P

LAN_TRD1N LAN_TRD1P

LAN_TRD2N LAN_TRD2P

LAN_TRD3N LAN_TRD3P

LAN_ACTLED#

LAN_LINKLED#

4

10

18

27

38

U18

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

LED0

20

LED1

54

LED2

17

SEL

5

NC

RN7 ND@0_4P2RRN7 ND@0_4P2R

1 2

RN8 ND@0_4P2RRN8 ND@0_4P2R

1 2

RN10 ND@0_4P2RRN10 ND@0_4P2R

1 2

RN9 ND@0_4P2RRN9 ND@0_4P2R

1 2

R89 ND@0_4R89 ND@0_4

R87 ND@0_4R87 ND@0_4

50

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

PI3L500

GND05

GND00

GND0116GND0221GND0324GND04

33

13

28

D@PI3L500 (LAN SW)

43

LAN_ACTLED#_SYS

LAN_LINKLED#_SYS

56

9

6

1

TX0P_PR

48

0B1

GND13

0LED1 1LED1 2LED1

0LED2 1LED2 2LED2

GND10

57

1B1

2B1 3B1

4B1 5B1

6B1 7B1

0B2 1B2

2B2 3B2

4B2 5B2

6B2 7B2

GND10

TX0N_PR

47

TX1P_PR

43

TX1N_PR

42

TX2P_PR

37

TX2N_PR

36

TX3P_PR

32

TX3N_PR

31

22 23 52

TX0P_SYS

46

TX0N_SYS

45

TX1P_SYS

41

TX1N_SYS

40

TX2P_SYS

35

TX2N_SYS

34

TX3P_SYS

30

TX3N_SYS

29

LAN_ACTLED#_SYS

25

LAN_LINKLED#_SYS

26 51

VDD7

GND12

GND11

GND06

GND07

GND08

GND09

39

44

49

53

55

TX0N_SYS TX0P_SYS

TX1N_SYS TX1P_SYS

TX2N_SYS TX2P_SYS

TX3N_SYS TX3P_SYS

to Docking

TX0P_PR <31> TX0N_PR <31>

TX1P_PR <31> TX1N_PR <31>

TX2P_PR <31> TX2N_PR <31>

TX3P_PR <31> TX3N_PR <31>

D_ACTLED# <31> D_LINKLED# <31>

Transfomer

Source 2:

VAUX_25_R

C85

.01U/16V_4

Bothand GST5009

TX0P_SYS TX0N_SYS

TX1P_SYS TX1N_SYS

TX2P_SYS TX2N_SYS

TX3P_SYS TX3N_SYS

C88

.01U/16V_4

Close Transformer

1 2 3

4 5 6

7 8 9

10 11 12

U14

TCT1 TD1+ TD1-

TCT2 TD2+ TD2-

TCT3 TD3+ TD3-

TCT4 TD4+ TD4-

GST-5009 LF

MCT1 MX1+

MX1-

MCT2 MX2+

MX2-

MCT3 MX3+

MX3-

MCT4 MX4+

MX4-

LFE9249Source 1: DELTA

DB0ZR1LAN11 DBKN1NLAN03

24 23 22

21 20 19

18 17 16

15 14 13

R39

R36

75/F_4

MGND

R38

R38 75/F_4

75/F_4

C35

C35 1500P/2KV_1808

1500P/2KV_1808

X-TX0P X-TX0N

X-TX1P X-TX1N

X-TX2P X-TX2N

X-TX3P X-TX3N

R37

R37 75/F_4

75/F_4

RESET TIMING

POWER

PERSTn

110 ms

min

C C

RJ45-11

CN39

2

CN39

10

GREEN_N

9

GREEN_P

8

TX1-

7

TX1+

6

RX1-

5

TX2-

4

TX2+

3

RX1+

2

RX2-

1

RX2+

12

YELLOW_N

11

YELLOW_P

FOXCONN_RJ45

GND2

GND1

14

C26 .1U/10V_4C26 .1U/10V_4

13

C34 .01U/16V_4C34 .01U/16V_4 C33 1500P/2KV_1808C33 1500P/2KV_1808

MGND

3

4

+3V_S5

LAN_LINKLED#_SYS

R40 220_8R40 220_8

X-TX3N X-TX3P X-TX1N X-TX2N X-TX2P X-TX1P X-TX0N

D D

1

+3V_S5

R43 220_8R43 220_8

X-TX0P

LAN_ACTLED#_SYS

9/29: change footprint 11/27 :change footprint 11/28 : R43 & R40 Change to 0805 1/31 :Rev: C change PIN define about 9,10,11 & 12

BLUETOOTH MODULE CONNECTOR

+3VSUS

USBP5+<13>

USBP5-<13>

BT_LED<29>

1

5

3

Q32

2

AO3413

RP49 0X2_4RP49 0X2_4

1 3

C428 2.2U/10V_8

C414 1000P/X7R/50V_4C414 1000P/X7R/50V_4

2 4

BT_POWER

+

BT_POWERON# <32>

C427

*22P/50V_4

6

BT_POWER

USBP5+_R USBP5-_R

BT_LED

C426

*22P/50V_4

C412

.01U/16V_4

CN18

1 2 3 4 5 6 7

Aces 88266-0500

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

Size Document Number Rev

Date: Sheet

7

PROJECT : ZY2 & ZY6

BT/CCD/RJ45-11/CIR/2nd FAN

22 40Tuesday, April 08, 2008

of

8

1A

1

2

3

4

5

6

7

8

MINI-CARD

MODULE 'A' TV card

MODULE 'B' Wireless card

A A

USBP2+<13> USBP2-<13>

PCIE_TXP2<13> PCIE_TXN2<13>

PCIE_RXP2<13> PCIE_RXN2<13>

CLK_PCIE_TV<2> CLK_PCIE_TV#<2>

B B

LFRAME#<12,32>

LAD3<12,32> LAD2<12,32> LAD1<12,32> LAD0<12,32>

Debug

PCIRST#<13,27>

PCLK_DEBUG<2>

C C

L41 SP@FBJ3216HS800_12L41 SP@FBJ3216HS800_12

+5V

500mA, 25mil

FOR R446 & L41

LOW COST N

TM & AS

D D

+3V

Double Stack MINI CARD

+3V +3V

R536 *0_4R536 *0_4

USBP2+

RP27 0X2_4RP27 0X2_4

+3V

3 1

R538 *0_4R538 *0_4

R445 0_4R445 0_4 R444 0_4R444 0_4 R443 0_4R443 0_4 R442 0_4R442 0_4 R441 0_4R441 0_4

R450 *0_4R450 *0_4 R448 *0_4R448 *0_4

R446 SP@0_6R446 SP@0_6

USBP2-

TV use +3V

R557 *0_4R557 *0_4

C494

4.7U/6.3V_6

Y

+3V_S5 for WWAN card is 2.75A

R542 0_8R542 0_8

RF_LED#_ARF_LED#

4 2

A_LFRAME#_R

A_LAD3_R A_LAD2_R A_LAD1_R A_LAD0_R

+3V_MINI_R

C510

.1U/16V_4

+5V_TV-CARD

C493

.1U/16V_4

+3V_MINI_A

USBP2+_C USBP2-_C MINI_SMDATA MINI_SMCLK PCIE_TXP2 PCIE_TXN2 PCIE_RXP2 PCIE_RXN2 PLTRST# CLK_PCIE_TV CLK_PCIE_TV#

PCIE_WAKE#_R_APCIE_WAKE#_R

+1.5V +1.5V

CN27

92

A_+3.3V

71

A_+3.3Vaux

54

A_+3.3V

87

A_LED_WPAN#

85

A_LED_WLAN#

83

A_LED_WWAN#

80

A_USB_D+

78

A_USB_D-

76

A_SMB_DATA

74

A_SMB_CLK

33

A_PETp0

31

A_PETn0

25

A_PERp0

23

A_PERn0

69

A_PERST#

13

A_REFCLK+

11

A_REFCLK-

7

A_CLKREQ#

1

A_WAKE#

89

A_+1.5V

73

A_+1.5V

57

A_+1.5V

65

NC

64

NC

62

NC

60

NC

59

NC

51

NC

49

C-Link_RST

47

C-Link_DAT

45

C-Link_CLK

41

NC

39

NC

19

NC

17

NC

68

A_W_DISABLE#

5

A_BT_CHCLK

3

A_BT_DATA

43

GND

37

GND

26

GND

21

GND

18

GND

15

GND

9

GND

4

GND

B_+3.3V

B_+3.3Vaux

B_+3.3V

B_LED_WPAN# B_LED_WLAN#

B_LED_WWAN#

B_USB_D+

B_USB_D-

B_SMB_DATA

B_SMB_CLK

B_PETp0

B_PETn0 B_PERp0 B_PERn0

B_PERST#

B_REFCLK+

B_REFCLK-

B_CLKREQ#

B_WAKE#

B_+1.5V B_+1.5V B_+1.5V

C-Link_RST C-Link_DAT C-Link_CLK

B_W_DISABLE#

B_BT_CHCLK

B_BT_DATA

GND93GND

94

A/B MODULE Share pin

SP@QUASAR-CA0404-071N21_92P

CN27

MODULE 'B'MODULE 'A'

GND GND GND GND GND GND GND GND

52 24 2

46 44 42 38 36 32 30 77 75 72 70 22 63 61 58 53

48 28 6

16

NC

14

NC

12

NC

10

NC

8

NC

91

NC

90 88 86

82

NC

81

NC

67

NC

66

NC

20

56 55

84 79 50 40 35 34 29 27

+3V_MINI_B

RF_LED#_B

USBP3+_C

RP57 0X2_4RP57 0X2_4

USBP3-_C MINI_SMDATA MINI_SMCLK

PCIE_WAKE#_R_B

B_LFRAME#_R LFRAME# B_LAD3_R B_LAD2_R B_LAD1_R LAD1 B_LAD0_R LAD0

B_RF_ENA_RF_ENRF_EN

+1.5V

Rev:B PIN36,38 Add USB3 PIN69 Add R536 PIN1, 53 Add R537 & R538

R543 0_8R543 0_8

1 3

RF_LED#

USBP3+ USBP3-

PCIE_WAKE#_R

LAD3 LAD2

R447 0_4R447 0_4

2 4

R537 *0_4R537 *0_4

R561 0_4R561 0_4 R559 0_4R559 0_4 R558 0_4R558 0_4 R560 0_4R560 0_4 R562 0_4R562 0_4

R556 0_4R556 0_4

LC@ LOW COST

RF_LED# <29>

USBP3+ <13> USBP3- <13>

PCIE_TXP4 <13> PCIE_TXN4 <13>

PCIE_RXP4 <13> PCIE_RXN4 <13> PLTRST# <13,18,21,28,29,32>

CLK_PCIE_MINI1 <2>

CLK_PCIE_MINI1# <2>

RF_EN <32>

要打

PCLK_SMB<2,14,16,20,21,29>

PDAT_SMB<2,14,16,20,21,29>

PCIE_WAKE#<14,21,32>

FOR EMI

VCC_CORE VIN

+5V

C605

INVCC0

C605

1U/10V_4

C70

1U/10V_4

+VDR_SUS +VDR_SUS

C273

C607

1U/25V_6

C273

1U/10V_4

+3V_S5

3

C150

1U/25V_6

C394

1U/10V_4

+3V

R449 10K_4R449 10K_4

2

1

Q35

2N7002

+3V

R451

10K_4

2

1

Q36

2N7002

+3VSUS

2

Q34

*DTC144EUA

13

+3V +1.05V

C613

.1U/16V_4

+1.8V

C615

.1U/16V_4

MINI_SMDATA

PCIE_WAKE#_R

C614

.1U/16V_4

MINI_SMCLK

C512

C498

C499

C513

4.7U/6.3V_6

1

C499

4.7U/6.3V_6

2

C491

.1U/16V_4

C498

.1U/16V_4

3

C512

.1U/16V_4

4

C317

.1U/16V_4

C500

10U/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

Size Document Number Rev

MINI PCI-E card/TV/TPM

Date: Sheet

5

6

Date: Sheet

PROJECT : ZY2 & ZY6

7

1A

23 40Tuesday, April 08, 2008

of

8

1A

1

2

3

4

SATA HDD

11/8 REV:B Conn.

掉對調

CN28 & CN19

2ND SATA HDD

Main

CN19

A A

B B

C16654-122A4-L_Serial_ATA

CN19

GND23

GND1

RXP RXN

GND2

TXN TXP

GND3

3.3V

3.3V GND GND GND

GND

RSVD

GND

12V 12V 12V

GND24

CN28

23

1 2 3 4 5 6 7

8 9 10 11 12 13 14

5V

15

5V

16

5V

17 18 19 20 21 22

24

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

+3.3VSATA2

HDDB5V

+5V

C416 .01U/25V_4C416 .01U/25V_4 C417 .01U/25V_4C417 .01U/25V_4

C418 .01U/25V_4C418 .01U/25V_4 C419 .01U/25V_4C419 .01U/25V_4

R374 0_8R374 0_8

+3V

R371 0_8R371 0_8

C413

100U/6.3_3528

+3.3VSATA2

HDDB5V

C424

10U/10V_8

SATA_TXP0 <12> SATA_TXN0 <12>

SATA_RXN0 <12> SATA_RXP0 <12>

C429

10U/10V_8

C420

.1U/16V_4

C425

10U/10V_8

C421

.1U/16V_4

C415

.1U/10V_4

C422

.01U/16V_4

C423

.01U/16V_4

C16654-122A4-L_Serial_ATA

CN28

GND23

GND1

RXP RXN

GND2

TXN

TXP

GND3

3.3V

3.3V GND GND GND

GND

RSVD

GND

12V 12V 12V

GND24

23

1

SATA_TXP4_C

2

SATA_TXN4_C

3 4

SATA_RXN4_C

5

SATA_RXP4_C

6 7

+3.3VSATA1

8 9 10 11 12 13 14

5V

15

5V

16

5V

17 18 19 20 21 22

24

HDDA5V

R267 0_8R267 0_8

+5V

C290 .01U/25V_4C290 .01U/25V_4 C291 .01U/25V_4C291 .01U/25V_4

C292 .01U/25V_4C292 .01U/25V_4 C293 .01U/25V_4C293 .01U/25V_4

+3V

R266 0_8R266 0_8

+

C289

150U/6.3V_7343

+3.3VSATA1

SATA_TXP4 <12> SATA_TXN4 <12>

SATA_RXN4 <12> SATA_RXP4 <12>

C296

10U/10V_8

HDDA5V

C295

10U/10V_8

C285

.1U/16V_4

C297

10U/10V_8

C286

.1U/16V_4

C294

.1U/10V_4

C287

.01U/16V_4

C288

.01U/16V_4

Rev:B ,C413 change footprint to 3528

C C

ODD (SATA)

CN20

D D

C16654-122A4-L_Serial_ATA

1

GND14

GND

GND GND

GND15

14

1 2

A+

3

A-

4 5

B-

6

B+

7

8

DP

9

5V

10

5V

11

MD

12 13

15

SATA_DP

2

SATA_TXP1_C SATA_TXN1_C

SATA_RXN1_C SATA_RXP1_C

R373 1K_4R373 1K_4

C433 .01U/25V_4C433 .01U/25V_4 C432 .01U/25V_4C432 .01U/25V_4

C431 .01U/25V_4C431 .01U/25V_4 C430 .01U/25V_4C430 .01U/25V_4

C436

.01U/16V_4

C434

.01U/16V_4

SATA_TXP1 <12> SATA_TXN1 <12>

SATA_RXN1 <12> SATA_RXP1 <12>

C435

.1U/16V_4

HDDC5V

C437

.1U/16V_4

R372 0_8R372 0_8

C438

10U/10V_8

3

+5V

+

C439

150U/6.3V_7343

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

Size Document Number Rev

SATA-HDD & ODD

Date: Sheet of

Date: Sheet

4

of

24 40Tuesday, April 08, 2008

1A

5

CODEC(ALC268)

+5V +5V_ADO

L22 TI321611U480_1206L22 TI321611U480_1206

C97

C106

.1U/10V_4

10U/10V_8

D D

MONO_OUT_L<26>

C C

SPDIF_OUT<26>

SPDIF_DOUT<31>

B B

A A

BEEP_1

3

2

Q15

2N7002

1

EAPD_268

LP_ECR<14>

MONO_OUT_L

MUTE_BEEP

C62

.1U/10V_4

2

1

R533

*10K_4

5

C73

.1U/10V_4

R58

ADOGND

R75

R86 D@0_4R86 D@0_4

MUTE_BEEP <32>

R534 0_4R534 0_4

+5V_ADO

5

3

*SN74AHC1G32DCKR

ADOGND

C84

C71

.1U/10V_4

4.7U/10V_8

ADOGND

SURR-L<26>

SURR-R<26>

268@0_4

MONO_OUT_268

+5V_ADO

FRONT-L

R67 20K/F_6R67 20K/F_6

FRONT-R

888@0_4

MONO_OUT_888

EAPD_268

SPDIF_OUT

11/8 REV:B Remove R97, R98

C105

10U/10V_8

4

U50

EAPD <26>

C79

1000P/50V_4

SURR-L

SURR-R

U16

37

MONO-OUT/VREFO

38

AVDD2

39

HP-OUT-L/SURR-L

40

JDREF

41

HP-OUT-R/SURR-R

42

AVSS2

43

NC/CENTER

44

NC/LFE

45

NC/SIDE-L

46

DMIC_CLK/SIDE-R

47

EAPD

48

SPDIFO

+3V

.1U/10V_4

C78

1000P/50V_4

36

C101

10/10 : ADD. FOR NO CARDBUS

4

C63

C61

10P/50V_4

34

32

35

FRONT-L

FRONT-R

SP@ALC268/ALC888S-VC

DVDD11DMIC-1/2/GPIO02GPIO3/DMIC_CLK3DVSS1/DMIC_DATA

31

33

Sense B

4

NC/Sense C

R94 268@0_4R94 268@0_4

29

30

MIC2-VREFO

LINE1-VREFO

MIC1-VREFO-R

GPIO1/LINE2- REFO

SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD29SYNC10RESET#11PCBEEP

+AZA_VDD

BIT_CLK268

ACZ_SDIN268

REV:B Add R541

BEEP PCSPK

R519 NCB@0_4R519 NCB@0_4

4

27

28

MIC1-VREFO-L

MIC1-VREFO-R

MIC2-VREFO

MIC1-VREFO-L

VREF

MIC1-VREFO-R <26>

MIC2-VREFO <26>

MIC1-VREFO-L <26>

C65

C64

10U/10V_8

.1U/10V_4

ADOGND+5V_ADO

26

25

AVSS1

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

CD-R

CD-GND

CD-L

MIC2-R

MIC2-L

NC/LINE2-R

NC/LINE2-L

Sense A

12

R92 22_4R92 22_4

R93 22_4R93 22_4

C100 22P/50V_4C100 22P/50V_4

R541 *10K_4R541 *10K_4

D45 D@BAS316D45 D@BAS316

R96 888@0_4R96 888@0_4

24

23

22

21

20

19

18

17

16

15

14

13

LINE1-R

LINE1-L

MIC1-R

MIC1-L

*.1U/16V_4C72 *.1U/16V_4C72

*.1U/16V_4C77 *.1U/16V_4C77

*.1U/16V_4C82 *.1U/16V_4C82

MIC2_INT_R

MIC2_INT_L

SENSEA

C102 1U/16V_6C102 1U/16V_6

+3V

C86 1U/16V_6C86 1U/16V_6

C90 1U/16V_6C90 1U/16V_6

R28 20K/F_6R28 20K/F_6

R31 10K/F_6R31 10K/F_6

R25 39.2K/F_6R25 39.2K/F_6

C112

100P/50V_6

ACZ_RST#_AUDIO <12>

ACZ_SYNC_AUDIO <12>

ACZ_SDIN0 <12>

BIT_CLK_AUDIO <12>

ACZ_SDOUT_AUDIO <12>

DOCKIN# <22,31,32>

MXM_SPDIF_OUT <18>

REV:B, Please modify U16.PIN9.same as ZD1

R525 E@0_6R525 E@0_6

+3V

C602

4.7U/10V

+AZA_VDD

+1.5V

R526 I@0_6R526 I@0_6

3

LINE1-R <26>

LINE1-L <26>

MIC1-R <26>

MIC1-L <26>

ADOGND

R110 10K_4R110 10K_4

R111

1K_4

C603

.1U/10V_4

3

MIC2_INTL1 <26>

MIC1_JD <26,31>

LINEIN_JD <26,31>

LINE_JD <26,31>

BEEPBEEP_1PCBEEP

4

LINE OUT Amplifier

FRONT-L

+3V_AVDD

MUTE#<26>

SECNTL<26>

FRONT-R

L16 BLM11A601SL16 BLM11A601S

1 2

+3V

C28

*4.7U/10V_8

+3V

R119 *10K_4R119 *10K_4

PCMSPK

1

PCSPK

2

U20

3 5

CB@SN74LVC1G86DCKR

MDC

ACZ_SDOUT_MDC<12>

ACZ_SYNC_MDC<12>

ACZ_SDIN1<12>

ACZ_RST#_MDC<12> BIT_CLK_MDC <12>

2

R46 100K_4R46 100K_4

21

D15 MTW355D15 MTW355

21

D16 *MTW355D16 *MTW355

C53

4.7U/6.3V_6

ADOGND ADOGND

0C Change size to 0603 0111

ADOGND

PCMSPK <27>

PCSPK <14>

R386 22_4R386 22_4

2

Gain = -(Rf/Ri)

C41

.1U/10V_4

C582

4.7U/6.3V_6

R42 10K_6R42 10K_6

+3V_AVDD

+NVDD

1412MUTE#

R55 10K_6R55 10K_6

+3V_AVDD

10U/10V_8C38 10U/10V_8C38

10U/10V_8C60 10U/10V_8C60

+NVDD

VR

ACZ_SDOUT_MDC

ACZ_SYNC_MDC

MDC_SDIN1

C449

*10P/50V_4

1

R44 10K_6R44 10K_6

C42 47P/50V_4C42 47P/50V_4

U13

6

5

4

VR7

A

B

2

1 9

4

ADOGND

6

HPL

ADOGND

HPR

1412MUTE#

C

4

5

7

+3V_S5

25 40Tuesday, April 08, 2008

7

8

3

5

6

+NVDD+3V_AVDD

1

2

3

TM

AS & LOW COST

DIGVOL_UP<32>

DIGVOL_DN<32>

0C Change power from +3V to +3v_S5 to slove wake on ring issue 0111

CN16

1

GND

3

AC_SDO

5

GND

7

AC_SYNC

9

AC_SDI

11

AC_RST#

15

AC_BCLK

GND

MDC

Size Document Number Rev

REALTEK ALC268&888/MDC/VR

Date: Sheet

-

INL

PVDD

NVDD

SHDN#

INR

G1412

C55 47P/50V_4C55 47P/50V_4

R48 10K_6R48 10K_6

C578 4.7U/6.3V_6C578 4.7U/6.3V_6

U41

VOUT

VIN

C-

G5930

OUTL

+

PGND

GND

+

OUTR

-

C+

/SHDN

GND

N

Y

DIGVOL_UP

DIGVOL_DN

+3V_S5

2

RSV

4

RSV

6

3.3V

8

GND

10

GND

12 16

GND

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

2

3

SP@VR_XRE094_NOBLE

+1.5V_S5

R377

R383

E@0_6

I@0_6

C452 .1U/10V_4C452 .1U/10V_4

R358

*22_4

C403

*10P/50V_4

1

4

5

C443

.1U/10V_4

of

HPL <26>

HPR <26>

1A

5

Speaker Amplifier

C40

10U/10V_8

Gain = -(Rf/Ri)

SURR-L-1

SURR-R-1

R54 10K_6R54 10K_6 C57 330P/25V_4C57 330P/25V_4 R49 10K_6R49 10K_6 C54 330P/25V_4C54 330P/25V_4

+3V_AVDD

MUTE#

R57 10K_6R57 10K_6

R50 10K_6R50 10K_6

1441 MUTE

R508

10K_4

C581

47P/50V_4

INSPKR+ INSPKLINSPKL+

C66 2.2U/10V_8C66 2.2U/10V_8

C56 2.2U/10V_8C56 2.2U/10V_8

INSPKL+

INSPKR+

ADOGND

21

D41 MTW355D41 MTW355

21

D40 MTW355D40 MTW355

L50 0_6L50 0_6 L17 0_6L17 0_6 L51 0_6L51 0_6 L18 0_6L18 0_6

0C Change to 0 Ω0122

INSPKR-NINSPKRINSPKR+N INSPKL-N INSPKL+N

C59

47P/50V_4

2

+5V_ADO

ADOGND

SURR-L<25>

SURR-R<25>

3

1

R45

100K_4

1441 MUTE

Q11

2N7002

D D

MUTE#

EC MUTE

AMP_MUTE#<32>

C C

MUTE# <25>EAPD<25>

C504.7U/6.3V_6 C504.7U/6.3V_6

C514.7U/6.3V_6 C514.7U/6.3V_6

C58

47P/50V_4

ADOGND

SURR-L-2

SURR-R-2

ADOGND

SPEAKER

C580

47P/50V_4

ADOGND

4

+5V_ADO

+3V_AVDD

C45

.1U/10V_4

15

4

U12

1

LIN1

LVDD

18

RVDD

RIN1

2

LIN2

17

RIN2

16

RBYPASS

3

LBYPASS

5

SHDN

11

SE/BTL

THRMPAD

G1441

25

ADOGND

CN30

1 2

5

3

6

4

ADOGND

85204-04001_SPEAKER-CON

GND/HS22GND/HS

14

VDD3

GND/HS

21

10

C36 1U/16V_6C36 1U/16V_6

ADOGND

6

23

8

VOL

CT

NC

SECNTL

IN1/IN2

ROUT+

ROUTLOUT+ LOUT-

GND/HS

9

3

2

1

SYSTEM LINE OUT/SPDIF

LINEOUT_JD:

C9

47N/25V_4C947N/25V_4

HP not insert->H HP insert->L

SPDIF_OUT<25>

SECNTL

20

13

19 12 24 7

INSPKR+ INSPKRINSPKL+ INSPKL-

SECNTL <25>

ADOGND

HPL HPR

R13 75/F_4R13 75/F_4 R26 75/F_4R26 75/F_4

HPL<25> HPR<25>

R21

*1K_4

L9 BK1608LL121_6L9 BK1608LL121_6 L14 BK1608LL121_6L14 BK1608LL121_6

R9

*1K_4R9*1K_4

C14

47N/25V_4

ADOGND

D2C: NEW ADD FOR ESD

ADOGND

R18 0_8R18 0_8 R7 0_8R7 0_8 R88 0_8R88 0_8 R27 0_8R27 0_8 R79 0_8R79 0_8 R30 0_8R30 0_8 R65 0_8R65 0_8 R52 0_8R52 0_8

LINEOUT_JD

+5V

R12

+5V

R8

22K_4R822K_4

R12

10K_4

3

2

Q7

2N7002Q72N7002

1

LINE_JD

3

2

1

Q8

2N7002Q82N7002

LINE_JD <25,31>

3

D9

DA204UD9DA204U

Docking LINE OUT/SPDIF

HPL HPR

+3V_SPD

C27

.1U/10V_4

LINEOUT_JD

HPL_SYS HPR_SYS

SPDIF_OUT

ADOGND

+5V_ADO

1

2

ADOGND

Foxconn DFTJ10FR470 2FB5441-BKMC-7F Singatron DFTJ10FR437 2SJ1371-0010A1

L13 D@BK1608LL121_6L13 D@BK1608LL121_6 L15 D@BK1608LL121_6L15 D@BK1608LL121_6

5 4

10

3 2 1

7 8 6

SP@2SJ1371-0010A1_SPDIF

Normal OPEN Jack

LINEOUT_JD

BLACK

CN35

Drive

IC

1

AU_LINEOUT_L AU_LINEOUT_R

9

ADOGND

LED

3

+3V_SPD+3V

Q10

2

ME2347

AU_LINEOUT_L <31> AU_LINEOUT_R <31>

SYSTEM LINE IN/SUBWOOFER

BLUE

CN41

1

LINE1-L_1

CN31

1 2 3 4 5

LINE1-R_1

6 7

ADOGND

L58 BK1608LL121L58 BK1608LL121

L59 BK1608LL121L59 BK1608LL121

N

Y

+5V_ADO

1441 MUTE

ADOGND

10U/10V_8C587 10U/10V_8C587

10U/10V_8C588 10U/10V_8C588

SP@SUBWOOFER

LINE1-L<25>

B B

A A

LINE1-R<25>

MONO_OUT_L<25>

TM & LOW COST

AS

5

LINEINL_SYS

LINEINR_SYS

C596

470P/50V_4

ADOGND

D2C: NEW ADD FOR ESD

Docking LINE IN

LINE1-R_1

4

LINEIN_JD<25,31>

C595

470P/50V_4

2SJ-T351-S15

Normal OPEN Jack

LINEIN_JD

For ESD close to audio out connecter

Singatron DFTJ06FR732 2SJ-T351-S15 Foxconn DFTJ06FRA21 JA6233L-U3T4-7F Alltop DFTJ06FR902 C12107-906A9-L

L56 D@BK1608LL121_6L56 D@BK1608LL121_6

L57 D@BK1608LL121_6L57 D@BK1608LL121_6

ADOGND ADOGND

C594

*.1U/10V_4

3

D8

DA204UD8DA204U

2 6 3 4

5

1

2

AU_LINEIN_LLINE1-L_1

AU_LINEIN_L

AU_LINEIN_RAU_LINEIN_R

AU_LINEIN_R

C593

*.1U/10V_4

7

8

+5V_ADO

ADOGND

AU_LINEIN_L <31>

AU_LINEIN_R <31>

MIC

INT MIC array

3

CN32

INT_MIC

MIC1-VREFO-L<25>

MIC1-L<25>

MIC1-VREFO-R<25>

MIC1-R<25>

R509 2.2K_4R509 2.2K_4

C591 4.7U/6.3V_6C591 4.7U/6.3V_6

R510 2.2K_4R510 2.2K_4

C592 4.7U/6.3V_6C592 4.7U/6.3V_6

MIC1_L1

MIC1_R1

L60 BK1608LL121L60 BK1608LL121

L61 BK1608LL121L61 BK1608LL121

C598

470P/50V_4

MIC1_L

MIC1_R

MIC1_JD<25,31>

C597

470P/50V_4

For ESD close to audio out connecter

D2C: NEW ADD FOR ESD

MIC1_JD

R503 4.7K_4R503 4.7K_4

MIC2_INTL2

MIC1_L1

MIC1_R1

ADOGNDADOGND

R502 1K_4R502 1K_4

C579

*22P/50V_4

L54 D@BK1608LL121_6L54 D@BK1608LL121_6

L55 D@BK1608LL121_6L55 D@BK1608LL121_6

1 2 3 4

21

D39 MTW355D39 MTW355

AU_MIC_IN_L

AU_MIC_IN_R

MIC2-VREFO

MIC2-VREFO <25>

MIC2_INTL1 <25>

AU_MIC_IN_L <31>

AU_MIC_IN_R <31>

2

Singatron DFTJ06FR741 2SJ-T351-S11 Foxconn DFTJ06FRA39 JA6233L-P3T4-7F Alltop DFTJ06FR899 C12107-D06A9-L

Size Document Number Rev

Date: Sheet of

Date: Sheet

CN42

1

7 2 6 3 4

8 5

2SJ-T351-S11

Normal OPEN Jack

ADOGND

+5V_ADO

1

3

D7

2

DA204UD7DA204U

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

AMP /AUDIO JACK CONN

1

ADOGND

1A

of

26 40Tuesday, April 08, 2008

5

IDSEL SELECT POWER-ON-STRAPPING (SEE NOTE & TABLE FOR OPTIONS)

+3V

C186

CB@4.7U/10V_6

D D

NOTE: IDSEL SELECTION!

THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI AD LINES OR EXTERNAL IDSEL SIGNAL.

22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS.

CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC.

VCC5# VPP_PGM IDSEL SELECT

(124) (123)

DOWN DOWN AD18

DOWN UP AD20

UP DOWN AD25

UP UP PIN 127

C C

AD20 PCM_IDSEL PCM_IDSEL

R239 CB@100/F_4R239 CB@100/F_4

ID Select : AD20

Interrupt Pin : INTA#

Request Indicate : REQ0#

Grant Indicate : GNT0#

SKT_VCC

C171

C173

CB@4.7U/10V_6

B B

CB@4.7U/10V_6

C171

CB@.1U/10V_4

C232

CB@.1U/10V_4

PCMSPK<25>

PCIRST#<13,23>

PCI_PME#<13>

+3V

C222

CB@.1U/10V_4

AD[31..0]<13>

AD[31..0]

CBE3#<13> CBE2#<13> CBE1#<13> CBE0#<13>

PCLK_PCM<2>

DEVSEL#<13>

FRAME#<13>

IRDY#<13>

TRDY#<13>

STOP#<13>

PAR<13>

R214 CB@0_4R214 CB@0_4

REQ0#<13> GNT0#<13>

PCIRST#

R225 CB@0_4R225 CB@0_4

CLKRUN#<14,32>

SERIRQ<14,32>

INTA#<13>

22K TO 47K PULL-UPS MUST BE PLACED ON INTA#, PME#, SERIRQ# & CLKRUN#.

C202

CB@.1U/10V_4

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21

AD20

AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

CBE3# CBE2# CBE1# CBE0#

DEVSEL# FRAME# IRDY# TRDY# STOP# PAR

PCMSPK

REQ0# GNT0#

PCM_PME#

SERIRQ

4

U24

U24 CB@OZ601T

CB@OZ601T

64

CORE_VCC

77

CORE_VCC

97

CORE_VCC

115

CORE_VCC

1

PCI_VCC

20

PCI_VCC

33

PCI_VCC

4

AD31

5

AD30

6

AD29

7

AD28

8

AD27

9

AD26

10

AD25

13

AD24

14

AD23

15

AD22

16

AD21

17

AD20

18

AD19

19

AD18

21

AD17

22

AD16

28

AD15

29

AD14

30

AD13

31

AD12

34

AD11

35

AD10

36

AD9

37

AD8

38

AD7

39

AD6

40

AD5

41

AD4

42

AD3

43

AD2

44

AD1

46

AD0

127

IDSEL

11

C/BE3#

12

C/BE2#

49

C/BE1#

50

C/BE0#

26

PCI_CLK

27

DEVSEL#

23

FRAME#

24

IRDY#

25

TRDY#

47

STOP#

48

PAR

51

PERR#/SPKR_OUT

2

REQ#

3

GNT#

126

RST#

120

PME#/RI_OUT#

55

MF6 (CLKRUN#)

54

MF4 (RI_OUT#)

53

MF3 (SERIRQ#)

52

MF0 (INTA#)

GND32GND45GND65GND96GND

128

R236 CB@33K/F_6R236 CB@33K/F_6

R232 CB@33K/F_6R232 CB@33K/F_6

VCC5#/VCCD0#/SDATA

VCC3#/VCCD1#/SCLK

VPP_PGM/VPPD0/SLATCH

CFRAME#

CDEVSEL#

CBLOCK#

CCLKRUN#

CSTSCHG

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CCLK

CIRDY#

CTRDY#

CSTOP#

CPAR CPERR# CSERR#

CREQ# CGNT#

CINT#

CRST#

R2_D2

R2_D14

R2_A18

CVS1

CVS2

CCD1# CCD2#

CAUDIO

CC/BE3# CC/BE2# CC/BE1# CC/BE0#

124 125 123

103 102 101 100 99 110 109 108 106 105 104 118 95 94 93 75 73 74 71 72 70 69 68 85 84 82 83 80 81 78 79 76

R211 CB@33_4R211 CB@33_4

107 114 117 116 113 61 58 60 91 89 62 88 59 87 119 98 86 63 57 121 56 122 92 90

111 112 66 67

VCCD0 VCCD1

A_CAD31 A_CAD30A_CAD30 A_CAD29 A_CAD28 A_CAD27 A_CAD26 A_CAD25 A_CAD24 A_CAD23 A_CAD22 A_CAD21 A_CAD20 A_CAD19 A_CAD18 A_CAD17 A_CAD16 A_CAD15 A_CAD14 A_CAD13 A_CAD12 A_CAD11 A_CAD10 A_CAD9 A_CAD8 A_CAD7 A_CAD6 A_CAD5 A_CAD4 A_CAD3 A_CAD2 A_CAD1 A_CAD0

A_CFRAME# A_CIRDY# A_CTRDY# A_CDEVSEL# A_CSTOP# A_CPAR A_CPERR# A_CSERR# A_CREQ# A_CGNT# A_CINT# A_CBLOCK# A_CCLKRUN# A_CRST# A_CRSVD/D2 A_CRSVD/D14 A_CRSVD/A18 A_CVS1# A_CVS2# A_CCD1# A_CCD2# A_CAUDIO A_CSTSCHG

A_CC/BE3# A_CC/BE2# A_CC/BE1# A_CC/BE0#

3

A_CCLK

R223 CB@47K_6R223 CB@47K_6

SKT_VCC

A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9

A_CAD11

A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT#

A_CCLK

A_CIRDY# A_CC/BE2# A_CAD18 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD29 A_CRSVD/D2 A_CCLKRUN#

A_CCD1# A_CAD2 A_CAD4 A_CAD6 A_CRSVD/D14 A_CAD8 A_CAD10 A_CVS1# A_CAD13 A_CAD15 A_CAD16 A_CRSVD/A18 A_CBLOCK# A_CSTOP# A_CDEVSEL#

A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#

PCMCIA SOCKET

CN9

1

GND1

2

SKTAAD0/D3

3

SKTAAD1/D4

4

SKTAD3/D5

5

SKTAD5/D6

6

SKTAAD7/D7

7

-SKTACBE0/CE1#

8

SKTAAD9/A10

9

SKTABAD11/OE#

10

SKTAAD12/A11

11

SKTAAD14/A9

12

-SKTACBE1/A8

13

SKTAPAR/A13

14

-SKTAPERR/A14

15

-SKTAGNT/WE#

16

-SKTAINT/RDY

19

SKTAPCLK/A16

20

-SKTAIRDY/A15

21

-SKTACBE2/A12

22

SKTAAD18/A7

23

SKTAAD20/A6

24

SKTAAD21/A5

25

SKTAAD22/A4

26

SKTAAD23/A3

27

SKTAAD24/A2

28

SKTAAD25/A1

29

SKTAAD26/A0

30

SKTAAD27/D0

31

SKTAAD29/D1

32

SKTARSVD/D2

33

-SKTACLKRUN/WP

34

GND2

35

GND3

36

-SKTACD1/CD1#

37

SKTAAD2/D11

38

SKTAD4/D12

39

SKTAAD6/D13

40

SKTARSVD/D14

41

SKTAAD8/D15

42

SKTAAD10/CE2#

43

-SKTAVS1/VS1#

44

SKTAAD13/IORD#

45

SKTAAD15/IOWR#

46

SKTAAD16/A17

47

-SKTRSVD/A18

48

-SKTALOCK/A19

49

-SKTASTOP/A20

50

-SKTADEVSEL/A21

53

-SKTATRDY/A22

54

-SKTAFRAME/A23

55

SKTAAD17/A24

56

SKTAAD19/A25

57

-SKTAVS2VS2#

58

-SKTARST/RESET

59

0SKTASERR/WAIT#

60

-SKTAREQ/INPACK#

61

-SKTACBE3/REG#

62

SKTAAUDIO/BVD2

63

-SKTASTSCHG/BVD1

64

SKTAAD28/D8

65

SKTAAD30/D9

66

SKTAAD31/D10

67

-SKTACD2/CD2#

68

GND4

CB@PCMCIA_SOCKET

UPPER PIN

LOWER PIN

2

SKTA/VCC1 SKTA/VCC2

SKTA/VPP1 SKTA/VPP2

GND5 GND6 GND7 GND8

GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20

SKT_VCC

17 51

18 52

69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

85

NC

86

NC

87

NC

88

NC

A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9

A_CAD11

A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT#

A_CCLK

A_CIRDY# A_CC/BE2# A_CAD18 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD29 A_CRSVD/D2 A_CCLKRUN#

A_CCD1# A_CAD2 A_CAD4 A_CAD6 A_CRSVD/D14 A_CAD8 A_CAD10 A_CVS1# A_CAD13 A_CAD15 A_CAD16 A_CRSVD/A18 A_CBLOCK# A_CSTOP# A_CDEVSEL#

A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#

CN44

1

GND1

2

SKTAAD0/D3

3

SKTAAD1/D4

4

SKTAD3/D5

5

SKTAD5/D6

6

SKTAAD7/D7

7

-SKTACBE0/CE1#

8

SKTAAD9/A10

9

SKTABAD11/OE#

10

SKTAAD12/A11

11

SKTAAD14/A9

12

-SKTACBE1/A8

13

SKTAPAR/A13

14

-SKTAPERR/A14

15

-SKTAGNT/WE#

16

-SKTAINT/RDY

19

SKTAPCLK/A16

20

-SKTAIRDY/A15

21

-SKTACBE2/A12

22

SKTAAD18/A7

23

SKTAAD20/A6

24

SKTAAD21/A5

25

SKTAAD22/A4

26

SKTAAD23/A3

27

SKTAAD24/A2

28

SKTAAD25/A1

29

SKTAAD26/A0

30

SKTAAD27/D0

31

SKTAAD29/D1

32

SKTARSVD/D2

33

-SKTACLKRUN/WP

34

GND2

35

GND3

36

-SKTACD1/CD1#

37

SKTAAD2/D11

38

SKTAD4/D12

39

SKTAAD6/D13

40

SKTARSVD/D14

41

SKTAAD8/D15

42

SKTAAD10/CE2#

43

-SKTAVS1/VS1#

44

SKTAAD13/IORD#

45

SKTAAD15/IOWR#

46

SKTAAD16/A17

47

-SKTRSVD/A18

48

-SKTALOCK/A19

49

-SKTASTOP/A20

50

-SKTADEVSEL/A21

53

-SKTATRDY/A22

54

-SKTAFRAME/A23

55

SKTAAD17/A24

56

SKTAAD19/A25

57

-SKTAVS2VS2#

58

-SKTARST/RESET

59

0SKTASERR/WAIT#

60

-SKTAREQ/INPACK#

61

-SKTACBE3/REG#

62

SKTAAUDIO/BVD2

63

-SKTASTSCHG/BVD1

64

SKTAAD28/D8

65

SKTAAD30/D9

66

SKTAAD31/D10

67

-SKTACD2/CD2#

68

GND4

*CB@PCMCIA_SOCKET

1

PCMCIA SOCKET

SKTA/VCC1 SKTA/VCC2

UPPER PIN

LOWER PIN

SKTA/VPP1 SKTA/VPP2

GND5 GND6 GND7 GND8

GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20

NC NC NC NC

SKT_VCC

17 51

18 52

69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

85 86 87 88

C172

CB@4.7U/10V_6

SKT_VCC

A A

VCCD0 VCCD1

U23

6

VCC1

5

VCC2

7

VCC5#

8

VCC3#

CB@OZ2210G

1

+3.3

2

+3.3

3

+5V

4

GND

O2MICRO OZ2210 8PIN SINGLE SLOT PARALLEL POWER SWITCH

5

CB@4.7U/10V_6

C176

CB@4.7U/10V_6

C174

CB@.1U/10V_4

+5V

C177

CB@.1U/10V_4

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

Size Document Number Rev

Date: Sheet of

Date: Sheet

4

3

2

Date: Sheet

PROJECT : ZY2 & ZY6

PCMCIA(OZ601)

1

27 40Tuesday, April 08, 2008

1A

of

27 40Tuesday, April 08, 2008

C347

10U/6.3V_6

C327

.1U/16V_4

A

C325

.1U/16V_4

C355

.1U/16V_4

L30 *BK1608HS220_6_1AL30 *BK1608HS220_6_1A

C326

1000P/X7R/50V_4

+1.8V

B

+3V+1.8V_VDD

C353

C358

10U/6.3V_6

C353

.1U/16V_4

C346

.1U/16V_4

C

C348

.1U/16V_4

C349

.1U/16V_4

D

7 IN 1 CARD READER

E

4 4

3 3

2 2

+3V

Memory Card Power Supply

1 1

C640 & C639 close to APVDD(pin5) (length must under 120mil) and trace width = 20mil, after C640, pls put one more 0.1uF for it.

+1.8V_VDD

37 38

XD_CLE XD_WP#/SD_WP# XD_CE#/MS_SCLK/SD_CLK_L XD_WE#/MS_BS/SD_CMD

+3V

XD_D3/MS_D3/SD_D3 XD_D2/MS_D2/SD_D2 XD_D1/MS_D1/SD_D1 XD_D0/MS_D0/SD_D0

CLK_PCIE_CARD#<2> CLK_PCIE_CARD<2>

PLTRST#<13,18,21,23,29,32>

39 40 41 42 43 44 45 46 47 48

R276 8.2K_4R276 8.2K_4

Rev: B Add. for Vendor request

XD_CE#/MS_SCLK/SD_CLK_L XD_CE#/MS_SCLK/SD_CLK

REV:B Modify

R281 4.7K_4R281 4.7K_4

R277 4.7K_4R277 4.7K_4

R300 10K_4R300 10K_4

250mA

MC_PWR_CTRL#

VCC_XD

SD_CD#

MS_CD#

XD_CLE

C320

.01U/16V_4

A

R471 22_4R471 22_4

2 1

D44 BAS316D44 BAS316

2 1

D22 BAS316D22 BAS316

2 1

D21 BAS316D21 BAS316

R317 0_8R317 0_8

C345

.01U/16V_4

VCC_XD

Use 0805 type and Trace width = 30 mil" at MC_PWR_CTRL#,

C356

10U/6.3V_6

+3V

XD_D5/SD_D5

XD_D6/SD_D6

XD_D7/SD_D7

XD_D4/SD_D4

XD_RE#

34

NC36NC35NC

GND33GND32GND

DV18 PCIES_EN PCIES MDIO7 MDIO6 MDIO5 MDIO4 DV33 MDIO3 MDIO2 MDIO1 MDIO0

JMB385

XRSTN1XTEST2APCLKN3APCLKP4APVDD5APGND6APREXT7APRXP8APRXN9APV1810APTXN11APTXP

31

30

PREXT

TAV33

28

MDIO829MDIO9

CR1_PCTLN

25

MDIO1027MDIO1126MDIO12

MDIO13 MDIO14

CR1_LEDN

DV33 DV33 DV18

CR1_CD0N CR1_CD1N

SEECLK SEEDAT

12

APTXP_C APTXN_C

GND

Trace width = 12mil" at PREXT

CR_WAKE# <14>

XD_CD#

C343

270P/25V_4

VCC_XD

XD_RE#

XD_ALE

R313 10K_4R313 10K_4 R286 10K_4R286 10K_4

10/12 : BOM modify

MC_PWR_CTRL#

C360

.1U/16V_4

B

+3V

U27

24 23 22 21 20 19 18 17 16 15 14 13

+1.8V_VDD

JMICRON

R319 200K_4R319 200K_4

R314 200K_4R314 200K_4

R321

*10K_4

2

30mil

R322

*100K_4

XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_CE#/MS_SCLK/SD_CLK XD_WE#/MS_BS/SD_CMD

+1.8V_VDD+3V

XD_R/B# XD_ALE

MC_PWR_CTRL# XD_CE#/MS_SCLK/SD_CLK SD_CD# MS_CD#

T33T33 T32T32

.1U/10V_4C329 .1U/10V_4C329 .1U/10V_4C328 .1U/10V_4C328

XD_R/B# XD_WP#/SD_WP#

+3V

1

3

C359

4.7U/6.3V_6

Q29

*AO3403

VCC_XD

JMB_RXP <13> JMB_RXN <13>

JMB_TXN <13> JMB_TXP <13>

C

SD_CD# XD_WP#/SD_WP#

XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3

XD_WE#/MS_BS/SD_CMD

XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_CE#/MS_SCLK/SD_CLK XD_WE#/MS_BS/SD_CMD SD_CD# XD_WP#/SD_WP#

XD_D0/MS_D0/SD_D0 XD_D1/MS_D1/SD_D1 XD_D2/MS_D2/SD_D2 XD_D3/MS_D3/SD_D3 XD_CE#/MS_SCLK/SD_CLK MS_CD# XD_WE#/MS_BS/SD_CMD

CN21

23

(4)SD-VCC

25

(7)SD-DAT0

29

(8)SD-DAT1

10

(9)SD-DAT2

11

(1)SD-DAT3

24

(5)SD-CLK

12

(2)SD-CMD

36

SD-CD

35

SD-WP

14

(9)MS-VCC

19

(4)MS-DATA0

20

(3)MS-DATA1

18

(5)MS-DATA2

16

(7)MS-DATA3

15

(8)MS-SCLK

17

(6)MS-INS

21

(2)MS-BS

(3)SD/(1)MS/(1)XD-GND13SDIO-GND

22

(6)SD/(10)MS/(9)XD-GND

CARD_READER_TTN

CN22

21

SD-VCC

31

SD-DAT0

34

SD-DAT1

9

SD-DAT2

11

SD-DAT3

25

SD-CLK

15

SD-CMD

39

SD-C/D

41

SD-WP

19

SD-VSS1

29

SD-VSS2

40

SD-GND

12

MS-VCC

22

MS-DATA0

24

MS-DATA1

20

MS-DATA2

16

MS-DATA3

14

MS-SCLK

18

MS-INS

26

MS-BS

43

GND

10

MS-VSS1

28

MS-VSS2

42

GND

*CARD_READER_PROCONN

Size Document Number Rev

Date: Sheet

D

Date: Sheet

VCC_XDVCC_XD

(18)XD-VCC

(19)XD-CD

(5)XD-CLE (6)XD-ALE

(10)XD-D0 (11)XD-D1 (12)XD-D2 (13)XD-D3 (14)XD-D4 (15)XD-D5 (16)XD-D6 (17)XD-D7

SDIO-GND1

CARD READER JMB385

33

XD_CD#

34

XD_R/B#

1

(2)XD-R/B

(3)XD-RE (4)XD-CE

(7)XD-WE (8)XD-WP

XD-VCC

XD-CD

XD-R/B

XD-RE

XD-CE XD-CLE XD-ALE

XD-WE XD-WP

XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7

XG-GND1

XD-GND2

XD_RE#

2

XD_CE#/MS_SCLK/SD_CLK

3

XD_CLE

4

XD_ALE

5

XD_WE#/MS_BS/SD_CMD

6

XD_WP#/SD_WP#

7

XD_D0/MS_D0/SD_D0

8

XD_D1/MS_D1/SD_D1

9

XD_D2/MS_D2/SD_D2

26

XD_D3/MS_D3/SD_D3

27

XD_D4/SD_D4

28

XD_D5/SD_D5

30

XD_D6/SD_D6MS_CD#

31

XD_D7/SD_D7

32

37 38

VCC_XDVCC_XD

38

XD_CD#

2

XD_R/B#

3

XD_RE#

4

XD_CE#/MS_SCLK/SD_CLK

5

XD_CLE

6

XD_ALE

7

XD_WE#/MS_BS/SD_CMD

8

XD_WP#/SD_WP#

13

XD_D0/MS_D0/SD_D0

23

XD_D1/MS_D1/SD_D1

27

XD_D2/MS_D2/SD_D2

30

XD_D3/MS_D3/SD_D3

32

XD_D4/SD_D4

33

XD_D5/SD_D5

35

XD_D6/SD_D6

36

XD_D7/SD_D7

37

1 17

Quanta Computer Inc.

PROJECT :

ZY2 & ZY6

28 40Tuesday, April 08, 2008

E

1A

of

5

4

3

2

1

To NEW-CARD & EXT. USB

REV:B, CN10 change footprint

D D

NBSWON#<32>

MX0<31,32> MX5<31,32> MX6<31,32> MX7<31,32> MY0<31,32>

MY4<31,32> NUMLED#<32> CAPSLED#<32>

SATA_LED#_R<31>

PWRLED#<31,32> SUSLED#<31,32>

C C

LID591#<14,19,32>

PWRLED# SUSLED#

+5V+3V+3VPCU

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

CN10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

SW-20P

PDAT_SMB<2,14,16,20,21,23> PCLK_SMB<2,14,16,20,21,23>

USBON#<30,31,32>

USBP6-<13>

USBP6+<13>

USBP7-<13>

USBP7+<13>

USBP8-<13>

21

22

USBP8+<13>

PDAT_SMB PCLK_SMB USBON#

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

NEW CARD_CON20X2

REV:B, Please change PIN define.same as ZY5 CN8 change footprint

B B

+3V

CN8

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

+3V

CN17

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41

C611

*.1U/10V_4

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41

+3V+1.5V +5VPCU

275mA1.3A650mA 2A

+3V_S5

PLTRST# <13,18,21,23,28,32> NC_EN# <32> NEW_CLKREQ# <2>

CLK_PCIE_NEW_C# <2> CLK_PCIE_NEW_C <2>

PCIE_RXN1 <13> PCIE_RXP1 <13>

PCIE_TXN1 <13> PCIE_TXP1 <13>

CN43

1 2

5

3

6

4

*KEYBOARD LED

Fnction Keyboard Matrix

RF_LED#<23> BT_LED<22>

MX4<31,32> MX5<31,32> MX2<31,32> MX1<31,32> MX6<31,32>

ARCADE_KEY<32>

A A

MY0<31,32>

5

RF_LED# BT_LED MX4 MX5 MX2 MX1 MX6 MY0 Arcade_key

1 2 3 4 5 6 7 8

9 10 11 12

Aces 88501-120N

4

3

MX0/ MY0

MX1/ MY0

MX2/ MY0

MX3/ MY0

MX4/ MY0

MX5/ MY0

MX6/ MY0

MX5/ MY4

MX6/ MY4

MX7/ MY4

Size Document Number Rev

BTB CONN.

Date: Sheet

E-KEY

E-Mail

E-WWW

3G/TV

13 14

Wireless

BlueTooth

P-KEY

Presentation

Lock

Sync

Rev:B Add CN43 For backlight KB

Rev:B Change to

圓

to 方PAD C255,C234,C221,C199,R217,C198,R183, R182,R174,R257,R324,R335,R334,R349,C395

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

of

29 40Tuesday, April 08, 2008

2

29 40Tuesday, April 08, 2008

1

1A

5

4

3

2

1

Finger Printer

TM & AS

LOW COST

+3VSUS

RP50 0X2_4RP50 0X2_4

USBP9-<13>

D D

USBP9+<13>

HOLES

HOLE12

H-c256d142p2-8

2 3 4

1

8

C C

3 1

CPU NUT (BOT)

5 6 7

9

4 2

HOLE11

H-c256d142p2-8

2 3 4

1

8

USBP9-_R USBP9+_R

HOLE13

H-c256d142p2-8

5 6 7

9

H-c256d142p2-8

2 3 4

1

8

CN15

346 2 1

SP@Finger Printer

5 6 7

9

5

Y

N

Rev : B Add MINI NUT

HOLE22

HOLE33

HOLE33 H-C197D142P2

H-C197D142P2

1

HOLE34

HOLE34 H-C197D142P2

H-C197D142P2

1

HOLE25

HOLE25 *H-C177D142p2

*H-C177D142p2

1

HOLE22 H-C177D126p2

H-C177D126p2

1

PAD1

*Pad-obs

1

PAD2

*Pad-obs

1

USB

USBON#<29,31,32>

USBP0-<13>

USBP0+<13>

USBP1-<13>

USBP1+<13>

*H-TC256BC315D118P2-8

2 3 4

HOLE9

8

2

4 1 9

10/16: Change BOM

5 6 7

1

9

U8

IN1 IN23OUT2

EN# GND GND-C

G548A2P8U

1

2

*H-TC256BC315D118P2-8

2 3 4

OUT3

OUT1

OC#

U7

U7 CM1293-04SO

CM1293-04SO

CH1

VN

CH23CH3

HOLE8

1

8

9

8 7 6

R17 *6.34K/FR17 *6.34K/F

5

CH4

VP

5 6 7

USBPWR1

RP56 0X2_4RP56 0X2_4

+5V_S5

6

5

4

RP55 0X2_4RP55 0X2_4

HOLE17

*H-TC256BC315D118P2-8

2 3 4

1

8

9

+5V_S5+5V_S5

2 4

USBPWR1

2 4

*H-TC256BC315D118P2-8

5 6 7

C31

10U/10V_8

USBPWR1

1 3

2 3 4

C25

100U/6.3_3528

C23

100U/6.3_3528

HOLE24

5 6 7

1

8

9

USBP0-_R

USBP0+_R

USBP1-_R

USBP1+_R

REV:C Modify

C24

1000P/X7R/50V_4

USBP0-_R USBP0+_R

C22

1000P/X7R/50V_4

USBP1-_R USBP1+_R

HOLE31

*H-TC256BC315D118P2-8

2 3 4

1

8

D47 MLVG06031RD47 MLVG06031R

D48 MLVG06031RD48 MLVG06031R

D49 MLVG06031RD49 MLVG06031R

D50 MLVG06031RD50 MLVG06031R

9

12

CN38

1 2 3 4

Alltop_USB

1 2 3 4

Alltop_USB

5 6 7

5

1

5

6

2

6

7

3

7

8

4

8

CN37

5

1

5

6

2

6

7

3

7

8

4

8

HOLE10

*H-TC256BC315D118P2-8

2 3 4

1

8

9

5 6 7

B B

A A

HOLE14

H-c256d142p2-8

2 3 4

H-TC256BC295D63P2-8

2 3 4

8

HOLE26

8

5 6 7

1

9

5 6 7

1

9

HOLE15

H-c256d142p2-8

2 3 4

5 6 7

1

8

9

MDC NUT (TOP)

HOLE28

H-TC256D63PT-8

2 3 4

5

5 6 7

1

8

9

Rev:B New add HOLE32 HOLE26 & 28 Change footprint

HOLE16

H-c256d142p2-8

2 3 4

1

8

9

5 6 7

HOLE32

h-c256d142p2-8

2 3 4

1

8

9

HOLE19

H-c256d142p2-8

2 3 4

1

8

9

5 6 7

4

HOLE20

H-c256d142p2-8

5 6 7

H-c256d142p2-8

2 3 4

HOLE35

5 6 7

1

8

9

HOLE35

HOLE35 *H-BC256D138P2

*H-BC256D138P2

1

要搬到

BOT

去

HOLE30

*H-c256d118p2-8

2 3 4

1

8

9

HOLE7

*H-C276D118PT-8

2 3 4

1

8

9

3

5 6 7

HOLE27

*H-TC256BC315D118P2-8

2 3 4

*H-tc256bc315d118p2-8

2 3 4

1

8

HOLE18

1

8

5 6 7

9

5 6 7

9

HOLE29

HOLE21

HOLE23

*H-tc276bc315d118p2-8

2 3 4

Size Document Number Rev

Date: Sheet

2

Date: Sheet

5 6 7

1

8

9

USB/FINGER PRINTER

HOLE21

*H-tc276bc315d118p2-8

2 3 4

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

PROJECT : ZY2 & ZY6

5 6 7

1

8

9

HOLE29

*H-tc276bc315d118p2-8

2 3 4

8

30 40Wednesday, April 09, 2008

1

5 6 7

1

9

1A

of

MXM NUT (BOT)

5

Rev:B change footprint

INT K/B

D D

MY15<32> MY14<32> MY13<32> MY12<32> MY11<32> MY10<32> MY9<32> MY8<32> MY7<32> MY6<32> MY5<32> MY4<29,32> MY3<32> MX7<29,32> MX6<29,32> MY2<32> MX5<29,32> MX4<29,32> MX3<32> MX2<29,32> MY1<32> MY0<29,32> MX1<29,32> MX0<29,32> MY16<32> MY17<32>

MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0 MY16 MY17 MX0

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 MX7 MX6 MX5 MX4 MX3 MX2 MX1

4

CN12

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Aces 88502-2641

3

CPU FAN

+5V

U11

CPUFAN#_ON<3>

CPUFAN#<32>

+5V

C37

2.2U/10V_8

27 28

2.2U/10V_8

FANPWR = 1.6*VSET

1

4

G995

VIN2VO

GND

/FON

GND GND

VSET

GND

3 5 6 7 8

FANSIG<32>

TH_FAN_POWER

C52

2.2U/10V_8

2

C43

.01U/16V_4

C49

*.01U/16V_4

1

+3V

R47

10K_4

CN33

1 2 3

6

4

Thermistor_CTRL<38>

5

FAN_CON

7

LED

C C

+3VPCU

B B

+3V

SATA_LED#<12>

R53 330_6R53 330_6

R56 330_6R56 330_6

T/P

+5V

R339

A A

TPDATA<32>

TPCLK<32>

R339

10K_4

5

R280

10K_4

U26

TC7SH08FU

R278 *0_4R278 *0_4

53

1

2

Rev:B LED7 Change to SP@

LED7

1

2

SP@LED_DUAL_LIGHT

LED8

1

2

LED_DUAL_LIGHT

R345

10K_4

L33 LZA10-2ACB104MTL33 LZA10-2ACB104MT L34 LZA10-2ACB104MTL34 LZA10-2ACB104MT

SATA_LED#_R

4

TM & LOW COST

4

3

4

3

C396

*.01U/16V_4

SATA_LED#_R <29>

BEGA0017ZA0

AS

C379

.1U/16V_4

C384

*.01U/16V_4

BEAB0019ZA0

SUSLED# <29,32>

PWRLED# <29,32>

BATLED1# <32>

BATLED0# <32>

REV:B, CN14 change footprint

+5V

L32

BLM21P300S

+TPVDD

TPDATA_R TPCLK_R

ACES_88058-0601

4

CN14

1 2 3 4 5 6

7 8

CABLE DOCK

AU_LINEOUT_L<26>

AU_LINEOUT_R<26>

AU_LINEIN_L<26>

AU_LINEIN_R<26>

AU_MIC_IN_L<26>

AU_MIC_IN_R<26>

10/12 : BOM modify

R574 D@390_6R574 D@390_6 R575 D@390_6R575 D@390_6 R570 D@0_6R570 D@0_6 R571 D@0_6R571 D@0_6 R572 D@0_6R572 D@0_6 R573 D@0_6R573 D@0_6

HDMI_HP_A

10/03: Follow ZY5 ,Add R7432 & R580

Rev:B ,Add D43 for customer request

DCIN

VA2

+5V

C609

D@.1U/10V_4

C606

D@.1U/10V_4

3

D12 D@SW1010CD12 D@SW1010C

3

D14 D@PDS1040SD14 D@PDS1040S

Rev:B ,Add

+5V_S5

HDMI_DDCDATA<18,20>

HDMI_DDCCLK<18,20>

VGA_RED_PR<19>

VGA_GRN_PR<19>

VGA_BLU_PR<19>

C32

D@.1U/25V_4

+3V_S5

R23

D@100K_4

DOCKIN#

C21

D@.1U/10V_4

D_DVICLK+<20>

D_DVICLK-<20>

D_DVITX0+<20>

D_DVITX0-<20>

D_DVITX1+<20>

D_DVITX1-<20>

D_DVITX2+<20>

D_DVITX2-<20>

HDMI_HP_A<18,20>

CRT_VSYNC1<19> CRT_HSYNC1<19>

DDCCLK_1<19> DDCDAT_1<19>

DOCKIN#<22,25,32>

LINE_JD<25,26>

D43 D@MTW355D43 D@MTW355

USBON#<29,30,32>

USBP10-<13>

USBP10+<13>

+5V_S5

C20

D@.1U/25V_4

+5V

3

2

1

D_LINEOUT_L D_LINEOUT_R

DOCKIN2#

+5V

C13

*10U/25V_8

Rev:C ,change 1208 to 0805

R24

D@10K_4

Q9

D@2N7002

2

D_LINEOUT_L D_LINEOUT_R D_LINEIN_L D_LINEIN_R D_MIC_IN_L D_MIC_IN_R D_MIC_IN_R

R20 D@100K_4R20 D@100K_4

R22 D@1K_4R22 D@1K_4

CRT_SENSE#<19,32>

VA1

21

2

1

Rev:B ,change 0603 to 0402

C608

D@.1U/10V_4

CN34

2

DVI_CLK

3

DVI_CLK#

5

DVI_TX0

6

DVI_TX0#

8

DVI_TX1

9

DVI_TX1#

11

DVI_TX2

12

DVI_TX2#

25

DVI_DT

26

DVI_DDCDT

27

DVI_DDCCK

14

VGA_R

16

VGA_G

18

VGA_B

28

VGA_VS

29

VGA_HS

30

VGA_DDCCK

31

VGA_DDCDT

23

HP_DT#

21

HP_L

22

HP_R

40

DOCK_DT1#

20

DOCK_DT2#

51

VGA_DT#

49

USB_EN#

48

USB#

47

USB

32

5V_S0

68

P3-5V_USB, 3A

67

P4-19V, 5A

50

RESERVED

PR_INSERT_5V <19,20>

LIN_IN_DT#

LIN_IN_L LIN_IN_R

MIC_DT#

MIC_L

MIC_R

SPDIF

LAN_0

LAN_0#

LAN_1

LAN_1#

LAN_2

LAN_2#

LAN_3

LAN_3#

LAN_PWR

LAN_ACT

LAN_LINK

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GNDA GNDA

P1-GND P2-GND

GND

D@JAE CONN

33 34 35

36 37 38

41

56 57 59 60 43 44 62 63 52 53 54

64 1 4 7 10 13 15 17 19 42 45 46 55 58 61 69 70 71 72 24 39 65 66 73 74

D_LINEIN_L D_LINEIN_R

D_MIC_IN_L

+PWR_TRANSF

LINEIN_JD <25,26>

MIC1_JD <25,26>

SPDIF_DOUT <25>

TX0P_PR <22> TX0N_PR <22> TX1P_PR <22> TX1N_PR <22> TX2P_PR <22> TX2N_PR <22> TX3P_PR <22> TX3N_PR <22>

D_ACTLED# <22>

D_LINKLED# <22>

+PWR_TRANSF

C133

D@.01U/16V_4

To LAN

C126

D@.01U/16V_4

Close Dock

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 & ZY6

Size Document Number Rev

FAN,LED,KB,DEBUG PORT,TP

Date: Sheet

PROJECT : ZY2 & ZY6

31 40Wednesday, April 09, 2008

of

1

of

1A

5

+3VPCU

L36 BK1608HS220_6_1AL36 BK1608HS220_6_1A

30mil

+3VPCU

C447

C461

.1U/16V_4

EC_FPBACK#<19>

ARCADE_KEY<29>

PLTRST#<13,18,21,23,28,29>

LFRAME#<12,23>

PCLK_591<2>

CLKRUN#<14,27>

GATEA20<12>

RCIN#<12>

EC_SCI#<14>

USBON#<29,30,31>

SERIRQ<14,27>

KBSMI#<14>

E775AGND

C447

.1U/16V_4

LAD0<12,23> LAD1<12,23> LAD2<12,23> LAD3<12,23>

R413 20M_6R413 20M_6

C466

18P_4

C399

.1U/16V_4

D37 BAS316D37 BAS316

2 1

MX0<29,31> MX1<29,31> MX2<29,31> MX3<31> MX4<29,31> MX5<29,31> MX6<29,31> MX7<29,31>

MY0<29,31> MY1<31> MY2<31> MY3<31> MY4<29,31> MY5<31> MY6<31> MY7<31> MY8<31>

MY9<31> MY10<31> MY11<31> MY12<31> MY13<31> MY14<31> MY15<31> MY16<31> MY17<31>

MBCLK<33>

MBDATA<33>

2ND_MBCLK<3>

2ND_MBDATA<3>

TPCLK<31>

TPDATA<31>

CHG-EN<33>

T55T55

Y10

1 4

32.768KHz

C442

4.7U/6.3V_6

D D

For PCICLK

PCLK_591

R387

PU +3V for SCI

22_4

C450

C450 10P_4

10P_4

PU +3V for SMI

C C

FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, 2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS.

+3VSUS

B B

A A

RP48 10K_10P8RRP48 10K_10P8R

10

MX4

9

MX5

8

MX6

7 4

MX7

MX3

1

MX2

2

MX1 SPI_SCK_uR

3

MX0

56

+3VSUS

5

C468

.1U/16V_4

LFRAME# LAD0 LAD1 LAD2 LAD3 PCLK_591

EC_FPBACK#

ARCADE_KEY

PLTRST#

USBON#

SERIRQ

R412

33K/F_4

C462

18P_4

E775AGND

C398

.1U/16V_4

SCI#_uR

MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17

MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA

TPCLK TPDATA

TB2DATA

E775_32KX1

E775_32KX2

4

+A3VPCU

C440

C441

10U/6.3V_6

.1U/16V_4

U33

19

46

76

88

115

102

VCC1

VCC2

VCC3

VCC4

VCC5

3

LFRAME

126

LAD0

127

LAD1

128

LAD2

1

LAD3

2

LCLK

8

GPIO11/CLKRUN

121

GA20

122

KBRST

29

ECSCI/GPIO54

6

GPIO24/LDRQ

124

GPIO10/LPCPD

7

LREST

123

GPIO67/PWUREQ

125

SERIRQ

9

GPIO65/SMI

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

53

KBSOUT0/JENK

52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49

KBSOUT4/JEN0

48

KBSOUT5/TDO

47

KBSOUT6/RDY

43

KBSOUT7

42

KBSOUT8

41

KBSOUT9

40

KBSOUT10

39

KBSOUT11

38

KBSOUT12/GPIO64

37

KBSOUT13/GPIO63

36

KBSOUT14/GPIO62

35

KBSOUT15/GPIO61/XOR_OUT

34

GPIO60/KBSOUT16

33

GPIO57/KBSOUT17

70

GPIO17/SCL1

69

GPIO22/SDA1

67

GPIO73/SCL2

68

GPIO74/SDA2

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27PSDAT2

12

GPIO25/PSCLK3

13

GPIO12/PSDAT3

77

32KX1/32KCLKIN

79

32KX2

WPCE775

08/10 FAE: L43 CAN CHANGE FROM BEAD TO SHORT. BUT, PLEASE PUT AGND & 32K CAP & AVCC CAP AT ONE POINT.

AVCC

GND1

GND2

GND3

5

18

45

BK1608HS220_6_1A

ZS1 STILL USE BEAD FOR SAFE.

4

LPC

KB

SMB

PS/2

GND4

GND5

78

89

.1U/16V_4C445 .1U/16V_4C445 .1U/16V_4C446 .1U/16V_4C446

L37

E775AGND

GND6

116

A/D

D/A

GPIO30/CIRTX2

GPIO32/D_PWM GPIO33/H_PWM

GPIO40/F_PWM

GPIO

GPIO45/E_PWM

GPIO46/CIRRXM/TRST

GPIO52/CIRTX2/RDY

GPO84/BADDR0

TIMER

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO66/G_PWM

SPI

IR

FIU

GPIO77/SPI_DI

GPO76/SPI_DO/SHBM

GPIO75/SPI_SCK

GPIO72/IRRX1/SIN2

GPIO70/IRRX2_IRSL0

GPIO71/IRTX/SOUT2

GPIO87/CIRRXM/SIN_CR

GPIO34/CIRRXL

GPIO16/CIRTX

GPO83/SOUT_CR/BADDR1

GPIO55/CLKOUT

VCORF

AGND

44

103

VCORF_uR

C467

1U/10V_4

+3V

GPI90/AD0 GPI91/AD1 GPI92/AD2

GPI93/AD3 GPIO05/AD4 GPIO04/AD5

GPI94/DA0

GPI95/DA1

GPI96/DA2

GPI97/DA3

GPIO01/TB2

GPIO03/AD6

GPIO06

GPIO07/AD7

GPIO23/SCL3

GPIO31/SDA3

GPIO36/TB3

GPIO42/TCK GPIO43/TMS

GPIO44/TDI

GPO47/SCL4

GPIO50/TDO

GPIO51/TA3

GPIO53/SDA4

GPIO81

GPO82/TRIS

GPIO41

GPIO56/TA1 GPIO20/TA2 GPIO14/TB1

F_SDI F_SDO F_CS0 F_SCK

VCC_POR

VREF

CIR

3

C457

C453

.1U/16V_4

4.7U/6.3V_6

4

VDD

97

TEMP_ABAT

98 99 100

DIGVOL_UP

108

DIGVOL_DN

96

101 105 106 107

64 95 93 94 119 109 120 65 66 15 16

PWROK_MXM

17 20 21 22 23

HP_MUTE#

24 25 26 27

HWPG

28

DNBSWON#_uR

91 110

CCD_POWERON

112 80

31 117 63

32 118 62 81

CRT_SENSE#

84

RF_EN

83 82

RSMRST#_uR

75 73

PWROK_EC_uR

74 113

CIRRX2

14 114

uR_SOUT_CR

111

SPI_SDI_uR_R

86 87

SPI_CS0#_uR

90

SPI_SCK_uR_R

92

ECDB_CLOCK

30

VCC_POR#

85

VREF_uR +A3VPCU

104

Q37

*RHU002N06

3

T63T63

D30 BAS316D30 BAS316

R414 0_4R414 0_4

R415 0_4R415 0_4 R518 0_4R518 0_4

R407 22_4R407 22_4

R391 22_4R391 22_4

R409 4.7K_4R409 4.7K_4

R381 0_4R381 0_4

+3VPCU +3VPCU

R459

*10K_4

2

1

R461 SP@0_4R461 SP@0_4

3

2

1

I/O ADDRESS SETTING

BADDR1-0

0 0

0 1

1 0

1 1

SHBM=0: Enable shared memory with host BIOS

T57T57

.1U/16V_4C451 .1U/16V_4C451 .1U/16V_4C448 .1U/16V_4C448

TEMP_MBAT <33>

PCIE_WAKE# <14,21,23> ICMNT <33> DIGVOL_UP <25> DIGVOL_DN <25>

CC-SET <33> CPUFAN# <31> NC_EN# <29> CV-SET <33>

ACIN <18,33> NBSWON# <29> LID591# <14,19,29> SUSB# <14> MXM_SMCLK <18,20>

SUSLED# <29,31>

MXM_SMDATA <18,20> BATLED0# <31> BATLED1# <31> VRON <35> MAINON <36,37,38,39> PWROK_MXM <18> AMP_MUTE# <26>

SUSON <37,39>

ENERGY_DET <21>

D/C# <33>

S5_ON <34,39>

DNBSWON# <14> BT_POWERON# <22> CCD_POWERON <19>

DOCKIN# <22,25,31>

MUTE_BEEP <25>

FANSIG <31>

CONTRAST <19>

NUMLED# <29>

PWRLED# <29,31>

CAPSLED# <29>

CRT_SENSE# <19,31>

RF_EN <23>

CELL-SET <33>

RSMRST# <14> SUSC# <14> PWROK_EC <14>

NC_TEMP <38>

BADDR0 BADDR1 SHBM

1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware

SM BUS PU

MBCLK MBDATA

2ND_MBCLK 2ND_MBDATA

MXM_SMCLK MXM_SMDATA

CRT_SENSE#

ACER ID

2ND_MBCLK 2ND_MBDATA

SPI FLASH

+3VPCU

R390

10K_4

1009: Add.

1/13 Comfirm by vendor mail :

SPI_SDO_uRSPI_SDO_uR_R

T64T64

+3VPCU

Near Flash

R565 22_4R565 22_4

SPI_SDI_uRSPI_SDI_uR_R

If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster)

H/W POWER GOOD

REV: B D34 Change to E@

D34 E@BAS316D34 E@BAS316

D28 D2@BAS316D28 D2@BAS316

D36 D3@BAS316D36 D3@BAS316

D35 BAS316D35 BAS316

D31 BAS316D31 BAS316

D32 BAS316D32 BAS316

D33 *BAS316D33 *BAS316

INTERNAL KEYBOARD STRIP SET

Size Document Number Rev

Date: Sheet

R460

*10K_4

HWPG_2.5V<39>

HWPG_1.5V<39>

HWPG_1.8V<38,39>

HWPG_1.05V<36>

HWPG_VDR<6,37>

SYS_HWPG<34>

DELAY_VR_PWRGOOD<3,6,14,35>

TM & LOW COST

AS

+5VPCU

CIRRX2CIRR_X2

R456 SP@47_6R456 SP@47_6

CIRR_X2

C523

SP@4.7U/10V_8

N

Y

U37

1 2 3 4 5

SP@EVER_IRM-V038_TRI-P

2

I/O Address

Index

Data

XOR TREE TEST MODE

CORE DEFINED

2Eh 2Fh

164Eh

CCD_POWERON

uR_SOUT_CR

RF_EN

R416 4.7K_4R416 4.7K_4 R417 4.7K_4R417 4.7K_4

R418 4.7K_4R418 4.7K_4 R375 4.7K_4R375 4.7K_4

R378 *4.7K_4R378 *4.7K_4 R379 *4.7K_4R379 *4.7K_4

R410 4.7K_4R410 4.7K_4

SPI_SDI_uR

SPI_SDO_uR

SPI_SCK_uR

SPI_CS0#_uR

164Fh

R380 10K_4R380 10K_4

R365 *10K_4R365 *10K_4

R411 10K_4R411 10K_4

U34

6

SCL

5

SDA

7

WP

24LC08

U32

2

SO

5

SI

6

SCK

1

CE

W25X80VSSIG

REV: B remove D33

MY0

R419 10K_4R419 10K_4

Quanta Computer Inc.

PROJECT :

WPCE775C_0DG & FLASH

1

+3VPCU

+3V

1

A0

2

A1

3

A2

8

VCC

4

GND

VDD

HOLD

WP

VSS

+3V

R408

10K_4

HWPGHWPG

ZY2 & ZY6

R422

0_4

32 40Tuesday, April 08, 2008

8

7

3

4

+3VPCU

C469

.1U/16V_4

C444

.1U/16V_4

MPWROK <6,14>

of

1A

5

PL8

PR9

PR9 *10K/F_6

*10K/F_6

+3VPCU

3

1

PR202

PR202 100K/F_6

100K/F_6

12

PC159 0.1U/50V_6PC159 0.1U/50V_6

PL8

HI0805R800R-00_8

PL7

HI0805R800R-00_8

PD8 *ZD12VPD8 *ZD12V

2 1

PR196

4.7K/F_6

PR197

PR197 100K/F_6

100K/F_6

2

6251EN

TEMP_MBAT

PF8

1 2

BUS-10A-1206

PR184

PR184 100K/F_6

100K/F_6

PF7

PJ7

DCJK-2DC-G756-X06-5P-H

SP@POWER_JACK

D D

Input sense resistor and Constant power setting table

C C

1 2 3

4

5

ACIN<18,32>

PC7

0.1U/50V_6

PC9

0.1U/50V_6

PR10

PR10 *6.8K/F_6

*6.8K/F_6

65W 90W

20m Ohm 20m Ohm

R1

CS+020AGM00

71.5K Ohm

R2

10K Ohm

R3

CS31003F949

B B

CN23

1 2 3 4

8

5

9

6 7

SUYIN_BATTERY

CS+020AGM00

6.19K Ohm

CS26193F929CS37153F917

10K Ohm

CS31003F949

CHG-EN<32>

Rev. B

PC64 47P/50V_6PC64 47P/50V_6

PC65 47P/50V_6PC65 47P/50V_6

LITTLE-7A-1206

1 2

PC8

2200P/50V_6

PR7

PR7 *10K/F_6

*10K/F_6

DMN601K-7

100P/50V_6

MBAT+

PD21 RB500V-40PD21 RB500V-40

PR195 *0_6PR195 *0_6

Rev. B

PF7

Rev. B

ACIN_1

PQ49

PR201 0_6PR201 0_6

PC158

10mil

PR115

PR115 *0_6

PC157

PC157 .01U/50V_6

.01U/50V_6

*0_6

PR95

PR94

100_4

A A

+3VPCU

1

TEMP_MBAT

3

PD20

*DA204U

2

Add ESD diode base on EC FAE suggestion

PD15

PD15 ZD3.6V

ZD3.6V

2 1

5

PD14

PD14 ZD3.6V

ZD3.6V

MBCLK <32>

MBDATA <32>

PR185

*100K/F_6

12

4

VA

PC10

0.1U/50V_6

PD9

PD9 SW1010CPT

SW1010CPT

TEMP_MBAT <32>

HI0805R800R-00_8

6251CELLS_1

DCIN

PR102

PR102 10/F_6

10/F_6

PL15

BAT-V

PL16

+3VPCU

CELL-SET<32>

CELL-SET = Hi ----> Cells = VDD ---->4S CELL-SET = Low ----> Cells = GND ---->3S

4

PD7

PDS1040S-13

1

3

2

PC11

0.1U/50V_6

PD11

P4SMAJ20A

Rev. B

ISL6251_VDD 6251EN VREF

PR122

100K/F_6

6251LR

BAT-V

PR97 20/F_6PR97 20/F_6

PR132

10K/F_6

2

PR100

PR100 20/F_6

20/F_6

47N/25V_6

PR103

82.5K/F_6

PR104

10K/F_6

PR133

PR133 *10K/F_6

*10K/F_6

PR131

PR131 10K/F_6

10K/F_6

3

PQ27

DMN601K-7

1

PC69

VA2

2 1

CSOP

1 2

CSON

PC70

0.1U/50V_6

6251ACSET

6251CELLS_2

PR127

PR127 100K/F_6

100K/F_6

PR14

0.02_7520

1 2

21

22

23

24

2

3

6251CELLS_1

2

PQ26

DMN601K-7

Rev. B

2.2/F_6

CSOP

CSON

ACPRN

DCIN

ACSET

EN

R1

PR98

CELLS

4

3

1

3

PC16

0.1U/50V_6

PC68

0.1U/50V_6

CSIP

19

CSIP

PU11

ISL6251A

ICOMP5VCOMP

6

PC79 .01U/50V_6PC79 .01U/50V_6

6251ICOMP

6251VCOMP1

PC78 *100P/50V_6PC78 *100P/50V_6

6251VCOMP2

3

PR99

PR99 20/F_6

20/F_6

CSIN

20

CSIN

ICM

7

PR112

3.3K/F_6

PC82

PC82 .01U/50V_6

.01U/50V_6

PR18

PR18 220K/F_6

220K/F_6

PR19

PR19 220K/F_6

220K/F_6

ISL6251_VDD

15

1

VDD

VDDP

BOOT

UGATE

PHASE

LGATE

PGND

GND

VADJ

ACLIM

CHLIM

VRFE

9

8

PR110

PR110 100_4

100_4

1 6

2

3

PC71

2.2u/10V_8

1 2

PR96

4.7_6

ISL6251_VDDP

Rev. B

6251B_2

16

17

18

14

13

12

11

10

PC77

PC77 100P/50V_6

100P/50V_6

ICMNT

PC81

PC81 3300P/50V_4

3300P/50V_4

1 2

PQ7

IMD2AT108

PR101

2.7_6

ISL6251_UGATE

ISL6251_PHASE

ISL6251_LGATE

CC-SET <32>

2

PQ9

PQ9 FDD6685

FDD6685

43

1

5

4

6251B_1

ICMNT <32>

PR189 0_6PR189 0_6

PC67

4.7U/10V_8

1 2

PD16

PD16 RB500V-40

RB500V-40

PC66

.1U/50V_8

FDS6690AS

PR111

R2

SP@6.19K/F_6

VADJ

ACLIM

PR114

R3

10K/F_6

LIM = (1/R1)*(((0.05/VREF=2.39)VACLM)+0.050)

PC181

PC181 1U/25V_6

1U/25V_6

PC178

PC177

1U/25V_6

578

PQ42

FDS8878

3 6

241

578

PQ41

3 6

241

VREF

PR120

PR120 *514K/F_6

*514K/F_6

Float = 4.2V / CELL

PR121 *0_6PR121 *0_6

PR119

PR119 *514K/F_6

*514K/F_6

PC179

PC179 1U/25V_6

1U/25V_6

PC176

PC176 1U/25V_6

1U/25V_6

D/C# <32>

PC153

PC153 2200P/50V_6

2200P/50V_6

1 2

PC180

PC180 1U/25V_6

1U/25V_6

0.1U/50V_6

PC175

PC175 10U/25V_1206

10U/25V_1206

VA3

PC154

0.1U/50V_6

6R8UH

PR183

*2.2_6

PC156

*2200P/50V_6

PL14

PC164

CURRNT LIMIT POINT =(90w/19v)*0.85= 4.026A

4.026A=(1/0.02)((0.05/2.365)Vaclm+0.05)

Vaclm=((R3//152)/(R3//152+R2//152))*Vref R1=adapter current sense resistnece

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Rev. B for EMI

VIN

PL13

HI0805R800R-00_8

PC155

PC155 10U/25V_1206

10U/25V_1206

PR186

0.03_3720

6251LR

1 2

Rev. B

CV-SET <32>

CHARGER (ISL6251A)

1

PQ43

PQ43 FDD6685

FDD6685

PR187

PC122

PC122 2200P/50V_6

2200P/50V_6

DMN601K-7

VIN

PC161

2200P/50V_6

PROJECT : ZY2/ZY6

Quanta Computer Inc.

33K_6

1

PQ44

2

PC162 10U/25V_1206PC162 10U/25V_1206

10U/25V_1206

1

3

1

PC163

PR188

10K_6

33 40Tuesday, April 08, 2008

BAT-V

43

PC160

PC160 .01U/50V_6

.01U/50V_6

of

1ACustom

5

MAIND

SUSD

+5VPCU

VIN

+

PC139

PC139 100U/25V_6X7.7

100U/25V_6X7.7

PC76 *330U/6.3V_7343

PC144

PC144 10U/25V_1206

10U/25V_1206

D D

C C

B B

PC117

0.1U/50V_6

+5VPCU

PC148 330U/6.3V_6X5.7

+

VIN

PR179

PR179 1M_6

1M_6

MAIND <37,39>

SUSD <39>

PC120

PC120 2200P/50V_6

2200P/50V_6

PR128

PC151 0.1U/50V_6PC151 0.1U/50V_6

*0_4

PR129

PR129 0_4

0_4

+15V

PR180

PR180 1M_6

1M_6

PC123

PC123 *10U/25V_1206

*10U/25V_1206

1 2

+5VPCU

578

SYS_SHDN#<3,38>

PC128

PC128 10U/25V_1206

10U/25V_1206

PL11

2R2UH-5.8mR

PC137

*2200P/50V_6

FDS8878

PR175

*2.2_6

+15V

PQ33

1 2

4

1 2

PR124 0_4PR124 0_4

578

3 6

241

5V_LX

578

PQ34

PQ34 FDS6690AS

FDS6690AS

3 6

241

PR116 22_8PR116 22_8

3V5V_EN

5V_DH

5V_DL

+15V_ALWP

+5VPCU

VL

12

PC72

0.1U/50V_6

PR126

PR126 39K/F_4

39K/F_4

1 2

PR125 178K/F_6PR125 178K/F_6

0.1U/50V_6

2

1

2

1

PC73

0.1U/50V_6

PC86

PR136

PR136 390K_4

390K_4

PR138

PR138 150K_4

150K_4

0.1U/50V_6

3

PD17

PD17 1PS302

1PS302

3

PD18

PD18 1PS302

1PS302

1 2

+5VPCU

DDPWRGD_R

3V5V_EN

1 2

PC84

PR113

PR113 *200K_4

*200K_4

PC92

0.1U/50V_6

REFIN2

PR134

PR134 1/F_6

1/F_6

PC85

0.1U/50V_6

3

9 10 11 12 13 14 15 16 37 36

PC94

*.01U/16V_4

PR141

PR141 *0_6

*0_6

BYP OUT1 FB1 ILIM1 PGOOD1 EN1 DH1 LX1 PAD PAD

PAD33PAD34PAD

35

VL

PC93

1U/16V_6

+3VPCU

DDPWRGD_R

VL

PC89

4.7U/10V_8

1 2

PR147

0_4

1 2

6

5

8

7

3

4

NC

VIN

LDO

ONLDO

LDOREFIN

PU13

ISL6237

BST117DL118PVCC19NC20GND21PGND22DL223BST2

PR118 *0_6PR118 *0_6

12

PR117

PR117 *39K_4

*39K_4

1

TON2VCC

24

PR123

PR123 10K/F_6

10K/F_6

PC99

0.1U/50V_6

REF

REFIN2

ILIM2 OUT2

SKIP#

PGOOD2

EN2 DH2

PR140

PR140 0_6

0_6

1 2

PR130 0_4PR130 0_4

PC96

PC96 1U/16V_6

1U/16V_6

Rev. C for Margin TEST

12

*0_4

*0_4 PR203

PR203

REFIN2

32 31

1 2

30

SKIP

29

DDPWRGD_R

28

3V5V_EN

27 26 25

LX2

PC100

0.1U/50V_6

PR148

PR148 1/F_6

1/F_6

1 2

REFIN2

SYS_HWPG <32>

PR142

PR142 0_4

0_4

1 2

PR153

PR153 196K/F_6

196K/F_6

2

578

3V_DH

3 6

241

3V_LX

578

3 6

241

FDS6690AS

3V_DL

SKIP REF

PR155 *0_6PR155 *0_6

PR152 0_6PR152 0_6

+3VPCU

PQ29

PQ28

PQ28 FDS8878

FDS8878

PC118

0.1U/50V_6

2R2UH-5.8mR

12

PR166

PR166 *2.2_6

*2.2_6

PC115

PC115 *2200P/50V_6

*2200P/50V_6

SUSD

PL9

PC119

PC119 2200P50V_4

2200P50V_4

PR154

PR154 0_6

0_6

PR150

PR150 *0_6

*0_6

+3VPCU

3

PC116

PC116 10U/25V_1206

10U/25V_1206

+3VPCU

65241

PQ36

PQ36 FDC653N_NL

FDC653N_NL

1

PC126

0.1U/50V_6

VIN

+3VPCU

+

PC121

PC121 330U/6.3V_6X5.7

330U/6.3V_6X5.7

S5D

3

S5_ON<32,39>

A A

2

PQ38

DTC144EU

2

PR176

PR176 1M_6

1M_6

1 3

5

1

PQ39

PQ39 DMN601K-7

DMN601K-7

PQ40

PQ40 FDS8884

FDS8884

3 6

241

+5V_S5

MAIND

4

578

3 6

241

PC182

PC182 1U/25V_6

1U/25V_6

PQ24

PQ24 FDS8884

FDS8884

578

MAIND

PQ30

PQ30 FDS8884

FDS8884

3 6

241

+5V

+3V

S5D

Rev. B for EMI

3

65241

PQ37

3

2

PQ37 FDC653N_NL

FDC653N_NL

+3V_S5

Quanta Computer Inc.

PROJECT : ZY2 / ZY6

Size Document Number Rev

Date: Sheet

PROJECT : ZY2 / ZY6

SYSTEM 5V/3V (ISL6237)

1

+3VSUS

1A

of

34 40Tuesday, April 08, 2008

1A

5

4

3

2

1

+3VPCU +3VPCU

PR24

+5V_S5

0.1U/50V_6

1 2

PSI#_1PSI#

PGD_IN

PC45

12

0.022U/50V_6

VR_ON

DPRSLPVR

10n/X7R/16V_4

Rev:C Change

PC38

PC33

PC40

PR24 *0_6

*0_6

1 2

21

49

37

38

39

40

41

42

43

44

45

46

47

13

12

11

10

10/F_6

2

3

4

5

6

7

9

VIN

PR46

12

22

VCC

GND

GND_T

PSI#

PGD_IN

RBIAS

VR_TT#

NTC

SOFT

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VR_ON

DPRSLPVR

DPRSTP#

CLK_EN#

VDIFF

FB2

FB

COMP

VW

4

20

VIN

Rev:C Change

RTN

15

12

PR25

PR25 *0_6

*0_6

12

PR60

PR60 10_4

10_4

12

PC39

0.1U/50V_6

PU8

ISL6262A

VSEN

DROOP

14

16

PR54

3.48K/F_4

Rev:C Change

PC37 180P/50V_4PC37 180P/50V_4

PC41

.01U/16V_4

1 2

PR59 0_4PR59 0_4

PR57 0_4PR57 0_4

+3V

48

3V3

UGATE1

BOOT1

PHASE1

LGATE1

PGND1

ISEN1

PVCC

UGATE2

BOOT2

PHASE2

LGATE2

PGND2

ISEN2

OCSET

VSUM

1

PGOOD

NC

VO

DFB

17

12

PR26

PR26 *0_6

*0_6

H_VID0H_VID3 H_VID2H_VID5 H_VID4 H_VID1

PR63

1.91K/F_4

35

PR44 2.2_6PR44 2.2_6

36

1 2

0.22u/25V_8

34

32

33

24

31

1 2

4.7U/25V_8

27

PR40 2.2_6PR40 2.2_6

26

1 2

0.22u/25V_8

28

30

29

23

25

8

19

12

18

PR52

PR52 1K/F_4

1K/F_4

ISL6262_VO

Parallel

PR28

PR28 *0_6

*0_6

PC30

PC27

PC26

VSUM

12

PC36 0.22u/10V_6PC36 0.22u/10V_6

PC34

PC34 68N/25V_6

68N/25V_6

12

ISEN1

+5V_S5

12

ISEN2

0.22u/25V_6

PC43 1000P/50V_4PC43 1000P/50V_4

12

PR76 13.3K/F_4PR76 13.3K/F_4

PR51

PR51 11K/F_4

11K/F_4

12

PC35

0.22U/X5R/25V_6

Rev:C Change

DELAY_VR_PWRGOOD <3,6,14,32>

6266A_UG1

6266A_PH1

5

6266A_LG1

4

213

PQ50

*TPCA8019-H

12

PC29

0.22u/25V_6

6266A_UG2

6266A_LG2

12

PC31

PR47

2.7K/F_4

PR193

PR193 10K _6 NTC

10K _6 NTC

Panasonic ERT-J1VR103J

Close to Phase 1 Inductor

VCCSENSE <4>

VSSSENSE <4>

3

6266A_LG1

6266A_PH2

4

PQ12

TPCA8023-H

4

PQ48

TPCA8019-H

VSUM

ISEN2

4

PQ14

TPCA8023-H

4

PQ47

TPCA8019-H

VSUM

ISEN1

5

213

5

213

PR36 3.65K/F_6PR36 3.65K/F_6

PR35 10K/F_6PR35 10K/F_6

PR38 1/F_6PR38 1/F_6

PR37 *0_6PR37 *0_6

5

213

5

213

PR50 3.65K/F_6PR50 3.65K/F_6

PR48 10K/F_6PR48 10K/F_6

PR56 1/F_6PR56 1/F_6

PR58 *0_6PR58 *0_6

PR21

PR20

PR20 *0_6

*0_6

D D

H_VID6

12

PR80 4.99K/F_6PR80 4.99K/F_6

PC52

0.1U/50V_6

PSI#<3>

PR82 0_8PR82 0_8

PR21 *0_6

*0_6

PGD_INPWR_MON

12

PSI#

1U/25V_8

10/F_6

PC32

PR42

PR22

PR22 *0_6

*0_6

Close to Phase 1 Inductor

Throttling temp.

+3V_S5

C C

*10K/F_4

H_PROCHOT#<3>

Panasonic ERT-J0EV474J

PSI#_1

PR69

PR69 *0_6

*0_6

DPRSLPVR

B B

VR_ON

PR198

PR198 10K/F_4

10K/F_4

VR_PWRGD_CK410#<14>

Rev. B

A A

5

105 degree C

VR_ON

PR64

PR194 470K_4 NTCPR194 470K_4 NTC

PC51

1 2

.01U/16V_4

H_VID0<4>

H_VID1<4>

H_VID2<4>

H_VID3<4>

H_VID4<4>

H_VID5<4>

H_VID6<4>

VRON<32>

PM_DPRSLPVR<6,14>

ICH_DPRSTP#<3,6,12>

PR78

255/F_4

Rev:C Change

PR81 97.6K/F_4PR81 97.6K/F_4

PC49

12

220P/NPO/50V_4

Rev:C Change

PR79 4.02K/F_4PR79 4.02K/F_4

PR87 0_4PR87 0_4

PR86 499/F_4PR86 499/F_4

PR84 0_4PR84 0_4

PR83 0_4PR83 0_4

PR67 1K/F_4PR67 1K/F_4

1000P/50V_6

Rev:C Change

PR66 0_4PR66 0_4

PR65 *0_4PR65 *0_4

PR68 147K/F_6PR68 147K/F_6

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

CLKEN#

1 2

PC44

PC50 470P/X7R/50V_4PC50 470P/X7R/50V_4

PR62 1K/F_4PR62 1K/F_4

12

Rev:C Change

PR70 6.81K/F_4PR70 6.81K/F_4

Rev:C Change

1 2

PC42 1000P/50V_6PC42 1000P/50V_6

10n/X7R/16V_4

Rev:C Change

12

PR192

2.2_6

PC173

PC173 2200P/100V_6

2200P/100V_6

10U/25V_1206

6266A_LG2

PC19

2200P/50V_6

12

PC25

4

PQ51

*TPCA8019-H

10U/25V_1206

5

213

2

PC24

PC28

12

10U/25V_1206

12

PR191

2.2_6

PC172

PC172 2200P/100V_6

2200P/100V_6

12

PC21

0.1U/50V_6

PR32

PR32 0_6

0_6

PC20

PL19 0.36uHPL19 0.36uH

1 2

3

12

PL18 0.36uHPL18 0.36uH

1 2

3

PR49

PR49 0_6

0_6

12

PC17

0.1U/50V_6

VCC_CORE

PC174

PC174 *560U/2V_7

*560U/2V_7

4

+

PR33

PR33 0_6

0_6

PC22

PC22 2200P/50V_6

2200P/50V_6

4

PR55

PR55 0_6

0_6

Size Document Number Rev

Date: Sheet

+

PC15

330U/2V_7343

VIN

+

PC18

*560U/2V_7

CPU CORE(ISL6266)

+

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 / ZY6

PROJECT : ZY2 / ZY6

1

+

PC14

330U/2V_7343

PC171

PC171 100U/25V_6X7.7

100U/25V_6X7.7

35 40Tuesday, April 08, 2008

VIN

1ACustom

of

1

A A

2

3

4

5

R2

R3

VIN

PR73

4.02K/F_6

PR74

PR74 10K/F_6

10K/F_6

OCP=14A

PC47

PC47 *33P/50V_6

*33P/50V_6

Rev:B ,Remove it.

+1.05V

+5V_S5

PR71 10_6PR71 10_6

PC57

PU9

BOOT

UGATE

PHASE

VDDP

LGATE

PGND

TPAD

21

PC57

*.1U/50V_6

OC

PR88

PR88 0_6

0_6

13

12

11

10

9

8

7

17

PR93 3.24K/F_6PR93 3.24K/F_6

Rds*OCP=RILIM*20uA AO1412 Rds=4.6mOhm 14A OCP --- R1=3.24K(CS23243F930)

PR72

PR72 1M/F_6

PC53

12

1M/F_6

PC55

.01U/50V_6

15

EN/DEM

16

TON

1

VOUT

2

VDD

RT8202

3

FB

4

PGOOD

6

GND

5

NC

12

14

NC

GND18GND19GND20GND

B B

MAINON<32,37,38,39>

HWPG_1.05V<32>

C C

PR85 47K_6PR85 47K_6

+3V

PR75

PR75 *10K/F_6

*10K/F_6

PC46

1U/16V_6

PC54

0.1U/50V_6

*1000P/50V_6

PD13

PD13 RB500V-40

RB500V-40

12

PC56

PC56 .1U/50V_8

.1U/50V_8

UGATE-1.05V

PHASE-1.05V

R1

Rev. B

PC59

4.7U/10V_8

LGATE-1.05V

4

PQ46

TPCA8023-H

4

PQ45

TPCA8019-H

5

PC170

PC168

0.1U/50V_6

213

1R5UH-3.9mR

5

PR190

2.2_6

213

1 2

PC167

2200P/50V_6

0.1U/50V_6

Rev:B Change footprint

PL17

+

PC165

560U/2.5V_6X5.7

1.05V_FB

PC170

10U/25V_1206

12

PC166

10U/10V_8

VOUT=(1+R2/R3)*0.75

PC169

10U/25V_1206

TON=3.85p*RTON*Vout/(Vin-0.5)

Frequency=Vout/(Vin*TON)

D D

Quanta Computer Inc.

PROJECT : ZY2 / ZY6

Size Document Number Rev

VTT 1.05V (RT8202)

Date: Sheet

1

2

3

4

Date: Sheet

PROJECT : ZY2 / ZY6

36 40Tuesday, April 08, 2008

5

1A

of

5

D D

4

3

2

1

PC147

PC147 10U/10V_8

10U/10V_8

+VDR_SUS

VIN

65241

PQ25

D3@FDC653N_NL

+VDR_SUS

+1.5V

+VDR_SUS

PC88

10U/10V_1206

+VDR_VTT

PC87

PC91

10U/10V_8

C C

+VDR_VREF

PR135

0_6

PC87 10U/10V_8

10U/10V_8

PC90

0.033U/50V_6

5VIN

PR149

PR149 *0_6

*0_6

R3

DIS_MODE

+VDR_SUS

PR144 *0_6PR144 *0_6

PR137 0_6PR137 0_6

R2

B B

DDR2(1.8V) DDR3(1.5V)

76.8K

R1

CS37683F927

R2

CS41103F910

110K

CS37503F919

CS37683F927

75K

76.8K

R1

R1=(100*Vout-R2)K

PU14

PU14 TPS51116

TPS51116

1

VLDOIN

2

VTT

4

VTTSNS

5

GND

3

VTTGND

6

MODE

7

VTTREF

8

COMP

9

VDDSNS

10

VDDQSET

+5VPCU

PR139

SP@110K/F_6

PR143

SP@76.8K/F_6

Rev. B

DRVH

VBST

LL

DRVL

PGND

S3

S5

V5IN

PGOOD

GND21GND22GND23GND24GND25GND26GND

CS

27

PC104

*1000P/50V_6

PR165

0_6

PC95

PC95 *33P/50V_6

*33P/50V_6

S3_1.8V S5_1.8V

5VIN

19

20

18

17

16

S3_1.8VDIS_MODE

11

S5_1.8V

12

5VIN

14

13

15

R4

12

PC108

4.7U/6.3V_6

PC102

PC102 *.1U/50V_6

*.1U/50V_6

PC106 0.1U/50V_6PC106 0.1U/50V_6

PR151 0_6PR151 0_6

PR163 0_6PR163 0_6

+3VPCU

PR164

PR164 SP@100K/F_6

SP@100K/F_6

PR162 5.62K/F_6PR162 5.62K/F_6

Rev: B D3@ change to 2K D2@ 100K

PC105

PC105 *.1U/50V_6

*.1U/50V_6

MAINON <32,36,38,39>

SUSON <32,39>

PR200 *10K/F_6PR200 *10K/F_6

+3VPCU

Rev. B

HWPG_VDR <6,32>

MAIND<34,39>

if tune Vout R3 un-mount, R1 and R2 mount

5

4

213

PQ32

TPCA8023-H

5

4

213

PQ35

TPCA8019-H

DDR3 -- NC

+VDR_SUS

578

PQ23

PQ23 ED2@FDS8884

ED2@FDS8884

3 6

241

+1.8V

Rev:B Change footprint

Rev:C 2.2/F_6 change to 1/F_6

PR170

1/F_6

PC129

PC129 1000P/50V_6

1000P/50V_6

Rev:C 2200P change to 1000p

PR108

PR108 ID2@0_8

ID2@0_8

PL12

1.0UH-3.0mR

PC133

PC133 2200P/50V_6

2200P/50V_6

PC132

PC132 10U/25V_1206

10U/25V_1206

560U/2.5V_6X5.7

DDR2 --

PC150

+

PC124

PC124 10U/25V_1206

10U/25V_1206

OCP=14.25A DDR3 -- OCP=13.94A (10u*R4)/Rdson+Delta_I/2=Iocp

DDR2 -- NC

MAIND<34,39>

3

A A

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 / ZY6

Size Document Number Rev

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : ZY2 / ZY6

VDR (TPS51116)

1A

of

37 40Tuesday, April 08, 2008

1

2

3

4

5

PR172

A A

PR156

PR156 ED3@1M/F_6

ED3@1M/F_6

MAINON<32,36,37,39>

HWPG_1.8V<32,39>

B B

PR145 ED3@47K_6PR145 ED3@47K_6

+3V

PR167

ED3@10K/F_6

PR146

*10K/F_6

ED3@1U/16V_6

PC98

PC98 ED3@0.1U/50V_6

ED3@0.1U/50V_6

PC135

PC101

*1000P/50V_6

12

PC97

12

ED3@.01U/50V_6

15

16

1

2

3

4

6

5

14

ED3@10_6

PU16

PU16 ED3@RT8202

ED3@RT8202

EN/DEM

TON

VOUT

VDD

FB

PGOOD

GND

NC

BOOT

UGATE

PHASE

VDDP

LGATE

PGND

TPAD

GND18GND19GND20GND

21

PC131

*.1U/50V_6

OC

13

12

11

10

9

8

7

17

+5VPCU

LGATE-1.8V

Rev. B

PD19

PD19 ED3@RB500V-40

ED3@RB500V-40

12

PC130

ED3@4.7U/10V_8

PR174

PR174 ED3@0_6

ED3@0_6

PR171 ED3@3.01K/F_6PR171 ED3@3.01K/F_6

ED3@4.7U/10V_8

PC138

PC138 ED3@.1U/50V_8

ED3@.1U/50V_8

UGATE-1.8V

PHASE-1.8V

R1

LGATE-1.8V

Rds*OCP=R1*20uA

4A OCP --- R1=3.01K FDS6690AS Rds=15mOhm

PC134

ED3@0.1U/50V_6

PL10

+

PC140

ED3@560U/2.5V_6X5.7

ED3@0.1U/50V_6

12

PC146

ED3@10U/10V_8

VOUT=(1+R2/R3)*0.75

1.8V_FB

Rev.C for EMI

1

2

3

4

D1

D1 S1/D2

D1

D1 S1/D2

G2

S2

G2

S2

PQ31

ED3@FDS6900AS

G1

8

7

6

5

UGATE-1.8V

Rev:C Change footprint

ED3@2.5UH_7.5A

PR173

*2.2_6

1 2

PC136

*2200P/50V_6

VIN

PC125

ED3@10U/25V_1206

PC183

ED3@.1U/50V_8

R2

R3

PR169

ED3@14K/F_6

PR168

ED3@10K/F_6

OCP: 4A

PC127

ED3@33P/50V_6

3.5A

+1.8V

TON=3.85p*RTON*Vout/(Vin-0.5)

Frequency=Vout/(Vin*TON)

thermal protection --0928

VINVLVL VIN

PD22

PD22 RB500V-40

C C

Thermistor_CTRL<31>

VL

PR11

PR11 10K/F_6

10K/F_6

D D

PR12

PR12 1M/F_6

1M/F_6

1

PR13

PR13 1K/F_4

1K/F_4

PR17

PR17 200K/F_4

200K/F_4

2.469V

PR16

PR16 196K/F_4

196K/F_4

4.95V

2

RB500V-40

84

3

+

2

-

PU7B

5

+

6

-

LM393

Rev. B

SYS_SHDN# <3,34>

PR15

PR15 200K/_6

PD10

RB500V-40

200K/_6

PC13

0.1U/50V_6

+3VPCU

PR8

PR8 100K/F_6

100K/F_6

3

2

1

NC_TEMP <32>

PQ8

PQ8 DMN601K-7

DMN601K-7

PU7A

PU7A LM393

LM393

1

7

PC12

0.1U/50V_6

Rev. B

For EC control thermal protection (output 3.3V)

3

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 / ZY6

Size Document Number Rev

1.8V (RT8202)

Date: Sheet

4

Date: Sheet

PROJECT : ZY2 / ZY6

of

38 40Tuesday, April 08, 2008

5

1A

5

4

3

2

1

DDR3 -- NC

for DDR3 and UMA

+3VSUS

D D

+5VPCU

PU12

4

2

3 8 9

PU12

VPP

VEN

VIN GND GND

1

PGOOD

6

VO

5

NC

ADJ

ID3@RT9025-25PSP

7

+3VPCU

MAINON

PC80

ID3@10U/4V_8

PC83 ID3@0.1U/50V_6PC83 ID3@0.1U/50V_6

PR107 ID3@10K/F_6PR107 ID3@10K/F_6

PC75

ID3@0.1U/50V_6

PC74

ID3@0.1U/50V_6

0.8V

Vout =0.8(1+R1/R2) =1.8V

C C

R1

R2

PR106

ID3@100K_4

PR109

ID3@30.1K/F_6

ID3@10U/10V_8

PR105

ID3@24K/F_6

PC149

HWPG_1.8V <32,38>

+1.8V

0.5A

PC184

ID3@.1U/50V_8

Rev.C for EMI

MAINON<32,36,37,38>

PC113

D2@10U/6.3V_8

PR157 D2@0_6PR157 D2@0_6

12

PR159

100K_4

Rev. B

100K_4

Vout =0.8(1+R1/R2) =1.5V

PC112

D2@0.1U/10V_4

+5V_S5

PC103

*.1U/50V_6

+VDR_SUS

PC110

D2@1U/10V_4

1 2

PU15

5

VIN

9

VIN1

8

EN

6

VCNTL

R2

PR158

D2@100K/F_4

7

POK

1

GND

3

VOUT

4

VOUT

FB

D2@APL5913

2

PR160 D2@88.7K/F_4PR160 D2@88.7K/F_4

R1

1 2

PC107 D2@47NF/16V_4PC107 D2@47NF/16V_4

+3V_S5

12

PR161

100K_4

HWPG_1.5V <32>

+1.5V

PC111

10U/6.3V_8

+1.5V <4,10,12,13,15,23,25,29,37>

2.6A

PC109

PC114

10U/6.3V_8

PC109

0.1U/10V_4

1

6

5

4

2

3 8 9

+3VSUS

PR89

E@100K_4

HWPG_2.5V <32>

+2.5V

0.25A

PR91

R1

PR91

E@73.2K/F_6

PC61

E@10U/10V_8

0.8V

PR92

R2

E@34K/F_6

+3VPCU

PR178

PR178 I@100K_4

I@RT9025-25PSP

PU17

VPP

VEN

VIN GND GND

PGOOD

ADJ

7

VO

NC

HWPG_1.5VS5

1

6

5

R1

0.8V

R2

Size Document Number Rev

Discharge (2.5V/1.5V)

Date: Sheet

I@100K_4

PR182

I@88.7K/F_4

PR181

I@100K/F_4

Quanta Computer Inc.

Quanta Computer Inc. PROJECT : ZY2 / ZY6

PROJECT : ZY2 / ZY6

PC152

I@10u/10V_8

1

+1.5V_S5

0.3A

39 40Tuesday, April 08, 2008

1A

of

REV:B change to E@

VIN

+VDR_VREF

PR31

PR31 1M_6

1M_6

PR30

PR30 1M_6

1M_6

SUSON<32,37>

B B

2

PQ15

DTC144EU

1 3

2

3

1

PR23

PR23 22_8

22_8

PQ10

PQ10 DMN601K-7

DMN601K-7

+VDR_SUS

3

2

1

PR27

PR27 22_8

22_8

PQ11

PQ11 DMN601K-7

DMN601K-7

2

+3VSUS +15V

PR29

PR29 22_8

22_8

3

2

PQ13

PQ13 DMN601K-7

DMN601K-7

1

PR34

PR34 1M_6

1M_6

3

1

SUSDSUS_ON_G

PQ16

PQ16 DMN601K-7

DMN601K-7

PC23

PC23 *2200P/50V_4

*2200P/50V_4

SUSD <34>

PC63 E@0.1U/50V_6PC63 E@0.1U/50V_6

MAINON

PR90 E@10K/F_6PR90 E@10K/F_6

+3VSUS

PC62

E@10U/4V_8

Vout =0.8(1+R1/R2) =2.5V

PC60

E@0.1U/50V_6

+5VPCU

PC58

PC58 *.1U/50V_6

*.1U/50V_6

4

2

3 8 9

E@RT9025-25PSP

PU10

PGOOD

VPP

VEN

VIN GND GND

7

VO

NC

ADJ

REV:B change to I@

+5VPCU

PC145 I@0.1U/50V_6PC145 I@0.1U/50V_6

S5_ON<32,34>

VIN

PR43

PR43 1M_6

1M_6

A A

MAINON<32,36,37,38>

2

PQ18

DTC144EU

1 3

PR41

PR41 1M_6

1M_6

PR39

PR39 22_8

22_8

3

2

PQ17

PQ17 DMN601K-7

DMN601K-7

1

PR45

PR45 22_8

22_8

3

2

PQ19

PQ19 DMN601K-7

DMN601K-7

1

PR53

PR53 22_8

22_8

3

2

PQ20

PQ20 DMN601K-7

DMN601K-7

1

3

2

1

PR61

PR61 E@22_8

E@22_8

2

PQ21

E@DMN601K-7

+15V+5V+3V +VDR_VTT +1.8V

3

1

PR77

PR77 1M_6

1M_6

MAINDMAINON_ON_G

PQ22

PQ22 DMN601K-7

DMN601K-7

PC48

PC48 *2200P/50V_4

*2200P/50V_4

MAIND <34,37>

PR199

*10K/F_6

Rev. B

+3VPCU

I@10U/4V_8

PR177 I@10K/F_6PR177 I@10K/F_6

PC143

PC141

I@0.1U/50V_6

PC142

PC142 I@0.1U/50V_6

I@0.1U/50V_6

Vout =0.8(1+R1/R2) =1.5V

REV:B change to E@

5

4

3

2

5

Power Tree Table

1

AC

System

2

ISL6262A P.36

Charger

DC

D D

ISL6251A P.34

3

ISL6237 P.35

4

VCC_CORE

VRON enable

+5VPCU

AC/DC Insert enable

+3VPCU

AC/DC Insert enable

7

FDS8884 P.35

8

FDS8884 P.35

9

FDS8884 P.35

3

+5V_S5

S5_ON enable

+5V

MAINON enable

+3V

MAINON enable

2

1

DDR2 --> 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 16

DDR3 & UMA --> 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 14, 15, 16

DDR3 & MXM --> 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 16

15

RT9025-25PSP P.40

+1.8V

MAINON enable

4

RT8202 P.37

5

C C

Power Distribution List

B B

Power

VCC_CORE

+3VPCU RTC, HALL SENSOR, KB, TP/FP/LED /B, Power /B, Kill SW, EC, ID, SPI Flash, CIR +1.5V CPU, GMCH, ICH9M, Mini Card, New Card +VDR_SUS GMCH, DDR +VDR_VREF GMCH, DDR +VDR_VTT DDR +1.05V CPU, CLK, Thermal Trip, GMCH, ICH8M +5V_S5 ICH8M, G-SENSOR, Felica, USB/eSATA +5V

A A

+3V

+3V_S5 ICH8M, Mini Card, RJ45/USB /B, New Card +3VSUS ICH8M, FP +1.8V Cardreader +2.5V MXM

Distribution

CPU ICH8M, RJ45/USB /B, USB/eSATA, Satellite LED, CIR+5VPCU

CPU, ICH8M, VGA, Camera, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, TP/FP/LED /B, EC, Speaker, Headphone CLK, CPU Thermal Monitor, FAN, GMCH, DDR, ICH8M, VGA, LCD/LED Panel, HALL SENSOR, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, Cardreader (OZ129T) Mini Card, KB, TP/FP/LED /B, RJ45/USB /B, Bluetooth, MMB, New Card, PC BEEP, EC, Codec (CX20561), VR, Headphone, MDC

5

TPS51116 P.38

6

RT8202 P.39

+1.05V

MAINON enable

+VDR_VTT

MAINON enable

+VDR_VREF

MAINON enable

+VDR_SUS

SUSON enable

+1.8V

MAINON enable

4

10

FDS653N_NL P.35

11

FDS653N_NL P.35

12

FDS8884 P.38

13

APL5913 P.40 MAINON enable

14

FDS653N_NL P.38

+3V_S5

S5_ON enable

+3VSUS

SUSON enable

+1.8V

MAINON enable

+1.5V

3

16

RT9025-25PSP P.40

+2.5V

MAINON enable

2

+1.8V

MAINON enable

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Power Tree Table

Date: Sheet

PROJECT :

ZY2 & ZY6

40 40Tuesday, April 08, 2008

of

1

of

1A

5

4

3

2

1

Model

ZY2 MB

D D

C C

B B

REV

FIRST RELEASED: E200610-3793 (PCB: )

1A

Page2 : Add R475 ,531 & R532 to avoid active error. (follow CK505 design guideline) Page2 : Swap SRC4 & SRC9, because NEW_CLKREQ# is only to control SRC1 or 4

. Page3 : Add R540 to avoid active error. (CPU Thermal monitor)

Page6 : Follow DDR3 spec R251 change to 10K.

1B

Page18 : POP C282 &C284 and RSVD. C604 for DDR3 PCB boot issue. Page18 : HDA_RST# PIN change from 151 to 134 for customer request. Page18 : Swap Net:TX0 &TX2 (RN15 & RN17) For HDMI no function issue. Page20 : Add R527 ,R528 ,R529 ,R530 ,R539 ,R148 ,R153 ,R152 ,R104 & R105 for vendor request.(HDMI level shifter) Page20 : Change HDMI SW IC ( U9 ) & schematic Page23 : Add R536 ,R542 ,R538 ,RP57 ,R537 customer request.(MINI PCI-E card function) Page25 : add Intel Low Power ECR Solution(Audio) Page28 : Add part for D3 Enhanced (D3E).(cerd reader) Page29 : Add Keyboard LED function for customer request. Page30 : Location :C25 & C23 change to 100U & POP it for customer request.(USB) Page31 : Add D43 for customer request( FOR Dock :CRT _SENSE#) Page31 : CN12 & CN14 change footprint.(K/B & T/P CONN.) Page31 : Add C609 ,C606 & C608.(FOR DOCK : +5V & +5V_S5)

Page19 : change U22 LVDS PWR SW IC to TI for display isuue Page21 : remove 5787 schematic

2A

Page23 : Add C605 ,C70 ,C150 ,C613 &C614 for EMI request Page23 : Change CN27 CONN. & schematic for intel WL burnout issue Page25 :change U13 packing from TQFN to TDFN for vendor request

Page20 : Add

2B

CHANGE LIST

MODEL

ZY2

FROM To

X X 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A

1A 1A 1A 2A 1A 1A 1A 1A 1A 1A 2A 2A 2A 2A 2A 2A 2A 2A 2B 2B 2B 2B 2B 2B 2B 3A

1A 1A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A1A 2A 2A

2A 2A 2A 2A 2A 2A 2B 2B 2B 2B 2B 2B 2B 2B 3A 3A 3A 3A 3A 3A

A A

PROJECT : ZY2

Quanta Computer Inc.

Size Document Number Rev

Change list

Date: Sheet

5

of

41 41Wednesday, April 09, 2008

DOC NO.

1A

4

PART NUMBER:

3

APPROVED BY:PROJECT MODEL : ZY2 DRAWING BY: REVISON:

2

DATE:

2007/ 2/15

3A

1

QUANTA ZY2, ZY6 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual