Quanta ZRL DA0ZRLMB6D0, Aspire 5349, Aspire 5749 Schematic
5
4
3
2
1
VER : 1A
BOM P/N
31ZRLMB0000
31ZRLMB0010
D D
Description
ZRL MB ASSY(UMA,HR,DC)W/O CPU
ZRL MB(UMA,HR,DC,SURGE)W/O CPU
ZRL BLOCK DIAGRAM
CHARGER
ISL88731
3/5V SYS PWR
RT8223M
P27
P28
intel
<MCH Processor>
SandyBridge
DC 35W
DDR III - SODIMM 0
DDR III - SODIMM 1
C C
P14, 15
Dual Channel DDR III
1066 MHz
DDR SYSTEM MEMORY
FDI interface
HDD (SATA)
ODD (SATA)
P20
P20
USB 2.0 * 3
USB1,3,9 P24
SATA0
SATA1
USB 2.0
SATA Gen3
SATA Gen2
USB
rPGA 988
(37.5mm X 37.5mm)
CLK
FDI
FDI
CLK
DMI
DMI
intel
<PCH>
CougarPoint 0.7
PCI-E
X16
P4~P7
X4 DMI interface
5GT/s2.7GT/s
5GT/s
INT_CRT
INT_LVDS
iGFX Interfaces
PCI-E
INT_HDMI
CPU CORE PWR
ISL95835
CPU +1.05V_VTT
RT8238A
DDR3 +1.5_SUS
RT8207A
P29
P30
P31
+VCCSA
RT8241DZ
CRT
LVDS
HDMI
+1.8V
HPA00835RTER
discharger
Thermal protect
P16
P16
P17
P33
P33
P33P32
B B
A A
Bluetooth
USB4 P24
CCD (Camera)
P16USB8
Card Reader
P23USB12
Audio CODEC
REALTEK ALC271X
HP Jack MIC Jack DMIC
P22 P22
5
SPK
P21
P21
Azalia
X'TAL
32.768KHz
HDA
RTC
P9
SPI
Dual SPI ROM
4MB x1 (Basic ME+Braidwood)
SPI ROM
P21
P26
4
mBGA 989
(25mm X 25mm)
Note:
HM65 not support USB 6 & 7
HM65 not support SATA 2 & 3
WPCE791/FLASH
P9
NPCE971
Touch Pad
P25
P8~P13
LPC
P26
Keyboard
P25
PCI-Express Gen2
5GT/s
X'TAL
25MHz
Fan Driver
(DA Type)
3
P25
PCIE-6
USB-13
PCIE-1
MINI CARD
WLAN
P19
ATHEROS AR8158
10/100 LAN
2
X'TAL
25MHz
P18
RJ45
P18
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZRL
ZRL
ZRL
of
of
of
1 34Tuesday, June 21, 2011
1 34Tuesday, June 21, 2011
1 34Tuesday, June 21, 2011
1
1A
1A
1A
1
ZRL power tree
2
3
4
5
6
7
8
+5VPCU
MDV1660
RT8223M
A A
VINVIN
PU4
MDV1660
+3VPCU
AO3404
MDV1660
ADAPTER
Smart
Charger
ISL88731C
B B
BATTERY
PU2
+1.5V_SUS
HPA00835RTER
PU7
AO3404
RT8207L
PU9
+5VPCU
<Alway ON>
3A
+5V_S5
<S5_ON>
2.5A
+5V
<MAIND>
+3VPCU
<Alway ON>
0.21A
+3V_S5
<S5_ON>
3.65A
+3V
<MAIND>
1.75A
+1.8V
<MAINON>
+1.5V_SUS
<SUSON>
+1.5V
<MAINON>
+0.75V_DDR_VTT
<MAINON>
+SMDDR_VREF
<SUSON>
13A
0.38A
0.75A
0.38A
RT8238A
PU8
Power States
VOLTAGE
POWER PLANE
VIN
C C
+VCCRTC
+3VPCU
+5VPCU
+15V
+3V_S5
+5V_S5
+5V
+1.5VSUS
+0.75V_DDR_VTT
+VGFX_AXG S0GFX_ONInternal GPU POWER
+1.8V
+1.5V
+1.1V_VTT S0
+1.05V
+VCC_CORE
D D
LCDVCC
+5V_GPU
+GPU_CORE
+GPU_IO PG_GPUIO_EN+0.9V~+1.1V
1
+1.05V or +1.1V
DESCRIPTION
+10V~+19V
+3V~+3.3V
RTC POWER
+3.3V
EC POWER
CHARGE POWER
+5V
+15V
CHARGE PUMP POWER
LAN/BT/CIR POWER
+3.3V
USB POWER
+5V
+5V
HDD/ODD/Codec/TP/CRT/HDMI POWER
+3.3V
PCH/GPU/Peripheral component POWER+3V
+1.5V
CPU/SODIMM CORE POWER
+0.75V
SODIMM Termination POWER
variation
+1.8V
CPU/PCH/Braidwood POWER
+1.5V
MINI CARD/NEW CARD POWER
+1.05V
PCH CORE POWER MAINON
CPU CORE POWER
variation
+3.3V
LCD POWER
+5V Discrete enableSWITCHABLE PWM IC POWER
2
CONTROL
SIGNAL
ALWAYSMAIN POWER
ALWAYS
ALWAYS
ALWAYS
S5_ON
S5_ON
MAINON
MAINON
SUSON
MAINON
MAINON
MAINON
MAINONCPU VTT POWER
VRON
LVDS_VDDEN
dGPU_PWR_EN#
PG_1.5V_EN+1.5V+1.5V_GPU
+1.5V_GPU+1.8V+1.8V_GPU
PG_1V_EN+1V+1V Discrete enableDP/PEG POWER
3
ACTIVE IN
ALWAYS
ALWAYS
ALWAYS
ALWAYS
ALWAYSALWAYS
S0-S5
S0-S5
S0
S0
S0-S3
S0
S0
S0
S0
S0
S0
Discrete enable+3V_DGPU CORE POWER+0.9V~+1.1V
Discrete enableGPU I/O POWER
Discrete enableVRAM CORE POWER
Discrete enableGPU_CRE/LVDS/PLL POWER
RT8241DZ
PU6
ISL95835HRTZ-T
PU5
4
5
6
+1.05V_S5
<S5_ON>
+VCCSA
<HWPG_VTT>
+VCC_GFX
<VRON>
+VCC_CORE
<VRON>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
PWR Status & GPU PWR CRL & THRM
PWR Status & GPU PWR CRL & THRM
PWR Status & GPU PWR CRL & THRM
Date: Sheet
Date: Sheet
Date: Sheet
7
14A
6A
33A
53A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZRL
PROJECT :
ZRL
PROJECT :
ZRL
of
of
of
2 34Tuesday, June 21, 2011
2 34Tuesday, June 21, 2011
2 34Tuesday, June 21, 2011
8
1A
1A
1A
5
4
3
2
1
03
D D
+3V_S5
+3V_S5
+3V_GPU
2.2KΩ
2.2KΩ
SMB_ME0_CLK
SMB_ME0_DAT
+3V_S5
+3V_S5
C C
+3V_S5
+3VPCU
+3VPCU
G
D
NMOS
G
D
NMOS
+3V_GPU +3V_GPU
I2CS_SCL
S
I2CS_SDA
S
2.2KΩ2.2KΩ
N12P-GE
2.2KΩ
2.2KΩ
2.2KΩ
+3V_S5
2.2KΩ
S
+3V_S5
G
D S
NMOS
G
D
NMOS
G
NMOS
G
NMOS
SMB_RUN_CLK
SMB_RUN_DAT
S
intel
<PCH>
CougarPoint 0.7
mBGA 989
(25mm X
25mm)
B B
A A
SMB_ME1_CLK
+3V_S5
SMB_PCH_CLK
SMB_PCH_DAT
6.8KΩ
DS
MBCLK
6.8KΩ
EC
ITE 8518
+3V
4.7KΩ
MBDATASMB_ME1_DAT
+3V
Slave ADDRESS :A0H Slave ADDRESS :A4H
4.7KΩ
DDR3 DIMM-0-STD
(5.2H)
VREF DQ0
M2 Solution
DDR3 DIMM-1-STD
(9.2H)
VREF DQ1
M2 Solution
D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
5
4
3
2
Date: Sheet
PROJECT :
SMBus Address
SMBus Address
SMBus Address
ZRL
ZRL
ZRL
3 34
3 34
1
3 34
1A
1A
1A
of
5
4
3
2
1
Sandy Bridge Processor (DMI,PEG,FDI)
U17A
U17A
DMI_TXN0[8]
DMI_TXN1[8]
D D
C C
B B
DMI_TXN2[8]
DMI_TXN3[8]
DMI_TXP0[8]
DMI_TXP1[8]
DMI_TXP2[8]
DMI_TXP3[8]
DMI_RXN0[8]
DMI_RXN1[8]
DMI_RXN2[8]
DMI_RXN3[8]
DMI_RXP0[8]
DMI_RXP1[8]
DMI_RXP2[8]
DMI_RXP3[8]
FDI_TXN0[8]
FDI_TXN1[8]
FDI_TXN2[8]
FDI_TXN3[8]
FDI_TXN4[8]
FDI_TXN5[8]
FDI_TXN6[8]
FDI_TXN7[8]
FDI_TXP0[8]
FDI_TXP1[8]
FDI_TXP2[8]
FDI_TXP3[8]
FDI_TXP4[8]
FDI_TXP5[8]
FDI_TXP6[8]
FDI_TXP7[8]
FDI_FSYNC0[8]
FDI_FSYNC1[8]
FDI_INT[8]
FDI_LSYNC0[8]
FDI_LSYNC1[8]
eDP_COMP
INT_eDP_HPD_Q
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
CPU-989P-rPGA
CPU-989P-rPGA
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
+1.05V_VTT
H_PROCHOT#[26,29]
H_PWRGOOD[11]
R295 75_4R295 75_4
CPU_PLTRST#
H_SNB_IVB#[9]
SKTOCC#
TP75TP75
TP_CATERR#
TP76TP76
EC_PECI[11,26]
R23 56_4R23 56_4
PM_THRMTRIP#[11]
PM_SYNC[8]
R296 43_4R296 43_4
SYS_PWROK[8,26]
PM_DRAM_PWRGD[8]
H_PROCHOT#_R
PM_THRMTRIP#
R13 10K_4R13 10K_4
C17 0.1U/10V_4C17 0.1U/10V_4
PM_DRAM_PWRGD_R
CPU_PLTRST#_R
+3V_S5
U22
U22
2
1
74AHC1G09
74AHC1G09
3 5
C453
C453
0.1U/10V_4
0.1U/10V_4
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
U17B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
CPU-989P-rPGA
CPU-989P-rPGA
PM_DRAM_PWRGD_Q
4
R391 *39_4R391 *39_4
+1.5V_CPU
R393
R393
200/F_4
200/F_4
R392 130/F_4R392 130/F_4
3
Q21 *2N7002DQ21 *2N7002D
2
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
PM_DRAM_PWRGD_R
1
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
MAINON_ON_G [6,33]
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A28
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
TDI
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRST#
PLTRST#[10,18,19,23,26]
CLK_CPU_BCLKP [10]
CLK_CPU_BCLKN [10]
CLK_DPLL_SSCLKP [10]
CLK_DPLL_SSCLKN [10]
CPU_DRAMRST# [5]
R138 140/F_4R138 140/F_4
R369 25.5/F_4R369 25.5/F_4
R383 200/F_4R383 200/F_4
TP78TP78
XDP_DBRST# [8]
U14
U14
1
2
IN
GND3OUT
74LVC1G07GW
74LVC1G07GW
04
+3V_S5
C374
C374
0.1U/10V_4
4
0.1U/10V_4
CPU_PLTRST#
VCC5NC
DP & PEG Compensation
+1.05V_VTT+1.05V_VTT
R322 24.9/F_4R322 24.9/F_4
A A
eDP_COMPIO and ICOMPO signals should
be shorted near balls and routed with
typical impedance <25 mohms
5
R62 24.9/F_4R62 24.9/F_4
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
typical impedance = 43 mohms
PEG_ICOMPO signals should
be routed within 500 mils
typical impedance = 14.5 mohms
PEG_COMPeDP_COMP
4
Processor pull-up(CPU)
+1.05V_VTT
H_PROCHOT#
XDP_TDO
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TCLK
XDP_TRST#
R17 62_4R17 62_4
R47 51_4R47 51_4
R309 51_4R309 51_4
R306 51_4R306 51_4
R44 *51_4R44 *51_4
R310 51_4R310 51_4
R304 51_4R304 51_4
3
Q18
Q18
IMVP_PWRGD[8,29]
PM_THRMTRIP#
3
2
1 3
1
2
R289
R289
1K_4
1K_4
FDV301N
FDV301N
Q17
Q17
MMBT3904
MMBT3904
+1.05V_VTT
SYS_SHDN# [28,33]
2
eDP Hot-plug
HPD disable
INT_eDP_HPD_Q
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Date: Sheet
Date: Sheet of
Date: Sheet of
PROJECT :
Sandy Bridge 1/4
Sandy Bridge 1/4
Sandy Bridge 1/4
1
+1.05V_VTT
ZRL
ZRL
ZRL
4 34
4 34
4 34
R294
R294
10K_4
10K_4
1A
1A
1A
of
5
4
3
2
1
Sandy Bridge Processor (DDR3)
05
U17D
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
U17D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
CPU-989P-rPGA
CPU-989P-rPGA
AE2
SB_CLK[0]
SB_CLK#[0]
SB_CLK#[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
2
AD2
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
R10
SB_CKE[1]
AB2
AA2
T9
AA1
AB1
T10
AD3
SB_CS#[0]
AE3
SB_CS#[1]
AD6
AE6
AE4
SB_ODT[0]
AD4
SB_ODT[1]
AD5
AE5
M_B_DQSN0
D7
M_B_DQSN1
F3
M_B_DQSN2
K6
M_B_DQSN3
N3
M_B_DQSN4
AN5
M_B_DQSN5
AP9
M_B_DQSN6
AK12
M_B_DQSN7
AP15
M_B_DQSP0
C7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Tuesday, June 21, 2011
Date: Sheet of
Tuesday, June 21, 2011
Date: Sheet of
Tuesday, June 21, 2011
Date: Sheet
M_B_DQSP1
G3
M_B_DQSP2
J6
M_B_DQSP3
M3
M_B_DQSP4
AN6
M_B_DQSP5
AP8
M_B_DQSP6
AK11
M_B_DQSP7
AP14
M_B_A0
AA8
M_B_A1
T7
M_B_A2
R7
M_B_A3
T6
M_B_A4
T2
M_B_A5
T4
M_B_A6
T3
M_B_A7
R2
M_B_A8
T5
M_B_A9
R3
M_B_A10
AB7
M_B_A11
R1
M_B_A12
T1
M_B_A13
AB10
M_B_A14
R5
M_B_A15
R4
Sandy Bridge 2/4
Sandy Bridge 2/4
Sandy Bridge 2/4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
M_B_CLKP0 [15]
M_B_CLKN0 [15]
M_B_CKE0 [15]
M_B_CLKP1 [15]
M_B_CLKN1 [15]
M_B_CKE1 [15]
M_B_CS#0 [15]
M_B_CS#1 [15]
M_B_ODT0 [15]
M_B_ODT1 [15]
M_B_DQSN[7:0] [15]
M_B_DQSP[7:0] [15]
M_B_A[15:0] [15]
ZRL
ZRL
ZRL
1
of
5 34
5 34
5 34
1A
1A
1A
U17C
U17C
D D
C C
B B
A A
M_A_DQ[63:0][14]
M_A_BS#0[14]
M_A_BS#1[14]
M_A_BS#2[14]
M_A_CAS#[14]
M_A_RAS#[14]
M_A_WE#[14]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
5
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
AJ5
AJ6
AJ8
AJ9
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
CPU-989P-rPGA
CPU-989P-rPGA
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK#[0]
SA_CLK#[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
RSVD_TP[7]
RSVD_TP[8]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_CLK[0]
SA_CKE[0]
SA_CLK[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
4
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 [14]
M_A_CLKN0 [14]
M_A_CKE0 [14]
M_A_CLKP1 [14]
M_A_CLKN1 [14]
M_A_CKE1 [14]
M_A_CS#0 [14]
M_A_CS#1 [14]
M_A_ODT0 [14]
M_A_ODT1 [14]
R387 1K/F_4R387 1K/F_4
DRAMRST_CNTRL_PCH[10]
M_A_DQSN[7:0] [14]
M_A_DQSP[7:0] [14]
M_A_A[15:0] [14]
+1.5V_SUS
R388
R388
1K/F_4
1K/F_4
CD_DRAMRST#
M_B_DQ[63:0][15]
M_B_BS#0[15]
M_B_BS#1[15]
M_B_BS#2[15]
M_B_CAS#[15]
M_B_RAS#[15]
M_B_WE#[15]
3
3
Q20
Q20
2N7002D
2N7002D
2
C446
C446
0.047U/10V_4
0.047U/10V_4
1
R386
R386
4.99K/F_4
4.99K/F_4
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
CPU_DRAMRST# [4]DDR3_DRAMRST#[14,15]
5
4
3
2
1
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
CPU VTT
+1.05V_VTT
+
+
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
R61 *short_4R61 *short_4
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DATA
R284 100/F_4R284 100/F_4
R285 100/F_4R285 100/F_4
R339 10/F_4R339 10/F_4
R338 10/F_4R338 10/F_4
C96
C96
330u/2V_7343
330u/2V_7343
C419
C419
C424
C424
C93
C93
C415
C415
*22U/6.3V_8
*22U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
SNB 45W:8.5A
Spec
330uF/6mohm x 2
22uF x 12
22uF x 7 (Non-stuff)
+
+
C441
C441
*330U/2V_7343
*330U/2V_7343
C423
C423
C426
C426
10U/6.3V_8
10U/6.3V_8
C106
C106
C105
C105
10U/6.3V_8
10U/6.3V_8
C109
C109
C92
C92
10U/6.3V_8
10U/6.3V_8
C400
C400
*22U/6.3V_8
*22U/6.3V_8
+1.05V_VTT
CPU VCCPL
SNB 45W:1.5A
Spec
330uF/7mohm x 1
10uF x 1
1uF x 2
+VCC_CORE
VCC_SENSE [29]
VSS_SENSE [29]
+1.05V_VTT
VCCP_SENSE [30]
VSSP_SENSE [30]
MAIND[28,31,33]
C425
C425
10U/6.3V_8
10U/6.3V_8
C108
C108
10U/6.3V_8
10U/6.3V_8
C387
C387
*22U/6.3V_8
*22U/6.3V_8
R389 0_8R389 0_8
3
3
C94
C94
10U/6.3V_8
10U/6.3V_8
C107
C107
10U/6.3V_8
10U/6.3V_8
C377
C377
*22U/6.3V_8
*22U/6.3V_8
2
CPU VGT
SNB 45W:21.5A
Spec
470uF/4mohm x 2
22uF x 12
C37
C37
*22U/6.3V_8
*22U/6.3V_8
+VDDR_REF_CPU+SMDDR_VREF
1
Q19
Q19
*2N7002D
*2N7002D
+
+
C81
C81
*330U/2V_7343
*330U/2V_7343
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
4.7U/25V_8
4.7U/25V_8
C38
C38
*22U/6.3V_8
*22U/6.3V_8
+1.8V
4.7U/6.3V_6
4.7U/6.3V_6
R384
R384
*100K_4
*100K_4
Sandy Bridge Processor (GRAPHIC POWER)
+VCC_GFX
+
+
C413
C413
330U/2V_7343
330U/2V_7343
C73
C73
C52
C52
10U/6.3V_8
10U/6.3V_8
C389
C389
C74
C74
10U/6.3V_8
10U/6.3V_8
C417
C417
C395
C395
4.7U/25V_8
4.7U/25V_8
C87
C87
*22U/6.3V_8
*22U/6.3V_8
C443
C443
C445
C445
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
Layout note: need routing
together and ALERT need
between CLK and DATA
VR_SVID_CLK
Place PU resistor
close to CPU
VR_SVID_DATA
Place PU resistor
close to CPU
C53
C53
C40
C40
C396
C396
C449
C449
+
+
C50
C50
*330U/2V_7343
*330U/2V_7343
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
4.7U/25V_8
4.7U/25V_8
C379
C379
10U/6.3V_8
10U/6.3V_8
C39
C39
10U/6.3V_8
10U/6.3V_8
C394
C394
4.7U/25V_8
4.7U/25V_8
C88
C88
*22U/6.3V_8
*22U/6.3V_8
+1.05V_VTT
R31 43_4R31 43_4
+
+
C451
C451
*330u/6.3V_7343
*330u/6.3V_7343
R248
R248
130/F_4
130/F_4
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
U17G
U17G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
CPU-989P-rPGA
CPU-989P-rPGA
+1.05V_VTT
R29
R29
75_4
75_4
VR_SVID_ALERT#H_CPU_SVIDALRT#
2
POWER
POWER
SENSE
SENSE
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
SVID CLK
VR_SVID_CLK [29]
SVID DATA
VR_SVID_DATA [29]
SVID ALERT
VR_SVID_ALERT# [29]
VSSAXG_SENSE
LINES
LINES
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
FC_C22
VCCSA_VID1
R282 10/F_4R282 10/F_4
AK35
AK34
R283 10/F_4R283 10/F_4
+VDDR_REF_CPU
AL1
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
AF7
AF4
AF1
C131
C131
AC7
4.7U/25V_8
4.7U/25V_8
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
C141
C141
P7
4.7U/25V_8
4.7U/25V_8
P4
P1
CPU SA
SNB 45W: 6A
Spec
330uF/7mohm x 1
10uF x 3
M27
M26
L26
J26
4.7U/25V_8
4.7U/25V_8
J25
J24
H26
H25
H23
H_FC_C22
C22
C24
+VCC_GFX
+VDDR_REF_CPU
C125
C125
4.7U/25V_8
4.7U/25V_8
C126
C126
10U/6.3V_8
10U/6.3V_8
C32
C32
C43
C43
4.7U/25V_8
4.7U/25V_8
VCCSA_SENSE [32]
R315 10K_4R315 10K_4
VCCSA_SEL [32]
4.5A
R142 0.002/F_1206R142 0.002/F_1206
R143 0.002/F_1206R143 0.002/F_1206
8
7
5
Q7
4
MAIND
MAINON_ON_G[4,33]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Sandy Bridge 3/4
Sandy Bridge 3/4
Sandy Bridge 3/4
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
*AO4496Q7*AO4496
C149
C149
*470P/50V_4
*470P/50V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
VCC_AXG_SENSE [29]
VSS_AXG_SENSE [29]
CPU MCH
SNB 45W: 5A
Spec
330uF/6mohm x 1
10uF x 6
C147
C147
4.7U/25V_8
4.7U/25V_8
4.7U/25V_8
4.7U/25V_8
C148
C148
10U/6.3V_8
10U/6.3V_8
C369
C369
4.7U/25V_8
4.7U/25V_8
+1.5V_CPU+1.5V_SUS
1
2
36
3
2
1
ZRL
ZRL
ZRL
06
Real
10uF x 6
+1.5V_CPU
C132
C132
C140
C140
4.7U/25V_8
4.7U/25V_8
+
+
C152
C152
330U/2V_7343
330U/2V_7343
+VCCSA
+
+
C361
C361
*330U/2V_7343
*330U/2V_7343
R139
R139
*220_8
*220_8
Q6
Q6
*DMN601K-7
*DMN601K-7
6 34
6 34
6 34
1A
1A
1A
Sandy Bridge Processor (POWER)
POWER
U17F
U17F
C15
C15
10U/6.3V_8
10U/6.3V_8
C384
C384
10U/6.3V_8
10U/6.3V_8
C382
C382
10U/6.3V_8
10U/6.3V_8
C397
C397
10U/6.3V_8
10U/6.3V_8
C352
C352
+VCC_CORE
C346
C346
10U/6.3V_8
10U/6.3V_8
C383
C383
10U/6.3V_8
10U/6.3V_8
C357
C357
10U/6.3V_8
10U/6.3V_8
C360
C360
10U/6.3V_8
10U/6.3V_8
C348
C348
10U/6.3V_8
10U/6.3V_8
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CPU-989P-rPGA
CPU-989P-rPGA
D D
CPU Core Power
SNB 45W:52A
Spec
470uF/4mohm x 4
22uF x 16
10uF x 10
C343
C338
C338
C356
C356
C339
10U/6.3V_8
10U/6.3V_8
C34
C34
10U/6.3V_8
10U/6.3V_8
C359
C359
10U/6.3V_8
10U/6.3V_8
C407
C407
*22U/6.3V_8
*22U/6.3V_8
C339
10U/6.3V_8
10U/6.3V_8
C76
C76
10U/6.3V_8
10U/6.3V_8
C349
C349
10U/6.3V_8
10U/6.3V_8
C406
C406
10U/6.3V_8
10U/6.3V_8
+
+
C55
C55
470u/2V_7343
470u/2V_7343
*22U/6.3V_8
*22U/6.3V_8
C33
C33
C C
10U/6.3V_8
10U/6.3V_8
C358
C358
*22U/6.3V_8
*22U/6.3V_8
C408
C408
*22U/6.3V_8
*22U/6.3V_8
+
+
C54
C54
470u/2V_7343
470u/2V_7343
B B
A A
C344
C344
10U/6.3V_8
10U/6.3V_8
C69
C69
10U/6.3V_8
10U/6.3V_8
C380
C380
10U/6.3V_8
10U/6.3V_8
C405
C405
10U/6.3V_8
10U/6.3V_8
5
C343
10U/6.3V_8
10U/6.3V_8
C385
C385
10U/6.3V_8
10U/6.3V_8
C381
C381
10U/6.3V_8
10U/6.3V_8
C404
C404
10U/6.3V_8
10U/6.3V_8
+
+
C355
C355
*470u/2V_7343
*470u/2V_7343
10U/6.3V_8
10U/6.3V_8
POWER
CORE SUPPLY
CORE SUPPLY
4
SENSE LINES SVID
SENSE LINES SVID
PEG AND DDR
PEG AND DDR
VCCIO_SENSE
VSSIO_SENSE
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
5
4
3
2
1
Sandy Bridge Processor (GND)
U17I
M34
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
L33
L30
L27
K35
K32
K29
K26
J34
J31
F34
F31
F29
U17I
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Sandy Bridge Processor (RESERVED, CFG)
U17E
U17E
L7
RSVD28
AG7
TP7TP7
TP3TP3
TP9TP9
TP13TP13
TP2TP2
TP1TP1
TP80TP80
CFG0
CFG1
CFG2
CFG3
CFG4CFG4
CFG5
CFG6
CFG7CFG7
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
CPU-989P-rPGA
CPU-989P-rPGA
RESERVED
RESERVED
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
07
U17H
U17H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
D D
C C
B B
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
CPU-989P-rPGA
CPU-989P-rPGA
CPU-989P-rPGA
Processor Strapping
The CFG signals have a default value of '1' if not terminated on the board.
1 0
CFG2
A A
(PEG Static Lane Reversal)
CFG4
(DP Presence Strap)
CFG7
(PEG Defer Training)
5
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG train immediately following
xxRESETB de assertion
CPU-989P-rPGA
Enable; An ext DP device is connected to eDP
PEG wait for BIOS training
4
CFG2
R46 1K/F_4R46 1K/F_4
CFG4
R43 *1K/F_4R43 *1K/F_4
CFG7
R26 *1K/F_4R26 *1K/F_4
CFG5
R24 *1K/F_4R24 *1K/F_4
CFG6
R16 *1K/F_4R16 *1K/F_4
3
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Date: Sheet of
2
Date: Sheet of
PROJECT :
Sandy Bridge 4/4
Sandy Bridge 4/4
Sandy Bridge 4/4
1
ZRL
ZRL
ZRL
7 34
7 34
7 34
of
1A
1A
1A
5
4
3
2
1
08
Cougar Point (DMI,FDI,PM)
U16C
U16C
DMI_RXN0[4]
+1.05V_VTT
PM_DRAM_PWRGD[4]
DMI_RXN1[4]
DMI_RXN2[4]
DMI_RXN3[4]
DMI_RXP0[4]
DMI_RXP1[4]
DMI_RXP2[4]
DMI_RXP3[4]
DMI_TXN0[4]
DMI_TXN1[4]
DMI_TXN2[4]
DMI_TXN3[4]
DMI_TXP0[4]
DMI_TXP1[4]
DMI_TXP2[4]
DMI_TXP3[4]
R320 49.9/F_4R320 49.9/F_4
R325 750/F_4R325 750/F_4
XDP_DBRST#[4]
PWROK_EC[26]
ICH_RSMRST#[26]
DNBSWON#[26]
DMI_COMP
DMI2RBIAS
SUS_PWR_ACK
XDP_DBRST#
SYS_PWROK
PWROK_EC
PM_DRAM_PWRGD
ICH_RSMRST#
SUS_PWR_ACK
AC_PRESENT
PM_BATLOW#
PM_RI#
D D
C C
B B
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
CougarPoint_R1P0
CougarPoint_R1P0
+3V
+3V_S5
+3V_S5
+3V_S5
DSW
+3V_S5
+3V_S5
DMI
FDI
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
+3V_S5
SLP_LAN# / GPIO29
DSWVRMEN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
DSWVREN
ICH_RSMRST#
SLP_LAN#
FDI_TXN0 [4]
FDI_TXN1 [4]
FDI_TXN2 [4]
FDI_TXN3 [4]
FDI_TXN4 [4]
FDI_TXN5 [4]
FDI_TXN6 [4]
FDI_TXN7 [4]
FDI_TXP0 [4]
FDI_TXP1 [4]
FDI_TXP2 [4]
FDI_TXP3 [4]
FDI_TXP4 [4]
FDI_TXP5 [4]
FDI_TXP6 [4]
FDI_TXP7 [4]
FDI_INT [4]
FDI_FSYNC0 [4]
FDI_FSYNC1 [4]
FDI_LSYNC0 [4]
FDI_LSYNC1 [4]
PCIE_WAKE# [18,19]
CLKRUN# [26]
SUS_STAT# [26]
PCH_SUSCLK [26]
TP25TP25
SUSC# [26]
SUSB# [26]
TP26TP26
TP20TP20
PM_SYNC [4]
INT_LVDS_BLON[16]
INT_LVDS_VDDEN[16]
INT_LVDS_BRIGHT[16]
INT_LVDS_EDIDCLK[16]
INT_LVDS_EDIDDATA[16]
INT_TXLCLKOUT-[16]
INT_TXLCLKOUT+[16]
INT_TXLOUT0-[16]
INT_TXLOUT1-[16]
INT_TXLOUT2-[16]
INT_TXLOUT0+[16]
INT_TXLOUT1+[16]
INT_TXLOUT2+[16]
+3V
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA
R40 2.2K_4R40 2.2K_4
R21 2.2K_4R21 2.2K_4
R48 2.37K/F_4R48 2.37K/F_4
TP18TP18
R place close to PCH
R292 150/F_4R292 150/F_4
R291 150/F_4R291 150/F_4
R290 150/F_4R290 150/F_4
INT_CRT_BLU[16]
INT_CRT_GRE[16]
INT_CRT_RED[16]
INT_CRT_DDCCLK[16]
INT_CRT_DDCDAT[16]
INT_CRT_HSYNC[16]
INT_CRT_VSYNC[16]
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
R27 33_4R27 33_4
R30 33_4R30 33_4
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
INT_CRT_DDCCLK
INT_CRT_DDCDAT
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
DAC_IREF
R38
R38
1K/F_4
1K/F_4
Cougar Point (LVDS,DDI)
U16D
U16D
J47
M45
P45
T40
K47
T45
P39
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
N48
P49
T49
T39
M40
M47
M49
T43
T42
CougarPoint_R1P0
CougarPoint_R1P0
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
CRT
CRT
DDPD_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
INT_HDMITX2N_R
INT_HDMITX2P_R
INT_HDMITX1N_R
INT_HDMITX1P_R
INT_HDMITX0N_R
INT_HDMITX0P_R
INT_HDMICLKN_R
INT_HDMICLKP_R
DDPC_HPD_PU
DDPD_HPD_PU
INT. HDMI
INT_HDMI_DDCCLK [17]
INT_HDMI_DDCDATA [17]
C230 0.1U/10V_4C230 0.1U/10V_4
C231 0.1U/10V_4C231 0.1U/10V_4
C217 0.1U/10V_4C217 0.1U/10V_4
C219 0.1U/10V_4C219 0.1U/10V_4
C209 0.1U/10V_4C209 0.1U/10V_4
C210 0.1U/10V_4C210 0.1U/10V_4
C212 0.1U/10V_4C212 0.1U/10V_4
C215 0.1U/10V_4C215 0.1U/10V_4
DDPC_HPD_PU
DDPD_HPD_PU
R18 10K_4R18 10K_4
R37 10K_4R37 10K_4
Follow PDG eDP disable guide
INT_HDMI_HPD [17]
INT_HDMITX2N [17]
INT_HDMITX2P [17]
INT_HDMITX1N [17]
INT_HDMITX1P [17]
INT_HDMITX0N [17]
INT_HDMITX0P [17]
INT_HDMICLK- [17]
INT_HDMICLK+ [17]
+3V
INT. DP
PCH Pull-high/low(CLG) System PWR_OK(CLG)
U1
4
TC7SH08U1TC7SH08
+3V_S5
3 5
C124
C124
*0.1U/10V_4
*0.1U/10V_4
2
1
R89
R89
100K_4
100K_4
IMVP_PWRGD_R
PWROK_EC
R422 0_4R422 0_4
3
+3V
CLKRUN#
XDP_DBRST#
ICH_RSMRST#
A A
SYS_PWROK
R359 8.2K_4R359 8.2K_4 R368 10K_4R368 10K_4
R377 10K_4R377 10K_4
R362 *1K_4R362 *1K_4
R327 10K_4R327 10K_4
R91 10K_4R91 10K_4
5
PM_RI#
PM_BATLOW#
PCIE_WAKE#
SLP_LAN#
SUS_PWR_ACK
AC_PRESENT
PM_DRAM_PWRGD
R347 8.2K_4R347 8.2K_4
R381 10K_4R381 10K_4
R83 *10K_4R83 *10K_4
R343 10K_4R343 10K_4
R75 10K_4R75 10K_4
R342 200/F_4R342 200/F_4
+3V_S5
SYS_PWROK[4,26]
4
SYS_PWROK
IMVP_PWRGDIMVP_PWRGD_R
U2
U2
4
*TC7SH08
*TC7SH08
+3V_S5
3 5
C116
C116
*2.2U/6.3V_4
*2.2U/6.3V_4
2
1
IMVP_PWRGD [4,29]
GFX_PWRGD [29]
2
+3V_RTC
R336
R336
330K_4
330K_4
DSWVREN
R334
R334
On Die DSW VR Enable
*330K_4
*330K_4
High = Enable (Default)
Low = Disable
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
PROJECT :
Cougar Point 1/6
Cougar Point 1/6
Cougar Point 1/6
1
ZRL
ZRL
ZRL
8 34
8 34
8 34
1A
1A
1A
5
RTC Circuitry(RTC)
20mils
+3V_RTC
D20
+3V_RTC_1
20MIL
D20
BAT54C
BAT54C
R349 20K_4R349 20K_4
30mils
R350 20K_4R350 20K_4
C437
C437
1U/6.3V_4
1U/6.3V_4
C435
C435
1U/6.3V_4
1U/6.3V_4
C436
C436
1U/6.3V_4
1U/6.3V_4
RTC_RST#
12
J1
J1
*SHORT_ PAD1
*SHORT_ PAD1
SRTC_RST#
12
J2
J2
*SHORT_ PAD1
*SHORT_ PAD1
+3VPCU
D D
R385
R385
1K_4
1K_4
20MIL
12
BT1
BT1
RTC_CONN
RTC_CONN
HDA Bus(CLG)
ACZ_BITCLK[21]
ACZ_SYNC[21]
C C
ACZ_RST#[21]
ACZ_SDOUT[21]
R69 33_4R69 33_4
R66 33_4R66 33_4
R65 33_4R65 33_4
R59 33_4R59 33_4
ACZ_BITCLK_R
ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDOUT_R
PCH JTAG Debug (CLG)
+3V_S5
R131
R131
R132
R132
210/F_4
210/F_4
210/F_4
210/F_4
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TCK
R113
R113
R364
R364
51_4
51_4
100/F_4
100/F_4
R114
R114
100/F_4
100/F_4
4
PCH2(CLG)
C402 18P/50V_4C402 18P/50V_4
C403 18P/50V_4C403 18P/50V_4
R423 10K_4R423 10K_4
+5V
ACZ_SYNC_R ACZ_SYNC_CODEC
Add MOSFET to separate CODEC SYNC signal
2
1
3
Q26
Q26
2N7002D
2N7002D
23
4 1
+3V_RTC
+1.05V_VTT
+3VPCU
3
Y3
32.768KHZY332.768KHZ
R365 51_4R365 51_4
R324
R324
10M_4
10M_4
R77 1M_4R77 1M_4
SPKR[21]
ACZ_SDIN0[21]
TP19TP19
TP79TP79
R371 *10K_4R371 *10K_4
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BITCLK_R
SPKR
ACZ_RST#_R
ACZ_SDOUT_R
PCH_GPIO33
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDO
TP89TP89
2
Cougar Point (HDA,JTAG,SATA)
U16A
U16A
A20
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SO
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
CougarPoint_R1P0
CougarPoint_R1P0
JTAG
JTAG
RTCIHDA
RTCIHDA
SPI
SPI
+3V
+3V
+3V
+3V
+3V_S5
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ1# / GPIO23
SATA0RXN
SATA1RXN
SATA 6G
SATA 6G
SATA2RXN
SATA3RXN
SATA4RXN
SATA
SATA
SATA5RXN
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATA0GP / GPIO21
SATA1GP / GPIO19
LDRQ0#
SERIRQ
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXP
SATA5TXN
SATA5TXP
SATALED#
C38
A38
B37
C37
D36
E36
K36
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
P3
V14
P1
PCH_DRQ#0
PCH_DRQ#1
SERIRQ
SATA_COMPPCH_JTAG_TDI
SATA3_COMP
SATA3_RBIAS
R357 10KR357 10K
PCH_ODD_ENPCH_SPI_SI
BBS_BIT0
SERIRQ
PCH_ODD_EN
LAD0 [19,26]
LAD1 [19,26]
LAD2 [19,26]
LAD3 [19,26]
LFRAME# [19,26]
TP15TP15
TP17TP17
SERIRQ [26]
TP83TP83
TP87TP87
TP84TP84
TP88TP88
R87 37.4/F_4R87 37.4/F_4
R88 49.9/F_4R88 49.9/F_4
R353 750/F_4R353 750/F_4
+3V
R108 8.2K_4R108 8.2K_4
R105 *10K_4R105 *10K_4
+1.05V_VTT
1
+3V
SATA_RXN0 [20]
SATA_RXP0 [20]
SATA_TXN0 [20]
SATA_TXP0 [20]
SATA_RXN1 [20]
SATA_RXP1 [20]
SATA_TXN1 [20]
SATA_TXP1 [20]
09
SATA HDD
SATA ODD
PCH Strap Table
PCH Dual SPI (CLG)
B B
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
R145 3.3K_4R145 3.3K_4
+3V
MX25L3205DM2I-12G: AKE39FP0Z00
W25X32VSSIG: AKE39ZP0N00
U5
C120
C120
*22P/50V_4
*22P/50V_4
1
6
5
2
3
CE#
SCK
SI
SO
WP#
SPI FlashU5SPI Flash
VDD
HOLD#
VSS
8
R144 3.3K_4R144 3.3K_4
7
4
+3V
C143
C143
0.1U/10V_4
0.1U/10V_4
Pin Name
SPKR
Strap description
No reboot mode setting PWROK
GNT3# / GPIO55 Top-Block Swap Override
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up
GNT1# / GPIO51
GPIO19
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
HDA_SDO Flash Descriptor Security RSMRST
DF_TVS
GPIO28
A A
DMI/FDI Termination voltage
On-die PLL Voltage Regulator RSMRST#
HDA_SYNC On-Die PLL VR Voltage Select RSMRST
GPIO8
Integrated Clock Chip Enable
SPI_MOSI iTPM function Disable APWROK
Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 20kohm)NV_ALE
5
4
Sampled
PWROK
PWROK
PWROK
PWROK
RSMRST#
3
Configuration
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
Boot Location
GNT0#GNT1#
11
SPI
00
LPC
0 = Override
1 = Default (weak pull-up 20K)
0 = Set to Vss
1 = Set to Vcc (weak pull-down 20K)
0 = Disable
1 = Enable (Default)
0 = Support by 1.8V (weak pull-down)
1 = Support by 1.5V
Should be pull-down
(weak pull-up 20K)
0 = Default (weak pull-down 20K)
1 = Enable
R64 1K_4R64 1K_4
SPKR
PCI_GNT3# [10]
PCH_INVRMEN
BBS_BIT1 [10]
BBS_BIT0
ACZ_SDOUT_R
DF_TVS [11]
H_SNB_IVB# [4]
PLL_ODVR_EN [11]
ACZ_SYNC_CODEC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Cougar Point 2/6
Cougar Point 2/6
Cougar Point 2/6
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
1
ZRL
ZRL
ZRL
9 34
9 34
9 34
1A
1A
1A
of
R126 *1K_4R126 *1K_4
+3V
R14 *1K_4R14 *1K_4
R331 330K_4R331 330K_4
+3V_RTC
R33 *1K_4R33 *1K_4
+3V
R372 *1K_4R372 *1K_4
+3V
ME_WR#[26]
R109 *1K_4R109 *1K_4
+3V_S5
R32 *1K_4R32 *1K_4
R358 *1K_4R358 *1K_4
R56 *1K_4R56 *1K_4
R53 0_4R53 0_4
R351 *1K_4R351 *1K_4
*
+1.8V
R352 2.2K_4R352 2.2K_4
2
5
4
3
2
1
Cougar Point-M (PCI-E,SMBUS,CLK)
Cougar Point-M (PCI,USB,NVRAM)
U16E
U16E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
D D
C C
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
dGPU_EDIDSEL#
TP11TP11
DGPU_SELECT#
TP12TP12
TP10TP10
TP16TP16
TP6TP6
TP29TP29
R28 22_4R28 22_4
R50 22_4R50 22_4
R39 22_4R39 22_4
GPIO54
MPC_PWR_CTRL#
dGPU_PWM_SELECT#
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH
PCI_PME#
PCI_PLTRST#
CLK_LPC_DEBUG_R
CLK_PCI_EC_R
BBS_BIT1[9]
PCI_GNT3#[9]
CLK_PCI_FB CLK_PCI_FB_R
CLK_LPC_DEBUG[19]
CLK_PCI_EC[26]
B B
AH37
AK43
AK45
AH12
AB46
AB45
AY16
BG46
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
C18
N30
H3
AM4
AM5
Y13
K24
L24
B21
M20
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
CougarPoint_R1P0
CougarPoint_R1P0
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
RSVD
RSVD
PCI
PCI
USB
USB
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP1USBP1+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP12USBP12+
USB_BIAS
USB_OC0#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC6#
USB_OC7#
NV_ALE
TP28TP28
USBP1- [24]
USBP1+ [24]
USBP3- [24]
USBP3+ [24]
USBP4- [24]
USBP4+ [24]
USBP5- [24]
USBP5+ [24]
USBP8- [16]
USBP8+ [16]
USBP9- [24]
USBP9+ [24]
USBP10- [19]
USBP10+ [19]
USBP12- [23]
USBP12+ [23]
R312 22.6/F_4R312 22.6/F_4
USB_OC0# [24]
MB USB
EXT USB1
BlueTooth
*BlueTooth
CCD
EXT USB2
Mini Card (WLAN)
Card reader
USB_OC1_5# [24]
LAN
WLAN
EHCI1
WLAN
EHCI2
LAN
PCIE_RX1-[18]
PCIE_RX1+[18]
PCIE_TX1-[18]
PCIE_TX1+[18]
PCIE_RX6-[19]
PCIE_RX6+[19]
PCIE_TX6-[19]
PCIE_TX6+[19]
CLK_PCIE_WLANN[19]
CLK_PCIE_WLANP[19]
CLKREQ_WLAN#[19]
CLK_PCIE_LANN[18]
CLK_PCIE_LANP[18]
PCIE_CLKREQ_LAN#[18]
C46 0.1U/10V_4C46 0.1U/10V_4
C41 0.1U/10V_4C41 0.1U/10V_4
C35 0.1U/10V_4C35 0.1U/10V_4
C45 0.1U/10V_4C45 0.1U/10V_4
CLK_PCIE_WLANN
CLK_PCIE_WLANP
CLK_PCIE_LANN
CLK_PCIE_LANP
TP22TP22
TP24TP24
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN6_C
PCIE_TXP6_C
PCIE_CLKREQ0#
PCIE_CLKREQ1#
CLKREQ_WLAN#
PCIE_CLKREQ3#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ6#
PCIE_CLKREQ7#
U16B
U16B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
CougarPoint_R1P0
CougarPoint_R1P0
+3V_S5
+3V_S5
SMBUSController
SMBUSController
+3V_S5
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
+3V_S5
+3V_S5
CLOCKS
CLOCKS
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
+3V_S5
+3V_S5
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKIN_PCILOOPBACK
+3V
CLKOUTFLEX0 / GPIO64
+3V
CLKOUTFLEX1 / GPIO65
+3V
CLKOUTFLEX2 / GPIO66
+3V
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
SMBALERT#
E12
SMB_PCH_CLK
H14
SMB_PCH_DAT
C9
DRAMRST_CNTRL_PCH
A12
SMB_ME0_CLK
C8
SMB_ME0_DAT
G12
SML1ALERT#_R
C13
SMB_ME1_CLK
E14
SMB_ME1_DAT
M16
M7
T11
P10
PCIE_CLKREQ_PEG#
M10
CLK_PCIE_VGAN
AB37
CLK_PCIE_VGAP
AB38
AV22
AU22
AM12
AM13
CLK_BUF_PCIE_3GPLLN
BF18
CLK_BUF_PCIE_3GPLLP
BE18
CLK_BUF_BCLKN
BJ30
CLK_BUF_BCLKP
BG30
CLK_BUF_DREFCLKN
G24
CLK_BUF_DREFCLKP
E24
CLK_BUF_DREFSSCLKN
AK7
CLK_BUF_DREFSSCLKP
AK5
CLK_PCH_14M
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
K43
CLK_FLEX1
F47
CLK_FLEX2
H47
K49
R82 *0_4R82 *0_4
CLK_CPU_BCLKN [4]
CLK_CPU_BCLKP [4]
CLK_DPLL_SSCLKN [4]
CLK_DPLL_SSCLKP [4]
R288 90.9/F_4R288 90.9/F_4
TP5TP5
T11T11
DRAMRST_CNTRL_PCH [5]
SML1ALERT# [11,25]
CL_CLK1 [19]
CL_DATA1 [19]
CL_RST1# [19]
TP32TP32
TP14TP14
TP8TP8
+1.05V_VTT
SKU_ID1 [11]
EXT48MHZ [23]
R293
R293
1M_4
1M_4
10
For LAN
For EC
C367 27P/50V_4C367 27P/50V_4
21
Y2
25MHzY225MHz
C368 27P/50V_4C368 27P/50V_4
2
SMBus/Pull-up(CLG)CLK_REQ/Strap Pin(CLG)
MBCLK2[26]
MBDATA2[26]
+3V_S5
R344 1K_4R344 1K_4
R86 10K_4R86 10K_4
R141 2.2K_4R141 2.2K_4
R140 2.2K_4R140 2.2K_4
R367 2.2K_4R367 2.2K_4
R85 2.2K_4R85 2.2K_4
R81 10K_4R81 10K_4
+3V_S5
3
+3V_S5
3
R79
R79
2.2K_4
2.2K_4
2
SMB_ME1_CLK
1
Q5
2N7002DQ52N7002D
R73
R73
2.2K_4
2.2K_4
2
SMB_ME1_DAT
1
Q4
2N7002DQ42N7002D
DRAMRST_CNTRL_PCH
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
SMBus(PCH)
+3V
R148
R148
2
4.7K_4
SMB_PCH_CLK
3
Q9 2N7002DQ9 2N7002D
SMB_PCH_DAT
3
Q8 2N7002DQ8 2N7002D
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Cougar Point 3/6
Cougar Point 3/6
Cougar Point 3/6
Tuesday, June 21, 2011
Tuesday, June 21, 2011
Tuesday, June 21, 2011
4.7K_4
1
CLK_SCLK [14,15,19]
+3V
R147
R147
2
4.7K_4
4.7K_4
1
CLK_SDATA [14,15,19]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
ZRL
ZRL
ZRL
of
10 34
10 34
10 34
1A
1A
1A
PLTRST#(CLG)
+3V_S5
C121
C121
0.1U/10V_4
0.1U/10V_4
PCI_PLTRST#
A A
2
1
U3
3 5
TC7SH08FUU3TC7SH08FU
PLTRST#
4
R134
R134
100K_4
100K_4
PLTRST# [4,18,19,23,26]
PCI/USBOC# Pull-up(CLG)
R337
R337
10
USB_OC4#
USB_OC2#
USB_OC3#
9
8
7 4
10KX8
10KX8
1
2
3
56
MPC_PWR_CTRL#
GPIO54
dGPU_PWM_SELECT#
MPC Switch Control
MPC_PWR_CTRL#
MPC_PWR_CTRL#
USB_OC7#
USB_OC0#
USB_OC6#
USB_OC1_5#
+3V
10
9
8
7 4
R54 *1K_4R54 *1K_4
PCI_PIRQA#
R57 8.2K_4R57 8.2K_4
PCI_PIRQB#
R63 8.2K_4R63 8.2K_4
PCI_PIRQC#
R35 8.2K_4R35 8.2K_4
PCI_PIRQD#
R307 8.2K_4R307 8.2K_4
R49
R49
10KX8
10KX8
Low = MPC ON
High = MPC OFF (Default)
DGPU_HOLD_RST#
1
EXTTS_SNI_DRV1_PCH
2
dGPU_EDIDSEL#
3
DGPU_SELECT#
56
+3V_S5
+3V+3V_S5
R378 10K_4R378 10K_4
R380 10K_4R380 10K_4
R90 10K_4R90 10K_4
R84 10K_4R84 10K_4
R116 10K_4R116 10K_4
R373 10K_4R373 10K_4
R346 10K_4R346 10K_4
+3V
R375 10K_4R375 10K_4
R125 10K_4R125 10K_4
+3V_S5
R130 10K_4R130 10K_4
R112 *10K_4R112 *10K_4
CLK_BUF_BCLKN
CLK_BUF_BCLKP
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
PCIE_CLKREQ0#
PCIE_CLKREQ3#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ6#
PCIE_CLKREQ7#
PCIE_CLKREQ1#
CLKREQ_WLAN#
PCIE_CLKREQ_PEG#
R316 10K_4R316 10K_4
R313 10K_4R313 10K_4
R329 10K_4R329 10K_4
R333 10K_4R333 10K_4
R72 10K_4R72 10K_4
R70 10K_4R70 10K_4
R103 10K_4R103 10K_4
R104 10K_4R104 10K_4
R42 10K_4R42 10K_4
CLOCK TERMINATION for FCIM
5
4
3
5
4
3
2
1
Cougar Point (GPIO,VSS_NCTF,RSVD)
U16F
U16F
S_GPIO
EC_EXT_SMI#[26]
D D
check VR_ON GPIO
EC_EXT_SCI#[26]
TP86TP86
TP4TP4
PLL_ODVR_EN[9]
Need Check
C C
TP27TP27
TP30TP30
SML1ALERT#[10,25]
EC_EXT_SMI#
BOARD_ID1
EC_EXT_SCI#
SMIB#
PCH_GPIO15
SKU_ID0
dGPU_PWROK
BIOS_REC
CR_WAKER#
GPIO27
PLL_ODVR_EN
STP_PCI#
dGPU_VRON
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP
R354 *short_4R354 *short_4
BOARD_ID2
CRIT_TEMP_REP#
SV_SET_UP
High = Strong (Default)
B B
+3V
TEST_SET_UP
PCH_GPIO15
Intel ME Crypto Transport Layer
Security (TLS) cipher suite
Low = Disable (Default)
High = Enable
A A
FDI TERMINATION
VOLTAGE OVERRIDE
R124 10K_4R124 10K_4
R107 *0_4R107 *0_4
+3V_S5
R379 1K_4R379 1K_4
FDI_OVRVLTG DMI_OVRVLTG BIOS_REC
R129 *10K/F_4R129 *10K/F_4
LOW - Tx, Rx terminated
to same voltage
5
SGPIO
S_GPIO
MFG-TEST
MFG_MODE
R111 1K/F_4R111 1K/F_4
R95 *100_4R95 *100_4
R374 10K_4R374 10K_4
R360 *0_4R360 *0_4
DMI TERMINATION
VOLTAGE OVERRIDE
+3V
+3V
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
CougarPoint_R1P0
CougarPoint_R1P0
GPIO27:
Un-multiplexed. Can be configured as wake input to allow wakes from Deep Sleep.
If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.
R94 *200K/F_4R94 *200K/F_4
Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)
4
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V
+3V_S5
DSW
+3V_S5
+3V
+3V
+3V
+3V
+3V_S5
+3V
TACH4 / GPIO68
+3V
TACH5 / GPIO69
+3V
TACH6 / GPIO70
+3V
TACH7 / GPIO71
+3V_S5
PROCPWRGD
CPU/MISC
CPU/MISC
THRMTRIP#
INIT3_3V#
GPIO
GPIO
+3V
+3V
+3V
+3V
+3V+3V +3V
NCTF
NCTF
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
B41
C41
A40
P4
A20GATE
AU16
PECI
P5
RCIN#
AY11
AY10
T14
AY1
DF_TVS
AH8
TS_VSS1
AK11
TS_VSS2
AH10
TS_VSS3
AK10
TS_VSS4
P37
NC_1
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
BIOS RECOVERY
3
dGPU_PWR_CTRL#
R298 1.5K/F_4R298 1.5K/F_4
R302 1.5K/F_4R302 1.5K/F_4
R303 1.5K/F_4R303 1.5K/F_4
EC_A20GATE
R102 *0_4R102 *0_4
EC_RCIN#
PCH_THRMTRIP#
R101 390_4R101 390_4
GPIO Pull-up/Pull-down(CLG)
CR_WAKER#
SMIB#
PLL_ODVR_EN
EC_EXT_SMI#
EC_EXT_SCI#
STP_PCI#
EC_A20GATE
EC_RCIN#
CRIT_TEMP_REP#
dGPU_PWROK
R353??
R128 10K_4R128 10K_4
R110 *0_4R110 *0_4
GPIO27
High = Disable (Default)
Low = Enable
+3V
TP23TP23
R348 10K/F_4R348 10K/F_4
R366 10K_4R366 10K_4
R127 *10K_4R127 *10K_4
R299 10K_4R299 10K_4
R34 10K_4R34 10K_4
R363 *10K_4R363 *10K_4
R96 10K_4R96 10K_4
R93 10K_4R93 10K_4
R355 10K_4R355 10K_4
R36 *10K_4R36 *10K_4
R80 *10K_4R80 *10K_4
EC_A20GATE [26]
EC_PECI [4,26]
EC_RCIN# [26]
H_PWRGOOD [4]
PM_THRMTRIP# [4]
DF_TVS [9]
+3V_S5
+3V
2
dGPU_PWR_CTRL#
(GPIO68)
Switchable
(Mux)
Optimize
(Muxless)
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize)
1 = GPU power is control by H/W (pure Discrete SKU)
+3V
+3V
+3V
R361 *10K_4R361 *10K_4
R300 10K_4R300 10K_4
R115 10K_4R115 10K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, June 21, 2011
Date: Sheet of
Tuesday, June 21, 2011
Date: Sheet of
Tuesday, June 21, 2011
SKU_ID1
(GPIO64)
1
0 or 1
0
0
R297 10K_4R297 10K_4
R305 *100K_4R305 *100K_4
R15 *10K_4R15 *10K_4
R22 10K_4R22 10K_4
R370 *10K_4R370 *10K_4
R356 10K_4R356 10K_4
0
0
1
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Cougar Point 4/6
Cougar Point 4/6
Cougar Point 4/6
SKU_ID0
(GPIO16)
0
1
0
1
BOARD_ID0
BOARD_ID1
BOARD_ID2
dGPU_PWR_CTRL#
SKU_ID0
11
VGA H/W
Setup
Signal
Menu
UMA
HiddenUMA Only
GPU
HiddenDiscrete Only
UMA+GPU
DIS/SG
UMA/SG
UMA
SKU_ID1 [10]
R376 10K_4R376 10K_4
R301 *10K_4R301 *10K_4
R133 *10K_4R133 *10K_4
ZRL
ZRL
ZRL
11 34
11 34
11 34
1
UMA boot
GPU boot
UMA boot
UMA boot
+3V
1A
1A
1A
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