Quanta ZQTA DAZQSAMB6E0, ZQTA DAZQSAMB6E1, ZQSA DAZQSAMB6E0, ZQSA DAZQSAMB6E1 Schematic
5
4
3
2
1
BOM
=47$=46$&596<67(0%/2&.',$*5$0
D D
DIS._eDP
IV@ : iGPU
EV@ : dGPU
OP@ : Optimus
DO@ : Discrete only
SP@ : Special
SNP@: N13PGS/GL
IV@: UMA
GL@: N13PGL
GS@: N13P/MGS
P8
N13P-GS
N13P-GL
N13M-GS
eDP
GPU
Display
P15~P19
USB Charger
DIS._HDMI
DIS._CRT
DIS._LVDS
P29
USB-9
PCIE-8
USB-10
PCIE-3
VRAM
P20,P21
Int. MIC
USB-8
USB3 Port
MB side
MINI-SSD
MINI CARD
WLAN
RTL8411
10/100/1G
Cardreader
P29
P24
P25
P28
Optimus : IV@ + EV@ + OP@
Discrete only : EV@ + DO@
LVDS/CCD/MIC
Con.
CRT Con.
HDMI Con.
RJ45
Cardreader
CONN.
P22
P22
P23
P28
P29
eDP Con.
DDRIII-SODIMM1
DDRIII-SODIMM2
P22
P13, 14
INT._eDP
Dual Channel DDR III
1066/1333/1600 MHZ
eDP
IVY Bridge
rPGA 989
GFXIMC
P3, 4, 5, 6
FDI
DMI
PEG
TX/RX
DMI(x4)
FDI
CLK
C C
SATA - HDD
SATA - ODD
P25
P25
SATA 0
SATA
SATA 1
DMI
Display
USB3.0/2.0
INT_LVDS
INT_CRT
INT_HDMI
USB3-2/USB2-1
Panther Point
PCH
USB2-1,3
Small Board
CONNECTOR
P31
B B
Bluetooth Con.
CCD(Camera)
P31
P22
USB2-4
USB2-8
Azalia
P8
BATTERY
USB2.0
RTC
IHDA
P7, 8, 9, 10, 11, 12
LPC
SATA
PCI-E x1
CLK
SATA5
X'TAL
32.768KHz
X'TAL 25MHz
SPI
SPI ROM
Int. MIC
MIC JACK
A A
5
ALC271X-VB6
AUDIO CODEC
P27
HP
P27
P26
Speaker
P27
4
K/B Con.
P31
EM-6781-T3
HALL SENSOR
EC
NPCE885L
P22
Touch Pad
Board Con.
P31
BQ24707A
P32
Fan Driver
(PWM Type)
P31
3
Batery Charger
RT8223P
3V/5V
ISL95836
CPU core/VAXG
TPS51219
+1.05V_PCH / +1.05V_VTT
P33
P33
P35
P36
2
TPS51216
+1.5V_SUS
RT8241A
VCCSA
TPS51728
VGPU Core
MDV1660URH
+1.5V_GFX/1.05V_GFX/3V_GFX
P37
P38
P39
P40
Discharger
Thermal Protection
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
P41
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
1A
1A
144Friday, November 11, 2011
144Friday, November 11, 2011
144Friday, November 11, 2011
1A
of
of
of
1
2
VGA power up sequence
3
4
5
6
7
8
EC
A A
+3V
dGPU_RWR_EN
VIN
dGPU_VRON
MOSFET
PWM
+3V_GFX
+VGACORE
VGA_PG
+1.5VSUS
+1.5V_GFXMOSFET
+1.05V
MOSFET
+1.05V_GFX
DGPU_PWROK
VGA_VID
VGA_PG
B B
+1.8V
+1.8V_GFXMOSFET
Power States
POWER PLANE
VIN
+3V_RTC
+3VPCU
+5VPCU
+15V
+3V_S5
C C
D D
+5V_S5
+5V
+1.5VSUS
+0.75V_DDR_VTT
+VGFX_AXG S0VRONInternal GPU POWER
+1.8V
+1.5V
+1.05V
+VCCSA HWPG_VTT+0.9V
+VCC_CORE
LCDVCC
VOLTAGE
+10V~+19V
+3V~+3.3V
+3.3V
+5V
+15V
+3.3V
+5V
+5V
+3.3V
+1.5V
+0.75V
variation
+1.8V
+1.5V
+1.05V
variation
+3.3V
DESCRIPTION
RTC POWER
EC POWER
CHARGE POWER
CHARGE PUMP POWER
LAN/BT/CIR POWER
USB POWER
HDD/ODD/Codec/TP/CRT/HDMI POWER
PCH/GPU/Peripheral component POWER+3V
CPU/SODIMM CORE POWER
SODIMM Termination POWER
CPU/PCH/Braidwood POWER
MINI CARD/NEW CARD POWER
PCH CORE POWER/IVY/SNB bridge VCCIO MAINON
CPU CORE POWER
LCD POWER
CONTROL
SIGNAL
ALWAYSMAIN POWER
ALWAYS
ALWAYS
ALWAYS
S5_ON
S5_ON
MAINON
MAINON
SUSON
MAINON
MAINON
MAINON
VRON
LVDS_VDDEN
MAINON S0
ACTIVE IN
ALWAYS
ALWAYS
ALWAYS
ALWAYS
ALWAYSALWAYS
S0-S5
S0-S5
S0
S0
S0-S3
S0
S0
S0
S0
S0CPU POWER
S0
S0
Thermal Follow Chart
CPU
CORE PWR
H_PROCHOT#
H/W Throttling
NTC
Thermal
Protection
CPU
PCH
SM-Bus
EC
PM_THRMTRIP#
SML1ALERT#
CPUFAN#
WIRE-AND
SYS_SHDN#
3V/5 V
SYS PWR
FANFAN Driver
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
PWR Status & GPU PW R CRL & T HRM
PWR Status & GPU PW R CRL & T HRM
PWR Status & GPU PW R CRL & T HRM
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
PROJECT :
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
of
of
244Friday, November 11, 2011
244Friday, November 11, 2011
244Friday, November 11, 2011
8
1A
1A
1A
5
4
3
2
1
For Sandy Bridge processor only implementation:
PROC_SELECT can be left NC.
IVY Bridge Processor (DMI,PEG,FDI)
DMI_TXN0[7]
DMI_TXN1[7]
D D
DMI_TXN2[7]
DMI_TXN3[7]
DMI_T XP0[7]
DMI_T XP1[7]
DMI_T XP2[7]
DMI_T XP3[7]
DMI_RXN0[7]
DMI_RXN1[7]
DMI_RXN2[7]
DMI_RXN3[7]
DMI_RXP0[7]
DMI_RXP1[7]
DMI_RXP2[7]
DMI_RXP3[7]
FDI_TXN0[7]
FDI_TXN1[7]
FDI_TXN2[7]
FDI_TXN3[7]
FDI_TXN4[7]
FDI_TXN5[7]
FDI_TXN6[7]
FDI_TXN7[7]
FDI_TXP0[7]
FDI_TXP1[7]
FDI_TXP2[7]
FDI_TXP3[7]
FDI_TXP4[7]
FDI_TXP5[7]
C C
FDI_TXP6[7]
FDI_TXP7[7]
FDI_FSYNC0[7]
FDI_FSYNC1[7]
FDI_INT[7]
FDI_LSYNC0[7]
FDI_LSYNC1[7]
eDP_COMP
INT_eDP_HPD_Q[22]
EDP-AUX+[22]
EDP-AUX-[22]
EDP-ML0+[22]
EDP-ML0-[22]
B B
TP59TP59
TP58TP58
HPD disable
This signal can be left as no
connect if entire eDP interface
is disabled.
U16A
U16A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPI O
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
PEG_COM P
J22
PEG_ICOMPI
J21
PEG_ICOMPO
H22
PEG_RCOMPO
K33
PEG_RX#[0]
M35
PEG_RX#[1]
L34
PEG_RX#[2]
J35
PEG_RX#[3]
J32
PEG_RX#[4]
H34
PEG_RX#[5]
H31
PEG_RX#[6]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
eDP
eDP
G33
PEG_RX#[7]
G30
PEG_RX#[8]
F35
PEG_RX#[9]
E34
PEG_RX#[10]
E32
PEG_RX#[11]
D33
PEG_RX#[12]
D31
PEG_RX#[13]
B33
PEG_RX#[14]
C32
PEG_RX#[15]
J33
PEG_RX[0]
L35
PEG_RX[1]
K34
PEG_RX[2]
H35
PEG_RX[3]
H32
PEG_RX[4]
G34
PEG_RX[5]
G31
PEG_RX[6]
F33
PEG_RX[7]
F30
PEG_RX[8]
E35
PEG_RX[9]
E33
PEG_RX[10]
F32
PEG_RX[11]
D34
PEG_RX[12]
E31
PEG_RX[13]
C33
PEG_RX[14]
B32
PEG_RX[15]
M29
PEG_TX#[0]
M32
PEG_TX#[1]
M31
PEG_TX#[2]
L32
PEG_TX#[3]
L29
PEG_TX#[4]
K31
PEG_TX#[5]
K28
PEG_TX#[6]
J30
PEG_TX#[7]
J28
PEG_TX#[8]
H29
PEG_TX#[9]
G27
PEG_TX#[10]
E29
PEG_TX#[11]
F27
PEG_TX#[12]
D28
PEG_TX#[13]
F26
PEG_TX#[14]
E25
PEG_TX#[15]
M28
PEG_TX[0]
M33
PEG_TX[1]
M30
PEG_TX[2]
L31
PEG_TX[3]
L28
PEG_TX[4]
K30
PEG_TX[5]
K27
PEG_TX[6]
J29
PEG_TX[7]
J27
PEG_TX[8]
H28
PEG_TX[9]
G28
PEG_TX[10]
E28
PEG_TX[11]
F28
PEG_TX[12]
D27
PEG_TX[13]
E26
PEG_TX[14]
D25
PEG_TX[15]
DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
PCIe Gen3 on future platforms.
For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils.
PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.
PEG_RX#0 [15]
PEG_RX#1 [15]
PEG_RX#2 [15]
PEG_RX#3 [15]
PEG_RX#4 [15]
PEG_RX#5 [15]
PEG_RX#6 [15]
PEG_RX#7 [15]
PEG_RX#8 [15]
PEG_RX#9 [15]
PEG_RX#10 [15]
PEG_RX#11 [15]
PEG_RX#12 [15]
PEG_RX#13 [15]
PEG_RX#14 [15]
PEG_RX#15 [15]
PEG_RX0 [ 15]
PEG_RX1 [ 15]
PEG_RX2 [ 15]
PEG_RX3 [ 15]
PEG_RX4 [ 15]
PEG_RX5 [ 15]
PEG_RX6 [ 15]
PEG_RX7 [ 15]
PEG_RX8 [ 15]
PEG_RX9 [ 15]
PEG_RX10 [15]
PEG_RX11 [15]
PEG_RX12 [15]
PEG_RX13 [15]
PEG_RX14 [15]
PEG_RX15 [15]
R_PEG_TX#0
C395 EV@0.22u/6.3V_4C395 EV@0.22u/6.3V_4
R_PEG_TX#1
C400 EV@0.22u/6.3V_4C400 EV@0.22u/6.3V_4
R_PEG_TX#2
C402 EV@0.22u/6.3V_4C402 EV@0.22u/6.3V_4
R_PEG_TX#3
C405 EV@0.22u/6.3V_4C405 EV@0.22u/6.3V_4
R_PEG_TX#4
C407 EV@0.22u/6.3V_4C407 EV@0.22u/6.3V_4
R_PEG_TX#5
C413 EV@0.22u/6.3V_4C413 EV@0.22u/6.3V_4
R_PEG_TX#6
C414 EV@0.22u/6.3V_4C414 EV@0.22u/6.3V_4
R_PEG_TX#7
C418 EV@0.22u/6.3V_4C418 EV@0.22u/6.3V_4
R_PEG_TX#8
C421 EV@0.22u/6.3V_4C421 EV@0.22u/6.3V_4
R_PEG_TX#9
C424 EV@0.22u/6.3V_4C424 EV@0.22u/6.3V_4
R_PEG_TX#10
C425 EV@0.22u/6.3V_4C425 EV@0.22u/6.3V_4
R_PEG_TX#11
C430 EV@0.22u/6.3V_4C430 EV@0.22u/6.3V_4
R_PEG_TX#12
C431 EV@0.22u/6.3V_4C431 EV@0.22u/6.3V_4
R_PEG_TX#13
C434 EV@0.22u/6.3V_4C434 EV@0.22u/6.3V_4
R_PEG_TX#14
C439 EV@0.22u/6.3V_4C439 EV@0.22u/6.3V_4
R_PEG_TX#15
C440 EV@0.22u/6.3V_4C440 EV@0.22u/6.3V_4
R_PEG_TX0
C398 EV@0.22u/6.3V_4C398 EV@0.22u/6.3V_4
R_PEG_TX1
C401 EV@0.22u/6.3V_4C401 EV@0.22u/6.3V_4
R_PEG_TX2
C404 EV@0.22u/6.3V_4C404 EV@0.22u/6.3V_4
R_PEG_TX3
C406 EV@0.22u/6.3V_4C406 EV@0.22u/6.3V_4
R_PEG_TX4
C408 EV@0.22u/6.3V_4C408 EV@0.22u/6.3V_4
R_PEG_TX5
C409 EV@0.22u/6.3V_4C409 EV@0.22u/6.3V_4
R_PEG_TX6
C417 EV@0.22u/6.3V_4C417 EV@0.22u/6.3V_4
R_PEG_TX7
C419 EV@0.22u/6.3V_4C419 EV@0.22u/6.3V_4
R_PEG_TX8
C420 EV@0.22u/6.3V_4C420 EV@0.22u/6.3V_4
R_PEG_TX9
C422 EV@0.22u/6.3V_4C422 EV@0.22u/6.3V_4
R_PEG_TX10
C427 EV@0.22u/6.3V_4C427 EV@0.22u/6.3V_4
R_PEG_TX11
C428 EV@0.22u/6.3V_4C428 EV@0.22u/6.3V_4
R_PEG_TX12
C433 EV@0.22u/6.3V_4C433 EV@0.22u/6.3V_4
R_PEG_TX13
C436 EV@0.22u/6.3V_4C436 EV@0.22u/6.3V_4
R_PEG_TX14
C437 EV@0.22u/6.3V_4C437 EV@0.22u/6.3V_4
R_PEG_TX15
C444 EV@0.22u/6.3V_4C444 EV@0.22u/6.3V_4
For IVY/Sandy processor compatibility:
Needs a pull-up resistor to PCH VccDFTERM rail (1.8V) through a 2.2 K±5% pull-up resistor.
Connect to the DF_TVS of PCH though a 1K±5% series resistor.
H_SNB_IVB#[8]
EC_PECI[32]
H_PROCHOT#
PM_THRM TRIP#[10]
PM_SYNC[7]
H_PWRGOOD[10]
R107 75_4R107 75_4
CPU_PLTRST#
PEG_TX#0 [15]
PEG_TX#1 [15]
PEG_TX#2 [15]
PEG_TX#3 [15]
PEG_TX#4 [15]
PEG_TX#5 [15]
PEG_TX#6 [15]
PEG_TX#7 [15]
PEG_TX#8 [15]
PEG_TX#9 [15]
PEG_TX#10 [15]
PEG_TX#11 [15]
PEG_TX#12 [15]
PEG_TX#13 [15]
PEG_TX#14 [15]
PEG_TX#15 [15]
PEG_TX0 [15]
PEG_TX1 [15]
PEG_TX2 [15]
PEG_TX3 [15]
PEG_TX4 [15]
PEG_TX5 [15]
PEG_TX6 [15]
PEG_TX7 [15]
PEG_TX8 [15]
PEG_TX9 [15]
PEG_TX10 [15]
PEG_TX11 [15]
PEG_TX12 [15]
PEG_TX13 [15]
PEG_TX14 [15]
PEG_TX15 [15]
H_PROCHOT#[32,35]
Intel recommended UNCOREPWRGOOD
routing on one layer
apply C5205 for nosie
+1.05V
PCI_PLTR ST#[9]
IVY Bridge Processor (CLK,MISC,JTAG)
U16B
U16B
TP45TP45
TP11TP11
R124 56_4R124 56_4
C165 0.1u/10V_4C165 0.1u/10V_4
R116 10K_4R116 10K_4
PM_DRAM_PWRGD_R
R113 43_4R113 43_4
R114 *1.5K/F_4R114 *1.5K/F_4
U3
U3
1
2
IN
GND3OUT
74LVC1G07GW
74LVC1G07GW
H_SNB_IVB#
SKTOCC#
TP_CATERR#
H_PROCHOT#_R
PM_THRM TRIP#
PM_SYNC
H_PWRGOOD
CPU_PLTRST#_R
VCC5NC
4
PM_DRAM_PWRGD[7]
R115
R115
*750/F_4
*750/F_4
C167
C167
0.1u/10V_4
0.1u/10V_4
CPU_PLTRST#
SYS_PWROK[7]
AN34
AL33
AN33
AL32
AN32
AM34
AP33
AR33
C26
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
V8
SM_DRAMPWROK
RESET#
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
+3V
CRB 1.0 : change to +3V(S0)
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
+3V_S5
U18
U18
2
1
74AHC1G09
74AHC1G09
3 5
DPLL_REF_CLK#
CLOCKS
CLOCKS
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
C516
C516
0.1u/10V_4
0.1u/10V_4
4
BCLK
BCLK#
DPLL_REF_CLK
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
TRST#
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
+1.5V_CPU
wo eDP and dGPU
Connect DPLL_REF_SSCLK on Processor to GND through 1K ± 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K ± 5% resistor
CLK_CPU_BCLKP
A28
CLK_CPU_BCLKN
A27
CLK_DPLL_SSCLKP_R
A16
CLK_DPLL_SSCLKN_R
A15
CPU_DRAMRST#
R8
SM_RCOMP_0
AK1
SM_RCOMP_1
A5
SM_RCOMP_2
A4
CRB 1.0 : SM_RCOMP[2..0] W:20mils, S:15mils, L 500mils
XDP_PRDY #
AP29
XDP_PREQ #
AP27
XDP_TCLK
AR26
TCK
PCH_JTAG _TMS
AR27
TMS
XDP_TRST #
AP30
PCH_JTAG _TDI
AR28
TDI
PCH_JTAG _TDO
AP26
TDO
AL35
XDP_BPM0
AT28
XDP_BPM1
AR29
XDP_BPM2
AR30
XDP_BPM3
AT30
XDP_BPM4
AP32
XDP_BPM5
AR31
XDP_BPM6
AT31
XDP_BPM7
AR32
R461
R461
200/F_4
200/F_4
R459 130/F_4R459 130/F_4
R462 *39_4R462 *39_4
PM_DRAM_PWRGD_RPM_DRAM_PWRGD_Q
3
Q30 *2N7002KQ30 *2N7002K
Ra
3
1
R440 I V@0_4P2RR440 I V@0_4P2R
Rb
R442 DO@1K_4R442 DO@1K_4
Rc
R438 DO@1K_4R438 DO@1K_4
CPU_DRAMRST# [4]
R173 140/F_4R173 140/F_4
R458 25.5./F_4R458 25.5./F_4
R460 200/F_4R460 200/F_4
TP53TP53
TP18TP18
TP20TP20
TP19TP19
TP12TP12
TP56TP56
XDP_DBR ST# [7]
TP54TP54
TP55TP55
TP51TP51
TP52TP52
For XDP
TP49TP49
TP47TP47
TP50TP50
TP46TP46
1
2
MAINON_ON_G
4
2
+1.05V
MAINON_ON_G [5, 41]
CLK_CPU_BCLKP [9]
CLK_CPU_BCLKN [9]
CLK_DPLL_SSCLKP [9]
CLK_DPLL_SSCLKN [9]
EV UMA/OPT.
Ra
NA1K0 ohm
Rb
1K
Rc
NA
NA
FDI Disabling (Discrete Only)
9/26 add
FDI_INT
R444 DO@0_4R444 DO@0_4
R446 DO@0_4R446 DO@0_4
R441
R441
DO@1K/F_4
DO@1K/F_4
R443 DO@0_4R443 DO@0_4
R447
R447
DO@1K/F_4
DO@1K/F_4
A A
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
FDI_FSYNC can gang
all these 4
signals together
and tie them with
only one 1K
resistor to GND
(DG V0.5 Ch2.2.9).
5
DP & PEG Compensation
+1.05V
Routed within 25 mils
R433 24.9/F_4R433 24.9/F_4
eDP_COMPIO and ICOMPO signals should
be shorted near balls and routed with
typical impedance <25 mohms
eDP_COMP
+1.05V
Routed within 500 mils
R439 24.9/F_4R439 24.9/F_4
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
typical impedance = 43 mohms
PEG_ICOMPO signals should
be routed within 500 mils
typical impedance = 14.5 mohms
4
PEG_COM P
Processor pull-up(CPU)
H_PROCHOT#
PCH_JTAG _TDO
PCH_JTAG _TMS
PCH_JTAG _TDI
XDP_PREQ #
XDP_TCLK
XDP_TRST #
R122 62_4R122 62_4
R134 51_4R134 51_4
R135 51_4R135 51_4
R430 51_4R430 51_4
R132 *51_4R132 *51_4
R137 51_4R137 51_4
R128 51_4R128 51_4
3
+1.05V
9/27 modify
+1.05V
3
Q4
PM_THRM TRIP#
2
1 3
FDV301NQ4FDV301N
1
R86
R86
1K_4
1K_4
2
Q5
MMBT3904Q5MMBT3904
2
SYS_SHDN# [34,41]
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Date: Sheet of
Date: Sheet of
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
Date: Sheet
IMVP_PW RGD[7,35]
+1.05V[5,7,8,9,11,22,32,35,36,40,41]
+3V[7,8,9,10,11,13, 14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
IVY Bridge 1/4
IVY Bridge 1/4
IVY Bridge 1/4
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
1A
1A
1A
of
344
344
344
5
4
IVY Bridge Processor (DDR3)
U16C
U16C
3
U16D
U16D
2
1
M_A_DQ[63:0][13]
D D
C C
B B
M_A_BS#0[13]
M_A_BS#1[13]
M_A_BS#2[13]
M_A_CAS#[13]
M_A_RAS#[13]
M_A_WE#[13]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
K2
M8
N8
N7
M9
N9
M7
V6
J1
J5
J4
J2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLK0 [13]
M_A_CLK0# [13]
M_A_CKE0 [13]
M_A_CLK1 [13]
M_A_CLK1# [13]
M_A_CKE1 [13]
M_A_CS#0 [13]
M_A_CS#1 [13]
M_A_ODT0 [13]
M_A_ODT1 [13]
M_A_DQS#[7:0] [13]
M_A_DQS[7:0] [13]
M_A_A[15:0] [13]
M_B_DQ[63:0][14]
M_B_BS#0[14]
M_B_BS#1[14]
M_B_BS#2[14]
M_B_CAS#[14]
M_B_RAS#[14]
M_B_WE#[14]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
C8
D9
D8
G4
G1
G5
G2
J10
M5
N4
N2
N1
M4
N5
M2
M1
R6
A7
A9
A8
F4
F1
F5
F2
J7
J8
K9
J9
K8
K7
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_CLK0 [14]
M_B_CLK0# [14]
M_B_CKE0 [14]
M_B_CLK1 [14]
M_B_CLK1# [14]
M_B_CKE1 [14]
M_B_CS#0 [14]
M_B_CS#1 [14]
M_B_ODT0 [14]
M_B_ODT1 [14]
M_B_DQS#[7:0] [14]
M_B_DQS[7:0] [14]
M_B_A[15:0] [14]
Ivy Bridg e_rPGA_2DPC_Rev 0 p61
Ivy Bridg e_rPGA_2DPC_Rev 0 p61
+1.5VSUS
R503
R503
1K/F_4
A A
5
R502 1K/F_4R502 1K/F_4
DRAMRST_CNTRL_PCH[9,13,14]
4
1K/F_4
CD_DRAMRST#
Q36 2N7002KQ36 2N7002K
3
2
C547
C547
0.047u/16V_4
0.047u/16V_4
3
1
R500
R500
4.99K/F_4
4.99K/F_4
CPU_DRAMRST# [3]DDR3_DRAMRST#[13,14]
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
PROJECT :
IVY Bridge 2/4
IVY Bridge 2/4
IVY Bridge 2/4
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
444
444
444
1
1A
1A
1A
+
+
MAIND
8
7
5
C176
C176
C497
C497
22u/6.3V_8
22u/6.3V_8
*22u/6.3V_8
*22u/6.3V_8
C485
C485
C170
C170
22u/6.3V_8
22u/6.3V_8
*22u/6.3V_8
*22u/6.3V_8
C184
C184
C197
C197
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
C479
C479
C480
C480
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
C182
C182
*10u/6.3V_8
*10u/6.3V_8
C169
C169
+
+
*470u/2V_7343
*470u/2V_7343
JP12
JP12
*SHORT_PAD
*SHORT_PAD
Q34 AO4496Q34 AO4496
4
C543
C543
*470p/50V_4
*470p/50V_4
MAINON_ON_G
5
C187
C187
22u/6.3V_8
22u/6.3V_8
C181
C181
22u/6.3V_8
22u/6.3V_8
C491
C491
10u/6.3V_8
10u/6.3V_8
C481
C481
10u/6.3V_8
10u/6.3V_8
10uF (Reserved)
C205
C205
*10u/6.3V_8
*10u/6.3V_8
+1.5V_CPU+1.5VSUS
+1.5V_CPU
12
1
2
36
2
5
IVY Processor (POWER)
U16F
U16F
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
C186
C186
22u/6.3V_8
22u/6.3V_8
C486
C486
22u/6.3V_8
22u/6.3V_8
C496
C496
10u/6.3V_8
10u/6.3V_8
C194
C194
10u/6.3V_8
10u/6.3V_8
C195
C195
*10u/6.3V_8
*10u/6.3V_8
C168
C168
+
+
*470u/2V_7343
*470u/2V_7343
R466
R466
220_8
220_8
3
Q29
Q29
DMN601K-7
DMN601K-7
1
+VCC_CORE
POWER
POWER
CORE SUPPLY
CORE SUPPLY
+1.05V[3,7,8,9,11,22,32,35,36,40,41]
+VCC_CORE[35]
+1.8V[8,10,11,41]
+VCC_GFX[35]
+1.5V_CPU[3]
+VDDR_REF_CPU
+VCCSA[38]
CPU Core Power
IVY 45W:TDC 52A
IVY SPEC
D D
22uF_8 x8 Socket TOP cavity
22uF_8 x10 Socket BOT cavity
22uF_8 x8 Socket TOP edge
470uF_7343 x4
total : 10uF x 10 , RSVD x 1
total : 22uF x 16 , RSVD x 3
tatal : 470u x 4, RSVD x2
SNB : Spec
470uF/4mohm x 4
22uF x 16
10uF x 10
C185
C185
22u/6.3V_8
22u/6.3V_8
C211
C211
22u/6.3V_8
22u/6.3V_8
C C
B B
C489
C489
22u/6.3V_8
22u/6.3V_8
C201
C201
*22u/6.3V_8
*22u/6.3V_8
C191
C191
22u/6.3V_8
22u/6.3V_8
C193
C193
+
+
330u/2V_7343
330u/2V_7343
Cose down
330uF x2
22uF x 4
10uF x 20
reserved x 5
C498
C498
22u/6.3V_8
22u/6.3V_8
C487
C487
22u/6.3V_8
22u/6.3V_8
C490
C490
10u/6.3V_8
10u/6.3V_8
C199
C199
*10u/6.3V_8
*10u/6.3V_8
C189
C189
22u/6.3V_8
22u/6.3V_8
C200
C200
330u/2V_7343
330u/2V_7343
4.5A
A A
MAINON_ON_G[3,41]
4
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
PEG AND DDR
PEG AND DDR
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
4
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
CPU VTT
IVY 45W:8.5A
SNB : Spec
330uF/6mohm x 2
22uF x 12
+1.05V
22uF x 7 (Non-stuff)
C506
C506
22u/6.3V_8
22u/6.3V_8
C508
C508
22u/6.3V_8
22u/6.3V_8
C202
C202
*22u/6.3V_8
*22u/6.3V_8
+1.05V_VTT_40
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R100 0_4R100 0_4
R99 0_4R99 0_4
VTT_VCCP_SENSE
VTT_VSSP_SENSE
Trace Route to Power IC area.
Cose down
330uF x1
22uF x 2
10uF x 10
reserved x 4
+
+
+
+
C511
C511
330u/2V_7343
330u/2V_7343
IVY SPEC
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2
R436 *SHORT_4R 436 *SHORT_4
C198
C198
22u/6.3V_8
22u/6.3V_8
C507
C507
22u/6.3V_8
22u/6.3V_8
C495
C495
*22u/6.3V_8
*22u/6.3V_8
C213
C213
330u/2V_7343
330u/2V_7343
C209
C209
22u/6.3V_8
22u/6.3V_8
C215
C215
22u/6.3V_8
22u/6.3V_8
C500
C500
*22u/6.3V_8
*22u/6.3V_8
+1.05V
CPU VCCPL
IVY 45W:1.5A
Spec
330uF/7mohm x 1
10uF x 1
1uF x 2
IVY SPEC
330uF x1, 10uF_8 x1, 1uF_4 x2
Socket BOT edge.
+VCC_GFX[35]
+VCC_CORE[35]
R83 100/F_4R83 100/F_4
R82 100/F_4R82 100/F_4
R456 10/F_4R456 10/F_4
R457 10/F_4R457 10/F_4
+VCC_CORE
VTT_VCCP_SENSE [36]
VTT_VSSP_SENSE [36]
C509
C509
22u/6.3V_8
22u/6.3V_8
C501
C501
22u/6.3V_8
22u/6.3V_8
C494
C494
*22u/6.3V_8
*22u/6.3V_8
C212
C212
22u/6.3V_8
22u/6.3V_8
C503
C503
22u/6.3V_8
22u/6.3V_8
C512
C512
*22u/6.3V_8
*22u/6.3V_8
+1.8V
Real
10uF x 1
1uF x 2
VCC_SENSE [35]
VSS_SENSE [35]
+1.05V
3
CPU VGT
IVY 45W:TDC 38A
Spec
470uF/4mohm x 2
22uF x 12
+VCC_GFX
C510
C510
22u/6.3V_8
22u/6.3V_8
C505
C505
22u/6.3V_8
22u/6.3V_8
C515
C515
*22u/6.3V_8
*22u/6.3V_8
+
+
C502
C502
IV@330u/2V_7343
IV@330u/2V_7343
C477
C477
IV@22u/6.3V_8
IV@22u/6.3V_8
C484
C484
*IV@22u/6.3V_8
*IV@22u/6.3V_8
C183
C183
*IV@22u/6.3V_8
*IV@22u/6.3V_8
C488
C488
IV@22u/6.3V_8
IV@22u/6.3V_8
Cose down
330uF x1
22uF x 4
10uF x 10
IV@22u/6.3V_8
IV@22u/6.3V_8
*IV@22u/6.3V_8
*IV@22u/6.3V_8
*IV@22u/6.3V_8
*IV@22u/6.3V_8
IV@22u/6.3V_8
IV@22u/6.3V_8
R157 DO@0/J_4R157 DO@0/J_4
ZĂ ϬŽŚŵ
R476 0_8R476 0_8
R470 0_8R470 0_8
Layout note: need routing
together and ALERT need
between CLK and DATA
H_CPU_SVIDCLK
Place PU resistor close to CPU
H_CPU_SVIDDAT
CPU_VCCPLL
C537
C537
10u/6.3V_8
10u/6.3V_8
R78 *SHORT_4R78 *SHORT_4
+1.05V
R97
R97
130/F_4
130/F_4
Place PU resistor close to CPU
H_CPU_SVIDALRT#
3
R95 43_4R95 43_4
IVY SPEC
22uF_8 x2 Socket TOP cavity
22uF_8 x2 Socket BOT cavity
22uF_8 x4 Socket TOP edge
22uF_8 x4 Socket BOT edge
470uF_7343 x2
+
C493
C493
IV@22u/6.3V_8
IV@22u/6.3V_8
C190
C190
IV@22u/6.3V_8
IV@22u/6.3V_8
C179
C179
IV@22u/6.3V_8
IV@22u/6.3V_8
C482
C482
IV@22u/6.3V_8
IV@22u/6.3V_8
+
C514
C514
*IV@330u/2V_7343
*IV@330u/2V_7343
C470
C470
IV@22u/6.3V_8
IV@22u/6.3V_8
C180
C180
IV@22u/6.3V_8
IV@22u/6.3V_8
C178
C178
IV@22u/6.3V_8
IV@22u/6.3V_8
C492
C492
IV@22u/6.3V_8
IV@22u/6.3V_8
C471
C471
C472
C472
C473
C473
C499
C499
+
+
C233
C233
IV@330u/2V_7343
IV@330u/2V_7343
ZĂ
/^s'EhDKƉƚŝŵƵƐ
C528
C528
C529
C529
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
Remove PU resistor 54.9/F,
stuff at IMVP7 page
Remove PU resistor 130/F,
stuff at IMVP7 page
R80 *SHORT_4R80 *SHORT_4
+1.05V
R96
R96
75_4
75_4
R79 *SHORT_4R79 *SHORT_4
+
+
C535
C535
*330u/2V_7343
*330u/2V_7343
2
IVY Bridge Processor (GRAPHIC POWER)
U16G
U16G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
SVID CLK
VR_SVID _CLK [35]
SVID DATA
VR_SVID _DATA [35 ]
SVID ALERT
VR_SVID _ALERT# [35]
2
POWER
POWER
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
SA_DIMM_VREFDQ
VREFMISC
VREFMISC
SB_DIMM_VREFDQ
GRAPHICS
GRAPHICS
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
1.8V RAIL
1.8V RAIL
VCCIO_SEL
IVY SPEC
330uF x1, 10uF_8 x1 Socket BOT edge,
10uF_8 x2 Socket BOT cavity.
CPU SA
IVY 45W: 6A
Spec
330uF/7mohm x 1
10uF x 3
SM_VREF
0929 change value by CRB
AK35
AK34
10 mil
+VDDR_REF_CPU
AL1
Rb4
B4
D1
Rd1
IVY SPEC
330uF x1, 10uF_8 x6 Socket BOT edge.
AF7
VDDQ1
AF4
VDDQ2
AF1
VDDQ3
AC7
VDDQ4
AC4
VDDQ5
AC1
VDDQ6
Y7
VDDQ7
Y4
VDDQ8
Y1
VDDQ9
U7
VDDQ10
U4
VDDQ11
U1
VDDQ12
P7
VDDQ13
P4
VDDQ14
P1
VDDQ15
M27
VCCSA1
M26
VCCSA2
L26
VCCSA3
J26
VCCSA4
J25
VCCSA5
J24
VCCSA6
H26
VCCSA7
H25
VCCSA8
H23
C22
C24
VCCIO_SEL_NCVCCIO_SEL_NC
A19
Voltage selection for VCCIO:
this pin must be pulled high
on the motherboard
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
Real
10uF x 3
R492 *0_8R492 *0_8
3
MAIND[34,37,41]
MAIND
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
R81 IV@10/F_4R81 IV@10/F_4
R98 IV@10/F_4R98 IV@10/F_4
R234 *1K_4R234 *1K_4
R239 *1K_4R239 *1K_4
C526
C526
10u/6.3V_8
10u/6.3V_8
C236
C236
10u/6.3V_8
10u/6.3V_8
C196
C196
10u/6.3V_8
10u/6.3V_8
2
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
1
+VCC_GFX
+VDDR_REF_CPU
C534
C534
C524
C524
10u/6.3V_8
10u/6.3V_8
C234
C234
*10u/6.3V_8
*10u/6.3V_8
C188
C188
10u/6.3V_8
10u/6.3V_8
VCCSA_SENSE [38]
VCCSA_VID0 [38]
VCCSA_VID1 [38]
TP57TP57
+VDDR_REF_CPU+SMDDR_VREF +1.5VSUS
1
Q32
Q32
2N7002K
2N7002K
IVY Bridge 3/4
IVY Bridge 3/4
IVY Bridge 3/4
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
C533
C533
C229
C229
*10u/6.3V_8
*10u/6.3V_8
C192
C192
10u/6.3V_8
10u/6.3V_8
R499
R499
100K_4
100K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
VCC_AXG_SENSE [35]
VSS_AXG_SENSE [35]
For M3 solution
need Rb4, Rd1
W/O M3 then NC
ball B4 and D1
SMDDR_VREF_DQ0_M3 [13]
SMDDR_VREF_DQ1_M3 [14]
+1.5V_CPU
C531
C531
C232
C232
10u/6.3V_8
10u/6.3V_8
+
+
330u/2V_7343
330u/2V_7343
+VCCSA
+
+
C415
C415
330u/2V_7343
330u/2V_7343
CPU MCH
IVY 45W: 5A
Spec
330uF/6mohm x 1
10uF x 6
Real
10uF x 8
R497
R497
*1K/F_4
*1K/F_4
R498
R498
*1K/F_4
*1K/F_4
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
544
544
544
1A
1A
1A
5
4
3
2
1
IVY Bridge Processor (GND)
U16H
U16H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
D D
C C
B B
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
AT7
AT4
AT3
AR7
AR4
AR2
AP7
AP4
AP1
AN7
AN4
AL7
AL4
AL2
AK7
AK4
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
K35
K32
K29
K26
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
U16I
U16I
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
VSS199
VSS200
VSS201
VSS202
J34
VSS203
J31
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
IVY Bridge Processor (RESERVED, CFG)
U16E
U16E
VCC_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD56
RSVD57
RSVD58
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
VSS_DIE_SENSE
Rs
TP16TP16
TP13TP13
TP17TP17
TP10TP10
TP15TP15
XDP_CFG0
CFG1
CFG2
CFG3
CFG4CFG4
CFG5
CFG6
CFG7CFG7
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
CFG
CFG
RESERVED
RESERVED
VCC_DIE_SENSE
VSS_DIE_SENSE
R136
R136
*SP@0_4
*SP@0_4
TP8TP8
TP9TP9
TP43TP43
TP44TP44
TP14TP14
TP21TP21
For Sandy For IVY
Rs
Stuff NC
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
Processor Strapping
The CFG signals have a default value of '1' if not terminated on t he board.
10
CFG2
A A
(PEG Static Lane Reversal)
CFG4
(DP Presence Strap)
CFG7
(PEG Defer Training)
Normal Operation
Disable; No physical DP attach ed to eDP
PEG train immediately foll o wing
xxRESETB de assertion
5
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
Lane Reversed
Enable; An ext DP device is connected to eDP
PEG wait for BIOS training
4
9/26 modify
CFG2
R133 1K/F_4R133 1K/F_4
CFG4
R129 IV@1K/F_4R129 IV@1K/F_4
CFG7
R123 *1K/F_4R123 *1K/F_4
CFG5
R130 *1K/F_4R130 *1K/F_4
CFG6
R127 *1K/F_4R127 *1K/F_4
eDP_EN# [22]
3
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docume nt Number Rev
Size Docume nt Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Friday, November 11, 2011
Friday, November 11, 2011
2
Friday, November 11, 2011
PROJECT :
IVY Bridge 4/4
IVY Bridge 4/4
IVY Bridge 4/4
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
644
644
644
1A
1A
1A
of
5
+1.05V[3,5,8,9,11,22,32,35,36,40,41]
+3V9,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+3V_S5[3,8,9,10,11,15,28,30,31,34,35,36,41,42]
CPT/PPT (DMI,FDI,PM)
U20C
U20C
D D
C C
XDP_DBRST#[3]
SYS_PWROK
PWROK_EC
PM_DRAM_PWRGD[3]
PCH_RSMRST#[32]
DNBSWON#[32]
B B
+1.05V
SUS_PWR_ACK
R583 *0_4R583 *0_4
DMI_RXN0[3]
DMI_RXN1[3]
DMI_RXN2[3]
DMI_RXN3[3]
DMI_RXP0[3]
DMI_RXP1[3]
DMI_RXP2[3]
DMI_RXP3[3]
DMI_TXN0[3]
DMI_TXN1[3]
DMI_TXN2[3]
DMI_TXN3[3]
DMI_TXP0[3]
DMI_TXP1[3]
DMI_TXP2[3]
DMI_TXP3[3]
R521 49.9/F_4R521 49.9/F_4
R527 750/F_4R527 750/F_4
R539 *0_4R539 *0_4
C607 *1u/10V_4C607 *1u/10V_4
XDP_DBRST#
PM_DRAM_PWRGD
PCH_RSMRST#
SUS_PWR_ACK
AC_PRESENT
PM_BATLOW#
PM_RI#
DMI_COMP
SUSACK#_R
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PANTHER POINT
PANTHER POINT
DMI
FDI
DMI
FDI
+3V
CLKRUN# / GPIO32
+3V_S5
SUS_STAT# / GPIO61
+3V_S5
+3V_S5
SLP_S5# / GPIO63
+3V_S5
System Power Management
System Power Management
DSW
+3V_S5
+3V_S5
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_IN T
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
SUSCLK / GPIO62
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
4
3
2
1
CPT/PPT (LVDS,DDI)
U20D
U20D
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
PCH_RSMRST#
PCIE_WAKE#
CLKRUN#
SUS_STAT#
PCH_SUSCLK
PCH_SLP_S5#
SLP_A#
SLP_SUS#
SLP_LAN#
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
J47
M45
P45
T40
K47
T45
P39
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
PANTHER POINT
PANTHER POINT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
INT_LVDS_BLON[22]
INT_LVDS_DIGON[22]
INT_LVDS_BRIGHT[22]
FDI_TXN0 [3]
FDI_TXN1 [3]
FDI_TXN2 [3]
FDI_TXN3 [3]
FDI_TXN4 [3]
FDI_TXN5 [3]
FDI_TXN6 [3]
FDI_TXN7 [3]
FDI_TXP0 [3]
FDI_TXP1 [3]
FDI_TXP2 [3]
FDI_TXP3 [3]
FDI_TXP4 [3]
FDI_TXP5 [3]
FDI_TXP6 [3]
FDI_TXP7 [3]
FDI_INT [3]
FDI_FSYNC0 [3]
FDI_FSYNC1 [3]
FDI_LSYNC0 [3]
FDI_LSYNC1 [3]
DSWVREN [8]
PCIE_WAKE# [28]
CLKRUN# [32]
T15T15
T12T12
T14T14
SUSC# [32]
SUSB# [32]
SLP_A# [32]
T10T10
10/31 modify
PM_SYNC [3]
INT_HSYNC[22]
INT_VSYNC[22]
The required series-resistors are:
ɄɄɄɄ
Direct Connect - 33 ȍ
ɄɄɄɄ
Docking Topology - 20 ȍ
R place close to PCH
R483 IV@150/F_4R483 IV@150/F_4
R482 IV@150/F_4R482 IV@150/F_4
R484 IV@150/F_4R484 IV@150/F_4
INT_LVDS_EDIDCLK[22]
INT_LVDS_EDIDDATA[22]
+3V
INT_TXLCLKOUT-[22]
INT_TXLCLKOUT+[22]
INT_TXLOUT0-[22]
INT_TXLOUT1-[22]
INT_TXLOUT2-[22]
INT_TXLOUT0+[22]
INT_TXLOUT1+[22]
INT_TXLOUT2+[22]
INT_CRT_BLU[22]
INT_CRT_GRN[22]
INT_CRT_RED[22]
INT_CRT_DDCCLK[22]
INT_CRT_DDCDAT[22]
R126 IV@33_4R126 IV@33_4
R125 IV@33_4R125 IV@33_4
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
R164 2.2K_4R164 2.2K_4
R188 2.2K_4R188 2.2K_4
R186 2.37K/F_4R186 2.37K/F_4
T7T7
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
DAC_IREF
R187
R187
1K/F_4
1K/F_4
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
INT_HDMITX2N_R
INT_HDMITX2P_R
INT_HDMITX1N_R
INT_HDMITX1P_R
INT_HDMITX0N_R
INT_HDMITX0P_R
INT_HDMICLK-_R
INT_HDMICLK+_R
DDPC_HPD_PU
DDPD_HPD_PU
RP18 IV@0_4P2RRP18 IV@0_4P2R
4
3
2
RP19 IV@0_4P2RRP19 IV@0_4P2R
RP20 IV@0_4P2RRP20 IV@0_4P2R
RP21 IV@0_4P2RRP21 IV@0_4P2R
DDPC_HPD_PU
DDPD_HPD_PU
1
4
3
2
1
4
3
2
1
4
3
2
1
R169 *2.2K_4R169 *2.2K_4
R197 *2.2K_4R197 *2.2K_4
0 : Port not detected
HDMI_DDCCLK_SW [23]
HDMI_DDCDATA_SW [23]
HDMI_HP [23]
INT_HDMITX2N [23]
INT_HDMITX2P [23]
INT_HDMITX1N [23]
INT_HDMITX1P [23]
INT_HDMITX0N [23]
INT_HDMITX0P [23]
INT_HDMICLK- [23]
INT_HDMICLK+ [23]
INT. HDMI
PCH Pull-high/low(CLG)
+3V
CLKRUN#
R584 8.2K_4R584 8.2K_4
XDP_DBRST#
R567 4.99K/F_4R567 4.99K/F_4
R554 *1K_4R554 *1K_4
PCH_RSMRST#
SYS_PWROK
R219 10K_4R219 10K_4
R601 *10K_4R601 *10K_4
A A
CRB 1.0 change R8315 to 1K
PM_RI#
PM_BATLOW#
PCIE_WAKE#
SLP_LAN#
SUS_PWR_ACK
AC_PRESENT
PM_DRAM_PWRGD
R545 10K_4R545 10K_4
R282 8.2K_4R282 8.2K_4
R261 10K_4R261 10K_4
R230 *10K_4R230 *10K_4
R538 10K_4R538 10K_4
R220 10K_4R220 10K_4
R232 200/F_4R232 200/F_4
+3V_S5
System PWR_OK(CLG)
to PCH Pin12, XDP and EE debug
SYS_PWROK[3]
SYS_PWROK
U24
U24
4
TC7SH08FU
TC7SH08FU
wo S3 leakage, remove R
5
4
IMVP_PWRGD PU +3V
PWROK_EC PD
+3V_S5
so AND gate output dont need PD again
C629
C629
*0.1u/10V_4
*0.1u/10V_4
2
PWROK_EC
1
3 5
R594
R594
100K_4
100K_4
3
IMVP_PWRGD [3,35]
PWROK_EC [32]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Friday, November 11, 2011
Friday, November 11, 2011
2
Friday, November 11, 2011
PROJECT :
Panther Point 1/6
Panther Point 1/6
Panther Point 1/6
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
744
744
744
1A
1A
1A
5
RTC Circuitry(RTC)
20mils
R445 0_6R445 0_6
+3VPCU
20MIL
20MIL
D D
R448
R448
1K_4
1K_4
CN11
CN11
1
2
RTC_CON.
RTC_CON.
+3V_RTC_1
10/5 chnage footprint & PN
HDA Bus(CLG)
PCH JTAG Debug (CLG)
C C
PCH Dual SPI (CLG)
+3V_M
10/31 add
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
B B
SPI_CS0#_UR_ME[32]
R328 3.3K_4R328 3.3K_4
PCH_SPI_CS1#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
R339 3.3K_4R339 3.3K_4
+3V_PCH_ME
+3V_PCH_ME
A A
+3V_RTC
D11
D11
R596 20K_4R596 20K_4
C614
+3V_S5
C614
1u/6.3V_4
1u/6.3V_4
C612
C612
1u/6.3V_4
1u/6.3V_4
CN13
DFWF02MS118
R202 33_4R202 33_4
R176 33_4R176 33_4
R198 33_4R198 33_4
R506 33_4R506 33_4
BAT54C
BAT54C
30mils
R593 20K_4R593 20K_4
C620
C620
1u/6.3V_4
1u/6.3V_4
PCH_AZ_CODEC_BITCLK[26]
PCH_AZ_CODEC_SYNC[26]
PCH_AZ_CODEC_RST#[26]
PCH_AZ_CODEC_SDOUT[26]
RTC_RST#
12
J1
J1
*SHORT_PAD
*SHORT_PAD
SRTC_RST#
12
J2
J2
*SHORT_PAD
*SHORT_PAD
ACZ_BITCLK_R
ACZ_SYNC_CODEC
ACZ_RST#_R
ACZ_SDOUT_R
9/27 add
R293
R292
R292
210/F_4
210/F_4
R279
R279
100/F_4
100/F_4
R293
210/F_4
210/F_4
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TCK
PCH_JTAG_TDO_R
R280
R280
100/F_4
100/F_4
R553
R553
51_4
51_4
R564
R564
210/F_4
210/F_4
R552
R552
*100/F_4
*100/F_4
(Default for WIN8)
W25Q32BVSSIG / AKE391P0N00----->4MB
W25Q16BVSSIG / AKE38FP0N01----->2MB
for BA W25Q64BVSSIG / AKE3EFP0N00----->8MB
R319 VA@0_6R319 VA@0_6
R551 BA@0_6R551 BA@0_6
10/11 add
R324 33_4R324 33_4
R334 33_4R334 33_4
R322 33_4R322 33_4
C344
C344
*22p/50V_4
*22p/50V_4
10/11 add
R325 33_4R325 33_4
R333 33_4R333 33_4
R326 33_4R326 33_4
C343
C343
*22p/50V_4
*22p/50V_4
+3VPCU[22,25,30,31,32,33,34,41,42]
+5V[11,22,23,25,26,31,34,41]
+3V_S5[3,7,9,10,11,15,28,30,31,34,35,36,41,42]
+1.05V[3,5,7,9,11,22,32,35,36,40,41]
+3V23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+1.8V[5,10,11,41]
5
1
6
5
2
3
1
6
5
2
3
U6
CE#
SCK
SI
SO
WP#
ROM-2MU6ROM-2M
U8
CE#
SCK
SI
SO
WP#
ROM-4MU8ROM-4M
8
VDD
R320 3.3K_4R320 3.3K_4
7
HOLD#
4
VSS
8
VDD
R335 3.3K_4R335 3.3K_4
7
HOLD#
4
VSS
R321 *0_4R321 *0_4
R331 0_4R331 0_4
+3V_PCH_ME+3V_S5
+3V_PCH_ME
+3V_PCH_ME
battery
AHL03003022
AHL03003024
C338
C338
0.1u/10V_4
0.1u/10V_4
C351
C351
0.1u/10V_4
0.1u/10V_4
PCH_SPI_CS0#
PCH_SPI_CS1#
4
3
PCH2(CLG)
C564 18p/50V_4C564 18p/50V_4
C563 18p/50V_4C563 18p/50V_4
Add MOSFET to separate CODEC SYNC signal
ACZ_SYNC_CODEC
+5V
CRB 1.0
R201 10K_4R201 10K_4
1
R175
R175
1M_4
1M_4
2
Q13
Q13
2N7002K
2N7002K
PCH_SPI_CLK[32]
PCH_SPI_SI[32]
PCH_SPI_SO[32]
32.768KHZY332.768KHZ
+3V_RTC
3
PCH_AZ_CODEC_SDIN0[26]
+3VPCU
23
Y3
4 1
R216 1M_4R216 1M_4
R336 10K_4R336 10K_4
R524
R524
10M_4
10M_4
SPKR[26]
TP25TP25
TP60TP60
TP28TP28
PCH Strap Table
Pin Name
Strap description
No reboot mode setting PWROKSPKR
GNT3# / GPIO55 Top-Block Swap Override
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up
GNT1# / GPIO51
GPIO19
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
HDA_SDO Flash Descriptor Security RSMRST
DF_TVS
GPIO28
DMI/FDI Termination voltage
On-die PLL Voltage Regulator RSMRST#
HDA_SYNC On-Die PLL VR Voltage Select RSMRST
GPIO15
DSWVREN DSW
NV_ALE
4
Intel ME Crypto Transport Layer
Security (TLS) cipher suit e
internal PD
DEEP S4/S5 well
On Die DSW VR Enable
Intel Anti-Theft HDD protection
Only for Interposer
Sampled
Configuration
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
PWROK
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
PWROK
PWROK
0 = effect (default)(weak pull-down 20K)
1 = overridden
PWROK
0 = Set to Vss (weak pull-down 20K)
1 = Set to Vcc
0 = Disable
1 = Enable (weak pull-up 20K)
0 = Support by 1.8V (weak pull-down)
1 = Support by 1.5V
RSMRST
0 = Disable (Default)
1 = Enable
High = Enable (Default)
Low = Disable
PWROK 0 = Disable (Internal pull-down 20kohm)
3
CPT/PPT (HDA,JTAG,SATA)
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BITCLK_R
ACZ_SYNC_R
SPKR
ACZ_RST#_R
ACZ_SDOUT_R
PCH_GPIO33
PCH_GPIO13
PCH_JTAG_TCK
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
GNT0#GNT1#
11
00
U20A
U20A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER POINT
PANTHER POINT
Boot Location
SPI
*
LPC
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
+3V
+3V
+3V_RTC
+3V_RTC
+3V
+3V
+3V_S5
ME_WR[32]
+3V_S5
+1.8V
2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
R301 *1K_4R301 *1K_4
+3V
R171 *1K_4R171 *1K_4
R526 330K_4R526 330K_4
R473 *1K_4R473 *1K_4
R558 *1K_4R558 *1K_4
R548 2.2K_4R548 2.2K_4
R546 1K_4R546 1K_4
R277 *1K_4R277 *1K_4
+3V_S5
R563 1K_4R563 1K_4
R530 330K_4R530 330K_4
R528 *330K_4R528 *330K_4
R308 *1K_4R308 *1K_4
2
C38
A38
B37
C37
D36
PCH_DRQ#0
E36
PCH_DRQ#1
K36
V5
R287 8.2K_4R287 8.2K_4
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
SATA_COMP
Y10
SATA3_COMP
AB12
AB13
SATA3_RBIAS
AH1
SATA_ACT#
P3
SATA0GP
V14
BBS_BIT0
P1
SPKR
R505 *SHORT_4R505 *SHORT_4
+1.8V
R177 1K_4R177 1K_4
R570 10K_4R570 10K_4
R274 10K_4R274 10K_4
PCI_GNT3# [9]
PCH_INVRMEN
BBS_BIT0
H_SNB_IVB# [3]
DF_TVS [10]
PLL_ODVR_EN [10]
ACZ_SYNC_R
PCH_GPIO15 [10]
DSWVREN [7]
NV_ALE [9]
TP24TP24
TP23TP23
+3V
R236 37.4/F_4R236 37.4/F_4
R231 49.9/F_4R231 49.9/F_4
R561 750/F_4R561 750/F_4
BBS_BIT1 [9]
ACZ_SDOUT_R
0930
1
LPC_LAD0 [24,32]
LPC_LAD1 [24,32]
LPC_LAD2 [24,32]
LPC_LAD3 [24,32]
LPC_LFRAME# [24,32]
IRQ_S ERIRQ [32]
SATA_RXN0_C [25]
SATA_RXP0_C [25]
SATA_TXN0 [25]
SATA_TXP0 [25]
SATA_RXN_SSD [24]
SATA_RXP_SSD [24]
SATA_TXN_SSD [24]
SATA_TXP_SSD [24]
DG recommended that AC coupling capacitors should be
TP64TP64
close to the connector (<100 mils) for optimal signal quality.
TP65TP65
TP37TP37
SATA_RXN5_C [25]
SATA_RXP5_C [25]
SATA_TXN5 [25]
SATA_TXP5 [25]
+1.05V
+3V
SATA_ACT# [31]
+3V
SATA0GP/GPIO21
SATA4GP/GPIO16
SATA5GP/GPIO49
If these pins are unused use 8.2k
to 10k pull-up to +Vcc3_3 or 8.2k
to 10k pull-down to ground
SATA HDD
SSD
SATA ODD
Used as GPIO only. at chklist 1.2
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
ME_WR default EC setting folating
for future CPU, Sandy Bridge NC
DF_TVS needs to be pulled up to VccDFTERM power rail
through 2.2 kOhm ±5% - R8361 change to 0 or not??
Needs to be pulled High for Huron River platform.
chklist 1.2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Panther Point 2/6
Panther Point 2/6
Panther Point 2/6
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
844
844
844
1A
1A
1A
5
+3V13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+3V_S5[3,7,8,10,11,15,28,30,31,34,35,36,41,42]
+1.05V[3,5,7,8,11,22,32,35,36,40,41]
CPT/PPT (PCI,USB,NVRAM)
U20E
U20E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AW30
AH37
AK43
AK45
AH12
AB46
AB45
AY16
BG46
BE28
BC30
BE32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
C18
N30
AM4
AM5
Y13
K24
L24
B21
M20
BJ32
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
H49
H43
J48
K42
H40
TP7
TP8
TP9
TP10
TP11
H3
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#
C6
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PANTHER POINT
PANTHER POINT
USB30_RX1N
USB30_RX2N
USB30_RX3N
USB30_RX4N
USB30_RX1P
USB30_RX2P
USB30_RX3P
USB30_RX4P
USB30_TX1N
USB30_TX2N
USB30_TX3N
USB30_TX4N
USB30_TX1P
USB30_TX2P
USB30_TX3P
USB30_TX4P
RSVD
RSVD
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
PCI
PCI
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
D D
TX AC cap place at connector side, AC cap to
connector < 400mils
h^ϯϬ
C C
11/2 modify
B B
USB30_RX3-[30]
USB30_RX3+[30]
USB30_TX3-[30]
USB30_TX3+[30]
BBS_BIT1[8]
BOARD_ID2[10]
PCI_GNT3#[8]
G_SENSOR_INT#_PCH[25]
dGPU_PWR_EN[40]
DGPU_HOLD_RST#[15]
PCI_PLTRST#[3]
CLK_PCI_FB CLK_PCI_FB_C
R485 22_4R485 22_4
CLK_LPC_DEBUG[24]
CLK_PCI_775[32]
R183 22_4R183 22_4
R184 22_4R184 22_4
TP62TP62
TP61TP61
TP30TP30
TP26TP26
TP29TP29
TP27TP27
G_SENSOR_INT#_PCH
dGPU_PWR_EN
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH
TP32TP32
TP22TP22
USB30_RX3USB30_RX4-
USB30_RX3+
USB30_RX4+
USB30_TX1-
USB30_TX3USB30_TX4USB30_TX1+
USB30_TX3+
USB30_TX4+
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
dGPU_EDIDSEL#
dGPU_SELECT#
REQ#3
PCI_PME#
PCI_PLTRST#
CLK_LPC_DEBUG_C
CLK_PCI_775_C
USB
USB
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
4
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
USBP0-
C24
USBP0+
A24
C25
B25
C26
A26
USBP3-
K28
USBP3+
H28
E28
D28
USBP5-
C28
USBP5+
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB_BIAS
C33
B33
USB_OC0#
A14
USB_OC1#
K20
USB_OC2#
B17
USB_OC3#
C16
USB_OC4#
L16
USB_OC5#
A16
USB_OC6#
D14
USB_OC7#
C14
NV_ALE [8]
Port1 and port9 can be used on debug mode
T41T41
T40T40
Reserve for USB I/O function
USBP1- [30]
USB/B-USB1-1/USB debug
USBP1+ [30]
USBP2- [30]
MB USB
USBP2+ [30]
USBP3- [24]
Mini-SSD
USBP3+ [24]
USBP4- [30]
BLUETOOTH
USBP4+ [30]
T39T39
T38T38
Reserve for SIM card
USB port6/7 may not be available on all PCH sku
(HM55 support 12port only)
USBP8- [22]
Camera
USBP8+ [22]
USBP9- [30]
USB/B-USB1-2
USBP9+ [30]
USBP10- [24]
Mini Card (WLAN)
USBP10+ [24]
Reserve for card reader
Reserve for Touch pad
Reserve for FP
R507 22.6/F_4R507 22.6/F_4
USB_OC0# [30]
USB_OC1# [30]
XHCI for USBP0-3
EHCI1
EHCI2
Wireless
LAN
Wireless
LAN
3
CPT/PPT (PCI-E,SMBUS,CLK)
BG34
BJ34
AV32
AU32
BE34
BF34
BB32
AY32
PCIE_TXN3_C
PCIE_TXP3_C
PCIE_TXN8_C
PCIE_TXP8_C
AW38
BG36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BG38
AU36
AV36
BG40
AY40
BB40
BE38
BC38
AY38
AB49
AB47
AA48
AA47
AB42
AB40
AK14
AK13
BJ36
BJ38
BJ40
Y40
Y39
J2
M1
V10
Y37
Y36
A8
Y43
Y45
L12
V45
V46
L14
E6
V40
V42
T13
V38
V37
K12
CLK_PCH_SRC5#[24]
CLK_PCH_SRC5[24]
PCIE_CLK_REQ5#[24]
CLK_PCIE_LAN_REQ#[28]
PCIE_RX3-[28]
PCIE_RX3+[28]
PCIE_TX3-[28]
PCIE_TX3+[28]
PCIE_RX8-[24]
PCIE_RX8+[24]
PCIE_TX8-[24]
PCIE_TX8+[24]
CLK_PCIE_LOM#[28]
CLK_PCIE_LOM[28]
For XDP
C252 0.1u/10V_4C252 0.1u/10V_4
C249 0.1u/10V_4C249 0.1u/10V_4
C250 0.1u/10V_4C250 0.1u/10V_4
C253 0.1u/10V_4C253 0.1u/10V_4
T6T6
T8T8
T11T11
T13T13
PCIE_CLK_USB30_REQ#
PCIE_CLKREQ1#
PCIE_CLK_REQ2#
PCIE_CLKREQ3#
PCIE_CLKREQ4#
CLK_PCH_SRC5#
CLK_PCH_SRC5
PCIE_CLKREQ5#
CLK_PCIE_LOM#
CLK_PCIE_LOM
CLK_PCIE_LAN_REQ#
CLK_PCH_SRC6P
CLK_PCIE_REQ6#
CLK_PCH_SRC7P
CLK_PCIE_REQ7#
CLK_ITPN
CLK_ITPP
2
U20B
U20B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3# / GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
PANTHER POINT
PANTHER POINT
+3V_S5
+3V_S5
SMBUSController
SMBUSController
+3V_S5
SML1ALERT# / PCHHOT# / GPIO74
+3V_S5
+3V_S5
PCI-E*
PCI-E*
+3V_S5
+3V_S5
CLOCKS
CLOCKS
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V
+3V
SMBALERT# / GPIO11
SMBDATA
SML0ALERT# / GPIO60
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_DATA1
Link
Link
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SML0CLK
CL_CLK1
SMBALERT#
E12
SMB_PCH_CLK
H14
SMB_PCH_DAT
C9
DRAMRST_CNTRL_PCH
A12
SMB_ME0_CLK
C8
SMB_ME0_DAT
G12
SML1ALERT#_R
C13
SMB_ME1_CLK
E14
SMB_ME1_DAT
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
CLK_PEGA_REQ#
M10
AB37
AB38
AV22
AU22
AM12
AM13
CLK_BUF_PCIE_3GPLLN
BF18
CLK_BUF_PCIE_3GPLLP
BE18
CLK_BUF_BCLKN
BJ30
CLK_BUF_BCLKP
BG30
CLK_BUF_DREFCLKN
G24
CLK_BUF_DREFCLKP
E24
CLK_BUF_DREFSSCLKN
AK7
CLK_BUF_DREFSSCLKP
AK5
CLK_PCH_14M
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
SKU_ID1
K43
CLK_FLEX1
F47
H47
48M_CLK_CR
K49
For LAN
R536 *0_4R536 *0_4
For EC
TP33TP33
TP36TP36
TP35TP35
R478 90.9/F_4R478 90.9/F_4
T5T5
BOARD_ID4 [10,31]
T37T37
1
DRAMRST_CNTRL_PCH [4,13,14]
SML1ALERT# [10,31]
CLK_PEGA_REQ# [15]
CLK_PCIE_VGA# [15]
CLK_PCIE_VGA [15]
CLK_CPU_BCLKN [3]
CLK_CPU_BCLKP [3]
CLK_DPLL_SSCLKN [3]
CLK_DPLL_SSCLKP [3]
R486
R486
1M_4
1M_4
+1.05V
C538 27p/50V_4C538 27p/50V_4
21
Y2
25MHzY225MHz
C539 27p/50V_4C539 27p/50V_4
PLTRST#(CLG)
+3V
10/11 modify
C605
C605
0.1u/10V_4
0.1u/10V_4
PCI_PLTRST#
A A
2
4
1
U22
U22
3 5
TC7SH08FU
TC7SH08FU
5
R582
R582
100K_4
100K_4
PLTRST# [15,24,28,32]
PCI/USBOC# Pull-up(CLG )
+3V
R495 *SP@1K_4R495 *SP@1K_4
R496 SP@100K_4R496 SP@100K_4
+3V
R166 OP@10K_4R166 OP@10K_4
R162 SP@10K_4R162 SP@10K_4
+3V
R571 EV@10K_4R571 EV@10K_4
R559 SP@10K_4R559 SP@10K_4
USB_OC1#
USB_OC4#
USB_OC2#
USB_OC3#
+3V_S5
4
10
9
8
7 4
R534
R534
1
2
3
56
10K_10P8R
10K_10P8R
dGPU_PW_CTRL# [10]
SKU_ID1
SKU_ID0 [10]
PCI_PIRQA#
PCI_PIRQB#
G_SENSOR_INT#_PCH
REQ#3
dGPU_PWR_EN
dGPU_PW_CTRL#
(GPIO68)
CTL : dGPU_VRON
100
0
PCI_PIRQC#
PCI_PIRQD#
SKU_ID1
(GPIO64)
0
1
USB_OC6#
USB_OC0#
USB_OC7#
USB_OC5#
11/2 modify
UMA Only
dGPU Only
Switchable
(Mux)
Optimize
(Muxless)
dGPU_PW_CTRL#
1 = GPU power is control by H/W (pure Discrete SKU)
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize)
--->(Default)
+3V
10
9
8
7 4
SKU_ID0
(GPIO16)
0
1
1
R479
R479
10K_10P8R
10K_10P8R
R161 8.2K_4R161 8.2K_4
R191 8.2K_4R191 8.2K_4
R469 8.2K_4R469 8.2K_4
R170 8.2K_4R170 8.2K_4
1
2
dGPU_EDIDSEL#
3
dGPU_SELECT#
56
VGA H/W
Setup
Signal
Menu
UMA
Hidden
GPU
Hidden
UMA+GPU
dGPU/SG
UMA
UMA/SG
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH
3
+3V
11/2 modify
UMA boot
GPU boot
UMA boot
UMA boot
+3V_S5
R565 10K_4R565 10K_4
R549 10K_4R549 10K_4
R294 10K_4R294 10K_4
R225 10K_4R225 10K_4
R306 10K_4R306 10K_4
R278 10K_4R278 10K_4
R281 10K_4R281 10K_4
+3V
R556 10K_4R556 10K_4
R273 10K_4R273 10K_4
9/26 modify
R586 *10K_4R586 *10K_4
CLK_BUF_BCLKN
CLK_BUF_BCLKP
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
CLOCK TERMINATION for FCIM
PCIE_CLK_USB30_REQ#
PCIE_CLKREQ3#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
CLK_PCIE_LAN_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
PCIE_CLKREQ1#
PCIE_CLK_REQ2#
CLK_PEGA_REQ#
R514 10K _4R514 10K_4
R513 10K _4R513 10K_4
R532 10K _4R532 10K_4
R531 10K _4R531 10K_4
R211 10K _4R211 10K_4
R205 10K _4R205 10K_4
R240 10K _4R240 10K_4
R244 10K _4R244 10K_4
R163 10K _4R163 10K_4
SMBus(EC)CLK_REQ/Strap Pin(CLG)
2ND_MBCLK[32]
2ND_MBDATA[32]
+3V_S5
R246 1K_4R246 1K_4
R295 10K_4R295 10K_4
R590 2.2K_4R590 2.2K_4
R591 2.2K_4R591 2.2K_4
R296 2.2K_4R296 2.2K_4
R283 2.2K_4R283 2.2K_4
R537 10K_4R537 10K_4
2
+3V_S5
2
3
+3V_S5
2
3
DRAMRST_CNTRL_PCH
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
Q7
2N7002KQ72N7002K
Q8
2N7002KQ82N7002K
1
1
R149
R149
2.2K_4
2.2K_4
SMB_ME1_CLK
R150
R150
2.2K_4
2.2K_4
SMB_ME1_DAT
SMBus(PCH)
SMB_PCH_DAT
SMB_PCH_CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
Date: Sheet of
Date: Sheet of
+3V
R603
S5 S0
3
3
Panther Point 3/6
Panther Point 3/6
Panther Point 3/6
R603
4.7K_4
4.7K_4
2
1
R602
R602
4.7K_4
4.7K_4
1
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
CLK_SDATA [13,14,24,25,31]
CLK_SCLK [13,14,24,25,31]
944
944
944
Q41
Q41
2N7002K
2N7002K
+3V
2
Q40
Q40
2N7002K
2N7002K
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
of
1A
1A
1A
5
4
3
2
1
+3V9,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+3V_S5[3,7,8,9,11,15,28,30,31,34,35,36,41,42]
S_GPIO
SIO_EXT_SMI#[32]
D D
SIO_EXT_SCI#[32]
TP63TP63
TP66TP66
PCH_GPIO15[8]
SKU_ID0[9]
DGPU_PWROK[15,19]
11/2 modify
PLL_ODVR_EN[8]
C C
dGPU_VRON[39,40]
SML1ALERT#[9,31]
TP34TP34
SIO_EXT_SMI#
BOARD_ID1
SIO_EXT_SCI#
GPIO12
G_SENSOR_ID
PCH_GPIO24
PCH_GPIO27
PLL_ODVR_EN
STP_PCI#
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP
R572 *SHORT_4R572 *SHORT_4
SV_DET_NC
R266 100K_4R266 100K_4
10/11 modify
B B
SATA2GP : strap for reserved at chklist 1.2
SATA3GP : strap for reserved at chklist 1.2
NOTE: The internal pull-down is disabled after PLTRST# deasserts.
NOTE: This signal should not be pulled high when strap is sampled.
A A
R305 100K_4R305 100K_4
FDI TERMINATION
VOLTAGE OVERRIDE
FDI_OVRVLTG DMI_OVRVLTG G_SENSOR_ID
LOW - Tx, Rx terminated
to same voltage
R291 *1K_4R291 *1K_4
DMI TERMINATION
VOLTAGE OVERRIDE
5
CPT/PPT (GPIO,VSS_NCTF,RSVD)
U20F
U20F
R276 100_4R276 100_4
CRIT_TEMP_REP#
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
PANTHER POINT
PANTHER POINT
R286 *200K/F_4R286 *200K/F_4
Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)
4
+3V_S5
+3V_S5
DSW
+3V_S5
+3V
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V
+3V
+3V
GPIO
GPIO
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
NCTF
NCTF
+3V+3V +3V
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
PROCPWRGD
THRMTRIP#
CPU/MISC
CPU/MISC
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
B41
C41
A40
P4
A20GATE
AU16
PECI
P5
RCIN#
AY11
AY10
T14
INIT3_3V#
AY1
DF_TVS
AH8
TS_VSS1
AK11
TS_VSS2
AH10
TS_VSS3
AK10
TS_VSS4
P37
NC_1
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
BIOS RECOVERY
BOARD_ID3
R491 10K_4R491 10K_4
SIO_A20GATE
PCH_PECI
SIO_RCIN#
PCH_THRMTRIP#
DF_TVS
R288
R288
SP@10K_4
SP@10K_4
R275 SP@1K_4R275 SP@1K_4
High = W/O G_SENSOR
Low = W G_SENSOR
3
TP31TP31
R249 390_4R249 390_4
+3V
dGPU_PW_CTRL# [9]
CABLE_ID [22]
SIO_A20GATE [32]
SIO_RCIN# [32]
H_PWRGOOD [3]
PM_THRMTRIP# [3]
DF_TVS [8]
SV_SET_UP
High = Strong (Default)
TEST_SET_UP
SGPIO
S_GPIO
MFG-TEST
MFG_MODE
R569 10K_4R569 10K_4
GPIO Pull-up/Pull-down(CLG)
PCH_GPIO24
PLL_ODVR_EN
10/31 modify
SIO_EXT_SMI#
SIO_EXT_SCI#
STP_PCI#
SIO_A20GATE
SIO_RCIN#
CRIT_TEMP_REP#
DF_TVS
Follow the Emerald Lake 2 CRB
PCH_GPIO27
GPIO27 : If not used then use 8.2-kȍ to 10-kȍ pull-down to GND.
Reserve for future
BOARD_ID0
BOARD_ID1
BOARD_ID3
BOARD_ID4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
R272 10K_4R272 10K_4
R285 *1K_4R285 *1K_4
R302 1K_4R302 1K_4
R289 *1K_4R289 *1K_4
R557 *1K_4R557 *1K_4
2
R555 10K_4R555 10K_4 R568 *10K_4R568 *10K_4
+3V
R471 10K_4R471 10K_4
R490 *10K_4R490 *10K_4
R472 *10K_4R472 *10K_4
BOARD_ID2
8 Layer ------->High *
+3V
+3V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
6 Layer ------->Low
+3V
R167 *10K_4R167 *10K_4
R172 10K_4R172 10K_4
Panther Point 4/6
Panther Point 4/6
Panther Point 4/6
Friday, November 11, 2011
Friday, November 11, 2011
Friday, November 11, 2011
R307 *10K_4R307 *10K_4
R303 10K_4R303 10K_4
R148 10K_4R148 10K_4
R145 10K_4R145 10K_4
R566 *10K_4R566 *10K_4
R290 10K_4R290 10K_4
R304 10K_4R304 10K_4
R560 10K_4R560 10K_4
R550 *1K_4R550 *1K_4
R223 10K_4R223 10K_4
R467 *10K_4R467 *10K_4
R487 10K_4R487 10K_4
R468 10K_4R468 10K_4
BOARD_ID3 [31]
BOARD_ID4 [9,31]
BOARD_ID2 [9]
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
of
10 44
10 44
10 44
+3V_S5
+3V
+1.8V
+3V
1A
1A
1A
5
4
3
2
1
PCH5(CLG)
CPT/PPT (POWER)
POWER
POWER
U20G
+1.05V +1.05V_PCH_VCC
R284 0.002/F_1206R284 0.002/F_1206
D D
C C
B B
0,13,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
A A
R5285 near PCH ball for VCCP GND sense
+1.05V +1.05V_VCCAPLL_EXP
+1.05V +1.05V_VCCIO
+1.05V
R224 *SHORT_6R224 *SHORT_6
L36 *1uH/25mA_6L36 *1uH/25mA_6
R533 0.002/F_1206R533 0.002/F_1206
+1.5V
+1.05V_PCH_VCCDPL L_EXP+1.05V
R263 0_6R263 0_6
R264 *0_6R264 *0_6
+1.05V
+VCCAFDI_VRM
VccCORE =1.3 A(60mils)
C272
C266
C266
1u/6.3V_4
1u/6.3V_4
C569
C569
*10u/6.3V_6
*10u/6.3V_6
C272
1u/6.3V_4
1u/6.3V_4
C262
C262
1u/6.3V_4
1u/6.3V_4
C289
C289
10u/6.3V_6
10u/6.3V_6
VccIO =2.925 A(140mils)
C259
C259
C290
C290
1u/6.3V_4
1u/6.3V_4
R519 *SHORT_8R519 *SHORT_8
R542 *0_8R542 *0_8 R562 *SHORT_6R562 *SHORT_6
R267 *SHORT_8R267 *SHORT_8
VCCVRM: 1.8V (Destop)
1.5V (Mobile)
+3V_S5[3,7,8,9,10,15,28,30,31,34,35,36,41,42]
+5V_S5[26,30,34,35,36,37,38,39]
+1.5VSUS[4,5,13,14,37,40]
+5V[8,22,23,25,26,31,34,41]
+3V
+1.5V[24,37,41]
+1.05V[3,5,7,8,9,22,32,35 ,36,40,41]
+1.8V[5,8,10,41]
+3V_RTC[8]
1u/6.3V_4
1u/6.3V_4
C265
C265
1u/6.3V_4
1u/6.3V_4
+3V_VCC_EXP+3V
+VCCAFDI_VRM
+1.1V_VCC_DMI
C263
C263
1u/6.3V_4
1u/6.3V_4
C291
C291
10u/6.3V_6
10u/6.3V_6
C558
C558
0.1u/10V_4
0.1u/10V_4
+VCCAFDI_VRM
+1.05V_VCCAPLL_FDI
+1.05V_VCCDPLL_FDI
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
U20G
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
VCCIO[28]
VCCAPLLEXP
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCC3_3[3]
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
PANTHER POINT
PANTHER POINT
CRTLVDS
CRTLVDS
VCC CORE
VCC CORE
DMI
DMI
VCCIO
VCCIO
DFT / SPI HVCMOS
DFT / SPI HVCMOS
FDI
FDI
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
VccADAC =1mA(8mils)
C525
C525
22u/6.3V_8
22u/6.3V_8
VccALVDS=1mA(8mils)
When Dis sku, LVDS power can short to GND
VccTX_LVDS=60mA(10mils)
C554
C554
IV@0.01u/25V_ 4
IV@0.01u/25V_ 4
R196 *SHORT_6R196 *SHORT_6
C260
C260
0.1u/10V_4
0.1u/10V_4
+VCCAFDI_VRM
C532
C532
C530
C530
1u/6.3V_4
1u/6.3V_4
*10u/6.3V_6
*10u/6.3V_6
R300 *SHORT_8R300 *SHORT_8
C332
C332
0.1u/10V_4
0.1u/10V_4
VCCSPI = 20mA(8mils)
+3V_VCCME_SPI
R575 VA@0_6R575 VA@0_6
R647 BA@0_6R647 BA@0_6
C593
C593
1u/6.3V_4
1u/6.3V_4
+VCCA_DAC_1_2
L30
L30
C540
C540
C527
C541
C541
0.01u/25V_4
0.01u/25V_4
C553
C553
IV@0.01u/25V_4
IV@0.01u/25V_4
+VCCAFDI_VRM
L31
L31
C527
0.1u/10V_4
0.1u/10V_4
10u/6.3V_6
10u/6.3V_6
+VCCALVDS +3V
R195 IV@0_4R195 IV@0_4
R190 DO@0_4R190 DO@0_4
L34
L34
IV@0.1uH/250mA_ 8
IV@0.1uH/250mA_ 8
C552
C552
R511 DO@0_4R511 DO@0_4
IV@22u/6.3V_8
IV@22u/6.3V_8
+3V+3V_VCC_GIO
VCCDMI = 42mA(10mils)
+1.1V_VCC_DMI
R258 *SHORT_4R258 *SHORT_4
C318
C318
1u/6.3V_4
1u/6.3V_4
VCCCLKDMI = 20mA(8mils)
+VCC_DMI_CCI +1.05V+1.1V _VCC_DMI_CCI
R477 *1/F_4R477 *1/F_4
*10uH/100mA_8
*10uH/100mA_8
R474 0_4R474 0_4
+1.8V+VCCP_NAND
VCCPNAND = 190 mA(15mils)
+3V_S5
10/31 add
+3V_M
Reserve +3V_S5 to VCCSPI for EC 795
+3V
BKP1608HS181-T/180ohm/1.5A_6
BKP1608HS181-T/180ohm/1.5A_6
+1.8V+VCC_TX_LVDS
+1.05V
+1.05V
+1.05V_M
1mA(8mils)
VCCRTC<1mA(8mils)
+3V_S5
+VCCAPLL_CPY_PCH
L35 *10uH/100mA_8L35 *10uH/100mA_8
VCCME(+1.05V) = ??A(??mils)
BA@0.002/F_1206
BA@0.002/F_1206
+1.05V_VCCEPW
+1.05V
R587 VA@0.002/F_1206R587 VA@0.002/F_1206
R648
R648
10/31 add
+1.05V
R192 *SHORT_6R192 *SHORT_6
R481 *SHORT_6R481 *SHORT_6
+1.05V
R226 *0_6R226 *0_6
+1.05V
R535 *SHORT_4R535 *SHORT_4
+3V_RTC
+3V
R165 1/F_4R165 1/F_4
+1.05V
R250 *SHORT_4R250 *SHORT_4
+1.05V
C565
C565
*10u/6.3V_6
*10u/6.3V_6
VccASW =1.01 A(60mils)
C267
C267
C286
C286
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
1u/6.3V_4
C603
C603
22u/6.3V_8
22u/6.3V_8
C599
C599
1u/6.3V_4
1u/6.3V_4
C256
C256
1u/6.3V_4
1u/6.3V_4
C544
C544
1u/6.3V_4
1u/6.3V_4
VCCSSC= 95mA(10mils)
C295
C295
*1u/6.3V_4
*1u/6.3V_4
C583
C583
0.1u/10V_4
0.1u/10V_4
C580
C580
4.7u/6.3V_6
4.7u/6.3V_6
C296
C296
C288
C288
0.1u/10V_4
0.1u/10V_4
1u/6.3V_4
1u/6.3V_4
L15 10uH/100mA_8L15 10uH/100mA_8
R480 *0_8R480 *0_8
VCCDSW3_3= 3mA
C319
C319
0.1u/10V_4
0.1u/10V_4
C309
C309
*0.1u/10V_4
*0.1u/10V_4
R199 *SHORT_6R199 *SHORT_6
C271
C271
*1u/6.3V_4
*1u/6.3V_4
C273
C273
1u/6.3V_4
1u/6.3V_4
C257
C257
22u/6.3V_8
22u/6.3V_8
C299 0.1u/10V_4C299 0.1u/10V_4
+VCCRTCEXT
+VCCAFDI_VRM
+VCCAFDI_VRM
C298 0.1u/10V_4C298 0.1u/10V_4
C586
C586
0.1u/10V_4
0.1u/10V_4
C287
C287
0.1u/10V_4
0.1u/10V_4
C235
C235
10u/6.3V_6
10u/6.3V_6
+1.05V_VCCA_A_DPL
+1.05V_VCCA_B_DPL
+VCCDIFFCLK
+VCCDIFFCLKN
+V1.05V_SSCVCC
+VCCSST
+V1.05M_VCCSUS
+VTT_VCCPCPU
+3V_SUS_CLKF33
C237
C237
1u/10V_4
1u/10V_4
65mA(10mils)
8mA(8mils)
VCCDIFFCLKN= 55mA(10mils)
CPT/PPT (POWER)
U20J
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
AG33
V16
T17
V19
BJ8
A22
U20J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3[5]
VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]
VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCADPLLA
VCCADPLLB
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCSSC
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO
VCCRTC
PANTHER POINT
PANTHER POINT
+VCCACLK
+VCCPDSW
PCH_VCCDSW
+3V_SUS_CLKF33
+VCCDPLL_CPY
+VCCSUS1
POWER
POWER
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
CPURTC
CPURTC
HDA
HDA
L32 10uH/100mA_8L32 10uH/100mA_8
+1.05V
L33 10uH/100mA_8L33 10uH/100mA_8
VCCIO[29 ]
VCCIO[30 ]
VCCIO[31 ]
VCCIO[32 ]
VCCIO[33 ]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCIO[34 ]
V5REF_SU S
DCPSUS[4]
VCCSUS3_3[1]
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12 ]
VCCIO[13 ]
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
N26
P26
P28
T27
T29
+3V_VCCPUSB
T23
T24
V23
V24
+3V_VCCAUBG
P24
+VCCAUPLL
T26
+5V_PCH_VCC5REFSUS
M26
+VCCA_USBSUS
AN23
+3V_VCCPSUS
AN24
+5V_PCH_VCC5REF
P34
N20
N22
+3V_VCCPSUS
P20
P22
AA16
+3V_VCCPCORE
W16
T34
C255
C255
0.1u/10V_4
0.1u/10V_4
AJ2
AF13
+V1.05S_SATA3
AH13
AH14
AF14
+V1.1LAN_VCCAPLL
AK1
VCCVRM= 114mA(15mils)
+VCCAFDI_VRM
AF11
AC16
AC17
AD17
T21
V21
T19
+V3.3A_1.5A_HDA_IO
P32
C239
C239
*1u/6.3V_4
*1u/6.3V_4
+
+
C546
C546
220u/2.5V_3528
220u/2.5V_3528
+
+
C548
C548
220u/2.5V_3528
220u/2.5V_3528
R209 *SHORT_6R209 *SHORT_6
+3V
R228 *SHORT_6R228 *SHORT_6
C294
C294
1u/6.3V_4
1u/6.3V_4
+1.05V_VCCEPW
C238
C238
0.1u/10V_4
0.1u/10V_4
+1.05V_VCCA_A_DPL
C542
C542
1u/6.3V_4
1u/6.3V_4
+1.05V_VCCA_B_DPL
C551
C551
1u/6.3V_4
1u/6.3V_4
R203 *SHORT_8R203 *SHORT_8
C269
C269
1u/6.3V_4
1u/6.3V_4
R243 *SHORT_6R243 *SHORT_6
C316
C316
0.1u/10V_4
0.1u/10V_4
R235 *SHORT_6R235 *SHORT_6
C308
C308
0.1u/10V_4
0.1u/10V_4
C302
C302
0.1u/10V_4
0.1u/10V_4
C285
C285
*1u/6.3V_4
*1u/6.3V_4
C240
C240
1u/6.3V_4
1u/6.3V_4
VCCSUS3_3 = 119mA(15mils)
C311
C311
1u/10V_4
1u/10V_4
VCCPCORE = 28mA(10mils)
C315
C315
0.1u/10V_4
0.1u/10V_4
+3V
C317
C317
0.1u/10V_4
0.1u/10V_4
C331
C331
1u/10V_4
1u/10V_4
C594
C594
*10u/6.3V_6
*10u/6.3V_6
+1.05V
VCCME = 1.01A(60mils)
R159 *0_ 4R159 * 0_4
R160 0_4R160 0_4
+1.05V+1.05V_VCCUSBCORE
VCCSUS3_3 = 119mA(15mils)
+3V_S5
+1.05V
VCC5REFSUS=1mA
R229 10/F_4R229 10/F_4
D6 RB500V-40D6 RB500V-40
V5REF= 1mA
R168 10/F_4R168 10/F_4
D5 RB500V-40D5 RB500V-40
R238 *SHORT_6R238 *SHORT_6
R247 *SHORT_6R247 *SHORT_6
R299 *SHORT_8R299 *SHORT_8
??mA(??mils)
L37
L37
*10uH/100mA_8
*10uH/100mA_8
+1.5VSUS
VCCSUSHDA= 10mA(8mils)
+3V_S5
+5V_S5
+3V_S5
+5V
+3V
+3V_S5
+3V
+1.05V
+1.05V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZQTA/ZQSA
PROJECT :
ZQTA/ZQSA
PROJECT :
Size Documen t Number Rev
Size Documen t Number Rev
Size Document Number Rev
Panther Point 5/6
Panther Point 5/6
Panther Point 5/6
Date: Sheet of
Date: Sheet of
Date: Sheet
Friday, November 11, 2011
Friday, November 11, 2011
5
4
3
2
Friday, November 11, 2011
1
ZQTA/ZQSA
of
11 44
11 44
11 44
1A
1A
1A
5
4
3
2
1
PCH6(CLG)
U20I
U20I
AY4
VSS[159]
IBEX PEAK-M (GND)
D D
U20H
U20H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
C C
B B
A A
5
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD40
AD42
AD43
AD45
AD46
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF42
AF46
AG19
AG31
AG48
AH11
AH36
AH39
AH40
AH42
AH46
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AD4
AD8
AE2
AE3
AF4
AF5
AF7
AF8
AG2
AH3
AH7
AK3
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
PANTHER POINT
PANTHER POINT
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
B7
F45
D3
D8
F3
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
PANTHER POINT
PANTHER POINT
3
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Friday, November 11, 2011
Friday, November 11, 2011
2
Friday, November 11, 2011
PROJECT :
Panther Point 6/6
Panther Point 6/6
Panther Point 6/6
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
12 44
12 44
12 44
1
1A
1A
1A
of
5
M_A_A[15:0][4]
D D
M_A_BS#0[4]
M_A_BS#1[4]
M_A_BS#2[4]
M_A_CS#0[4]
M_A_CS#1[4]
M_A_CLK0[4]
M_A_CLK0#[4]
M_A_CLK1[4]
M_A_CLK1#[4]
M_A_CKE0[4]
M_A_CKE1[4]
M_A_CAS#[4]
M_A_RAS#[4]
R208 10K_4R208 10K_4
R207 10K_4R207 10K_4
C C
B B
M_A_WE#[4]
CLK_SCLK[9,14,24,25,31]
CLK_SDATA[9,14,24,25,31]
M_A_ODT0[4]
M_A_ODT1[4]
M_A_DQS[7:0][4]
M_A_DQS#[7:0][4]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIMM0_SA0
DIMM0_SA1
CLK_SCLK
CLK_SDATA
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
98
97
96
95
92
91
90
86
89
85
84
83
80
78
79
73
74
11
28
46
63
12
29
47
64
10
27
45
62
4
JDIM1A
JDIM1A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
(204P)
(204P)
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
M_A_DQ4
M_A_DQ0
M_A_DQ2
M_A_DQ3
M_A_DQ1
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ12
M_A_DQ13
M_A_DQ11
M_A_DQ10
M_A_DQ8
M_A_DQ9
M_A_DQ14
M_A_DQ15
M_A_DQ17
M_A_DQ20
M_A_DQ18
M_A_DQ19
M_A_DQ16
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ28
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ29
M_A_DQ31
M_A_DQ30
M_A_DQ36
M_A_DQ33
M_A_DQ34
M_A_DQ39
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ35
M_A_DQ45
M_A_DQ44
M_A_DQ40
M_A_DQ42
M_A_DQ47
M_A_DQ41
M_A_DQ46
M_A_DQ43
M_A_DQ53
M_A_DQ52
M_A_DQ50
M_A_DQ55
M_A_DQ49
M_A_DQ48
M_A_DQ54
M_A_DQ51
M_A_DQ56
M_A_DQ57
M_A_DQ62
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ58
3
M_A_DQ[63:0] [4]
M3 solution
SMDDR_VREF_DQ0_M3[5]
+SMDDR_VREF
R222 *M3@0_6R222 *M3@0_6
+SMDDR_VREF_DIMM
change to 1K/F_4
R182 *0_6R182 *0_6
+3V
DDR3_DRAMRST#[4,14]
+1.5VSUS
R206 *10K_4R206 *10K_4
+SMDDR_VREF_DIMM
R194
R194
1K/F_4
1K/F_4
R218
R218
1K/F_4
1K/F_4
C300
C300
470p/50V_4
470p/50V_4
2.48A
+3V
+SMDDR_VREF_DQ0
2
+1.5VSUS
PM_EXTTS#0
JDIM1B
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM1_H=9.2_Reverse
DDR3-DIMM1_H=9.2_Reverse
+SMDDR_VREF_DIMM [14]
+1.5VSUS
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
203
VTT1
204
VTT2
205
GND
206
GND
+SMDDR_VREF_DQ0
1
+0.75V_DDR_VTT
R213
DDR3-DIMM1_H=9.2_Reverse
DDR3-DIMM1_H=9.2_Reverse
M1 solution
Place these Caps near So-Dimm0.
+1.5VSUS
C278
C243
C243
0.1u/16V_4
0.1u/16V_4
C557
C557
1u/6.3V_4
1u/6.3V_4
C278
0.1u/16V_4
0.1u/16V_4
C276
C276
0.1u/16V_4
0.1u/16V_4
+
+
C561
C561
1u/6.3V_4
1u/6.3V_4
C274
C277
C277
10u/6.3V_6
10u/6.3V_6
C575
C575
0.1u/16V_4
0.1u/16V_4
C274
10u/6.3V_6
10u/6.3V_6
C245
C245
0.1u/16V_4
0.1u/16V_4
+0.75V_DDR_VTT
C555
C555
1u/6.3V_4
1u/6.3V_4
C247
C247
0.1u/16V_4
0.1u/16V_4
C279
C242
C242
10u/6.3V_6
10u/6.3V_6
C576
C576
2.2u/6.3V_6
2.2u/6.3V_6
C279
10u/6.3V_6
10u/6.3V_6
5
C244
C244
10u/6.3V_6
10u/6.3V_6
C246
C246
10u/6.3V_6
10u/6.3V_6
A A
+3V
C293
C293
C241
C241
*330u/2V_7343
*330u/2V_7343
0.1u/16V_4
0.1u/16V_4
C572
C572
1u/6.3V_4
1u/6.3V_4
4
+SMDDR_VREF_DIMM
C283
C283
2.2u/6.3V_6
2.2u/6.3V_6
C560
C560
4.7u/6.3V_6
4.7u/6.3V_6
+SMDDR_VREF_DQ0
C280
C280
0.1u/16V_4
0.1u/16V_4
C562
C562
4.7u/6.3V_6
4.7u/6.3V_6
2.2u/6.3V_6
2.2u/6.3V_6
C567
C567
4.7u/6.3V_6
4.7u/6.3V_6
C275
C275
3
+SMDDR_VREF
SMDDR_VREF_DQ0_M3
DRAMRST_CNTRL_PCH[4,9,14]
+1.5VSUS[4,5,11,14,37,40]
+3V[3,7,8,9,10,11,14,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+0.75V_DDR_VTT[14,37,41]
+SMDDR_VREF[5,14,37]
REV:B Add
R221 *0_6R221 *0_6
1
2
3
Q14
Q14
2
BA@AP2302GN
BA@AP2302GN
R213
1K/F_4
1K/F_4
change to 1K/F_4
+SMDDR_VREF_DQ0
C281
C281
470p/50V_4
470p/50V_4
R214
R214
1K/F_4
1K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
13 44Friday, November 11, 2011
13 44Friday, November 11, 2011
13 44Friday, November 11, 2011
1
of
of
of
1A
1A
1A
5
4
3
2
1
M_B_A[15:0][4]
D D
M_B_BS#0[4]
M_B_BS#1[4]
M_B_BS#2[4]
M_B_CS#0[4]
M_B_CS#1[4]
M_B_CLK0[4]
M_B_CLK0#[4]
M_B_CLK1[4]
M_B_CLK1#[4]
M_B_CKE0[4]
M_B_CKE1[4]
M_B_CAS#[4]
M_B_RAS#[4]
CLK_SCLK[9,13,24,25,31]
CLK_SDATA[9,13,24,25,31]
M_B_ODT0[4]
M_B_ODT1[4]
M_B_DQS[7:0][4]
M_B_DQS#[7:0][4]
C306
C306
10u/6.3V_6
10u/6.3V_6
+0.75V_DDR_VTT
M_B_WE#[4]
C303
C303
10u/6.3V_6
10u/6.3V_6
C307
C307
0.1u/16V_4
0.1u/16V_4
R573 10K_4R573 10K_4
R574 10K_4R574 10K_4
+3V
C C
B B
+1.5VSUS
C324
C324
10u/6.3V_6
10u/6.3V_6
+3V
Place these Caps near So-Dimm1.
C325
C325
10u/6.3V_6
10u/6.3V_6
C304
C304
10u/6.3V_6
10u/6.3V_6
C326
C326
10u/6.3V_6
10u/6.3V_6
C305
C305
0.1u/16V_4
0.1u/16V_4
C321
C321
0.1u/16V_4
0.1u/16V_4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DIMM1_SA0
DIMM1_SA1
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
C322
C322
0.1u/16V_4
0.1u/16V_4
C323
C323
0.1u/16V_4
0.1u/16V_4
JDIM2A
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3-DIMM1_H=5.2_Reverse
DDR3-DIMM1_H=5.2_Reverse
+SMDDR_VREF_DIMM
+
+
C301
C301
C248
C248
330u/2V_7343
330u/2V_7343
0.1u/16V_4
0.1u/16V_4
C328
C328
M_B_DQ5
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ0
M_B_DQ4
M_B_DQ6
M_B_DQ7
M_B_DQ13
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ8
M_B_DQ14
M_B_DQ15
M_B_DQ20
M_B_DQ17
M_B_DQ23
M_B_DQ18
M_B_DQ16
M_B_DQ21
M_B_DQ19
M_B_DQ22
M_B_DQ28
M_B_DQ24
M_B_DQ31
M_B_DQ27
M_B_DQ29
M_B_DQ25
M_B_DQ30
M_B_DQ26
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ46
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ47
M_B_DQ42
M_B_DQ49
M_B_DQ53
M_B_DQ55
M_B_DQ54
M_B_DQ52
M_B_DQ48
M_B_DQ51
M_B_DQ50
M_B_DQ60
M_B_DQ56
M_B_DQ59
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ62
M_B_DQ63
C329
C329
2.2u/6.3V_6
2.2u/6.3V_6
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
(204P)
(204P)
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
C282
C282
0.1u/16V_4
0.1u/16V_4
2.2u/6.3V_6
2.2u/6.3V_6
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+SMDDR_VREF_DQ1
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
M_B_DQ[63:0] [4]
M3 solution
SMDDR_VREF_DQ1_M3[5]
R529 *10K_4R529 *10K_4
+3V
DDR3_DRAMRST#[4,13]
R270 *M3@0_6R270 *M3@0_6
+SMDDR_VREF_DIMM
2.48A
DRAMRST_CNTRL_PCH[4,9,13]
+1.5VSUS
+3V
PM_EXTTS#1
+SMDDR_VREF_DQ1
+SMDDR_VREF
SMDDR_VREF_DQ1_M3
REV:B Add
JDIM2B
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM1_H=5.2_Reverse
DDR3-DIMM1_H=5.2_Reverse
M1 solution
R233 *0_6R233 *0_6
change to 1K/F_4
1
Q15
Q15
2
BA@AP2302GN
BA@AP2302GN
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
3
203
VTT1
204
VTT2
205
GND
206
GND
+1.5VSUS +SMDDR_VREF_DQ1
R271
R271
1K/F_4
1K/F_4
+SMDDR_VREF_DQ1
C327
C327
470p/50V_4
470p/50V_4
R269
R269
1K/F_4
1K/F_4
+0.75V_DDR_VTT
C589
C588
A A
C601
C601
2.2u/6.3V_6
2.2u/6.3V_6
C600
C600
0.1u/16V_4
0.1u/16V_4
5
C588
1u/6.3V_4
1u/6.3V_4
C589
1u/6.3V_4
1u/6.3V_4
C568
C568
1u/6.3V_4
1u/6.3V_4
C570
C570
1u/6.3V_4
1u/6.3V_4
C581
C581
4.7u/6.3V_6
4.7u/6.3V_6
4
C584
C584
4.7u/6.3V_6
4.7u/6.3V_6
C587
C587
4.7u/6.3V_6
4.7u/6.3V_6
+SMDDR_VREF_DIMM[13]
3
+1.5VSUS[4,5,11,13,37,40]
+3V[3,7,8,9,10,11,13,19,22,23,24,25,26,27,28,31,32,34,35,36,37,38,39,40,41]
+0.75V_DDR_VTT[13,37,41]
+SMDDR_VREF[5,13,37]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDRIII SO-DIMM-1
DDRIII SO-DIMM-1
DDRIII SO-DIMM-1
Date: Sheet
Date: Sheet
2
Date: Sheet
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZQTA/ZQSA
ZQTA/ZQSA
ZQTA/ZQSA
14 44Friday, November 11, 2011
14 44Friday, November 11, 2011
14 44Friday, November 11, 2011
1
of
of
of
1A
1A
1A
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