QUANTA ZQR Schematics

http://mycomp.su/x/

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D D

intel

SandyBridge QC /DC 35W

DDR III - SODIMM 0 DDR III - SODIMM 1

P14, 15

C C

Dual Channel DDR III

1066 MHz

DDR SYSTEM MEMORY

FDI interface

HDD (SATA)

ODD (SATA)

P20

P0

P1

SATA0

SATA1

SATA Gen3

SATA Gen2

rPGA 988

(37.5mm X 37.5mm)

FDI

CLK

intel

<PCH>

P1

M/B USB*1

D/B USB*2

B B

USB Bluetooth

USB CCD

CardReader

AU6435-GDL

P23

P3,P9

P23

P4

P24

P8

P17

P12

P23

USB 2.0

Azalia

X'TAL

32.768KHz

USB

CougarPoint 0.7

mBGA 989

(25mm X 25mm)

HDA

1RWH +0QRWVXSSRUW86% +0QRWVXSSRUW6$7$

RTC P9

SPI

PCI-E X16

DMI

P4~P7

X4 DMI interface

5GT/s2.7GT/s

DMIFDI

iGFX Interfaces

PCI-E

P8~P13

LPC

5GT/s

INT_CRT

INT_LVDS

INT_HDMI

PCI-Express Gen2

5GT/s

X'TAL 25MHz

CHARGER

ISL88731

3/5V SYS PWR

RT8206

CPU CORE PWR

ISL95835

CPU +1.05V_VTT

RT8238

DDR3 PWR

RT8207A

+1.8V

HPA00835RTER

P1

Atheros AR8158L

P26

P28

P29

P30

P31

discharger

P32

Thermal protect

CRT

LVDS

HDMI

P6

Mini Card-1

P34

P34P34

P16

P17

P19

P10USB 2.0

Int. MIC

A A

MIC JACK Int. Speaker HP

5

ALC271X-VB3 AUDIO CODEC

P21

P24

EC

NPCE971

Keyboard

3

P25

P24

Fan Driver

(D/A Type)

P24

Dual SPI ROM

4Mbit x1 (Basic ME+Braidwood)

P22P22P22

SPI ROM

P25

4

P9

Touch Pad

Transformer

10/100M

RJ45

2

P18

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet

Date: Sheet of

Monday, May 09, 2011

PROJECT :

Block Diagram

ZQR

135

1

of

1A

http://mycomp.su/x/

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8

Power States

POWER PLANE

A A

B B

VIN +VCCRTC +3VPCU +5VPCU +15V +3V_S5 +5V_S5 +5V

+1.5VSUS +0.75V_DDR_VTT +VGFX_AXG S0GFX_ONInternal GPU POWER +1.8V +1.5V +1.1V_VTT S0 +1.05V +VCC_CORE LCDVCC +5V_GPU +GPU_CORE +GPU_IO PG_GPUIO_EN+0.9V~+1.1V

VOLTAGE

+10V~+19V +3V~+3.3V +3.3V +5V +15V +3.3V +5V +5V +3.3V +1.5V +0.75V variation +1.8V +1.5V

+1.05V or +1.1V

+1.05V variation +3.3V +5V Discrete enableSWITCHABLE PWM IC POWER

DESCRIPTION

RTC POWER EC POWER CHARGE POWER CHARGE PUMP POWER LAN/BT/CIR POWER USB POWER HDD/ODD/Codec/TP/CRT/HDMI POWER PCH/GPU/Peripheral component POWER+3V CPU/SODIMM CORE POWER SODIMM Terminati on POWER

CPU/PCH/Braidwood POWER MINI CARD/NEW CARD POWER

PCH CORE POWER MAINON CPU CORE POWER LCD POWER

CONTROL SIGNAL

ALWAYSMAIN POWER ALWAYS ALWAYS ALWAYS

S5_ON S5_ON MAINON MAINON SUSON MAINON

MAINON MAINON MAINONCPU VTT POWER

VRON LVDS_VDDEN

dGPU_PWR_EN#

PG_1.5V_EN+1.5V+1.5V_GPU +1.5V_GPU+1.8V+1.8V_GPU PG_1V_EN+1V+1V Discrete enableDP/PEG POWER

ACTIVE IN

ALWAYS ALWAYS ALWAYS ALWAYS ALWAYSALWAYS S0-S5 S0-S5 S0 S0 S0-S3 S0

S0 S0

S0 S0 S0

Discrete enable+3V_DGPU CORE POWER+0.9V~+1.1V Discrete enableGPU I/O POWER Discrete enableVRAM CORE POWER Discrete enableGPU_CRE/LVDS/PLL POWER

Thermal Follow Chart

CPU CORE PWR

H_ORICHOT#

H/W Throttling

NTC Thermal Protection

CPU

PCH

SM-Bus

EC

PM_THRMTRIP#

SML1ALERT#

CPUFAN#

WIRE-AND

SYS_SHDN#

3V/5 V SYS PWR

FANFAN Driver

C C

D D

Quanta Computer Inc.

1

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PROJECT :

Size Document Number Rev

PWR Status & GPU PW R CRL & T HRM

Date: Sheet

5

6

Date: Sheet

7

PROJECT :

ZQR

1A

of

235Monday, May 09, 2011

8

http://mycomp.su/x/

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03

D D

+3V_S5

2.2Kȍ

SMB_ME0_CLK

SMB_ME0_DAT

+3V_S5

C C

2.2Kȍ

intel

<PCH>

SMB_ME1_CLK

2.2Kȍ

CougarPoint 0.7

mBGA 989

(25mm X 25mm)

B B

SMB_PCH_CLK

SMB_PCH_DAT

+3V_S5

2.2Kȍ

+3V_S5

2.2Kȍ

DS

D

+3V_S5

G

NMOS

G

NMOS

+3V_S5

S

G

NMOS

G

NMOS

SMB_RUN_CLK

SMB_RUN_DAT

S

+3VPCU

DS

10Kȍ

MBCLK

+3VPCU

10Kȍ

EC

WPCE

+3V

4.7Kȍ

MBDATASMB_ME1_DAT

+3V

Slave ADDRESS :A0H Slave ADDRESS :A4H

DDR3 DIMM-0-STD (5.2H)

4.7Kȍ

D

791/FLASH

DDR3 DIMM-1-STD (9.2H)

WLAN Mini 3G

A A

Quanta Computer Inc.

5

4

PROJECT :

Size Document Number Rev

Monday, May 09, 2011

Date: Sheet of

3

2

Date: Sheet

PROJECT :

SMBus Address

ZQR

335

1

335

1A

of

http://mycomp.su/x/

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1

Sandy Bridge Processor (DMI,PEG,FDI)

U14A

DMI_TXN08 DMI_TXN18 DMI_TXN28 DMI_TXN38

DMI_TXP08

D D

DMI_TXP18 DMI_TXP28 DMI_TXP38

DMI_RXN08 DMI_RXN18 DMI_RXN28 DMI_RXN38

DMI_RXP08 DMI_RXP18 DMI_RXP28 DMI_RXP38

FDI_TXN08 FDI_TXN18 FDI_TXN28 FDI_TXN38 FDI_TXN48 FDI_TXN58 FDI_TXN68 FDI_TXN78

FDI_TXP08 FDI_TXP18 FDI_TXP28

C C

FDI_TXP38 FDI_TXP48 FDI_TXP58 FDI_TXP68 FDI_TXP78

FDI_FSYNC08 FDI_FSYNC18

FDI_INT8

FDI_LSYNC08 FDI_LSYNC18

eDP_COMP INT_eDP_HPD_Q

B B

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

CPU-989P-rPGA

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD

eDP_AUX eDP_AUX#

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11]

PCI EXPRESS* - GRAPHICS

PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

SNB_IVB# N.A at SNB EDS #27637 0.7v1

H_SNB_IVB#9

EC_PECI11,27

H_PROCHOT#27,30

PM_THRMTRIP#11

PM_SYNC8

H_PWRGOOD11

R277 75_4R277 75_4

+1.05V_VTT

CPU_PLTRST#

SYS_PWROK8

PM_DRAM_PWRGD8

R26 56_4R26 56_4

+3V_S5

C168

0.1U/10V_4

U7

2 1

74AHC1G09

3 5

Sandy Bridge Processor (CLK,MISC,JTAG)

U14B

C26

PROC_SELECT#

TP73TP73

TP14TP14

R24 10K_4R24 10K_4

C34 0.1U/10V_4C34 0.1U/10V_4

PM_DRAM_PWRGD_R

R273 43_4R273 43_4

PM_DRAM_PWRGD_Q

4

R155 *39_4R155 *39_4

SKTOCC#

TP_CATERR#

H_PROCHOT#_R

PM_THRMTRIP#

CPU_PLTRST#_R

+1.5V_CPU

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

CPU-989P-rPGA

R153

R153 200/F_4

200/F_4 R152 130/F_4R152 130/F_4

3

Q10 *2N7002KQ10 *2N7002K

2

PM_DRAM_PWRGD_R

1

MISCTHERMALPWR MANAGEMENT

MAINON_ON_G 6,34

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

PLTRST#10,18,19,23,27

BCLK

BCLK#

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

04

A28 A27

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY#

XDP_PREQ# XDP_TCLK

XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRST#

U12

1

VCC5NC

2

IN GND3OUT

74LVC1G07GW

CLK_CPU_BCLKP 10 CLK_CPU_BCLKN 10

CLK_DPLL_SSCLKP 10 CLK_DPLL_SSCLKN 10

CPU_DRAMRST# 5

R151 140/F_4R151 140/F_4 R358 25.5/F_4R358 25.5/F_4 R363 200/F_4R363 200/F_4

TP81TP81

XDP_DBRST# 8

+3V_S5

C366

0.1U/10V_4

CPU_PLTRST#

4

DP & PEG Compensation

+1.05V_VTT+1.05V_VTT

R300 24.9/F_4R300 24.9/F_4

A A

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

5

R70 24.9/F_4R70 24.9/F_4

PEG_ICOMPI and RCOMPO signals should be routed within 500 mils typical impedance = 43 mohms

PEG_ICOMPO signals should be routed within 500 mils typical impedance = 14.5 mohms

PEG_COMPeDP_COMP

4

Processor pull-up(CPU)

+1.05V_VTT

H_PROCHOT# XDP_TDO XDP_TMS XDP_TDI XDP_PREQ# XDP_TCLK XDP_TRST#

R39 62_4R39 62_4 R57 51_4R57 51_4 R285 51_4R285 51_4 R283 51_4R283 51_4 R55 *51_4R55 *51_4 R286 51_4R286 51_4 R56 51_4R56 51_4

IMVP_PWRGD8,30

PM_THRMTRIP#

3

2

1 3

3

Q2 FDV301NQ2FDV301N

1

R75

R75 1K_4

1K_4

2

Q3

Q3 MMBT3904

MMBT3904

+1.05V_VTT

SYS_SHDN# 29,34

2

eDP Hot-plug

HPD disable

INT_eDP_HPD_Q

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Monday, May 23, 2011

Date: Sheet of

Date: Sheet

PROJECT :

Sandy Bridge 1/4

+1.05V_VTT

ZQR

435

1

R306

R306 10K_4

10K_4

of

1A

http://mycomp.su/x/

5

4

3

2

1

Sandy Bridge Processor (DDR3)

05

U14D

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2

J7 J8

K9

J9

J10

K8 K7 M5 N4 N2 N1 M4 N5 M2 M1

R6

U14D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

CPU-989P-rPGA

AE2

SB_CLK[0]

SB_CLK#[0]

SB_CLK#[1]

RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]

RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17] RSVD_TP[18]

RSVD_TP[19] RSVD_TP[20]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

DDR SYSTEM MEMORY B

2

AD2 R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1 R10

SB_CKE[1]

AB2 AA2 T9

AA1 AB1 T10

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6 AE6

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5 AE5

M_B_DQSN0

D7

M_B_DQSN1

F3

M_B_DQSN2

K6

M_B_DQSN3

N3

M_B_DQSN4

AN5

M_B_DQSN5

AP9

M_B_DQSN6

AK12

M_B_DQSN7

AP15

M_B_DQSP0

C7

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

Size Document Number Rev

Date: Sheet

Date: Sheet of

Monday, May 23, 2011

M_B_DQSP1

G3

M_B_DQSP2

J6

M_B_DQSP3

M3

M_B_DQSP4

AN6

M_B_DQSP5

AP8

M_B_DQSP6

AK11

M_B_DQSP7

AP14

M_B_A0

AA8

M_B_A1

T7

M_B_A2

R7

M_B_A3

T6

M_B_A4

T2

M_B_A5

T4

M_B_A6

T3

M_B_A7

R2

M_B_A8

T5

M_B_A9

R3

M_B_A10

AB7

M_B_A11

R1

M_B_A12

T1

M_B_A13

AB10

M_B_A14

R5

M_B_A15

R4

Sandy Bridge 2/4

Quanta Computer Inc.

PROJECT :

M_B_CLKP0 15 M_B_CLKN0 15 M_B_CKE0 15

M_B_CLKP1 15 M_B_CLKN1 15 M_B_CKE1 15

M_B_CS#0 15 M_B_CS#1 15

M_B_ODT0 15 M_B_ODT1 15

M_B_DQSN[7:0] 15

M_B_DQSP[7:0] 15

M_B_A[15:0] 15

ZQR

1

1A

of

535

U14C

D D

C C

B B

A A

M_A_DQ[63:0]14

M_A_BS#014 M_A_BS#114 M_A_BS#214

M_A_CAS#14 M_A_RAS#14 M_A_WE#14

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

5

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11 AL12

AM12 AM11

AL11 AP12

AN12

AJ14

AH14

AL15 AK15 AL14 AK14

AJ15

AH15

AE10 AF10

AE8

AD9

AF9

C5 D5 D3 D2 D6 C6 C2 C3

F10

F8

G9

F9

F7 G8 G7 K4 K5 K1

J1

J5

J4

J2 K2 M8

N8 N7

M9 N9 M7

AJ5 AJ6 AJ8

AJ9

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

CPU-989P-rPGA

SA_CLK#[0]

SA_CLK#[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

RSVD_TP[7] RSVD_TP[8]

RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

DDR SYSTEM MEMORY A

SA_CLK[0] SA_CKE[0]

SA_CLK[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_CLKP0 14 M_A_CLKN0 14 M_A_CKE0 14

M_A_CLKP1 14 M_A_CLKN1 14 M_A_CKE1 14

M_A_CS#0 14 M_A_CS#1 14

M_A_ODT0 14 M_A_ODT1 14

R162 1K/F_4R162 1K/F_4

DRAMRST_CNTRL_PCH10

M_A_DQSN[7:0] 14

M_A_DQSP[7:0] 14

M_A_A[15:0] 14

+1.5V_SUS

R160

R160 1K/F_4

1K/F_4

CD_DRAMRST#

M_B_DQ[63:0]15

M_B_BS#015 M_B_BS#115 M_B_BS#215

M_B_CAS#15 M_B_RAS#15 M_B_WE#15

3

Q11

Q11 2N7002K

2N7002K

2

C181

0.047U/10V_4

1

R161

4.99K/F_4

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

CPU_DRAMRST# 4DDR3_DRAMRST#14,15

http://mycomp.su/x/

5

4

3

2

1

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

CPU VTT

+1.05V_VTT

+

10U/6.3V_8

R65 *short_4R65 *short_4

H_CPU_SVIDALRT# VR_SVID_CLK VR_SVID_DATA

R249 100/F_4R249 100/F_4

R248 100/F_4R248 100/F_4 R315 10/F_4R315 10/F_4

R317 10/F_4R317 10/F_4

C110

C110 330u/2V_7343

330u/2V_7343

C405

C411

C103

C401

C401 *22U/6.3V_8

*22U/6.3V_8

10U/6.3V_8

SNB 45W:8.5A

Spec

330uF/6mohm x 2 22uF x 12 22uF x 7 (Non-stuff)

+

C409

C409 *330U/2V_7343

*330U/2V_7343

C410

C413

10U/6.3V_8

C123

C124

10U/6.3V_8

C102

C128

10U/6.3V_8

C381

C391

*22U/6.3V_8

+1.05V_VTT

CPU VCCPL

SNB 45W:1.5A

Spec

330uF/7mohm x 1 10uF x 1 1uF x 2

+VCC_CORE

VCCSENSE 30 VSSSENSE 30

+1.05V_VTT

VCCP_SENSE 31 VSSP_SENSE 31

MAIND29,32,34

C412

10U/6.3V_8

C127

10U/6.3V_8

R359 *short_8R359 *short_8

3

2

3

C109

C126

C370

C370 *22U/6.3V_8

*22U/6.3V_8

Q17

Q17 *2N7002E

*2N7002E

CPU VGT

SNB 45W:21.5A

Spec

470uF/4mohm x 2 22uF x 12

+

C407

C407 *330U/2V_7343

*330U/2V_7343

C67

C67 *22U/6.3V_8

*22U/6.3V_8

+1.8V

+VDDR_REF_CPU+SMDDR_VREF

1

R357

R357 *100K_4

*100K_4

C107

10U/6.3V_8

C59

10U/6.3V_8

C418

4.7U/25V_8

C66

C66 *22U/6.3V_8

*22U/6.3V_8

C439

4.7U/6.3V_6

Sandy Bridge Processor (GRAPHIC POWER)

POWER

R43

R43 75_4

75_4

VR_SVID_ALERT#H_CPU_SVIDALRT#

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

1.8V RAIL

SVID CLK

VR_SVID_CLK 30

SVID DATA

VR_SVID_DATA 30

SVID ALERT

VR_SVID_ALERT# 30

VAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

VCCSA_VID1

Size Document Number Rev

Date: Sheet of

Date: Sheet

+VCC_GFX

+

C392

C392 330U/2V_7343

330U/2V_7343

10U/6.3V_8

4.7U/25V_8

+

C368

C368 *330U/2V_7343

*330U/2V_7343

C374

C105

C106

C373

C417

C87

C87 *22U/6.3V_8

*22U/6.3V_8

C422

1U/6.3V_4

10U/6.3V_8

C57

C58

10U/6.3V_8

C416

C404

4.7U/25V_8

C89

C89 *22U/6.3V_8

*22U/6.3V_8

Del C442. 5/20B54

C438

1U/6.3V_4

Layout note: need routing together and ALERT need between CLK and DATA

VR_SVID_CLK

Place PU resistor close to CPU

+1.05V_VTT

R231

R231 130/F_4

VR_SVID_DATA

Place PU resistor

close to CPU

130/F_4

R42 43_4R42 43_4

AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18

AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24

AL23

AL21

AL20

AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

B6 A6 A2

U14G

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

CPU-989P-rPGA

+1.05V_VTT

2

R247 10/F_4R247 10/F_4

AK35 AK34

R246 10/F_4R246 10/F_4

+VDDR_REF_CPU

AL1

CAD Note: +VDDR_REF_CPU should have 10 mil trace width

AF7 AF4 AF1

C171

AC7

4.7U/25V_8

AC4 AC1 Y7 Y4 Y1 U7 U4 U1

C154

P7

4.7U/25V_8

P4 P1

CPU SA

SNB 45W: 6A

Spec

330uF/7mohm x 1

10uF x 3

M27 M26 L26 J26

4.7U/25V_8

J25 J24 H26 H25

H23

H_FC_C22

C22 C24

8 7

5

MAIND

MAINON_ON_G4,34

Sandy Bridge 3/4

Monday, May 23, 2011

+VCC_GFX

VCC_AXG_SENSE 30 VSS_AXG_SENSE 30

CPU MCH

SNB 45W: 5A

Spec

330uF/6mohm x 1 10uF x 6

+VDDR_REF_CPU

C165

C166

4.7U/25V_8

C161

C155

10U/6.3V_8

C62

C44

VCCSA_SENSE 33

R72 10K_4R72 10K_4

VCCSA_SEL 33

4.5A

R157 *short_1206R157 *short_1206 R158 *short_1206R158 *short_1206

4

Quanta Computer Inc.

PROJECT :

4.7U/25V_8

Q8 *AO4496Q8*AO4496

C164

C164 *470P/50V_4

*470P/50V_4

1

4.7U/25V_8

+1.5V_CPU+1.5V_SUS

1 2 36

2

ZQR

C359

06

Real

10uF x 6

+1.5V_CPU

C153

C159

4.7U/25V_8

+

C156

C156 330U/2V_7343

330U/2V_7343

+VCCSA

+

C335

C335 *330U/2V_7343

*330U/2V_7343

R156

R156 *220_8

*220_8

3

Q9

Q9 *DMN601K-7

*DMN601K-7

1

1A

of

635

Sandy Bridge Processor (POWER)

POWER

U14F

C30

10U/6.3V_8

C379

10U/6.3V_8

C377

10U/6.3V_8

C384

10U/6.3V_8

C321

+VCC_CORE

C31

10U/6.3V_8

C378

10U/6.3V_8

C325

10U/6.3V_8

C332

10U/6.3V_8

C319

10U/6.3V_8

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100

CPU-989P-rPGA

D D

CPU Core Power

SNB 45W:52A

Spec

470uF/4mohm x 4 22uF x 16 10uF x 10

C310

C324

C313 *22U/6.3V_8

*22U/6.3V_8

C53

C C

10U/6.3V_8

C326

C326 *22U/6.3V_8

*22U/6.3V_8

C399

C399 *22U/6.3V_8

*22U/6.3V_8

Mount C70, C71 for +Vcc_core overshoot issue. 5/18B23

+

B B

A A

10U/6.3V_8

C54

10U/6.3V_8

C318

10U/6.3V_8

C398

*22U/6.3V_8

C70

C70 470u/2V_7343

470u/2V_7343

10U/6.3V_8

C84

10U/6.3V_8

C327

10U/6.3V_8

C397

10U/6.3V_8

+

C71

C71 470u/2V_7343

470u/2V_7343

B45 Remove C315 for cost issue. 5/19

C324

C323

C313

10U/6.3V_8

C73

10U/6.3V_8

C375

10U/6.3V_8

C396

10U/6.3V_8

5

C314

10U/6.3V_8

C380

10U/6.3V_8

C376

10U/6.3V_8

C395

10U/6.3V_8

+

C315

*470u/2V_7343

10U/6.3V_8

POWER

PEG AND DDR

CORE SUPPLY

SENSE LINES SVID

4

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

http://mycomp.su/x/

5

4

3

2

1

Sandy Bridge Processor (GND)

U14H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

D D

C C

B B

AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31

F34 F31 F29

U14I

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Sandy Bridge Processor (RESERVED, CFG)

U14E

L7

RSVD28

AG7

TP18TP18 TP79TP79

TP82TP82 TP17TP17 TP80TP80 TP77TP77

TP88TP88

CFG0 CFG1 CFG2 CFG3 CFG4CFG4 CFG5 CFG6 CFG7CFG7

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

VCCIO_SEL

J15

RSVD27

CPU-989P-rPGA

RESERVED

RSVD29 RSVD30 RSVD31 RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

RSVD46 RSVD47 RSVD48 RSVD49 RSVD50

RSVD51 RSVD52

VCC_DIE_SENSE

RSVD54 RSVD55

RSVD56 RSVD57 RSVD58

KEY

AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

AN35 AM35

AT2 AT1 AR1

B1

07

CPU-989P-rPGA

Processor Strapping

The CFG signals have a default value of '1' if not terminated on the board.

10

CFG2

A A

(PEG Stati c Lane Reversal)

CFG4 (DP Presence Strap)

CFG7 (PEG Defer Training)

5

Normal Operation Lane Reversed

Disable; No physical D P attached to eDP

PEG train immediately following xxRESETB de assertion

CPU-989P-rPGA

Enable; An ext DP devi c e is connected to eDP

PEG wait for BIOS training

4

CFG2

CFG7

3

R52 1K/F_4R52 1K/F_4

R30 *1K/F_4R30 *1K/F_4

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Monday, May 09, 2011

Date: Sheet of

Monday, May 09, 2011

Date: Sheet of

2

Monday, May 09, 2011

PROJECT :

Sandy Bridge 4/4

ZQR

735

1

1A

http://mycomp.su/x/

5

4

3

2

1

+3V

Cougar Point (DMI,FDI,PM)

U13C

DMI_RXN04 DMI_RXN14

D D

DMI_RXN24 DMI_RXN34

DMI_RXP04 DMI_RXP14 DMI_RXP24 DMI_RXP34

DMI_TXN04 DMI_TXN14 DMI_TXN24 DMI_TXN34

DMI_TXP04 DMI_TXP14 DMI_TXP24 DMI_TXP34

+1.05V_VTT

C C

B B

R302 49.9/F_4R302 49.9/F_4 R307 750/F_4R307 750/F_4

XDP_DBRST#4

PWROK_EC27

PM_DRAM_PWRGD4

ICH_RSMRST#27

DNBSWON#27

DMI_COMP

DMI2RBIAS

SUS_PWR_ACK

XDP_DBRST#

SYS_PWROK

PWROK_EC INT_CRT_DDCCLK

PM_DRAM_PWRGD

ICH_RSMRST#

SUS_PWR_ACK

AC_PRESENT

PM_BATLOW#

PM_RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

CougarPoint_R1P0

DMI

FDI

DMI

FDI

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

+3V

CLKRUN# / GPIO32

+3V_S5

SUS_STAT# / GPIO61

+3V_S5

SUSCLK / GPIO62

+3V_S5

SLP_S5# / GPIO63

System Power Management

+3V_S5

DSW

+3V_S5

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWVREN

ICH_RSMRST#

PCIE_WAKE#

CLKRUN#

SUS_STAT#

SLP_LAN#

FDI_TXN0 4 FDI_TXN1 4 FDI_TXN2 4 FDI_TXN3 4 FDI_TXN4 4 FDI_TXN5 4 FDI_TXN6 4 FDI_TXN7 4

FDI_TXP0 4 FDI_TXP1 4 FDI_TXP2 4 FDI_TXP3 4 FDI_TXP4 4 FDI_TXP5 4 FDI_TXP6 4 FDI_TXP7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

PCIE_WAKE# 18,19

CLKRUN# 27

TP43TP43

PCH_SUSCLK 27

TP34TP34

SUSC# 27

SUSB# 27

TP38TP38

TP33TP33

PM_SYNC 4

SYNC RS 33ohm for Direct Connect 20ohm for Dock Support 20ohm for Switchable Graphics Device Down Topology 10ohm for Switchable Graphics Dock Support

INT_CRT_HSYNC16 INT_CRT_VSYNC16

R10 2.2K_4R10 2.2K_4 R12 2.2K_4R12 2.2K_4

INT_LVDS_BLON16

INT_LVDS_DIGON16

INT_LVDS_BRIGHT16

INT_LVDS_EDIDCLK16 INT_LVDS_EDIDDATA16

INT_TXLCLKOUTN16 INT_TXLCLKOUTP16

R place close to PCH

R259 150/F_4R259 150/F_4 R258 150/F_4R258 150/F_4 R257 150/F_4R257 150/F_4

+3V

R34 2.7K_4R34 2.7K_4 R35 2.7K_4R35 2.7K_4

INT_CRT_BLU16 INT_CRT_GRE16 INT_CRT_RED16

INT_CRT_DDCCLK16 INT_CRT_DDCDAT16

INT_TXLOUTN016 INT_TXLOUTN116 INT_TXLOUTN216

INT_TXLOUTP016 INT_TXLOUTP116 INT_TXLOUTP216

INT_LVDS_EDIDCLK

INT_LVDS_EDIDDATA

+3V

INT_CRT_BLU INT_CRT_GRE INT_CRT_RED

INT_CRT_DDCDAT

R261 33_4R261 33_4 R260 33_4R260 33_4

INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA

R33 2.2K_4R33 2.2K_4 R32 2.2K_4R32 2.2K_4

R51 2.37K/F_4R51 2.37K/F_4

TP20TP20

INT_TXLCLKOUTN INT_TXLCLKOUTP

INT_TXLOUTN0 INT_TXLOUTN1 INT_TXLOUTN2

INT_TXLOUTP0 INT_TXLOUTP1 INT_TXLOUTP2

INT_CRT_BLU INT_CRT_GRE INT_CRT_RED

INT_CRT_DDCCLK INT_CRT_DDCDAT

INT_CRT_HSYNC_R INT_CRT_VSYNC_R

DAC_IREF

R53

R53 1K/F_4

1K/F_4

Cougar Point (LVDS,DDI)

U13D

J47

M45

P45 T40

K47 T45

P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47

AJ48

AN47 AM49 AK49

AJ47

AF40 AF39

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

N48

P49 T49

T39

M40

M47 M49

T43 T42

CougarPoint_R1P0

L_BKLTEN L_VDD_EN

L_BKLTCTL L_DDC_CLK

L_DDC_DATA L_CTRL_CLK

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

DDPD_AUXP

CRT

DDPD_HPD

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46 P42

AP47 AP49 AT38

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

M43 M36

AT45 AT43 BH41

BB43

DDPD_0N

BB45

DDPD_0P

BF44

DDPD_1N

BE44

DDPD_1P

BF42

DDPD_2N

BE42

DDPD_2P

BJ42

DDPD_3N

BG42

DDPD_3P

DDPC_HPD_PU DDPD_HPD_PU

Follow PDG eDP disable guide

DDPC_HPD_PU

DDPD_HPD_PU

R48 10K_4R48 10K_4 R287 10K_4R287 10K_4

INT_HDMI_SCL 17 INT_HDMI_SDA 17

INT_HDMI_HPD 17

INT_HDMI_TX DN2 17 INT_HDMI_TX DP2 17 INT_HDMI_TX DN1 17 INT_HDMI_TX DP1 17 INT_HDMI_TX DN0 17 INT_HDMI_TX DP0 17 INT_HDMI_TX CN 17 INT_HDMI_TX CP 17

08

INT. HDMI INT. DP

+3V

PCH Pull-high/low(CLG) System PWR_OK(CLG)

U6

4

TC7SH08U6TC7SH08

+3V_S5

3 5

C150

C150 *0.1U/10V_4

*0.1U/10V_4

2 1

R145

R145 100K_4

100K_4

IMVP_PWRGD_R

PWROK_EC

R409

R409 0_4

0_4

+3V

CLKRUN# XDP_DBRST#

ICH_RSMRST#

A A

SYS_PWROK

R350 8.2K_4R350 8.2K_4 R353 10K_4R353 10K_4 R337 *1K_4R337 *1K_4 R303 10K_4R303 10K_4 R91 *10K_4R91 *10K_4 R111 10K_4R111 10K_4

PM_RI# PM_BATLOW# PCIE_WAKE# SLP_LAN# SUS_PWR_ACK AC_PRESENT

PM_DRAM_PWRGD

R326 10K_4R326 10K_4 R105 8.2K_4R105 8.2K_4 R329 10K_4R329 10K_4

R324 10K_4R324 10K_4 R83 10K_4R83 10K_4

R319 200/F_4R319 200/F_4

+3V_S5

SYS_PWROK4

SYS_PWROK

Use R409 to exchange U5, C142 for saving cost 05/17B05

5

4

3

U5

4

*TC7SH08

+3V_S5

3 5

C142

C142 *2.2U/6.3V_4

*2.2U/6.3V_4

2 1

IMVP_PWRGD 4,30 GFX_PWRGD 30

2

+3V_RTC

R309

R309 330K_4

330K_4

DSWVREN

R310

On Die DSW VR Enable

*330K_4

High = Enable (Default)

Low = Disable

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet

Monday, May 23, 2011

Date: Sheet of

PROJECT :

Cougar Point 1/6

ZQR

835

1

of

1A

http://mycomp.su/x/

5

RTC Circuitry(RTC)

20mils

+3V_RTC

D19

+3V_RTC_1

20MIL

+5V

+3V_S5

R338

R338 51_4

51_4

R102 3.3K_4R102 3.3K_4

D19

R301 20K_4R301 20K_4

BAT54C

30mils

R305 20K_4R305 20K_4

C387

C387 1U/6.3V_4

1U/6.3V_4

ACZ_SYNC_R_1 ACZ_RST#_R ACZ_SDOUT_R

2

1

R54 33_4R54 33_4

C39

C39 *10p/50V_4

*10p/50V_4

Q26

2N7002K

ACZ_BITCLK21

R64 33_4R64 33_4 R58 33_4R58 33_4 R288 33_4R288 33_4

R410 10K_4R410 10K_4

R412 1M_4R412 1M_4

R143

R144

210/F_4

PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK

R125

R124

100/F_4

MX25L3205DM2I-12G: AKE39FP0Z00

W25X32VSSIG: AKE39ZP0N00

U4

1

PCH_SPI1_CLK_R PCH_SPI1_SI_R PCH_SPI1_SO_R

C144

C144 *22P/50V_4

*22P/50V_4

5

CE#

6

SCK

5

SI

2

SO

HOLD#

3

WP#

SPI FlashU4SPI Flash

REV: B modify footprint

C400

C400 1U/6.3V_4

1U/6.3V_4

C406

C406 1U/6.3V_4

1U/6.3V_4

ACZ_SYNC_RACZ_SYNC_R_1

3

VDD

VSS

12

J2

*SHORT_ PAD1

12

J1

*SHORT_ PAD1

ACZ_BITCLK_R

EMI

8

R146 3.3K_4R146 3.3K_4

7 4

RTC_RST#

SRTC_RST#

+3VPCU

D D

R299

R299 1K_4

1K_4

20MIL

CON1

1

2

AAA-BAT-054-K01

bat-23_2-4_2

HDA Bus(CLG)

ACZ_SYNC21

C C

ACZ_RST#21

ACZ_SDOUT21

Add a MOSFET Q26,R410,R412 to separate CODE SYNC and PCH Strap signal to avoid leakage issue. 5/19B41

PCH JTAG Debug ( C LG)

B B

PCH Dual SPI (CLG)

PCH_SPI_CS0# PCH_SPI_CLK

A A

PCH_SPI_SI PCH_SPI_SO

R126 *short_4R126 *short_4 R131 *short_4R131 *short_4 R103 *short_4R103 *short_4

+3V

C151

0.1U/10V_4

4

PCH2(CLG)

C389 18P/50V_4C389 18P/50V_4

C390 18P/50V_4C390 18P/50V_4

PCH Strap Table

Pin Name

SPKR

GNT3# / GPIO55

INTVRMEN

GNT1# / GPIO51

GPIO19

HDA_SDO

DF_TVS

GPIO28

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO8

SPI_MOSI

NV_ALE

4

23

4 1

+3V_RTC

+3VPCU

Y2

32.768KHZY232.768KHZ

R298

R298 10M_4

10M_4

R80 1M_4R80 1M_4

SPKR21

ACZ_SDIN021

TP25TP25

TP83TP83

TP115TP115

R333 *10K_4R333 *10K_4

Strap description

No reboot mode setting PWROK

Top-Block Swap Override

Integrated 1.05V VRM enable ALWAYS Should be always pull-up

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

Flash Descriptor Security

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

Integrated Clock Chip Enable

iTPM function Disable APWROK

Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 20kohm)

3

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN

ACZ_BITCLK_R ACZ_SYNC_R SPKR ACZ_RST#_R

ACZ_SDOUT_R

PCH_GPIO33

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO

Sampled

PWROK

RSMRST

PWROK

RSMRST#

3

2

Cougar Point (HDA,JTAG,SATA)

U13A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CougarPoint_R1P0

Configuration

0 = Default (weak pull-down 20K) 1 = Setting to No-Reboot mode

0 = "top-block swap" mode 1 = Default (weak pull-up 20K)

GNT0#GNT1#

11 00

0 = Override 1 = Default (weak pull-up 20K)

0 = Set to Vss 1 = Set to Vcc (weak pull-down 20K)

0 = Disable 1 = Enable (Default)

0 = Support by 1.8V (weak pull-down) 1 = Support by 1.5V

Should be pull-down (weak pull-up 20K)

0 = Default (weak pull-down 20K) 1 = Enable

RTCIHDA

JTAG

SPI

+3V

Boot Location

LPC

FWH4 / LFRAME#

+3V

LDRQ1# / GPIO23

SATA 6G

+3V

SATA

+3V_S5

SATA3RCOMPO

SATA0GP / GPIO21 SATA1GP / GPIO19

SPI

*

LPC

SATAICOMPO

SATA3COMPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPI

SATA3RBIAS

SATALED#

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

+3V_RTC

2

PCH_DRQ#0 PCH_DRQ#1

SERIRQ

SATA_TXN0_C SATA_TXP0_C

SATA_TXN1_C SATA_TXP1_C

SATA_COMP

SATA3_COMP

SATA3_RBIAS

PCH_ODD_EN BBS_BIT0

+3V

ME_WR#27

R327 2.2K_4R327 2.2K_4 R328 1K_4R328 1K_4

R138 *1K_4R138 *1K_4

+3V_S5

R116 *1K_4R116 *1K_4

R264 *1K_4R264 *1K_4

R304 330K_4R304 330K_4

TP23TP23 TP26TP26

C272 0.01U/25V_4C272 0.01U/25V_4 C274 0.01U/25V_4C274 0.01U/25V_4

C101 0.01U/25V_4C101 0.01U/25V_4 C112 0.01U/25V_4C112 0.01U/25V_4

TP45TP45 TP41TP41 TP113TP113 TP114TP114

R101 37.4/F_4R101 37.4/F_4

R104 49.9/F_4R104 49.9/F_4

R342 750/F_4R342 750/F_4

R347 10K_4R347 10K_4

R266 *1K_4R266 *1K_4 R348 *1K_4R348 *1K_4 R272 *1K_4R272 *1K_4 R334 *1K_4R334 *1K_4

R290 *1K_4R290 *1K_4

R284 *Short_4R284 *Short_4

R61 1K_4R61 1K_4

1

LAD0 19,27 LAD1 19,27 LAD2 19,27 LAD3 19,27

LFRAME# 19,27

SERIRQ 27

+3V

SPKR

PCI_GNT3# 10

PCH_INVRMEN

ACZ_SDOUT_R

B06

+1.8V

DF_TVS 11 H_SNB_IVB# 4

PLL_ODVR_EN 11

ACZ_SYNC_R

Size Document Number Rev

Date: Sheet of

Date: Sheet

SERIRQ PCH_ODD_EN

SATA_RXN0 20 SATA_RXP0 20 SATA_TXN0 20 SATA_TXP0 20

SATA_RXN1 20 SATA_RXP1 20 SATA_TXN1 20 SATA_TXP1 20

+1.05V_VTT

BBS_BIT1 10

Change Bottom side 0ȍ R284 to short pad for cost and SMT cycle time issue. 5/17

Default weak pull-up on GNT0/1# [Need external pul l-down for LPC BIOS]

BBS_BIT0

Cougar Point 2/6

Monday, May 23, 2011

R115 8.2K_4R115 8.2K_4 R121 *10K_4R121 *10K_4

SATA HDD

SATA ODD

Quanta Computer Inc.

PROJECT :

1

09

+3V

ZQR

of

935

1A

http://mycomp.su/x/

5

4

3

2

1

Cougar Point-M (PCI-E,SMBUS,CLK)

Cougar Point-M (PCI,USB,NVRAM)

U13E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

D D

C C

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

dGPU_EDIDSEL#

TP12TP12

DGPU_SELECT#

TP11TP11

TP16TP16

TP15TP15 TP13TP13

TP44TP44

R263 22_4R263 22_4 R29 22_4R29 22_4 R49 22_4R49 22_4

GPIO54

MPC_PWR_CTRL# dGPU_PWM_SELECT# DGPU_HOLD_RST# EXTTS_SNI_DRV1_PCH

PCI_PME# PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_EC_R

BBS_BIT19

PCI_GNT3#9

CLK_PCI_FB CLK_PCI_FB_R

CLK_PCI_LPC19

CLK_PCI_EC27

B B

AH37 AK43 AK45

AH12

AB46 AB45

AY16 BG46

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

C18 N30

H3

AM4 AM5

Y13 K24 L24

B21

M20

K40 K38 H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

C6

H49 H43 J48 K42 H40

TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55

PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

PME# PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

CougarPoint_R1P0

RSVD

PCI

+3V +3V +3V

+3V +3V +3V +3V

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

USB

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

USBP1USBP1+

USBP3USBP3+ USBP4USBP4+ USBP5USBP5+

USBP8USBP8+ USBP9USBP9+ USBP10USBP10+

USBP12USBP12+

USB_BIAS

USB_OC0# USB_OC2#

USB_OC3# USB_OC4#

USB_OC6# USB_OC7#

NV_ALE

TP84TP84 TP87TP87

TP30TP30 TP27TP27

TP117TP117

USBP1- 25 USBP1+ 25

USBP3- 25 USBP3+ 25 USBP4- 25 USBP4+ 25 USBP5- 25 USBP5+ 25

USBP8- 16 USBP8+ 16 USBP9- 25 USBP9+ 25 USBP10- 19 USBP10+ 19

USBP12- 23 USBP12+ 23

R291 22.6/F_4R291 22.6/F_4

MB/B-USB1-1

EXT/B-USB1-1 BlueTooth BlueTooth (reserve)

CCD EXT/B-USB1-2 Mini Card (WLAN)

Card Reader

USB_OC0# 25

USB_OC1_5# 25

On Board LAN

WLAN

EHCI1

WLAN CLK

EHCI2

On board LAN CLK

PCIE_R X1-18 PCIE_R X1+18 PCIE_TX1-18 PCIE_TX1+18

PCIE_R X6-19 PCIE_R X6+19 PCIE_TX6-19 PCIE_TX6+19

C42 0.1U/10V_4C42 0.1U/10V_4 C41 0.1U/10V_4C41 0.1U/10V_4

C56 0.1U/10V_4C56 0.1U/10V_4 C49 0.1U/10V_4C49 0.1U/10V_4

PCIE_TXN1_C PCIE_TXP1_C

TP29TP29 TP28TP28 TP31TP31 TP32TP32

PCIE_TXN6_LAN_C PCIE_TXP6_LAN_C

PCIE_CLKREQ0#

Mini - 3G

PCIE_CLKREQ_3G#

TP24TP24 TP19TP19

CLK_PCIE_WLANN CLK_PCIE_WLANP

CLKREQ_WLAN#

PCIE_CLKREQ_REV0#

PCIE_CLKREQ_REV1#

CLK_PCIE_WLANN19 CLK_PCIE_WLANP19

CLKREQ_WLAN#19

Card reader CLK

PCIE_CLKREQ5#

CLK_PCIE_LANN18

CLK_PCIE_LANP18

PCIE_CLKREQ_LAN#18

CLK_PCIE_LANN CLK_PCIE_LANP

PCIE_CLKREQ_LAN#

TP35TP35 TP37TP37

CLK_PCIE_REQ6#

CLK_PCIE_REQ7#

U13B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_R1P0

+3V_S5

SMBUSController

+3V_S5

SML1ALERT# / PCHHOT# / GPIO74

+3V_S5

PCI-E*

+3V_S5

CLOCKS

+3V

+3V_S5

+3V

+3V_S5

+3V

SMBALERT# / GPIO11

SMBDATA

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_DATA1

Link

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SML0CLK

CL_CLK1

SMBALERT#

E12

SMB_PCH_CLK

H14

SMB_PCH_DAT

C9

DRAMRST_CNTRL_PCH

A12

SMB_ME0_CLK

C8

SMB_ME0_DAT

G12

SML1ALERT#_R

C13

SMB_ME1_CLK

E14

SMB_ME1_DAT

M16

M7

T11

P10

PCIE_CLKREQ_PEG#

M10

CLK_PCIE_VGAN

AB37

CLK_PCIE_VGAP

AB38

AV22 AU22

AM12 AM13

CLK_BUF_PCIE_3GPLLN

BF18

CLK_BUF_PCIE_3GPLLP

BE18

CLK_BUF_BCLKN

BJ30

CLK_BUF_BCLKP

BG30

CLK_BUF_DREFCLKN

G24

CLK_BUF_DREFCLKP

E24

CLK_BUF_DREFSSCLKN

AK7

CLK_BUF_DREFSSCLKP

AK5

CLK_PCH_14M

K45

CLK_PCI_FB

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

CLK_FLEX1

F47

CLK_FLEX2

H47 K49

R322 *0_4R322 *0_4

CLK_CPU_BCLKN 4 CLK_CPU_BCLKP 4

CLK_DPLL_SSCLKN 4 CLK_DPLL_SSCLKP 4

R31 90.9/F_4R31 90. 9/F_4

TP74TP74 TP76TP76

DRAMRST_CNTRL_PCH 5

SML1ALERT# 11,26

CL_CLK1 19

CL_DATA1 19

CL_RST1# 19

TP49TP49

TP22TP22 TP21TP21

+1.05V_VTT

SKU_ID1 11

EXT48MHZ 23

R255

R255 1M_4

1M_4

10

For LAN

For EC

C351 27P/50V _4C351 27P/50V_4

21

Y1 25MHzY125MHz

C344 27P/50V_4C344 27P/50V_4

2

SMBus/Pull-up(CLG)CLK_REQ/Strap Pin(CLG)

MBCLK227

MBDATA227

+3V_S5

R321 1K_4R321 1K_4 R93 10K_4R93 10K_4

R109 2.2K_4R109 2.2K_4 R100 2.2K_4R100 2.2K_4 R331 2.2K_4R331 2.2K_4 R95 2.2K_4R95 2.2K_4 R320 10K_4R320 10K_4

+3V_S5

3

+3V_S5

3

R87

2.2K_4

2

SMB_ME1_CLK

1

Q5 2N7002KQ52N7002K

R84

2.2K_4

2

SMB_ME1_DAT

1

Q4 2N7002KQ42N7002K

DRAMRST_CNTRL_PCH SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R

SMBus(PCH)

+3V

R110

2

4.7K_4

SMB_PCH_CLK

3

Q7 2N7002KQ7 2N7002K

SMB_PCH_DAT

3

Q6 2N7002KQ6 2N7002K

Size Document Number Rev

Date: Sheet of

Date: Sheet

Cougar Point 3/6

Monday, May 23, 2011

4.7K_4

1

SMB_RUN_CLK 14,15,19

+3V

R94

2

4.7K_4

1

SMB_RUN_DAT 14,15,19

Quanta Computer Inc.

PROJECT :

1

ZQR

of

10 35

1A

PLTRST#(CLG)

+3V_S5

C440

0.1U/10V_4

PCI_PLTRST#

A A

2 1

3 5

U16

U16 TC7SH08FU

TC7SH08FU

PLTRST#

4

R364

R364 100K_4

100K_4

PLTRST# 4,18,19,23,27

PCI/USBOC# Pull-up(CLG)

R314

10

USB_OC4# USB_OC2#

USB_OC3#

9 8 7 4

10KX8

1 2 3

56

MPC_PWR_CTRL# GPIO54

dGPU_PWM_SELECT#

MPC Switch Control

MPC_PWR_CTRL#

USB_OC7# USB_OC0# USB_OC6# USB_OC1_5#

+3V

10

9 8 7 4

R50 *1K_4R50 *1K_4

PCI_PIRQA#

R22 8.2K_4R22 8.2K_4

PCI_PIRQB#

R25 8.2K_4R25 8.2K_4

PCI_PIRQC#

R27 8.2K_4R27 8.2K_4

PCI_PIRQD#

R38 8.2K_4R38 8.2K_4

R40

10KX8

Low = MPC ON High = MPC OFF (Default)

DGPU_HOLD_RST#

1

EXTTS_SNI_DRV1_PCH

2

dGPU_EDIDSEL#

3

DGPU_SELECT#

56

+3V_S5

+3V+3V_S5

R355 10K_4R355 10K_4 R330 10K_4R330 10K_4 R112 10K_4R112 10K_4 R89 10K_4R89 10K_4 R140 10K_4R140 10K_4 R137 10K_4R137 10K_4 R106 10K_4R106 10K_4

+3V

R351 10K_4R351 10K_4 R362 10K_4R362 10K_4

+3V_S5

R142 10K_4R142 10K_4 R141 *10K_4R141 *10K_4

CLK_BUF_BCLKN CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN CLK_BUF_PCIE_3GPLLP CLK_BUF_DREFCLKN CLK_BUF_DREFCLKP CLK_BUF_DREFSSCLKN CLK_BUF_DREFSSCLKP CLK_PCH_14M

PCIE_CLKREQ0# PCIE_CLKREQ_REV0# PCIE_CLKREQ_REV1# PCIE_CLKREQ5# PCIE_CLKREQ_LAN# CLK_PCIE_REQ6# CLK_PCIE_REQ7#

PCIE_CLKREQ_3G# CLKREQ_WLAN#

PCIE_CLKREQ_PEG#

R294 10K_4R294 10K_4 R292 10K_4R292 10K_4

R313 10K_4R313 10K_4 R311 10K_4R311 10K_4 R82 10K_4R82 10K_4 R79 10K_4R79 10K_4 R107 10K_4R107 10K_4 R113 10K_4R113 10K_4 R262 10K_4R262 10K_4

CLOCK TERMINATION for FCIM

5

4

3

http://mycomp.su/x/

5

4

3

2

1

Cougar Point (GPIO,VSS_NCTF,RSVD)

U13F

S_GPIO

EC_EXT_SMI#27

D D

check VR_ON GPIO

EC_EXT_SCI#27

TP111TP111

TP10TP10

PLL_ODVR_EN9

Need Check

C C

TP40TP40 TP42TP42

SML1ALERT#10,26

EC_EXT_SMI# BOARD_ID1 EC_EXT_SCI#

SMIB# PCH_GPIO15

SKU_ID0

dGPU_PWROK BIOS_REC CR_WAKER# GPIO27 PLL_ODVR_EN STP_PCI# dGPU_VRON DMI_OVRVLTG FDI_OVRVLTG MFG_MODE BOARD_ID0 TEST_SET_UP

R148 *short_4R148 *short_4

BOARD_ID2

CRIT_TEMP_REP#

SV_SET_UP

High = Strong (Default)

B B

+3V

TEST_SET_UP

PCH_GPIO15

Intel ME Crypto Transport Layer Security (TLS) cipher suite

Low = Disable (Default)

High = Enable

A A

FDI TERMINATION VOLTAGE OVERRIDE

R136 10K_4R 136 10K_4 R120 *0_4R120 *0_4

+3V_S5

R356 1K_4R356 1K_4

FDI_OVRVLTG DMI_OVRVLTG BIOS_REC

R122 *10K/F_4R122 *10K/F_4

LOW - Tx, Rx terminated to same voltage

5

SGPIO

S_GPIO

MFG-TEST

MFG_MODE

R135 1K/F_4R135 1K/F_4 R118 *100_4R118 *100_4

R349 10K_4R349 10K_4 R335 *0_4R335 *0_4

DMI TERMINATION

VOLTAGE OVERRIDE

+3V

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_R1P0

GPIO27: Un-multiplexed. Can be configured as wake input to allow wakes from Deep Sleep. If not used then use 8.2-kȍ to 10-kȍ pull-down to GND.

R128 *200K/F_4R 128 *200K/F_4

Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT)

4

+3V

+3V_S5

+3V

+3V_S5

DSW

+3V_S5

+3V

+3V_S5

+3V

TACH4 / GPIO68

+3V

TACH5 / GPIO69

+3V

TACH6 / GPIO70

+3V

TACH7 / GPIO71

+3V_S5

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

+3V

+3V+3V +3V

NCTF

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

C40 B41 C41 A40

P4

A20GATE

AU16

PECI

P5

RCIN#

AY11 AY10 T14

INIT3_3V#

AY1

DF_TVS

AH8

TS_VSS1

AK11

TS_VSS2

AH10

TS_VSS3

AK10

TS_VSS4

P37

NC_1

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

BIOS RECOVERY

3

DGPU_PRSNT#

R280 1.5K/F_4R280 1.5K/F_4 R276 1.5K/F_4R276 1.5K/F_4 R279 1.5K/F_4R279 1.5K/F_4

EC_A20GATE

R325 *0_4R325 *0_4

EC_RCIN#

PCH_THRMTRIP#

R323 390_4R323 390_4

GPIO Pull-up/Pull-down(CLG)

CR_WAKER# SMIB#

PLL_ODVR_EN

EC_EXT_SMI# EC_EXT_SCI#

STP_PCI# EC_A20GATE EC_RCIN# CRIT_TEMP_REP#

dGPU_PWROK

R353??

R134 10K_4R 134 10K_4 R117 *0_4R117 *0_4

GPIO27

High = Disable (Default)

Low = Enable

+3V

TP36TP36

EC_A20GATE 27 EC_PECI 4,27 EC_RCIN# 27 H_PWRGOOD 4 PM_THRMTRIP# 4

DF_TVS 9

R108 10K/F_4R108 10K/F_4 R341 10K_4R341 10K_4 R139 *10K_4R139 *10K_4

R278 10K_4R278 10K_4 R41 10K_4R41 10K_4

R354 *10K_4R354 *10K_4 R119 10K_4R119 10K_4 R123 10K_4R123 10K_4 R147 10K_4R147 10K_4

R23 *10K_4R23 *10K_4

R86 *10K_4R86 *10K_4

2

+3V_S5

+3V

DGPU_PRSNT# (GPIO68)

Size Document Number Rev

Date: Sheet of

Date: Sheet

SKU_ID1 (GPIO64)

1

0

+3V

R281 IV@10K_4R281 IV@10K_4 R282 *EV@100K_4R282 *EV@100K_4

+3V

R37 *EV@10K_4R37 *EV@10K_4 R36 IV@10K_4R36 IV@10K_4

+3V

R345 *10K_4R345 *10K_4 R332 IV@10K_4R332 IV@10K_4

R336 10K_4R 336 10K_4 R45 10K_4R45 10K_4

R339 100K_4R339 100K_4

Cougar Point 4/6

Monday, May 23, 2011

SKU_ID0 (GPIO16)

0

DGPU_PRSNT#

SKU_ID0

BOARD_ID0 BOARD_ID1

BOARD_ID2

Quanta Computer Inc.

PROJECT :

11

VGA H/W

Setup Menu

Signal

UMA HiddenUMA Only

SKU_ID1 10

R352 *10K_4R352 *10K_4 R46 *10K_4R46 *10K_4

R340 *10K_4R340 *10K_4

ZQR

11 35

1

of

UMA boot

+3V_S5

+3V

1A