QUANTA ZQK Schematics

5

Memory Down x8pcs

4

3

ZQK ULV SYSTEM BLOCK DIAGRAM

2

1

Channel A

D D

Max. 4G

P13,14

DDRIII-SODIMM x1pc

P15

256Mb X 16 * 8pcs

Channel B

Dual Channel DDR III 1333/1600 MHZ

IMC

Ivy Bridge

BGA 1023
17W

P2,3,4,5,6

FDI

DMI

PCI-E
X8

eDP

INT_eDP

GPU

N14P-GV2

Display

P16~P21

4 Lane reserve

DMI(x4)

SATA - HDD

MINI CARD 2
mSATA SSD

USB3.0/2.0 Port
(Charger)

C C

USB2.0 Port

I/O board

USB2.0 Port

P31

CCD(Camera)

P31

P27

P26

P31

P24

SATA 0

SATA 1

USB3.0-(1)
USB2.0-(0)

USB2.0-(1)

USB2.0-(4)

USB2.0-(8)

P8

USB2.0

BATTERY

Azalia

B B

FDI

SATA

SATA

USB3.0

Panther Point

USB2.0

RTC

IHDA

P7, 8, 9, 10, 11, 12

PCH
BGA 989

LPC

DMI

Display

Display

PCI-E x1

PCI-E x1

INT_DP

USB3.0-(3)

INT_HDMI

X'TAL

32.768KHz

X'TAL
25MHz

SPI

SPI ROM*2

2M+4M(EC)

P8

128Mb X 16 * 4pcs = 1GB
256Mb X 16 * 4pcs = 2GB

X'TAL

27.0MHz

USB2.0-(3)

Dongle SW

HD3SS2521RHUR

PCIE-8

USB2.0-(10)

PCIE-3

eDP Con.
Touch Panel (option)

P23

HDMI Con.

MINI CARD1
WLAN+BT

RTL8411AAR

W/Card Reader

P25

Giga LAN

VRAM Max. 2G

DDR3

P24

Mini DP Con.

P26

P28

P21

P23

RJ45 CONN

Card Reader CONN

P28

P29

ALC3225

AUDIO CODEC

Int. DMIC

TPL@

Touch panel
TPM@ TPM module
NP@
CH@
NCH@

A A

EV@
RAMID@
SUG@
NSW@
SW@

Normal panel(Default)

Charge function(Default)

No Charge function

Optimize SKU

RAMID strap pin

LAN Surge

w/o Dongle switch

w Dongle switch

P30

Combo Jack

P30

Speaker

ALC1001

P30

P30

AMP

P30

K/B Conn

P30

HALL SENSOR

AH9249NTR-G1

EC ITE 8587

P24

Touch Pad
Con.

P30

P34

Fan*2 (PWM Type)

P32

KBL@ KB Backlight LED
RD@

mSATA Re-driver

5

4

3

TPM

2

P27

BQ24737RGRR

Batery Charger

TPS51225RUKR

3V/5V

TPS51650RSLR

+VCC_CORE/+VCC_GFX

TPS51219RTER

+1.05V_VTT

TPS51216RUKR

+1.5V_SUS

P35

TPS51463

VCCSA

P36

uP1642PQAG

+VGPU_CORE

P40

TPS51211DSCR

+1.5V_GFX/1.05V_GFX/3V_GFX

P38

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Discharger

P37

Thermal Protection

P39

P43

P42

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Block Diagram

Block Diagram

Block Diagram

1

ZQK

ZQK

ZQK

P41

1A

1A

1 46Monday, January 07, 2013

1 46Monday, January 07, 2013

1 46Monday, January 07, 2013

1A

5

4

3

2

1

Ivy Bridge Processor (DMI,PEG,FDI) (CPU)

PEG_ICOMPI and RCOMPO signals
should be shorted and routed with

U47A

P10

P11

W11

AA6

AC9

W10

AA7

AA3
AC8

AA11
AC12

U11

AA10

AG8

AF3
AD2

AG11

AG4

AF4

AC3
AC4

AE11

AE7
AC1

AA4

AE10

AE6

W1
W6

W3
W7

M2

P6
P1

N3

P7
P3

K1
M8
N4
R2

K3
M7

P4

T3

U7

V4

Y2

U6

T4

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT
FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

eDP_AUX#
eDP_AUX

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

Ivy Bridge

DMI Intel(R) FDI DP

DMI_TXN0[7]
DMI_TXN1[7]
DMI_TXN2[7]

D D

C C

eDP_ICOMPO 12mil
eDP_COMPIO 4mil

B B

DMI_TXN3[7]

DMI_TXP0[7]
DMI_TXP1[7]
DMI_TXP2[7]
DMI_TXP3[7]

DMI_RXN0[7]
DMI_RXN1[7]
DMI_RXN2[7]
DMI_RXN3[7]

DMI_RXP0[7]
DMI_RXP1[7]
DMI_RXP2[7]
DMI_RXP3[7]

FDI_TXN0[7]
FDI_TXN1[7]
FDI_TXN2[7]
FDI_TXN3[7]
FDI_TXN4[7]
FDI_TXN5[7]
FDI_TXN6[7]
FDI_TXN7[7]

FDI_TXP0[7]
FDI_TXP1[7]
FDI_TXP2[7]
FDI_TXP3[7]
FDI_TXP4[7]
FDI_TXP5[7]
FDI_TXP6[7]
FDI_TXP7[7]

FDI_FSYNC0[7]
FDI_FSYNC1[7]

FDI_INT[7]

FDI_LSYNC0[7]
FDI_LSYNC1[7]

EDP_COMP
INT_EDP_HPD#

EDP_AUXN[24]
EDP_AUXP[24]

EDP_TXN0[24]
EDP_TXN1[24]
EDP_TXN2[24]
EDP_TXN3[24]

EDP_TXP0[24]
EDP_TXP1[24]
EDP_TXP2[24]
EDP_TXP3[24]

EDP_AUXN
EDP_AUXP

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS -- GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_COMP

PEG_RX#15 [16]
PEG_RX#14 [16]
PEG_RX#13 [16]
PEG_RX#12 [16]
PEG_RX#11 [16]
PEG_RX#10 [16]
PEG_RX#9 [16]
PEG_RX#8 [16]

PEG_RX15 [16]
PEG_RX14 [16]
PEG_RX13 [16]
PEG_RX12 [16]
PEG_RX11 [16]
PEG_RX10 [16]
PEG_RX9 [16]
PEG_RX8 [16]

PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,

PEG_TX#15 [16]
PEG_TX#14 [16]
PEG_TX#13 [16]
PEG_TX#12 [16]
PEG_TX#11 [16]
PEG_TX#10 [16]
PEG_TX#9 [16]
PEG_TX#8 [16]

PEG_TX15 [16]
PEG_TX14 [16]
PEG_TX13 [16]
PEG_TX12 [16]
PEG_TX11 [16]
PEG_TX10 [16]
PEG_TX9 [16]
PEG_TX8 [16]

0.22uF AC coupling Caps for PCIE GEN1/2/3

- max length = 500 mils

- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical impedance = 14.5 mohms

02

DG 1.0 :

DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with

- typical impedance < 25 mohms

DP & PEG Compensation

CAD Note: Place PU resistor
within 2 inches of CPU

A A

EDP_COMP

PEG_COMP

R669 24.9/F_4

R675 24.9/F_4

+1.05V_VTT

+1.05V_VTT

5

The recommended AC cap value is changed to 220nF for compatibility with
PCIe Gen3 on future platforms.
For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

eDP Hot-plug (Disable)

HPD PU/PD resistor values based
on CRB and different to DG

4

+1.05V_VTT

INT_EDP_HPD#

Q23

2N7002K

R327
1K/J_4

3

2

1

R310
100K/J_4

3

EDP_HPD [24]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

2

Monday, January 07, 2013

PROJECT :

Ivy Bridge 1/5 (HOST & PCIE)

Ivy Bridge 1/5 (HOST & PCIE)

Ivy Bridge 1/5 (HOST & PCIE)

1

ZQK

ZQK

ZQK

1A

1A

1A

462

462

462

5

4

3

2

Boot S3 S3 RSM

1

+1.5V_CPU

03

DRAM_PWRGD

Ivy Bridge Processor (CLK,MISC,JTAG) (CPU)

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

C841
39P/50V_4

U47B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPW ROK

RESET#

Ivy Bridge

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

JTAG & BPM

BCLK#

BCLK_ITP

BCLK_ITP#

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H2

AG3

CLK_DPLL_SSCLKP_R

AG1

CLK_DPLL_SSCLKN_R

N59

CLK_PCIE_XDPP_R

N58

CLK_PCIE_XDPN_R

Isolate Space:20mils

AT30

BF44

SM_RCOMP_0

BE43

SM_RCOMP_1

BG43

SM_RCOMP_2

SM_RCOMP Impedance 85ohm

N53
N55

L56
L55
J58

M60

TDI

L59

K58

XDP_DBRST#_R

G58
E55
E59
G55
G59
H60
J59
J61

TP44
TP49
TP47
TP43
TP74
TP77
TP78
TP75

CLK_CPU_BCLKP [9]
CLK_CPU_BCLKN [9]

R677 0/J_4
R676 0/J_4

R750 *0/J_4
R749 *0/J_4

CPU_DRAMRST# [4]

R707 140/F_4
R702 25.5/F_4
R705 200/F_4

XDP_PRDY#
XDP_PREQ#

XDP_TRST#
XDP_TDI_VT

R745 0/J_4

TP50
TP42

XDP_TCLK_VT [8]
XDP_TMS_VT [8]

TP73
TP76

PCH_XDP_TDO_VT [8]

XDP_DBRST# [7]

CLK_DPLL_SSCLKP [9]
CLK_DPLL_SSCLKN [9]

CLK_PCIE_XDPP [9]
CLK_PCIE_XDPN [9]

Momory Down Layout notes

CAD NOTE: All DDR_COMP signals
should be routed such that :-

- max length = 500 mils

- trace width = 15mils and

- MB trace impedance < 68 mohms
(worst case resistance)

Layout Notes: Place near to XDP connector
05/15：PCH_XDP_TDO_VT already pull high
+3V_S5 on PCH side

+1.05V_VTT

Option for Prochot# function
68 ohm for unused, 62 ohm for used

H_PROCHOT#

XDP_TMS_VT
XDP_TDI_VT

XDP_PREQ#

XDP_TCLK_VT
XDP_TRST#

When MP, JTAG PU/PD resistor can be
removed? (Yes Intel, TDI, TDO, TMS, TRST#,
TCK,PREQ#, PRDY#)

D D

H_SNB_IVB#[8]

TP46

TP_CATERR#

TP54

EC_PECI[10,34]

H_PROCHOT#[34,35,40]

PM_THRMTRIP#[10]

R715 56/J_4
C770 *43P/50V_4

H_PROCHOT#_R

12

Over 130 degree C will drive low

C C

PM_SYNC[7]

H_PWRGOOD[10]

Isolate Space:20mils

+1.05V_VTT

B B

R735 75/F_4

CPU_PLTRST#

R720 0/J_4

C774 39P/50V_4
R719 0/J_4
R717 10K/J_4

PM_DRAM_PWRGD_R

R740 43/J_4

PM_SYNC_R

H_PWRGOOD_R

CPU_PLTRST#_R

R736

*750/F_4

SYS_PWROK

SM_DRAMPWROK

If motherboard only supports external graphics or if it supports
Processor Graphics but without eDP:
Connect DPLL_REF_SSCLK on Processor to GND through 1K +/­5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistor

R754 51/J_4

R722 62/J_4

R379 51/J_4
R755 51/J_4

R378 *51/J_4

R746 51/J_4
R744 51/J_4

PCH_XDP_TDO_VT

+1.05V_VTT

100 ns after +1.5V_CPU
reaches 80%

+3V

Thermal Trip (CPU) S3 leakage circuit (CPU)

C453

4

CPU_PLTRST#

CPU_PLTRST#_R

ZQK

ZQK

ZQK

0.1u/10V_4

1A

1A

1A

463

463

463

If PM_DRAM_PWEGD connector,the R5180 must stuff.

+3V_S5

+1.05V_VTT

3

2

1

2

1 3

Q67

2N7002K

R734
1K/J_4

Q66

MMBT3904-7-F_200MA

SYS_SHDN# [27,36,41]

IMVP_PWRGD[7,40]

A A

PM_THRMTRIP#

5

+1.5V_CPU

4

20111121 add Q31 becaue Vh=2.1/Vl=0.9.

R368

R367
*10K/J_4

*1K/J_4

6

2

5

*2N7002DW
Q31

1

4 3

PM_DRAM_PWRGD[7]

20111030 add resistor.

SYS_PWROK[7]

R384 0/J_4

+3V_S5

U24

2
1

74AHC1G09

3 5

R385 *0/J_4

3

C446

0.1u/10V_4

4

+1.5V_CPU

R396
200/F_4

R395 130/F_4

R387 *39/J_4

MAINON_G[5,41]

PM_DRAM_PWRGD_RPM_DRAM_PWRGD_Q

3

Q33 *2N7002K

2

2

1

20111128 change net to PCI_PLTRST#

PCI_PLTRST#[9,34]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Ivy Bridge 2/5 (CLK & JTAG)

Ivy Bridge 2/5 (CLK & JTAG)

Ivy Bridge 2/5 (CLK & JTAG)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

U50

1

VCC5NC

2

IN
GND3OUT

74LVC1G07GW_NC

R747 *1.5K/F_4

IN OUT

L L
H High-Z

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

5

4

3

2

1

Ivy Bridge Processor (CPU)

Channel A: On board RAM 2Rx16 8pcs

U47C

M_A_DQ[63:0][13,14]

D D

C C

M_A_BS#0[13,14]
M_A_BS#1[13,14]
M_A_BS#2[13,14]

B B

M_A_CAS#[13,14]
M_A_RAS#[13,14]
M_A_WE#[13,14]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AP11
AJ10

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

AG6

SA_DQ[0]

AJ6

SA_DQ[1]
SA_DQ[2]

AL6

SA_DQ[3]
SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]
SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]
SA_DQ[14]
SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AT40
AU40
BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 [13]
M_A_CLK0# [13]
M_A_CKE0 [13]

M_A_CLK1 [14]
M_A_CLK1# [14]
M_A_CKE1 [14]

M_A_CS#0 [13]
M_A_CS#1 [14]

M_A_ODT0 [13]
M_A_ODT1 [14]

M_A_DQSN[7:0] [13,14]

M_A_DQSP[7:0] [13,14]

M_A_A[15:0] [13,14]

M_B_DQ[63:0][15]

M_B_BS#0[15]
M_B_BS#1[15]
M_B_BS#2[15]

M_B_CAS#[15]
M_B_RAS#[15]
M_B_WE#[15]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

Channel B: SO-DIMM

U47D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7

M_B_CLK0 [15]
M_B_CLK0# [15]
M_B_CKE0 [15]

M_B_CLK1 [15]
M_B_CLK1# [15]
M_B_CKE1 [15]

M_B_CS#0 [15]
M_B_CS#1 [15]

M_B_ODT0 [15]
M_B_ODT1 [15]

DDR SYSTEM MEMORY B

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

04

M_B_DQSN[7:0] [15]

M_B_DQSP[7:0] [15]

M_B_A[15:0] [15]

Ivy Bridge

+0.75V_DDR_VTT

M_A_A0

R263 36/J_4

M_A_A1

R617 36/J_4

M_A_A2

R603 36/J_4

M_A_A3

R262 36/J_4

M_A_A4

R636 36/J_4

M_A_A5

R293 36/J_4

M_A_A6

R304 36/J_4

M_A_A7

R650 36/J_4

M_A_A8

R297 36/J_4

M_A_A9

R619 36/J_4

M_A_A10

R239 36/J_4

M_A_A11

R282 36/J_4

M_A_A12

R602 36/J_4

M_A_A13

R640 36/J_4

M_A_A14

S3 leakage circuit (CPU)

S3 circuit: DRAM_RST# to memory should be high

A A

during S3

DDR3_DRAMRST#[13,14,15] CPU_DRAMRST# [3]

DRAMRST_CNTRL_PCH[9]

EC_DRAMRST_CNTRL[34]

DEEPS3_EC[13,14,15]

R681 1K/F_4

R682 *0/J_4

R683 0/J_4

20120204 Change to EC for new BIOS 0.6

5

+1.5VSUS

20120914 Follow Z09 design to move R682 close to Q62

+3V_S5

R686
1K/J_4

3

R684 *0/J_4

Q62 2N7002K

2

C678

0.047u/10V_4

1

4

R680
1K/F_4

R693

4.99K/F_4

M_A_A15
M_A_CS#0

M_A_CS#1
M_A_CKE0

M_A_CKE1
M_A_ODT0

M_A_ODT1
M_A_WE#

M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1
M_A_BS#2

R287 36/J_4
R601 36/J_4

R238 36/J_4
R259 36/J_4

R237 36/J_4
R260 36/J_4

R257 36/J_4
R256 36/J_4

R240 36/J_4
R258 36/J_4
R236 36/J_4

R600 36/J_4
R264 36/J_4
R261 36/J_4

3

Ivy Bridge

C239
1u/6.3V_4

C238
1u/6.3V_4

C240
1u/6.3V_4

20120112 for memory down PU CAP.

2

C237
1u/6.3V_4

C236
1u/6.3V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

10u/6.3V_6

1u/6.3V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Ivy Bridge 3/5 (DDR3 I/F)

Ivy Bridge 3/5 (DDR3 I/F)

Ivy Bridge 3/5 (DDR3 I/F)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

ZQK

ZQK

ZQK

1

C279

C241

1A

1A

1A

464

464

464

5

IVY Bridge Processor (POWER) (CPU)

U47F

+VCC_CORE

A26

20120120 remove C621 for debug IC.

C755
10u/6.3V_6

C754
10u/6.3V_6

C756
10u/6.3V_6

C354

2.2u/10V_4

C367

2.2u/10V_4

C730

2.2u/10V_4

C366

2.2u/10V_4

C392

2.2u/10V_4

C846

39P/50V_4

SVID CLK

VR_SVID_CLK [40]

C760
10u/6.3V_6

C344

2.2u/10V_4

C744

2.2u/10V_4

C700

2.2u/10V_4

C696

2.2u/10V_4

C369

2.2u/10V_4

C737

+

470u/2V_7343

39P/50V_4

C847

C759
10u/6.3V_6

C758
10u/6.3V_6

C705
10u/6.3V_6

C743

2.2u/10V_4

C377

2.2u/10V_4

C697

2.2u/10V_4

C748

2.2u/10V_4

C375

2.2u/10V_4

C738

470u/2V_7343

20120120 remove C622 for debug IC.

C698

C336

2.2u/10V_4

2.2u/10V_4

C365

C356

2.2u/10V_4

2.2u/10V_4

C345

C368

2.2u/10V_4

2.2u/10V_4

C701

C731

2.2u/10V_4

2.2u/10V_4

C393

C363

2.2u/10V_4

2.2u/10V_4

C844

C843

39P/50V_4

R710 0/J _4

C757
10u/6.3V_6

C753
10u/6.3V_6

C706
10u/6.3V_6

C355

2.2u/10V_4

C699

2.2u/10V_4

C346

2.2u/10V_4

C376

2.2u/10V_4

C391

2.2u/10V_4

C845

39P/50V_4

5

D D

C364

C C

B B

A A

2.2u/10V_4

C374

2.2u/10V_4

C338

2.2u/10V_4

C695

2.2u/10V_4

C337

2.2u/10V_4

CPU Core Power

IVY 17W:TDC 33A
IVY SPEC

1.9mΩ/LoadlineDesign
total : 2.2uF x 35
total : 22uF x 12
tatal : 470u x3(Power side*1)

Cose down

IVY SPEC

1.9mΩ/LoadlineDesign
total : 2.2uF x 35
total : 10uF x 12
tatal : 470u x1(Power side*1)

20121203：：：：Add 39pF for ESD

+VCC_CORE +1.05V_VTT +VCC_GFX +VCCSA +1.5V_CPU +1.8V

C842

39P/50V_4

39P/50V_4

Layout note: need routing
together and ALERT need
between CLK and DATA

H_CPU_SVIDCLK

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

+

Place PU resistor close to CPU Place PU resistor close to CPU

H_CPU_SVIDDAT

CORE SUPPLY

VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

Ivy Bridge

+1.05V_VTT +1.05V_VTT

R709
130/F_4

R712 0/J _4

PEG AND DDRSENSE LINES SVID QUIET RAILS

POWER

VSS_SENSE_VCCIO

VCCIO_SENSE

4

+1.05V_VTT

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]

AB20

VCCIO[33]

AC13

VCCIO[34]

AD16

VCCIO[35]

AD18

VCCIO[36]

AD21

VCCIO[37]

AE14

VCCIO[38]

AE15

VCCIO[39]

AF16

VCCIO[40]

AF18

VCCIO[41]

AF20

VCCIO[42]

AG15

VCCIO[43]

AG16

VCCIO[44]

AG17

VCCIO[45]

AG20

VCCIO[46]

AG21

VCCIO[47]

AJ14

VCCIO[48]

AJ15

VCCIO[49]

W16

VCCIO50

W17

VCCIO51

BC22

VIDSCLK

VIDSOUT

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

VCCIO_SEL

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R357 100/F_4

R354 100/F_4

R325 10/J_4

R326 10/J_4

4

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VCC_SENSE
VSS_SENSE

SVID DATA SVID ALERT

VR_SVID_DATA [40]

CPU VCCIO

IVY 17W:8.5A

SNB : Spec

330uF/6mohm x 2
10uF x 10
1uF x 26

C654

C655

10u/6.3V_6

10u/6.3V_6

C660

C648

10u/6.3V_6

10u/6.3V_6

C407

C401

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C394

C325

C331

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

IVY SPEC
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2

R328 0/J _6

TP70

R344 0/J _4
C340 1u/6.3 V_4

+VCC_CORE

+1.05V_VTT

Cose down

330uF/6mohm x 1
10uF x 10
1uF x 26

+

C641
330u/2V_7343

C342

C652

C372

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C645

C349

C353

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C348

C299

C297

C328

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C298

C400

C296

+1.05V_VTT

+1.05V_VTT

1u/6.3V_4

VCC_SENSE [40]
VSS_SENSE [40 ]

VCCP_SENSE [38]
VSSP_SENSE [3 8]

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

Voltage selection for VCCIO:
this pin must be pulled high
on the motherboard

On CRB
H_SNB_IVB#_PWRC TRL = low, 1.0 V
H_SNB_IVB#_PWRC TRL = high/NC, 1.05V

R714 43/J_4

C409
1u/6.3V_4

C395
1u/6.3V_4

C408
1u/6.3V_4

C321
1u/6.3V_4

R711
75/F_4

VR_SVID_ALERT#_RH_CPU_SVIDALRT#

C664
1u/6.3V_4

C370
1u/6.3V_4

C323
1u/6.3V_4

C326
1u/6.3V_4

R713 0/J _4

C295
1u/6.3V_4

C350
1u/6.3V_4

C332
1u/6.3V_4

C324
1u/6.3V_4

3

CPU VCCAXG

IVY 17W:TDC 18A

Spec

3.9mΩ/LoadlineDesign
total : 1uF x 11
total : 10uF x 6
total : 22uF x 6
tatal : 470u x 1(power side*2)

VR_SVID_ALERT# [40 ]

3

Cose down

3.9mΩ/LoadlineDesign
total : 1uF x 11
total : 10uF x 12
tatal : 470u x 1(power side*2)

CPU VCCPL

IVY 17W:1.5A

Spec

330uF/7mohm x 1
1uF x 2

IVY SPEC
330uF x1, 10uF_8 x1, 1uF_4 x2
Socket BOT edge.

IVY SPEC
330uF x1, 10uF_8 x1 Socket BOT edge,
10uF_8 x2 Socket BOT cavity.

CPU VCCSA

IVY 17W: 6A

Spec

330uF/7mohm x 1
10uF x 5
1uF x 5

Real

10uF x 3

+SMDDR_VREF +VDDR_R EF_CPU +1.5V_CPU

MAIND[36,37,41]

S3 circuit: 1.5V input to IVB is gated &
IVB Read Vref 0.75V is gated

C463
10u/6.3V_6

C468
10u/6.3V_6

C402
1u/6.3V_4

VCCAXG_SENSE/VS SAXG_SENSE R=1 00,
Trace impedance 15.5~34.5, <2 5mils.

Real

10uF x 1

+1.8V

1uF x 2

C658
10u/6.3V_6

R739 *0/J_8

3

2

MAIND

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C449

C444

C467

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C404

C435

C447

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C399

C405

C406

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

+VCC_GFX

VCC_AXG_SENSE[40]

VSS_AXG_SENSE[40]

R667 0/J_8

C670

C666

10u/6.3V_6

10u/6.3V_6

C334

C320

1u/6.3V_4

1u/6.3V_4

S3 ST UFF NO_ STUFF
enable -
disable -

R5347/R6362

20111024 from +1.5VSUS change to +1.5V_CPU

1

Q65
2N7002K

R751
100K/J_4

C462

C457

C445

2

IVY Bridge Processor (GRAPHIC POWER) (CPU)

U47G

+VCC_GFX

AA46

VAXG[1]

AB47

VAXG[2]

AB50

C657

10u/6.3V_6

C327
1u/6.3V_4

C455
10u/6.3V_6

C454
10u/6.3V_6

C451
1u/6.3V_4

C410
1u/6.3V_4

R386 100/J_4

R388 100/J_4

CPU_VCCPLL

C668
1u/6.3V_4

10u/6.3V_6

C322
1u/6.3V_4

C669
1u/6.3V_4

C672

R738
*1K/F_4

R748
*1K/F_4

2

C792

+

470u/2V_7343

C458
10u/6.3V_6

C450
10u/6.3V_6

C443
1u/6.3V_4

C403
1u/6.3V_4

TP56

TP57

+

C656
330u/2V_7343

C335
1u/6.3V_4

R5347/R6362

change to 1K/F_4

+

C662
*330u/2.5V_352 8

+VCCSA

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

Ivy Bridge

20111107 stuff Q5010 and un-stuff R5347/R362.

4.5A

MAINON_G[3,41]

GRAPHICS

LINES

1.8V RAIL

SA RAIL

POWER

SENSE

R362 *0_1206

R365 *0_1206

Q64 AO4496

8
7

5

4

MAIND

MAINON_G

SM_VREF

VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]

DDR3 - 1.5V RAILS

VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

VCCDQ[1]
VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

1
2
36

C779
470P/50V_4

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]

+1.5V_CPU+1.5VSUS

2

1

CAD Note: +VDDR_REF_CPU should
have 10 mil trace width

AY43

+VDDR_REF_CPU

+1.5V_CPU

AJ28
AJ33
AJ36
AJ40
AL30

10u/6.3V_6

AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38

10u/6.3V_6

AR26
AR28
AR30
AR32
AR34
AR36

C397

AR40
AV41

1u/6.3V_4

AW26
BA40
BB28
BG33

C439
1u/6.3V_4

AM28
AN26

C378 1u/6.3V_4

BC43

R373 *51/J_4

BA43

R372 *51/J_4

R674 *100 /F_4

U10

SNB_IVB# N.A at SNB EDS #27637 0.7v1

R723 *10K /J_4
C777 *33n/1 0V_4

D48

R728 0/J_4

D49

R374 *10K /J_4

R377
220/J_8

3

Q32
2N7002K

1

C396

C333

C380

10u/6.3V_6

10u/6.3V_6

C411

C440

C414

*10u/6.3V_6

*10u/6.3V_6

C361

C437

1u/6.3V_4

1u/6.3V_4

C329

C389

1u/6.3V_4C339

1u/6.3V_4

+1.5V_CPU

+VCCSA

201201117 C767 for Intel fw issue,
if solve need un-stuff.

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Ivy Bridge 4/5 (POWER)

Ivy Bridge 4/5 (POWER)

Ivy Bridge 4/5 (POWER)

Date: Sheet of

Monday, January 0 7, 2013

Date: Sheet of

Monday, January 0 7, 2013

Date: Sheet of

Monday, January 0 7, 2013

1

05

CPU VDDQ

IVY 45W: 5A

Spec

330uF/6mohm x 1
10uF x 8
1uF x 10

C441

C387

10u/6.3V_6

10u/6.3V_6

C775

+

330u/2V_7343

C362

C379

1u/6.3V_4C347

1u/6.3V_4

C438

C360

1u/6.3V_4

1u/6.3V_4

+1.5V_CPU

VCCSA_SENSE [39]

VCCSA_VID0 [39]
VCCSA_VID1 [39]

For IV Bridge

VID[1]

VID[0]

0
0
1
1

For SN Bridge

VID[1]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

+VCCSA

0.9V

0

0.8V

1

0.725V

0

0.675V

1

+VCCSA

0.9V0

0.8V

1

ZQK

ZQK

ZQK

465

465

465

1A

1A

1A

5

4

3

2

1

IVY Bridge Processor (GND) (CPU)

U47H

A13

VSS[1]

D D

C C

B B

A A

A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

AM13
AM20
AM22
AM26
AM30
AM34

A9

VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

Ivy Bridge

VSS

5

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

R375
*0/J_4

U47I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46
D50
D54
D58

E25
E29

E35
E40
F13
F15
F19
F29
F35
F40
F55
G48
G51

G61
H10
H14
H17
H21

H53
H58

K11
K21
K51

M11
M15

J49
J55

L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

D6

E3

G6

H4

K8

J1

VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]

Ivy Bridge

VSS

G48：no stuff for IVY

Processor Strapping

CFG2
(PCI-E Static x16 Lane Reversal)

CFG3
(PCI-E Static x4 Lane Reversal)

CFG4
(DP Presence Strap)

CFG7
(PEG Defer Training)

4

M4

VSS[251]

M58

VSS[252]

M6

VSS[253]

N1

VSS[254]

N17

VSS[255]

N21

VSS[256]

N25

VSS[257]

N28

VSS[258]

N33

VSS[259]

N36

VSS[260]

N40

VSS[261]

N43

VSS[262]

N47

VSS[263]

N48

VSS[264]

N51

VSS[265]

N52

VSS[266]

N56

VSS[267]

N61

VSS[268]

P14

VSS[269]

P16

VSS[270]

P18

VSS[271]

P21

VSS[272]

P58

VSS[273]

P59

VSS[274]

P9

VSS[275]

R17

VSS[276]

R20

VSS[277]

R4

VSS[278]

R46

VSS[279]

T1

VSS[280]

T47

VSS[281]

T50

VSS[282]

T51

VSS[283]

T52

VSS[284]

T53

VSS[285]

T55

VSS[286]

T56

VSS[287]

U13

VSS[288]

U8

VSS[289]

V20

VSS[290]

V61

VSS[291]

W13

VSS[292]

W15

VSS[293]

W18

VSS[294]

W21

VSS[295]

W46

VSS[296]

W8

VSS[297]

Y4

VSS[298]

Y47

VSS[299]

Y58

VSS[300]

Y59

VSS[301]

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

VSS_NCTF_10

NCTF

VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

The CFG signals have a default value of '1' if not terminated on the board.

1 0

Normal Operation

Normal Operation

Disable; No physical DP attached to eDP

PEG train immediately following
xxRESETB de assertion

3

IVY Bridge Processor (RESERVED, CFG) (CPU)

U47E

TP72
TP79

CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

TP45
TP71

TP53
TP48

TP51

TP52
TP55

1
0

11: 1x16 - Device 1 functions 1 and 2 disabled
10: (Default)2x8, 2x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: 1x8,2x4,2x4 - Device 1 functions 1 and 2 enabled

Lane Reversed

Lane Reversed

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

CFG6

CFG5

AU19
AU21
BD21
BD22
BD25
BD26
BG22

BG26

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

BE22

RSVD23
RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

Ivy Bridge

R753 *1K/F_4

R752 1K/F_4

RESERVED

CFG[6:5] (PCIE Port Bifurcation Straps)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

RSVD28
RSVD29

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

CFG2

0

CFG3

0
0

CFG4

CFG7

1

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

BE7 SA_DIMM_VREFDQ
BG7 SB_DIMM_VREFDQ

BE7
BG7

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

N14P-GV2

R743 1K/F_4

R742 1K/F_4

R741 1K/F_4

R376 *1K/F_4

Ivy Bridge 5/5 (GND)

Ivy Bridge 5/5 (GND)

Ivy Bridge 5/5 (GND)

R678 *1K/J_4

SMDDR_VREF_DQ0_M3 [13,14]
SMDDR_VREF_DQ1_M3 [15]

R679 *1K/J_4

processor signal balls BF3 and BG4 for
Ivy Bridge 4-core and balls BE7
and BG7 for Ivy Bridge 2-core

for M3 solution
need R5265/R5266,
W/O M3 then NC

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQK

ZQK

ZQK

1

06

466

466

466

1A

1A

1A

5

4

3

2

1

CPT/PPT (DMI,FDI,PM) (CLG)

U38C

DMI_COMP
DMI_BIAS

SUSACK#_ R

SYS_PWROK_R

EC_PWROK_R

APWROK _R

SUSWARN#_R

PM_BATLOW #

PM_RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

Panther Point_ R1P0

+3V_S5

+3V_S5

+3V_S5

DSW

+3V_S5

+3V_S5

DMI

FDI

+3V

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

DMI_RXN0[2]
DMI_RXN1[2]
DMI_RXN2[2]
DMI_RXN3[2]

D D

20121219：SUSACK# connect to Pin79 of EC (GPJ3)

PCH_SUSACK#[34]

SYS_PWROK

C C

PWROK_ EC

PM_DRAM_P WRGD[3]

PCH_RSMRST#[34 ]

PCH_SUSW ARN#[34]

DNBSWON#[34]

ACPRESENT[35]

DMI_RXP0[2]
DMI_RXP1[2]
DMI_RXP2[2]
DMI_RXP3[2]

DMI_TXN0[2]
DMI_TXN1[2]
DMI_TXN2[2]
DMI_TXN3[2]

DMI_TXP0[2]
DMI_TXP1[2]
DMI_TXP2[2]
DMI_TXP3[2]

R543 49.9/F_4

+1.05V_V TT

R550 750/F_4

R604 0/J_4

XDP_DBRST#[3]

R591 0/J_4

R614 *0/J_4

R615 0/J_4

20121219：SUSWARN# connect to Pin78 of EC (GPJ2)

C206 *1 U/10V_4

R611 0/J_4

R3

R612 *0 /J_4

PM_DRAM_P WRGD

PCH_RSMRST#

R836 0/J_4

R198 0/J_4

ACPRESENT

XDP_DBRST#

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

+3V_S5

SLP_SUS#

PMSYNCH

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DPWROK_R

PCIE_W AKE#_LAN

CLKRUN#

PCH_SUSCL K

SLP_A#

SLP_SUS#

SLP_LAN#

DSWVREN [8]

R169 0/J_4

R616 0/J_4

TP30

TP32

TP34

TP29

FDI_TXN0 [2]
FDI_TXN1 [2]
FDI_TXN2 [2]
FDI_TXN3 [2]
FDI_TXN4 [2]
FDI_TXN5 [2]
FDI_TXN6 [2]
FDI_TXN7 [2]

FDI_TXP0 [2]
FDI_TXP1 [2]
FDI_TXP2 [2]
FDI_TXP3 [2]
FDI_TXP4 [2]
FDI_TXP5 [2]
FDI_TXP6 [2]
FDI_TXP7 [2]

FDI_INT [2]
FDI_FSYNC0 [2]
FDI_FSYNC1 [2]
FDI_LSYNC0 [2]
FDI_LSYNC1 [2]

CLKRUN# [27,34]

LPCPD# [27 ]

SUSC# [34]

SUSB# [34]

SLP_SUS# [1 1,34]

PM_SYNC [3]

DPWROK [34]

PCIE_LAN_WAKE # [28]

20120914 Add for TPM LPCPD#

INT_LVDS_B LON[24]
INT_LVDS_DI GON[24]

INT_LVDS_B RIGHT[24]

Close to PCH

DAC_IREF

R139
1K/F_4

The required series-resistors are:

‧‧‧‧

Direct Connect - 33 Ω

‧‧‧‧

Docking Topology - 20 Ω

CPT/PPT (LVDS,DDI)

U38D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48
AM47

AK47
AJ48

AN47
AM49

AK49
AJ47

AF40
AF39

AH45
AH47

AF49
AF45

AH43
AH49

AF47
AF43

N48
P49
T49

T39
M40

M47
M49

T43
T42

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

Panther Point_ R1P0

LVDS

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_INTN

SDVO_INTP

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLK­INT_HDMICLK+

DisplayPort D

HDMI_DDCCLK_SW [25]
HDMI_DDCDATA_ SW [25]

HDMI_HP [25]

INT_HDMITX2N [25]
INT_HDMITX2P [25]
INT_HDMITX1N [25]
INT_HDMITX1P [25]
INT_HDMITX0N [25]
INT_HDMITX0P [25]
INT_HDMICLK- [25]
INT_HDMICLK+ [25]

DDPC_CTRLCLK [23]
DDPC_CTRLDAT [2 3]

INT_DP_AUXDN [23]
INT_DP_AUXDP [23]

[23]

DP_HPD_Q

DP_TXN0 [23]
DP_TXP0 [23]
DP_TXN1 [23]
DP_TXP1 [23]
DP_TXN2 [23]
DP_TXP2 [23]
DP_TXN3 [23]
DP_TXP3 [23]

INT. HDMI

DisplayPort C

07

B B

PCH Pull-high/low (CLG)

Follow CRB 1.5 to pull
up 1K ohm to +3V

CLKRUN#

R275 8.2K/J_4

XDP_DBRST#

R283 1K/F_4
R271 *1K/J_4

PCH_RSMRST#

R547 10K/J_4

DPWROK_R

R174 10K/J_4

SYS_PWROK

R577 *10K/J_4

A A

20120706:Speed up 250ms to boot up
R1,R2,R3 for EC power on 250 ms

20121004(EC Anda)：：：：Chage trigger pin from +0.75V_ON to APWROK；；；；R2 change to 100K

APWROK[34]

+3V

CRB 1.0 use 1K

PM_RI#
PM_BATLOW #
PCIE_W AKE#_LAN
SLP_LAN#
SUSWARN#_R
ACPRESENT

PM_DRAM_P WRGD

ACPRESENT would need a pull-up to DSW well if DSW
mode is supported on platform

R1

R607 0/J_4

5

R2

R609 10K/J_4
R242 8.2K/J_4
R618 10K/J_4
R208 *10K/J_4
R196 10K/J_4
R180 *10K/J_4

Follow Z09 NO STUFF

R586 200/F_4

APWROK _R

R608
100K/J_4

System PWR_OK (CLG)

+3V_S5

to PCH Pin12, XDP and EE debug

SYS_PWROK[3]

SYS_PWROK

4

U41

4

TC7SH08FU

IMVP_PWRGD PU +3V
PWROK_EC PD

+3V_S5

so AND gate output dont need PD again

C631

0.1u/10V _4

2
1

PWROK_ EC

3 5

R599
100K/J_4

R576 *0/J_4

PWROK_ EC

+3V_S5

C598
*0.1U/10V _4

U40

2

IMVP_PW RGD_R

[34]

4

*TC7SH08

R554 0/J_4

1

3 5

IMVP_PW RGD [3,4 0]
GFX_PW RGD [34,40 ]

20111128 add 0ohm to passed IMVP_PERGD

include GFX_PWRGD to SYS_PWROK for PCH check

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

3

2

Monday, January 07, 2013

PROJECT :

PCH 1/6 (DMI/FDI/VIDEO)

PCH 1/6 (DMI/FDI/VIDEO)

PCH 1/6 (DMI/FDI/VIDEO)

ZQK

ZQK

ZQK

1

1A

1A

1A

467

467

467

5

RTC (RTC)

20MIL

R665 0/J_6

+3VPCU

D D

20MIL

HDA Bus (CLG)

PCH JTAG Debug (CLG)

C C

R663
1K/J_4

12

CN14
RTC_SOCKET

R621
51/J_4

VCCRTC_1

20MIL

Q70

MMBT3904

PCH_AZ_CODEC_SYNC[30]

PCH_AZ_CODEC_RST#[30]

PCH_AZ_CODEC_SDOUT[30]

+3V_S5

R289
210/F_4

R272
100/F_4

PCH_AZ_CODEC_BITCLK[30]

PCH Dual SPI (CLG)

+3V_RTC

R672 20K/J_4

C650

D30

30MIL

R673 20K/J_4

BAT54C

C647
1u/6.3V_4

1 3

VCCRTC_3 VCCRTC_4VCCRTC_2

R809 4.7K/J_4

2

ML1220 Coin type
AHL03001424 FDK (SAY) 15mAH
AHL03017100 Panasonic (MAT) 17mAH

R302

R294

210/F_4

210/F_4

XDP_TMS_VT
PCH_XDP_TDO_VT
PCH_XDP_TDO
XDP_TCLK_VT

R292

R303

100/F_4

100/F_4

1u/6.3V_4

C651
1u/6.3V_4

R163 33/J_4
R153 33/J_4
R166 33/J_4
R529 33/J_4

(Default for WIN8)

RTC_RST#

12

J2

*SHORT_ PAD1

SRTC_RST#

12

J1

*SHORT_ PAD1

R811 4.7K/J_4

68.1K/F_4

150K/F_4

C141 *22p/50V_4

ACZ_BITCLK_R
ACZ_SYNC_CODEC
ACZ_RST#_R
ACZ_SDOUT_R

+5V_S5

R808

R810

W25Q32BVSSIG / AKE391P0N00----->4MB
W25Q16BVSSIG / AKE38FP0N01----->2MB

R661 0/J_6

PCH_SPI_CLK_R2
PCH_SPI_SI_R2
PCH_SPI_SO_R2

C636
*22p/50V_4

R654 3.3K/J_4

R560 33/J_4
R551 33/J_4
R566 33/J_4

R589 3.3K/J_4

R555 33/J_4
R552 33/J_4
R558 33/J_4

Layout Notes:
Place Series Resistors close to Flash ROM

PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

R584 0/J_4

5

+3V_PCH_ME

PCH_SPI_CS1#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

+3V_S5

R652 33/J_4
R653 33/J_4
R655 33/J_4

PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

Layout Notes:
Place Series Resistors close to Flash ROM

B B

A A

PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

Layout Notes:
Place Series Resistors close to Flash ROM

C601 *22p/50V_4

+3V_PCH_ME

PCH_SPI_CLK_EC[34]

PCH_SPI_SI_EC[34]

PCH_SPI_SO_EC[34]

SPI_CS0#_UR_ME[34]

U44

1

CE#

6

SCK

5

SI

2

SO

3

WP#

ROM-2M_ME

U39

1

CE#

6

SCK

5

SI

2

SO

3

WP#

ROM-4M_EC

PCH_SPI_CS1#

SPI_CS0#_UR_ME

+3V_PCH_ME

VDD

HOLD#

VSS

VDD

HOLD#

VSS

8

7

R656 3.3K/J_4

4

8

7

R570 3.3K/J_4

4

R596 47K/J_4

+3V_PCH_ME

+3V_PCH_ME

C621

0.1u/10V_4

+3V_PCH_ME

C640

0.1u/10V_4

4

3

PCH2 (CLG)

C591 18p/50V_4

C595 18p/50V_4

Add MOSFET to separate CODEC SYNC signal

+5V

R133 0/J_4

ACZ_SYNC_CODEC

CRB 1.0

R143
1M/J_4

2

1

12

Y4

32.768KHZ

+3V_RTC

ZRH use 2N7002D

3

Q17
2N7002K

PCH_AZ_CODEC_SDIN0[30]

SYS_COM_REQ[23]

XDP_TCLK_VT[3]
XDP_TMS_VT[3]

PCH_XDP_TDO_VT[3]

R549
10M/J_4

R173 1M/J_4

SPKR[30]

TP12

TP35

RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

ACZ_BITCLK_R
ACZ_SYNC_R

SPKR

ACZ_RST#_R

TP24

ACZ_SDOUT_R

PCH_GPIO33

SYS_COM_REQ

XDP_TCLK_VT
XDP_TMS_VT
PCH_XDP_TDO_VT
PCH_XDP_TDO

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_SI
PCH_SPI_SO

PCH Strap Table

Pin Name

Strap description

No reboot mode setting PWROKSPKR

GNT3# / GPIO55 Top-Block Swap Override

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up

GNT1# / GPIO51

GPIO19

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

HDA_SDO Flash Descriptor Security RSMRST

DF_TVS

GPIO28

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO15

DSWVREN DSW

NV_ALE Intel Anti-Theft HDD protection

4

Intel ME Crypto Transport Layer
Security (TLS) cipher suite
internal PD

DEEP S4/S5 well
On Die DSW VR Enable

Only for Interposer

Sampled

Configuration

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

PWROK

PWROK

0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

GPIO19GNT1#

11

PWROK

00

0 = effect (default)(weak pull-down 20K)

1 = overridden

PWROK

0 = Set to Vss (weak pull-down 20K)

1 = Set to Vcc

0 = Disable

1 = Enable (weak pull-up 10K)

0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V

RSMRST

0 = Disable (Default)

1 = Enable

High = Enable (Default)

Low = Disable

PWROK 0 = Disable (Internal pull-down 20kohm)

3

2

CPT/PPT (HDA,JTAG,SATA) (CLG)

U38A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

Panther Point_R1P0

Boot Location

SPI

*

LPC

RTCIHDA

JTAG

SPI

[34]

+3V_RTC

+3V
+3V

+3V_RTC

+3V_S5

LPC

FWH4 / LFRAME#

+3V

LDRQ1# / GPIO23

SATA 6G

+3V

SATA

+3V_S5

SATAICOMPO

SATA3RCOMPO

SATA0GP / GPIO21
SATA1GP / GPIO19

+3V

ME_WR#

R606 2.2K/J_4
R613 1K/J_4

R299 *1K/J_4

+3V_S5

R557 330K/J_4

+1.8V

C38

FWH0 / LAD0

A38

FWH1 / LAD1

B37

FWH2 / LAD2

C37

FWH3 / LAD3

D36
E36

LDRQ0#

K36
V5

SERIRQ

AM3

SATA0RXN

AM1

SATA0RXP

AP7

SATA0TXN

AP5

SATA0TXP

AM10

SATA1RXN

AM8

SATA1RXP

AP11

SATA1TXN

AP10

SATA1TXP

AD7

SATA2RXN

AD5

SATA2RXP

AH5

SATA2TXN

AH4

SATA2TXP

AB8

SATA3RXN

AB10

SATA3RXP

AF3

SATA3TXN

AF1

SATA3TXP

Y7

SATA4RXN

Y5

SATA4RXP

AD3

SATA4TXN

AD1

SATA4TXP

Y3

SATA5RXN

Y1

SATA5RXP

AB3

SATA5TXN

AB1

SATA5TXP

Y11
Y10

SATAICOMPI

AB12
AB13

SATA3COMPI

AH1

SATA3RBIAS

P3

SATALED#

V14
P1

R291 *1K/J_4

R508 *1K/J_4

R564 330K/J_4

R507 *1K/J_4
R627 *1K/J_4

R164 1K/J_4

R622 1K/J_4

R597 *1K/J_4

2

R536 0/J_4

+1.8V

PCH_DRQ#0
PCH_DRQ#1

TP14
TP9

R634 10K/J_4

TP31

UM77 SATA port 1,3 disable.

SATA_COMP

R219 37.4/F_4

SATA3_COMP

R210 49.9/F_4

SATA3_RBIAS

R633 750/F_4

SATA_ACT#

BBS_BIT0

SPKR

R553 *330K/J_4

R628 10K/J_4
R222 10K/J_4
R643 *10K/J_4

20120919 FOLLOW Z09 NO STUFF

PCI_GNT3# [9]

PCH_INVRMEN

BBS_BIT1 [9]

BBS_BIT0

ACZ_SDOUT_R

DF_TVS [10]
H_SNB_IVB# [3]

PLL_ODVR_EN [10]

ACZ_SYNC_R

PCH_GPIO15 [10]

DSWVREN [7]

NV_ALE [9]

1

08

LPC_LAD0 [26,27,34]
LPC_LAD1 [26,27,34]
LPC_LAD2 [26,27,34]
LPC_LAD3 [26,27,34]

LPC_LFRAME# [26,27,34]

Follow CRB 1.5 to use 10K ohm pull high

SERIRQ [27,34]

TP69

Used as GPIO only. at chklist 1.2

Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]

ME_WR default EC setting folating

for future CPU, Sandy Bridge NC
DF_TVS needs to be pulled up to VccDFTERM power rail
through 2.2 kOhm ±5% - R8361 change to 0 or not??

Needs to be pulled High for Chief River platform
chklist 2.0

+3V

SATA_RXN0 [27]
SATA_RXP0 [27]
SATA_TXN0 [27]
SATA_TXP0 [27]

SATA_RXN1 [26]
SATA_RXP1 [26]
SATA_TXN1 [26]
SATA_TXP1 [26]

DG recommended that AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.

+1.05V_VTT

+3V
+3V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

SATA HDD

mSATA

SATA0GP/GPIO21
SATA4GP/GPIO16
SATA5GP/GPIO49
If these pins are unused use 8.2k
to 10k pull-up to +Vcc3_3 or 8.2k
to 10k pull-down to ground

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PCH 2/6 (SATA/RTC/HDA/LPC)

PCH 2/6 (SATA/RTC/HDA/LPC)

PCH 2/6 (SATA/RTC/HDA/LPC)

ZQK

ZQK

ZQK

1

1A

1A

1A

468

468

468

5

CPT/PPT (PCI,USB,NVRAM) (CLG)

U38E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

D D

Layout Notes:
USB3 TX AC cap place at connector side, AC cap to
connector < 400mils

C C

PCLK_TPM[27]

CLK_LPC_DEBUG[26 ]

CLK_PCI_EC[34]

B B

PLTRST#(CLG) PCI/USBOC# Pull-up(CLG)

PCI_PLTRST#

DDRIII Memory down strap (CLG)

A A

R574 RAMID@15K/F_4
R567 *RAMID@15K/F_4
R200 RAMID@15K/F_4
R581 RAMID@15K/F_4

Vender

Hynix

Elpida

USB30 Port1: EXT USB3.0 Port
USB30 Port3: Mini DP port

USB30_RX1-[31]
USB30_RX3-[23]
USB30_RX1+[31]
USB30_RX3+[23]
USB30_TX1-[31]
USB30_TX3-[23]
USB30_TX1+[31]
USB30_TX3+[23]

BBS_BIT1[8]

BOARD_ID2[10,32]

PCI_GNT3#[8]

DGPU_PWR_EN[42]

DGPU_HOLD_RST#[16]

PCI_PLTRST#[3,34]

CLK_PCI_FB CLK_PCI_FB_R

R132 *100K/J_4

DGPU_PWR_EN

+3V

2
1

U42

3 5

TC7SH08FU

R658 *0/J_4

RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3

Q PN

RAM_IDn

0000

AKD5JGST400

0001

AKD5JGST407 EDJ4216 EFBG-GNL-F

0010

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

REQ1#_GPIO50
REQ2#_GPIO52
REQ#3

BOARD_ID2

MPC_PWR_CTRL#
DGPU_PWR_EN
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH

TP33

PCI_PLTRST#

PCLK_TPM_R

R91 22/J_4
R122 22/J_4

CLK_LPC_DEBUG_R

R116 22/J_4

CLK_PCI_775_R

R138 22/J_4

R137 10K/J_4

20120522：follow CRB to modify power plan to +3V
check list 2.0：When connected to the processor the PLTRST# signal
should be level shifted to 1.05V.

C634

0.1u/10V_4

4

PLTRST#

R575 *RAMID@10K/J_4
R569 RAMID@10K/J_4
R203 *RAMID@10K/J_4
R582 *RAMID@10K/J_4

Mfr. PN

EDJ4216EBBG-DJ- F

5

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

TP21
TP22
TP23
TP24

USB3.0

USB30_RX1N

TP25

USB30_RX2N

TP26

USB30_RX3N

TP27

USB30_RX4N

TP28

USB30_RX1P

TP29

USB30_RX2P

TP30

USB30_RX3P

TP31

USB30_RX4P

TP32

USB30_TX1N

TP33

USB30_TX2N

TP34

USB30_TX3N

TP35

USB30_TX4N

TP36

USB30_TX1P

TP37

USB30_TX2P

TP38

USB30_TX3P

TP39

USB30_TX4P

TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PME#
PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

Panther Point_R1P0

PLTRST# [16,26,27,28,34]

RSVD

PCI

+3V
+3V
+3V

+3V
+3V
+3V

+3V
+3V
+3V
+3V

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

B21

M20

AY16

BG46

BE28
BC30

TP23

BE32
BJ32

TP62

BC28
BE30

TP18

BF32

BG32

TP61

AV26
BB26

TP27

AU28
AY30

TP16

AU26
AY26

TP28

AV28

AW30

TP19

K40
K38
H38

G38
C46

C44
E40

D47
E42
F46

G42
G40
C42
D44

K10

PCI_PME#

C6

H49
H43

J48
K42
H40

+3V

R624
100K/J_4

+3V_S5

Freq.

1333MHz
1600MHz

USB2.0

USB

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25
RSVD26

RSVD27
RSVD28

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

4

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29

USB port6/7 may not be available on all PCH sku

N28

(HM55 support 12port only)

M28
L30
K30
G30

TP21

E30

TP25

C30
A30
L32
K32
G32
E32
C32
A32

C33

USB_BIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

RAM_ID0

L16

USB_OC4#

A16

RAM_ID1

D14

RAM_ID2

C14

RAM_ID3

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC4#

MPC Switch Cont rol

MPC_PWR_CTRL#

MPC_PWR_CTRL#

EV@: For Optimize SKU
IV@: For UMA SKU

+3V

R115 EV@10K/J_4
R123 *IV@10K/J_4

+3V

R642 EV@10K/J_4
R626 *IV@10K/J_4

+3V

R144 *IV@1K/J_4
R145 EV@100K/F_4

4

NV_ALE [8]

USBP0- [31]
USBP0+ [31]
USBP1- [31]
USBP1+ [31]
USBP2- [23]
USBP2+ [23]
USBP3- [24]
USBP3+ [24]
USBP4- [31]
USBP4+ [31]

USBP8- [24]
USBP8+ [24]

USBP10- [26]
USBP10+ [26]

UM77 USB port 6,7,12,13 disable.

R539 22.6/F_4

USB_OC0# [31]

R587 10K/J_4
R201 10K/J_4
R561 10K/J_4
R206 10K/J_4

Low = MPC ON
High = MPC OFF (Default)

R129 *1K/J_4

SKU_ID1

MB USB WITH 3.0 PORT
MB USB 2.0 Port

Mini DP WITH 3.0 PORT
Touch Panel
DB USB 2.0 Port

Camera

BT+WL

+3V_S5

SKU_ID0 [10]

DGPU_PW_CTRL# [10]

USB Port1 can be used on debug mode

XHCI for USBP0-3

EHCI1

USB Port9 can be used on debug mode

1001：(BIOS) Use port1 is enough

EHCI2

20110908 WLAN support S3 wake up function.

Wireless

LAN

+3V

SKU_ID1
(GPIO64)

0

0

1

1

RP1

10

9
8
7 4

10K_10P8R

SKU_ID0
(GPIO16)

+3V

1
2
3

56

VGA H/W
Signal

0

1

0

UMA+GPU

1

PCI_PIRQA#

R149 8.2K/J_4

PCI_PIRQB#

R152 8.2K/J_4

PCI_PIRQC#

R159 8.2K/J_4

PCI_PIRQD#

R155 8.2K/J_4

REQ2#_GPIO52 REQ#3
EXTTS_SNI_DRV1_PCH

dGPU_PW_CTRL#
(GPIO68)
CTL : dGPU_VRON

UMA Only

dGPU Only

Switchable
(Mux)

Optimize
(Muxless)

dGPU_PW_CTRL#
1 = GPU power is control by H/W (pure Discrete SKU)
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize)

1

0 or 1

0

0

3

PCIE port 1 for commeral model S3 can't weak up.

PCIE_RX8-[26]
PCIE_RX8+[26]

Wireless

LAN

PCIE_TX8-[26]
PCIE_TX8+[26]

PCIE_RXN3_LAN[28]
PCIE_RXP3_LAN[28]
PCIE_TXN3_LAN[28]
PCIE_TXP3_LAN[28]

UM77/HM70 will disable 5~8 PC IE ports

CLK_PCIE_WLAN#[2 6]
CLK_PCIE_WLAN[26 ]

CLK_PCIE_WLAN_REQ#[26]

CLK_PCIE_LANN[28]
CLK_PCIE_LANP[28]

CLK_PCIE_LAN_REQ#[28]

CLK_PCIE_XDPN[3]
CLK_PCIE_XDPP[3]

CLK_REQ/Strap Pin(CLG) SMBus(EC) (CLG) SMBus(PCH) (CLG)

+3V_S5

DGPU_HOLD_RST#
MPC_PWR_CTRL#REQ1#_GPIO50

Setup
Menu

UMA

Hidden

UMA boot

CLK_BUF_BCLKN

GPU

Hidden

dGPU/SG

UMA

UMA/SG

3

GPU boot

UMA boot

UMA boot

CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M

2

1

CPT/PPT (PCI-E,SMBUS,CLK)

U38B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

+3V_S5

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

+3V

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

+3V

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

+3V_S5

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

+3V_S5

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

+3V_S5

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

+3V_S5

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N

CLKOUT_PCIE7P

+3V_S5

PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

Panther Point_R1P0

+3V_S5

2

AB49
AB47

TP60

AA48
AA47

AB42
AB40

TP10

TP17

AK14
AK13

PCIE_CLKREQ4#
CLK_PCIE_WLAN_REQ#
PCIE_CLKREQ0#
PCIE_CLKREQ3#
CLK_PCIE_LAN_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
PCIE_CLKREQ_PEG#_R

PCIE_CLKREQ1#
PCIE_CLKREQ2#

R535 10K/J_4
R530 10K/J_4

R183 10K/J_4
R192 10K/J_4
R190 10K/J_4
R191 10K/J_4
R249 10K/J_4
R247 10K/J_4
R141 10K/J_4

J2

M1

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

E6

V40
V42

T13
V38

V37
K12

PCIE_CLKREQ0#

PCIE_CLKREQ1#

PCIE_CLKREQ2#

PCIE_CLKREQ3#

PCIE_CLKREQ4#

CLK_PCIE_REQ6#

CLK_PCIE_REQ7#

R216 10K/J_4 R659
R205 10K/J_4
R648 10K/J_4
R620 10K/J_4
R276 10K/J_4
R300 10K/J_4
R228 10K/J_4
R301 10K/J_4

+3V

R630 10K/J_4
R632 10K/J_4

CLOCK TERMINATION for FCIM
(Full Clock Integration Mode )

+3V_S5

PCI-E*

+3V_S5

2ND_MBCLK[19,34]

2ND_MBDATA[19,34]

R218 10K/J_4
R625 2.2K/J_4
R649 2.2K/J_4
R231 2.2K/J_4
R221 2.2K/J_4
R595 10K/J_4

+3V_S5

SMBALERT# / GPIO11

+3V_S5

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

+3V_S5

SML1CLK / GPIO58

+3V_S5

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

+3V_S5

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

CLKOUT_DMI_P

CLKIN_GND1_N

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_PCILOOPBACK

+3V

CLKOUTFLEX0 / GPIO64

+3V

CLKOUTFLEX1 / GPIO65

+3V

CLKOUTFLEX2 / GPIO66

+3V

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

+3V_S5

5

2
6

2N7002DW

R215 *0/J_4
R220 *0/J_4

20120712：Add 0ohm reserved for two sides of
SMBUS since they are the same power plane
(CRB no level shift)

SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R

20111122 add fo r Touch pad in terrupt pin fr om GPIO13 to GP IO11.

E12

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

R559

2.2K/J_4

Q57

43

1

SMBALERT#

H14

SMB_PCH_CLK

C9

SMB_PCH_DAT

A12

DRAMRST_CNTRL_PCH

C8

SMB_ME0_CLK

G12

SMB_ME0_DAT

C13

SML1ALERT#_R

E14

SMB_ME1_CLK

M16

SMB_ME1_DAT

M7

CL_CLK1

T11

CL_DATA1

P10

CL_RST1#

M10

PCIE_CLKREQ_PEG#_R

AB37
AB38

AV22
AU22

AM12
AM13

BF18

CLK_BUF_PCIE_3GPLLN

BE18

CLK_BUF_PCIE_3GPLLP

BJ30

CLK_BUF_BCLKN

BG30

CLK_BUF_BCLKP

G24

CLK_BUF_DREFCLKN

E24

CLK_BUF_DREFCLKP

AK7

CLK_BUF_DREFSSCLKN

AK5

CLK_BUF_DREFSSCLKP

K45

CLK_PCH_14M

H45

CLK_PCI_FB

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

SKU_ID1

F47

CLK_FLEX1

H47
K49

R592

2.2K/J_4

SMB_ME1_CLK

SMB_ME1_DAT

SMBALERT# [32]
SMB_PCH_CLK [23,26]
SMB_PCH_DAT [23,26]

DRAMRST_CNTRL_PCH [4]

TP68

CL_CLK1 [26]

CL_DATA1 [26]

CL_RST1# [26]

R308 EV@0/J_4

CLK_PCIE_VGAN [16]
CLK_PCIE_VGAP [16]

CLK_CPU_BCLKN [3]
CLK_CPU_BCLKP [3]

CLK_DPLL_SSCLKN [3]
CLK_DPLL_SSCLKP [3]

R504 9 0.9/F_4

TP8

TP59

S5 S0

SMB_PCH_DAT

SMB_PCH_CLK

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.05V_VTT

+3V

5

2
6

2N7002DW

PCH 3/6 (PCIE/USB/CLK/SMB)

PCH 3/6 (PCIE/USB/CLK/SMB)

PCH 3/6 (PCIE/USB/CLK/SMB)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

1

For LAN

For EC

XTAL25_IN

XTAL25_OUT

20120201 Change CAP from 27P to 10P.

BOARD_ID4 [10,24]

R645

4.7K/J_4
Q60

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PEG_A_CLKREQ# [16]

C564 10p/50V_4

R511
1M/J_4

C565 10p/50V_4

4.7K/J_4

43

1

ZQK

ZQK

ZQK

09

Y3
25MHz_XTAL

2 4

1 3

CLK_SDATA [13,15,32 ]

CLK_SCLK [1 3,15,32]

469

469

469

1A

1A

1A

5

4

3

2

1

CPT/PPT (GPIO,VSS_NCTF,RSVD) (CLG)

U38F

S_GPIO

R278 100/J_4

SIO_EXT_SMI#[34]

D D

C C

B B

SATA2GP/SATA3GP : When Unused as GPIO or SATA*GP - Use

8.2K-10K pull-down to ground by chklist 2.0
NOTE: The internal pull-down is disabled after PLTRST#
deasserts.
NOTE: This signal should not be pulled high when strap is
sampled.

A A

2011/09/01 add select resistor

TACH5_GPIO69

LVDS = Pull HIGH
eDP = Pull LOW

SIO_EXT_SCI#[34]
TP_INT_PCH[24]

PCH_GPIO15[8]

SKU_ID0[9]

DGPU_PW ROK[20]

PLL_ODVR_EN[8]

DGPU_VRON[20,43]

TP36

R510 1K/J_4

5

SIO_EXT_SMI#
BOARD_ID1
SIO_EXT_SCI#

TP_INT_PCH

SMIB

DGPU_PW ROK
SCLOCK_GPIO22
PCH_GPIO24
WK_GPIO27
PLL_ODVR_EN
STP_PCI#
DGPU_VRON
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP
CRIT_TEMP_REP#
SV_DET

R298 100K/J_4

FDI TERMINATION
VOLTAGE OVERRIDE

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

Panther Point_R1P0

20120607：follow CRB pull down

FDI_OVRVLTG SCLOCK_GPIO22

LOW - Tx, Rx terminated
to same voltage

4

+3V_S5

+3V_S5

DSW
+3V_S5

+3V

+3V_S5

+3V
+3V
+3V
+3V

+3V

+3V

+3V

+3V_S5

+3V

+3V

+3V
+3V

+3V
+3V

+3V

R290 *1K/J_4

+3V
+3V
+3V
+3V

+3V_S5

GPIO

NCTF

+3V +3V

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

PROCPWRGD

THRMTRIP#

CPU/MISC

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

A20GATE

PECI

RCIN#

INIT3_3V#

DF_TVS

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

G_SENSOR_ID

C40
B41
C41
A40

R524 1.5K/F_4

P4

SIO_A20GATE

AU16

EC_PECI_R

P5

SIO_RCIN#

AY11
AY10

PCH_THRMTRIP#

T14
AY1

AH8
AK11
AH10
AK10

P37

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

R268 10K/J_4
R250 *1K/J_4

3

TACH5_GPIO69

DGPU_PW _CTRL# [9]

BOARD_ID3

+3V

R212 *0/J_4

R225 390/J_4

High = Disable (Default)
Low = Enable

SIO_A20GATE [34]

EC_PECI [3,34]

SIO_RCIN# [34]
H_PWRGOOD [3]
PM_THRMTRIP# [3]

DF_TVS [8]

USB3.0 IC CTL

LOW = USB3.0 IC

SMIB

R623 10K/J_4

SV_SET_UP

High = Strong (Default)

TEST_SET_UP

SGPIO

S_GPIO

MFG-TEST

MFG_MODE

GPIO Pull-up/Pull-down (CLG)

20120625

：：：：

<PCH_GPIO24>Follow CRB to pull up 10K ohm

GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.

+3V_S5

+3V

R273 10K/J_4

R248 *1K/J_4

+3V

R285 1K/J_4
R284 *1K/J_4

R644 10K/J_4
R629 *1K/J_4

2

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

+3V

10

+3V_S5

PCH_GPIO24
PLL_ODVR_EN

SIO_EXT_SMI#
SIO_EXT_SCI#

STP_PCI#
SIO_A20GATE
SIO_RCIN#
CRIT_TEMP_REP#

20111017 un-stuff R5126 for DSW

DMI TERMINATION
VOLTAGE OVERRIDE

R229 *10K/J_4

+3V_S5

R280 *10K/J_4

R631 10K/J_4
R162 10K/J_4
R99 *10K/J_4 R105 10K/J_4
R520 10K/J_4
R506 *10K/J_4

WK_GPIO27

DGPU_PW ROK

Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)

DMI_OVRVLTG

high VDDR=+1.35V_SUS for DDR3L
Low VDDR =+1.5V_SUS(default)

assign to VID for VDDR control

SV_DET

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

BOARD_ID4

BOARD_ID2[9,32]
BOARD_ID4[9,24]

High Low

GDDR5 DDR3

Disable on board memory Enable on board memory

Pin8 of SYNAPTICS and ELAN are NC pin
Default is pull high

BIOS maybe will use EEPROM detection

No touch panel

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

PROJECT :

PCH 4/6 (GPIO/MISC)

PCH 4/6 (GPIO/MISC)

PCH 4/6 (GPIO/MISC)

R252 *10K/J_4
R307 10K/J_4

R509 10K/J_4
R148 10K/J_4

R647 *10K/J_4
R270 10K/J_4
R288 10K/J_4
R635 10K/J_4

R185 10K/J_4
R181 *10K/J_4

R131 *10K/J_4

R279 *200K/F_4

R274 100K/J_4

R646 *10K/J_4
R151 *10K/J_4

R522 *10K/J_4
R505 10K/J_4

Touch panel

ZQK

ZQK

ZQK

1

+3V

+3VPCU

+3V

4610

4610

4610

+3V

1A

1A

1A

5

4

3

2

1

PCH5(CLG)

20111018 change for DSW

+1.05V_VTT

3

ZQK

ZQK

ZQK

11

+5VCC_S5
+3VCC_S5

20111018 change for DSW

+5V
+3V

+3VCC_S5

+3V

4611

4611

4611

1A

1A

1A

CPT/PPT (POWER) (CLG)

POWER

+1.05V_VTT

R135 0/J_8

D D

+1.05V_VTT +1.05V_VCCAPLL_EXP

L30 *1uH/25mA_6

+1.05V_VTT

R165 0/J_8

R172 0/J_6

C C

VccDMI needs to be powered by the same 1.05 V voltage source as
the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/
VCC reference plane.

B B

A A

+1.05V_VTT

R108 0/J_6

+1.5V

R130 *0/J_6

VccCORE =1.3 A(60mils)

+1.05V_VCCCORE

C184

C156

C173
1u/6.3V_4

+1.05V_VTT

C590
*10u/6.3V_6

1u/6.3V_4

R182 0/J_6

1u/6.3V_4

VccIO =2.925 A(140mils)

C161

C187

1u/6.3V_4

R540 0/J_8

+1.05V_VTT

+VCCAFDI_VRM

VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1

1.5V (Mobile)

5

C166

1u/6.3V_4 C157

1u/6.3V_4

C172

C201

10u/6.3V_6

1u/6.3V_4

+3V_VCC_EXP+3V

C583

0.1u/10V_4

+VCCAFDI_VRM

R605 *0/J_8

R556 0/J_8

+1.1V_VCC_DMI

+1.1V VCC_DMI witdth >= 20mils.

C169

4.7u/6.3V_6

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

+1.05V_VCCDPLL_FDI

AA23
AC23
AD21
AD23

AF21

AF23
AG21
AG23
AG24
AG26
AG27
AG29

AJ23

AJ26

AJ27

AJ29
AJ31

AN19

BJ22

AN16
AN17

AN21
AN26
AN27

AP21
AP23
AP24
AP26
AT24

AN33
AN34

BH29

AP16

BG6

AP17

AU20

U38G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCIO[25]
VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

Panther Point_R1P0

U48

VCCADAC

U47

VSSADAC

CRTLVDS

AK36

VCCALVDS

AK37

VCC CORE

VCCIO

FDI

VSSALVDS

AM37

VCCTX_LVDS[1]

AM38

VCCTX_LVDS[2]

AP36

VCCTX_LVDS[3]

AP37

VCCTX_LVDS[4]

V33

VCC3_3[6]

V34

VCC3_3[7]

AT16

VCCVRM[3]

AT20

VCCDMI[1]

DMI

DFT / SPI HVCMOS

AB36

VCCCLKDMI

AG16

VCCDFTERM[1]

AG17

VCCDFTERM[2]

AJ16

VCCDFTERM[3]

AJ17

VCCDFTERM[4]

V1

VCCSPI

20120105 change power plant to +3V for power saving.

+3V_VCCME_SPI +3V_S5

Reserve +3V_S5 to VCCSPI for EC 795 co-layout

+3V

R89 * 0/J_6
R81 1/F_4

4

VccADAC =1mA(8mils)

C567

10u/6.3V_6

When Dis sku and eDP , LVDS power can short to GND

R93 0/J_6
C85

0.1u/10V_4

+VCCAFDI_VRM

C120

C131

*10u/6.3V_6

1u/6.3V_4

R568 0/J_8

C203

0.1u/10V_4

+3V_VCCME_SPI

C635
1u/6.3V_4

+3V

R638 *0/J_6
R637 0/J_6

L8 10uH/100mA_8

C566

C562

0.01u/25V_4

0.1u/10V_4

+3V+3V_VCC_GIO

VCCDMI = 42mA(10mils)

+1.1V_VCC_DMI

+VCCAFDI_VRM

L12 *10uH/100mA_8

+1.8V+VCCP_NAND

VCCSPI = 20mA(8mils)

+VCCA_DAC_1_2

+VCC_DMI_CCI +1.05 V_VTT+1.1V_VCC_DMI_CCI

L26 180ohm/1.5A

C561
10u/6.3V_6

20120104 change power plant from +3V_S5 to +3VPCU.

+1.05V_VTT

R197 0/J_4

C182

20120216 remove R168 for power plant chnge to +1.05V_VTT.

1u/6.3V_4

+1.1V VCC_DMI witdth >= 20mils.

VCCCLKDMI = 20mA(8mils)

R124 *1/F_4
R125 0/J_4

VCCPNAND = 190 mA(15mils)

20120216 remove R172 for power plant chnge to +1.05V_VTT.

VCCRTC<1mA(8mils)

+3V_SUS_CLKF33

C86

C77

1u/10V_4

4.7u/6.3V_6

+3V

+3VPCU

+1.05V_VTT

L29 *10uH/100mA_8

VCCME(+1.05V) = ??A(??mils)

+1.05V_VTT

R204 0/J_6

+1.05V_VTT

R213 0/J_6

R158 0/J_6

R157 0/J_6

+1.05V_VTT

R209 *0/J_6

+1.05V_VTT

R585 0/J_4

+3V_RTC

L27 10uH/100mA_8

+1.05V_VTT

L28 10uH/100mA_8

3

R104 *0/J_8

+1.05V_VTT

C219
*0.1u/10V_4

C176
*1u/6.3V_4

C619

0.1u/10V_4

C587

0.1u/10V_4

+1.05V_VCCA_A_DPL

C569
1u/6.3V_4

+1.05V_VCCA_B_DPL

C571
1u/6.3V_4

+VCCACLK

+VCCPDSW

PCH_VCCDSW

+3V_SUS_CLKF33

+VCCDPLL_CPY

+VCCSUS1

+VCCRTCEXT

+VCCAFDI_VRM

+1.05V_VCCA_A_DPL
+1.05V_VCCA_B_DPL

+VCCDIFFCLK
+VCCDIFFCLKN

+V1.05V_SSCVCC

+VCCSST

+V1.05M_VCCSUS

+VTT_VCCPCPU

R269 0/J_4 C151

+VCCAPLL_CPY_PCH

VccASW =1.01 A(60mils)

C204
1u/6.3V_4

C143
1u/6.3V_4

C142
1u/6.3V_4

C209
*1u/6.3V_4

+1.05V_VTT

C589
*10u/6.3V_6

+1.05V_VCCASW

1u/6.3V_4

VCCDSW3_3= 3mA

C253

0.1u/10V_4

R170 0/J_6

C180

C179

1u/6.3V_4

1u/6.3V_4

C167

C159

10u/6.3V_6

10u/6.3V_6

C200 0.1u/10 V_4

+VCCAFDI_VRM

65mA(10mils)
8mA(8mils)

VCCDIFFCLKN= 55mA(18mils)
VCCSSC= 95mA(10mils)

C190 0.1u/10 V_4

1mA(8mils)

C618

C616

0.1u/10V_4

4.7u/6.3V_6

C586

C585

1u/6.3V_4

0.1u/10V_4

+

C563
220u/2.5V_3528

+

C574
220u/2.5V_3528

CPT/PPT (POWER) (CLG)

POWER

U38J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23
W24
W26
W29
W31
W33

N16

Y49

BD47
BF47

AF17
AF33
AF34
AG34

AG33

V16

T17
V19

BJ8

A22

2

Panther Point_R1P0

Clock and Miscellaneous

VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA
VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

CPURTC

VCCRTC

+5V_S5 +5VCC_S5 +3VCC_S5

SLP_SUS#[7,34]

VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]

VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]

VCC3_3[1]
VCC3_3[8]

PCI/GPIO/LPCMISC

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]
VCCIO[13]

VCCIO[6]

VCCAPLLSATA

SATA USB

VCCVRM[1]

VCCIO[2]
VCCIO[3]
VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

HDA

R521 *0/J_4

1

R515

C568

100K/J_4

*0.33u/10V_6

20111018 ADD DSW Cricuit
20111030 modify cuirucit.

+1.05V_VCCIO

N26
P26
P28
T27
T29

T23

+3V_VCCPUSB

T24
V23
V24
P24

+3V_VCCAUBG

T26

+VCCAUPLL

M26

+5V_PCH_VCC5REFSUS

AN23

+VCCA_USBSUS

AN24

+3V_VCCPSUS

P34

+5V_PCH_VCC5REF

N20
N22
P20

+3V_VCCPSUS

P22

AA16
W16

+3V_VCCPCORE

T34

C130

0.1u/10V_4

AJ2

AF13

AH13

+1.05V_VCC_IO

AH14

AF14
AK1

+V1.1LAN_VCCAPLL

VCCVRM= 114mA(15mils)

AF11

+VCCAFDI_VRM

AC16
AC17
AD17

T21

V21

T19

P32

+V3.3A_1.5A_HDA_IO

C139
*1u/6.3V_4

3

Q51
AO3413

2

R514
0/J_6

+1.05V_VTT

R178 0/J_6

1u/6.3V_4

R193 0/J_6

C186
*1u/6.3V_4

+3V

L31 *10uH/100mA_8
C638

*10u/6.3V_6

+1.05V_VTT

C202
1u/6.3V_4

R146 0/J_6

R179 0/J_4

C160

0.1u/10V_4

+3V_S5

C570
*0.33u/10V_6

6

215

Q55
2N7002DW

20111117 change mose footprint to dual type.

4 3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet o f

Monday, January 07, 2013

Date: Sheet o f

Monday, January 07, 2013

Date: Sheet o f

Monday, January 07, 2013

VCCSUS3_3 = 119mA(15mils)

+3VCC_S5

R537 0/J_6

C582

0.1u/10V_4

R545 0/J_6

C181

0.1u/10V_4

C155

0.1u/10V_4

C105
1u/6.3V_4

C594
1u/10V_4

C188

0.1u/10V_4

C637

0.1u/10V_4

C224
1u/10V_4

+1.05V_VTT

20111018 change for DSW

+1.05V_VTT

VCC5REFSUS=1mA

R532 10/F_4

D24 RB500V-40

V5REF= 1mA

R117 10/F_4

D6 RB500 V-40

R548 0/J_6

VCCSUS3_3 = 119mA(15mils)

R202 0/J_6

VCCPCORE = 28mA(10mils)

+3V

R267 0/J_6

??mA(??mils)

+1.05V_VTT

VCCME = 1.01A(60mils)

VCCSUSHDA= 10mA(8mils)

+3V_S5

R531 *0/J_4

1

R518
100K/J_4

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PCH 5/6 (POWER)

PCH 5/6 (POWER)

PCH 5/6 (POWER)

1

Q54
AO3413

R546
0/J_6

5

4

3

2

1

PCH6(CLG)

ZQK

ZQK

ZQK

12

4612

4612

4612

1A

1A

1A

IBEX PEAK-M (GND) (CLG)

U38H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

D D

C C

B B

A A

5

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

Panther Point_R1P0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

4

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

U38I

AY4
AY42
AY46

AY8

B11
B15
B19
B23
B27
B31
B35
B39

B7

F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38

BB4
BB46
BC14
BC18

BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46

BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28

BD3
BF30
BF38
BF40

BF8

BG17
BG21
BG33
BG44

BG8

BH11
BH15
BH17
BH19

H10

BH27
BH31
BH33
BH35
BH39
BH43

BH7

D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42

D8

E18

E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34

F3

Panther Point_R1P0

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46

VSS[259]

K18

VSS[260]

K26

VSS[261]

K39

VSS[262]

K46

VSS[263]

K7

VSS[264]

L18

VSS[265]

L2

VSS[266]

L20

VSS[267]

L26

VSS[268]

L28

VSS[269]

L36

VSS[270]

L48

VSS[271]

M12

VSS[272]

P16

VSS[273]

M18

VSS[274]

M22

VSS[275]

M24

VSS[276]

M30

VSS[277]

M32

VSS[278]

M34

VSS[279]

M38

VSS[280]

M4

VSS[281]

M42

VSS[282]

M46

VSS[283]

M8

VSS[284]

N18

VSS[285]

P30

VSS[286]

N47

VSS[287]

P11

VSS[288]

P18

VSS[289]

T33

VSS[290]

P40

VSS[291]

P43

VSS[292]

P47

VSS[293]

P7

VSS[294]

R2

VSS[295]

R48

VSS[296]

T12

VSS[297]

T31

VSS[298]

T37

VSS[299]

T4

VSS[300]

W34

VSS[301]

T46

VSS[302]

T47

VSS[303]

T8

VSS[304]

V11

VSS[305]

V17

VSS[306]

V26

VSS[307]

V27

VSS[308]

V29

VSS[309]

V31

VSS[310]

V36

VSS[311]

V39

VSS[312]

V43

VSS[313]

V7

VSS[314]

W17

VSS[315]

W19

VSS[316]

W2

VSS[317]

W27

VSS[318]

W48

VSS[319]

Y12

VSS[320]

Y38

VSS[321]

Y4

VSS[322]

Y42

VSS[323]

Y46

VSS[324]

Y8

VSS[325]

BG29

VSS[328]

N24

VSS[329]

AJ3

VSS[330]

AD47

VSS[331]

B43

VSS[333]

BE10

VSS[334]

BG41

VSS[335]

G14

VSS[337]

H16

VSS[338]

T36

VSS[340]

BG22

VSS[342]

BG24

VSS[343]

C22

VSS[344]

AP13

VSS[345]

M14

VSS[346]

AP3

VSS[347]

AP1

VSS[348]

BE16

VSS[349]

BC16

VSS[350]

BG28

VSS[351]

BJ28

VSS[352]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

3

2

Monday, January 07, 2013

PROJECT :

PCH 6/6 (GND)

PCH 6/6 (GND)

PCH 6/6 (GND)

1

DDR ON BOARD RAM (DDR)

Checklist 2.0:
M3 has to be no stuff on Chief River

SMDDR_VREF_DQ0_M3[6,14]

A A

B B

M_A_CLK0

M_A_CLK0#

C C

Place these Caps near Memory Down

+1.5VSUS

C420
1u/6.3V_4

+1.5VSUS

C802
1u/6.3V_4

+1.5VSUS

C431

D D

1u/6.3V_4

+1.5VSUS

C671
1u/6.3V_4

1

R694 *M3@0/J_6

M_A_A[15:0][4,14]

SO-DIMMB SPD Address is 0XA4
SO-DIMMB TS Address is 0X34

DDR3_DRAMRST#[4,14,15]

C485

1.6P/50V_4

R265

R266

30/F_4

30/F_4

C244

0.1u/10V_4

C745
1u/6.3V_4

C684
1u/6.3V_4

C290
1u/6.3V_4

C274
1u/6.3V_4

1

C278
1u/6.3V_4

C768
1u/6.3V_4

C789
1u/6.3V_4

C417
1u/6.3V_4

C741
1u/6.3V_4

C661
1u/6.3V_4

C673
1u/6.3V_4

C688
1u/6.3V_4

M_A_BS#0[4,14]
M_A_BS#1[4,14]
M_A_BS#2[4,14]

M_A_CLK0[4]

M_A_CLK0#[4]

M_A_CKE0[4]

M_A_ODT0[ 4]

M_A_CS#0[4]
M_A_RAS#[4,14]
M_A_CAS#[4,14]

M_A_WE#[4,14]

Should be 240
Ohms +-1%

M_A_DQSP[7:0][4,14]

M_A_DQSN[7:0][4,14]

M_A_DQ[63:0][4,14]

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQSP0
M_A_DQSP1

M_A_DQSN0
M_A_DQSN1

R255
240/F_4

1 2

C746

C470

1u/6.3V_4

1u/6.3V_4

C251

C398

1u/6.3V_4

1u/6.3V_4

C293

C783

1u/6.3V_4

1u/6.3V_4

C682

C771

1u/6.3V_4

1u/6.3V_4

C653
1u/6.3V_4

C689
1u/6.3V_4

C252
1u/6.3V_4

C250
1u/6.3V_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

2

U19

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C421
1u/6.3V_4

C436
1u/6.3V_4

C473
1u/6.3V_4

C432
1u/6.3V_4

2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

+1.5VSUS

+1.5VSUS

+1.5VSUS

+1.5VSUS

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

C793
1u/6.3V_4

C739
1u/6.3V_4

C752
1u/6.3V_4

C767
1u/6.3V_4

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

BYTE0_0-7
BYTE1_8-15

M_A_DQ6
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ0

M_A_DQ8
M_A_DQ15
M_A_DQ14
M_A_DQ11
M_A_DQ13
M_A_DQ10
M_A_DQ9
M_A_DQ12

+1.5VSUS

+1.5VSUS

C633

C687

1u/6.3V_4

1u/6.3V_4

C686

C665

1u/6.3V_4

1u/6.3V_4

C285

C675

1u/6.3V_4

1u/6.3V_4

C287

C728

1u/6.3V_4

1u/6.3V_4

Should be 240
Ohms +-1%

C809
1u/6.3V_4

C642
1u/6.3V_4

C488
1u/6.3V_4

C639
1u/6.3V_4

3

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

DDR3_DRAMRST#

M_A_ZQ2M_A_ZQ1

R323
240/F_4

1 2

C785
1u/6.3V_4

C459
1u/6.3V_4

C685
1u/6.3V_4

C284
1u/6.3V_4

3

1u/6.3V_4

C772
1u/6.3V_4

C649
1u/6.3V_4

C632
1u/6.3V_4

M8

M7

M2
M3

H1
N3

P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

N8

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

U21

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C644
1u/6.3V_4

C315
1u/6.3V_4

C256
1u/6.3V_4

C646
1u/6.3V_4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

C667
1u/6.3V_4

C674
1u/6.3V_4

C294
1u/6.3V_4

C258
1u/6.3V_4

BYTE2_16-23
BYTE3_24-31

E3

M_A_DQ19

F7

M_A_DQ22

F2

M_A_DQ18

F8

M_A_DQ16

H3

M_A_DQ21

H8

M_A_DQ20

G2

M_A_DQ23

H7

M_A_DQ17

D7

M_A_DQ28

C3

M_A_DQ25

C8

M_A_DQ30

C2

M_A_DQ27

A7

M_A_DQ24

A2

M_A_DQ26

B8

M_A_DQ29

A3

M_A_DQ31

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

C763
10u/6.3V_6

+1.5VSUS

C764
10u/6.3V_6

+1.5VSUS

C780
10u/6.3V_6

+1.5VSUS

C681
10u/6.3V_6

4

+1.5VSUS

+1.5VSUS

4

C663
10u/6.3V_6

C314
10u/6.3V_6

C786
10u/6.3V_6

C736
10u/6.3V_6

Should be 240
Ohms +-1%

C283
10u/6.3V_6

C289
10u/6.3V_6

C735
10u/6.3V_6

C723
10u/6.3V_6

C304
10u/6.3V_6

C690
10u/6.3V_6

C691
10u/6.3V_6

C280
10u/6.3V_6

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

DDR3_DRAMRST#

M_A_ZQ3

R697
240/F_4

1 2

C801
10u/6.3V_6

C489
10u/6.3V_6

C643
10u/6.3V_6

C483
10u/6.3V_6

5

U23

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

RAM _DDR3

+

C742

330u/2V_7343

C781

+

*150u/6.3V_3528

5

100-BALL
SDRAM DDR3

BYTE4_32-39
BYTE5_40-47

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

+SMDDR_VREF_DIMM

C602

0.1u/10V_4

+1.5VSUS

R226
1K/F_4

+SMDDR_VREF_DIMM

R232
1K/F_4

WP =1 : WRITE DISABLE

C725

0.1u/10V_4

C245

0.1u/10V_4

CLK_SCLK[9,15,32]
CLK_SDATA[9,15,32]

+3V

M_A_DQ42
M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ45
M_A_DQ40
M_A_DQ43
M_A_DQ47

M_A_DQ36
M_A_DQ38
M_A_DQ35
M_A_DQ37
M_A_DQ32
M_A_DQ39
M_A_DQ33
M_A_DQ34

+1.5VSUS

+1.5VSUS

C703

0.1u/10V_4

+SMDDR_VREF_DIMM

R227 *0/J_6C418

CLK_SCLK
CLK_SDATA

R321 *0/J_4

6

Should be 240
Ohms +-1%

C717

0.1u/10V_4

+SMDDR_VREF

R322
*0/J_4

6

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

DDR3_DRAMRST#

1 2

C493

0.1u/10V_4

U45

6

SCL

5

SDA

7

WP

*M24C02-WMN6TP

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP7
M_A_DQSP6

M_A_DQSN7
M_A_DQSN6

M_A_ZQ4

R724
240/F_4

VCC
GND

0.1u/10V_4

A0
A1
A2

U26

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

C481

0.1u/10V_4

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

SMDDR_VREF_DQ0

C714

0.1u/10V_4

CRB Add

DEEPS3_EC[4,14,15]

SPD address= A0 hex (for MD devices)

+3V

R666 *1K/F_4

MD0_SA0
MD0_SA1

+3V

R662 *1K/F_4

C286
*0.1u/10V_4

1
2
3

8
4

7

BYTE6_48-55
BYTE7_56-63

E3

M_A_DQ60

F7

M_A_DQ61

F2

M_A_DQ63

F8

M_A_DQ57

H3

M_A_DQ62

H8

M_A_DQ56

G2

M_A_DQ58

H7

M_A_DQ59

D7

M_A_DQ53

C3

M_A_DQ55

C8

M_A_DQ52

C2

M_A_DQ50

A7

M_A_DQ49

A2

M_A_DQ54

B8

M_A_DQ48

A3

M_A_DQ51

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C715

0.1u/10V_4

1

Q21

2

*AP2302GN

MD0_SA0
MD0_SA1

7

8

+1.5VSUS

+1.5VSUS

SMDDR_VREF_DQ0+SMDDR_VREF_DIMM

C711

0.1u/10V_4C720

change to 1K/F_4

3

R668 1K/F_4
R664 1K/F_4

C710

C713

0.1u/10V_4

0.1u/10V_4

+1.5VSUS

R224
1K/F_4

SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M3

R230
1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

C480

C712

0.1u/10V_4

0.1u/10V_4

R214 *0/J_6

C223

0.1u/10V_4

CHA0

SA0SA1

00
CHA1
CHB0

1100

CHB1

1 1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQK

ZQK

ZQK

8

+SMDDR_VREF

13

4613

4613

4613

1A

1A

1A

DDR ON BOARD RAM (DDR)

Checklist 2.0:
M3 has to be no stuff on Chie f River

SMDDR_VREF_DQ0_M3[6,13]

A A

B B

M_A_CLK1

M_A_CLK1#

C C

1

R246 *M3@0/J_6

M_A_A[15:0][4,13]

SO-DIMMB SPD Ad dress is 0XA4
SO-DIMMB TS Add ress is 0X34

M_A_BS#0[4,13]
M_A_BS#1[4,13]
M_A_BS#2[4,13]

M_A_CLK1[4 ]

M_A_CLK1#[4]

M_A_CKE1[4]

M_A_ODT1[4]
M_A_CS#1[4 ]
M_A_RAS#[4,13]
M_A_CAS#[4,13]

M_A_WE#[4,13]

DDR3_DRAMRST#[4,13,15]

Should be 240
Ohms +-1%

C484

1.6P/50V_4

R254

R253

30/F_4

30/F_4

C243

0.1u/10V_4

M_A_DQSP[7:0][4,13]

M_A_DQSN[7:0][4,13]

M_A_DQ[63:0][4,13]

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

R671
240/F_4

1 2

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQSP0
M_A_DQSP1

M_A_DQSN0
M_A_DQSN1

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

2

U43

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

RAM _DDR3

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE0_0-7
BYTE1_8-15

E3

M_A_DQ3

F7

M_A_DQ6

F2

M_A_DQ0

F8

M_A_DQ2

H3

M_A_DQ5

H8

M_A_DQ4

G2

M_A_DQ1

H7

M_A_DQ7

D7

M_A_DQ15

C3

M_A_DQ8

C8

M_A_DQ11

C2

M_A_DQ14

A7

M_A_DQ12

A2

M_A_DQ9

B8

M_A_DQ10

A3

M_A_DQ13

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

3

SMDDR_VREF_DQ0

DDR3_DRAMRST#

M_A_ZQ6M_A_ZQ5

1 2

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

R688
240/F_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

U46

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

4

BYTE2_16-23
BYTE3_24-31

E3

M_A_DQ22

F7

M_A_DQ19

F2

M_A_DQ17

F8

M_A_DQ18

H3

M_A_DQ20

H8

M_A_DQ23

G2

M_A_DQ16

H7

M_A_DQ21

D7

M_A_DQ25

C3

M_A_DQ28

C8

M_A_DQ27

C2

M_A_DQ30

A7

M_A_DQ31

A2

M_A_DQ29

B8

M_A_DQ26

A3

M_A_DQ24

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

5

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

DDR3_DRAMRST#

M_A_ZQ7

R718
240/F_4

1 2

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

U48

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

BYTE4_32-39
BYTE5_40-47

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

+SMDDR_VREF_DIMM

C716

0.1u/10V_4

+1.5VSUS

R572
1K/F_4

+SMDDR_VREF_DIMM

R573
1K/F_4

M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ42
M_A_DQ47
M_A_DQ45
M_A_DQ40
M_A_DQ43

M_A_DQ38
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ39
M_A_DQ33
M_A_DQ34
M_A_DQ32

C693

0.1u/10V_4

+SMDDR_VREF_DIMM

C603

0.1u/10V_4

6

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

C721

0.1u/10V_4

+SMDDR_VREF

R571 *0/J_6

C726

0.1u/10V_4

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP7
M_A_DQSP6

M_A_DQSN7
M_A_DQSN6

DDR3_DRAMRST#

M_A_ZQ8

R765
240/F_4

1 2

C507

0.1u/10V_4

C680

0.1u/10V_4

CRB Add

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

U49

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C702

0.1u/10V_4

DEEPS3_EC[4,13,15]

7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

SMDDR_VREF_DQ0

C249

0.1u/10V_4

1

2

BYTE6_48-55
BYTE7_56-63

E3

M_A_DQ61

F7

M_A_DQ63

F2

M_A_DQ57

F8

M_A_DQ60

H3

M_A_DQ59

H8

M_A_DQ58

G2

M_A_DQ56

H7

M_A_DQ62

D7

M_A_DQ55

C3

M_A_DQ53

C8

M_A_DQ50

C2

M_A_DQ52

A7

M_A_DQ54

A2

M_A_DQ48

B8

M_A_DQ51

A3

M_A_DQ49

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C506

0.1u/10V_4

change to 1K/F_4

3

Q56
*AP2302GN

+1.5VSUS

+1.5VSUS

C733

0.1u/10V_4

+1.5VSUS

8

14

SMDDR_VREF_DQ0+SMDDR_VREF_DIMM

C719

0.1u/10V_4

C492

0.1u/10V_4

+SMDDR_VREF

R562
1K/F_4

R563
1K/F_4

C724

C254

0.1u/10V_4

0.1u/10V_4

SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M3

C600

0.1u/10V_4

R565 *0/J_6

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

1

2

3

4

5

6

7

Monday, January 07, 2013

PROJECT :

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

ZQK

ZQK

ZQK

8

1A

1A

1A

4614

4614

4614