QUANTA ZQK Schematics

5

Memory Down x8pcs

4

3

ZQK ULV SYSTEM BLOCK DIAGRAM

2

1

Channel A

D D

Max. 4G

P13,14

DDRIII-SODIMM x1pc

P15

256Mb X 16 * 8pcs

Channel B

Dual Channel DDR III 1333/1600 MHZ

IMC

Ivy Bridge

BGA 1023
17W

P2,3,4,5,6

FDI

DMI

PCI-E
X8

eDP

INT_eDP

GPU

N14P-GV2

Display

P16~P21

4 Lane reserve

DMI(x4)

SATA - HDD

MINI CARD 2
mSATA SSD

USB3.0/2.0 Port
(Charger)

C C

USB2.0 Port

I/O board

USB2.0 Port

P31

CCD(Camera)

P31

P27

P26

P31

P24

SATA 0

SATA 1

USB3.0-(1)
USB2.0-(0)

USB2.0-(1)

USB2.0-(4)

USB2.0-(8)

P8

USB2.0

BATTERY

Azalia

B B

FDI

SATA

SATA

USB3.0

Panther Point

USB2.0

RTC

IHDA

P7, 8, 9, 10, 11, 12

PCH
BGA 989

LPC

DMI

Display

Display

PCI-E x1

PCI-E x1

INT_DP

USB3.0-(3)

INT_HDMI

X'TAL

32.768KHz

X'TAL
25MHz

SPI

SPI ROM*2

2M+4M(EC)

P8

128Mb X 16 * 4pcs = 1GB
256Mb X 16 * 4pcs = 2GB

X'TAL

27.0MHz

USB2.0-(3)

Dongle SW

HD3SS2521RHUR

PCIE-8

USB2.0-(10)

PCIE-3

eDP Con.
Touch Panel (option)

P23

HDMI Con.

MINI CARD1
WLAN+BT

RTL8411AAR

W/Card Reader

P25

Giga LAN

VRAM Max. 2G

DDR3

P24

Mini DP Con.

P26

P28

P21

P23

RJ45 CONN

Card Reader CONN

P28

P29

ALC3225

AUDIO CODEC

Int. DMIC

TPL@

Touch panel
TPM@ TPM module
NP@
CH@
NCH@

A A

EV@
RAMID@
SUG@
NSW@
SW@

Normal panel(Default)

Charge function(Default)

No Charge function

Optimize SKU

RAMID strap pin

LAN Surge

w/o Dongle switch

w Dongle switch

P30

Combo Jack

P30

Speaker

ALC1001

P30

P30

AMP

P30

K/B Conn

P30

HALL SENSOR

AH9249NTR-G1

EC ITE 8587

P24

Touch Pad
Con.

P30

P34

Fan*2 (PWM Type)

P32

KBL@ KB Backlight LED
RD@

mSATA Re-driver

5

4

3

TPM

2

P27

BQ24737RGRR

Batery Charger

TPS51225RUKR

3V/5V

TPS51650RSLR

+VCC_CORE/+VCC_GFX

TPS51219RTER

+1.05V_VTT

TPS51216RUKR

+1.5V_SUS

P35

TPS51463

VCCSA

P36

uP1642PQAG

+VGPU_CORE

P40

TPS51211DSCR

+1.5V_GFX/1.05V_GFX/3V_GFX

P38

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Discharger

P37

Thermal Protection

P39

P43

P42

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Block Diagram

Block Diagram

Block Diagram

1

ZQK

ZQK

ZQK

P41

1A

1A

1 46Monday, January 07, 2013

1 46Monday, January 07, 2013

1 46Monday, January 07, 2013

1A

5

4

3

2

1

Ivy Bridge Processor (DMI,PEG,FDI) (CPU)

PEG_ICOMPI and RCOMPO signals
should be shorted and routed with

U47A

P10

P11

W11

AA6

AC9

W10

AA7

AA3
AC8

AA11
AC12

U11

AA10

AG8

AF3
AD2

AG11

AG4

AF4

AC3
AC4

AE11

AE7
AC1

AA4

AE10

AE6

W1
W6

W3
W7

M2

P6
P1

N3

P7
P3

K1
M8
N4
R2

K3
M7

P4

T3

U7

V4

Y2

U6

T4

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT
FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

eDP_AUX#
eDP_AUX

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

Ivy Bridge

DMI Intel(R) FDI DP

DMI_TXN0[7]
DMI_TXN1[7]
DMI_TXN2[7]

D D

C C

eDP_ICOMPO 12mil
eDP_COMPIO 4mil

B B

DMI_TXN3[7]

DMI_TXP0[7]
DMI_TXP1[7]
DMI_TXP2[7]
DMI_TXP3[7]

DMI_RXN0[7]
DMI_RXN1[7]
DMI_RXN2[7]
DMI_RXN3[7]

DMI_RXP0[7]
DMI_RXP1[7]
DMI_RXP2[7]
DMI_RXP3[7]

FDI_TXN0[7]
FDI_TXN1[7]
FDI_TXN2[7]
FDI_TXN3[7]
FDI_TXN4[7]
FDI_TXN5[7]
FDI_TXN6[7]
FDI_TXN7[7]

FDI_TXP0[7]
FDI_TXP1[7]
FDI_TXP2[7]
FDI_TXP3[7]
FDI_TXP4[7]
FDI_TXP5[7]
FDI_TXP6[7]
FDI_TXP7[7]

FDI_FSYNC0[7]
FDI_FSYNC1[7]

FDI_INT[7]

FDI_LSYNC0[7]
FDI_LSYNC1[7]

EDP_COMP
INT_EDP_HPD#

EDP_AUXN[24]
EDP_AUXP[24]

EDP_TXN0[24]
EDP_TXN1[24]
EDP_TXN2[24]
EDP_TXN3[24]

EDP_TXP0[24]
EDP_TXP1[24]
EDP_TXP2[24]
EDP_TXP3[24]

EDP_AUXN
EDP_AUXP

EDP_TXN0
EDP_TXN1
EDP_TXN2
EDP_TXN3

EDP_TXP0
EDP_TXP1
EDP_TXP2
EDP_TXP3

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS -- GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_COMP

PEG_RX#15 [16]
PEG_RX#14 [16]
PEG_RX#13 [16]
PEG_RX#12 [16]
PEG_RX#11 [16]
PEG_RX#10 [16]
PEG_RX#9 [16]
PEG_RX#8 [16]

PEG_RX15 [16]
PEG_RX14 [16]
PEG_RX13 [16]
PEG_RX12 [16]
PEG_RX11 [16]
PEG_RX10 [16]
PEG_RX9 [16]
PEG_RX8 [16]

PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,

PEG_TX#15 [16]
PEG_TX#14 [16]
PEG_TX#13 [16]
PEG_TX#12 [16]
PEG_TX#11 [16]
PEG_TX#10 [16]
PEG_TX#9 [16]
PEG_TX#8 [16]

PEG_TX15 [16]
PEG_TX14 [16]
PEG_TX13 [16]
PEG_TX12 [16]
PEG_TX11 [16]
PEG_TX10 [16]
PEG_TX9 [16]
PEG_TX8 [16]

0.22uF AC coupling Caps for PCIE GEN1/2/3

- max length = 500 mils

- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical impedance = 14.5 mohms

02

DG 1.0 :

DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with

- typical impedance < 25 mohms

DP & PEG Compensation

CAD Note: Place PU resistor
within 2 inches of CPU

A A

EDP_COMP

PEG_COMP

R669 24.9/F_4

R675 24.9/F_4

+1.05V_VTT

+1.05V_VTT

5

The recommended AC cap value is changed to 220nF for compatibility with
PCIe Gen3 on future platforms.
For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

eDP Hot-plug (Disable)

HPD PU/PD resistor values based
on CRB and different to DG

4

+1.05V_VTT

INT_EDP_HPD#

Q23

2N7002K

R327
1K/J_4

3

2

1

R310
100K/J_4

3

EDP_HPD [24]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

2

Monday, January 07, 2013

PROJECT :

Ivy Bridge 1/5 (HOST & PCIE)

Ivy Bridge 1/5 (HOST & PCIE)

Ivy Bridge 1/5 (HOST & PCIE)

1

ZQK

ZQK

ZQK

1A

1A

1A

462

462

462

5

4

3

2

Boot S3 S3 RSM

1

+1.5V_CPU

03

DRAM_PWRGD

Ivy Bridge Processor (CLK,MISC,JTAG) (CPU)

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

C841
39P/50V_4

U47B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPW ROK

RESET#

Ivy Bridge

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

JTAG & BPM

BCLK#

BCLK_ITP

BCLK_ITP#

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H2

AG3

CLK_DPLL_SSCLKP_R

AG1

CLK_DPLL_SSCLKN_R

N59

CLK_PCIE_XDPP_R

N58

CLK_PCIE_XDPN_R

Isolate Space:20mils

AT30

BF44

SM_RCOMP_0

BE43

SM_RCOMP_1

BG43

SM_RCOMP_2

SM_RCOMP Impedance 85ohm

N53
N55

L56
L55
J58

M60

TDI

L59

K58

XDP_DBRST#_R

G58
E55
E59
G55
G59
H60
J59
J61

TP44
TP49
TP47
TP43
TP74
TP77
TP78
TP75

CLK_CPU_BCLKP [9]
CLK_CPU_BCLKN [9]

R677 0/J_4
R676 0/J_4

R750 *0/J_4
R749 *0/J_4

CPU_DRAMRST# [4]

R707 140/F_4
R702 25.5/F_4
R705 200/F_4

XDP_PRDY#
XDP_PREQ#

XDP_TRST#
XDP_TDI_VT

R745 0/J_4

TP50
TP42

XDP_TCLK_VT [8]
XDP_TMS_VT [8]

TP73
TP76

PCH_XDP_TDO_VT [8]

XDP_DBRST# [7]

CLK_DPLL_SSCLKP [9]
CLK_DPLL_SSCLKN [9]

CLK_PCIE_XDPP [9]
CLK_PCIE_XDPN [9]

Momory Down Layout notes

CAD NOTE: All DDR_COMP signals
should be routed such that :-

- max length = 500 mils

- trace width = 15mils and

- MB trace impedance < 68 mohms
(worst case resistance)

Layout Notes: Place near to XDP connector
05/15：PCH_XDP_TDO_VT already pull high
+3V_S5 on PCH side

+1.05V_VTT

Option for Prochot# function
68 ohm for unused, 62 ohm for used

H_PROCHOT#

XDP_TMS_VT
XDP_TDI_VT

XDP_PREQ#

XDP_TCLK_VT
XDP_TRST#

When MP, JTAG PU/PD resistor can be
removed? (Yes Intel, TDI, TDO, TMS, TRST#,
TCK,PREQ#, PRDY#)

D D

H_SNB_IVB#[8]

TP46

TP_CATERR#

TP54

EC_PECI[10,34]

H_PROCHOT#[34,35,40]

PM_THRMTRIP#[10]

R715 56/J_4
C770 *43P/50V_4

H_PROCHOT#_R

12

Over 130 degree C will drive low

C C

PM_SYNC[7]

H_PWRGOOD[10]

Isolate Space:20mils

+1.05V_VTT

B B

R735 75/F_4

CPU_PLTRST#

R720 0/J_4

C774 39P/50V_4
R719 0/J_4
R717 10K/J_4

PM_DRAM_PWRGD_R

R740 43/J_4

PM_SYNC_R

H_PWRGOOD_R

CPU_PLTRST#_R

R736

*750/F_4

SYS_PWROK

SM_DRAMPWROK

If motherboard only supports external graphics or if it supports
Processor Graphics but without eDP:
Connect DPLL_REF_SSCLK on Processor to GND through 1K +/­5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistor

R754 51/J_4

R722 62/J_4

R379 51/J_4
R755 51/J_4

R378 *51/J_4

R746 51/J_4
R744 51/J_4

PCH_XDP_TDO_VT

+1.05V_VTT

100 ns after +1.5V_CPU
reaches 80%

+3V

Thermal Trip (CPU) S3 leakage circuit (CPU)

C453

4

CPU_PLTRST#

CPU_PLTRST#_R

ZQK

ZQK

ZQK

0.1u/10V_4

1A

1A

1A

463

463

463

If PM_DRAM_PWEGD connector,the R5180 must stuff.

+3V_S5

+1.05V_VTT

3

2

1

2

1 3

Q67

2N7002K

R734
1K/J_4

Q66

MMBT3904-7-F_200MA

SYS_SHDN# [27,36,41]

IMVP_PWRGD[7,40]

A A

PM_THRMTRIP#

5

+1.5V_CPU

4

20111121 add Q31 becaue Vh=2.1/Vl=0.9.

R368

R367
*10K/J_4

*1K/J_4

6

2

5

*2N7002DW
Q31

1

4 3

PM_DRAM_PWRGD[7]

20111030 add resistor.

SYS_PWROK[7]

R384 0/J_4

+3V_S5

U24

2
1

74AHC1G09

3 5

R385 *0/J_4

3

C446

0.1u/10V_4

4

+1.5V_CPU

R396
200/F_4

R395 130/F_4

R387 *39/J_4

MAINON_G[5,41]

PM_DRAM_PWRGD_RPM_DRAM_PWRGD_Q

3

Q33 *2N7002K

2

2

1

20111128 change net to PCI_PLTRST#

PCI_PLTRST#[9,34]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Ivy Bridge 2/5 (CLK & JTAG)

Ivy Bridge 2/5 (CLK & JTAG)

Ivy Bridge 2/5 (CLK & JTAG)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

U50

1

VCC5NC

2

IN
GND3OUT

74LVC1G07GW_NC

R747 *1.5K/F_4

IN OUT

L L
H High-Z

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

5

4

3

2

1

Ivy Bridge Processor (CPU)

Channel A: On board RAM 2Rx16 8pcs

U47C

M_A_DQ[63:0][13,14]

D D

C C

M_A_BS#0[13,14]
M_A_BS#1[13,14]
M_A_BS#2[13,14]

B B

M_A_CAS#[13,14]
M_A_RAS#[13,14]
M_A_WE#[13,14]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AP11
AJ10

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

AG6

SA_DQ[0]

AJ6

SA_DQ[1]
SA_DQ[2]

AL6

SA_DQ[3]
SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]
SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]
SA_DQ[14]
SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AT40
AU40
BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7

M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 [13]
M_A_CLK0# [13]
M_A_CKE0 [13]

M_A_CLK1 [14]
M_A_CLK1# [14]
M_A_CKE1 [14]

M_A_CS#0 [13]
M_A_CS#1 [14]

M_A_ODT0 [13]
M_A_ODT1 [14]

M_A_DQSN[7:0] [13,14]

M_A_DQSP[7:0] [13,14]

M_A_A[15:0] [13,14]

M_B_DQ[63:0][15]

M_B_BS#0[15]
M_B_BS#1[15]
M_B_BS#2[15]

M_B_CAS#[15]
M_B_RAS#[15]
M_B_WE#[15]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

Channel B: SO-DIMM

U47D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7

M_B_CLK0 [15]
M_B_CLK0# [15]
M_B_CKE0 [15]

M_B_CLK1 [15]
M_B_CLK1# [15]
M_B_CKE1 [15]

M_B_CS#0 [15]
M_B_CS#1 [15]

M_B_ODT0 [15]
M_B_ODT1 [15]

DDR SYSTEM MEMORY B

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

04

M_B_DQSN[7:0] [15]

M_B_DQSP[7:0] [15]

M_B_A[15:0] [15]

Ivy Bridge

+0.75V_DDR_VTT

M_A_A0

R263 36/J_4

M_A_A1

R617 36/J_4

M_A_A2

R603 36/J_4

M_A_A3

R262 36/J_4

M_A_A4

R636 36/J_4

M_A_A5

R293 36/J_4

M_A_A6

R304 36/J_4

M_A_A7

R650 36/J_4

M_A_A8

R297 36/J_4

M_A_A9

R619 36/J_4

M_A_A10

R239 36/J_4

M_A_A11

R282 36/J_4

M_A_A12

R602 36/J_4

M_A_A13

R640 36/J_4

M_A_A14

S3 leakage circuit (CPU)

S3 circuit: DRAM_RST# to memory should be high

A A

during S3

DDR3_DRAMRST#[13,14,15] CPU_DRAMRST# [3]

DRAMRST_CNTRL_PCH[9]

EC_DRAMRST_CNTRL[34]

DEEPS3_EC[13,14,15]

R681 1K/F_4

R682 *0/J_4

R683 0/J_4

20120204 Change to EC for new BIOS 0.6

5

+1.5VSUS

20120914 Follow Z09 design to move R682 close to Q62

+3V_S5

R686
1K/J_4

3

R684 *0/J_4

Q62 2N7002K

2

C678

0.047u/10V_4

1

4

R680
1K/F_4

R693

4.99K/F_4

M_A_A15
M_A_CS#0

M_A_CS#1
M_A_CKE0

M_A_CKE1
M_A_ODT0

M_A_ODT1
M_A_WE#

M_A_CAS#
M_A_RAS#

M_A_BS#0
M_A_BS#1
M_A_BS#2

R287 36/J_4
R601 36/J_4

R238 36/J_4
R259 36/J_4

R237 36/J_4
R260 36/J_4

R257 36/J_4
R256 36/J_4

R240 36/J_4
R258 36/J_4
R236 36/J_4

R600 36/J_4
R264 36/J_4
R261 36/J_4

3

Ivy Bridge

C239
1u/6.3V_4

C238
1u/6.3V_4

C240
1u/6.3V_4

20120112 for memory down PU CAP.

2

C237
1u/6.3V_4

C236
1u/6.3V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

10u/6.3V_6

1u/6.3V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Ivy Bridge 3/5 (DDR3 I/F)

Ivy Bridge 3/5 (DDR3 I/F)

Ivy Bridge 3/5 (DDR3 I/F)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

ZQK

ZQK

ZQK

1

C279

C241

1A

1A

1A

464

464

464

5

IVY Bridge Processor (POWER) (CPU)

U47F

+VCC_CORE

A26

20120120 remove C621 for debug IC.

C755
10u/6.3V_6

C754
10u/6.3V_6

C756
10u/6.3V_6

C354

2.2u/10V_4

C367

2.2u/10V_4

C730

2.2u/10V_4

C366

2.2u/10V_4

C392

2.2u/10V_4

C846

39P/50V_4

SVID CLK

VR_SVID_CLK [40]

C760
10u/6.3V_6

C344

2.2u/10V_4

C744

2.2u/10V_4

C700

2.2u/10V_4

C696

2.2u/10V_4

C369

2.2u/10V_4

C737

+

470u/2V_7343

39P/50V_4

C847

C759
10u/6.3V_6

C758
10u/6.3V_6

C705
10u/6.3V_6

C743

2.2u/10V_4

C377

2.2u/10V_4

C697

2.2u/10V_4

C748

2.2u/10V_4

C375

2.2u/10V_4

C738

470u/2V_7343

20120120 remove C622 for debug IC.

C698

C336

2.2u/10V_4

2.2u/10V_4

C365

C356

2.2u/10V_4

2.2u/10V_4

C345

C368

2.2u/10V_4

2.2u/10V_4

C701

C731

2.2u/10V_4

2.2u/10V_4

C393

C363

2.2u/10V_4

2.2u/10V_4

C844

C843

39P/50V_4

R710 0/J _4

C757
10u/6.3V_6

C753
10u/6.3V_6

C706
10u/6.3V_6

C355

2.2u/10V_4

C699

2.2u/10V_4

C346

2.2u/10V_4

C376

2.2u/10V_4

C391

2.2u/10V_4

C845

39P/50V_4

5

D D

C364

C C

B B

A A

2.2u/10V_4

C374

2.2u/10V_4

C338

2.2u/10V_4

C695

2.2u/10V_4

C337

2.2u/10V_4

CPU Core Power

IVY 17W:TDC 33A
IVY SPEC

1.9mΩ/LoadlineDesign
total : 2.2uF x 35
total : 22uF x 12
tatal : 470u x3(Power side*1)

Cose down

IVY SPEC

1.9mΩ/LoadlineDesign
total : 2.2uF x 35
total : 10uF x 12
tatal : 470u x1(Power side*1)

20121203：：：：Add 39pF for ESD

+VCC_CORE +1.05V_VTT +VCC_GFX +VCCSA +1.5V_CPU +1.8V

C842

39P/50V_4

39P/50V_4

Layout note: need routing
together and ALERT need
between CLK and DATA

H_CPU_SVIDCLK

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

+

Place PU resistor close to CPU Place PU resistor close to CPU

H_CPU_SVIDDAT

CORE SUPPLY

VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]

Ivy Bridge

+1.05V_VTT +1.05V_VTT

R709
130/F_4

R712 0/J _4

PEG AND DDRSENSE LINES SVID QUIET RAILS

POWER

VSS_SENSE_VCCIO

VCCIO_SENSE

4

+1.05V_VTT

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]

AB20

VCCIO[33]

AC13

VCCIO[34]

AD16

VCCIO[35]

AD18

VCCIO[36]

AD21

VCCIO[37]

AE14

VCCIO[38]

AE15

VCCIO[39]

AF16

VCCIO[40]

AF18

VCCIO[41]

AF20

VCCIO[42]

AG15

VCCIO[43]

AG16

VCCIO[44]

AG17

VCCIO[45]

AG20

VCCIO[46]

AG21

VCCIO[47]

AJ14

VCCIO[48]

AJ15

VCCIO[49]

W16

VCCIO50

W17

VCCIO51

BC22

VIDSCLK

VIDSOUT

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

VCCIO_SEL

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R357 100/F_4

R354 100/F_4

R325 10/J_4

R326 10/J_4

4

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VCC_SENSE
VSS_SENSE

SVID DATA SVID ALERT

VR_SVID_DATA [40]

CPU VCCIO

IVY 17W:8.5A

SNB : Spec

330uF/6mohm x 2
10uF x 10
1uF x 26

C654

C655

10u/6.3V_6

10u/6.3V_6

C660

C648

10u/6.3V_6

10u/6.3V_6

C407

C401

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C394

C325

C331

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

IVY SPEC
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2

R328 0/J _6

TP70

R344 0/J _4
C340 1u/6.3 V_4

+VCC_CORE

+1.05V_VTT

Cose down

330uF/6mohm x 1
10uF x 10
1uF x 26

+

C641
330u/2V_7343

C342

C652

C372

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C645

C349

C353

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C348

C299

C297

C328

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C298

C400

C296

+1.05V_VTT

+1.05V_VTT

1u/6.3V_4

VCC_SENSE [40]
VSS_SENSE [40 ]

VCCP_SENSE [38]
VSSP_SENSE [3 8]

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

Voltage selection for VCCIO:
this pin must be pulled high
on the motherboard

On CRB
H_SNB_IVB#_PWRC TRL = low, 1.0 V
H_SNB_IVB#_PWRC TRL = high/NC, 1.05V

R714 43/J_4

C409
1u/6.3V_4

C395
1u/6.3V_4

C408
1u/6.3V_4

C321
1u/6.3V_4

R711
75/F_4

VR_SVID_ALERT#_RH_CPU_SVIDALRT#

C664
1u/6.3V_4

C370
1u/6.3V_4

C323
1u/6.3V_4

C326
1u/6.3V_4

R713 0/J _4

C295
1u/6.3V_4

C350
1u/6.3V_4

C332
1u/6.3V_4

C324
1u/6.3V_4

3

CPU VCCAXG

IVY 17W:TDC 18A

Spec

3.9mΩ/LoadlineDesign
total : 1uF x 11
total : 10uF x 6
total : 22uF x 6
tatal : 470u x 1(power side*2)

VR_SVID_ALERT# [40 ]

3

Cose down

3.9mΩ/LoadlineDesign
total : 1uF x 11
total : 10uF x 12
tatal : 470u x 1(power side*2)

CPU VCCPL

IVY 17W:1.5A

Spec

330uF/7mohm x 1
1uF x 2

IVY SPEC
330uF x1, 10uF_8 x1, 1uF_4 x2
Socket BOT edge.

IVY SPEC
330uF x1, 10uF_8 x1 Socket BOT edge,
10uF_8 x2 Socket BOT cavity.

CPU VCCSA

IVY 17W: 6A

Spec

330uF/7mohm x 1
10uF x 5
1uF x 5

Real

10uF x 3

+SMDDR_VREF +VDDR_R EF_CPU +1.5V_CPU

MAIND[36,37,41]

S3 circuit: 1.5V input to IVB is gated &
IVB Read Vref 0.75V is gated

C463
10u/6.3V_6

C468
10u/6.3V_6

C402
1u/6.3V_4

VCCAXG_SENSE/VS SAXG_SENSE R=1 00,
Trace impedance 15.5~34.5, <2 5mils.

Real

10uF x 1

+1.8V

1uF x 2

C658
10u/6.3V_6

R739 *0/J_8

3

2

MAIND

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C449

C444

C467

10u/6.3V_6

10u/6.3V_6

10u/6.3V_6

C404

C435

C447

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C399

C405

C406

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

+VCC_GFX

VCC_AXG_SENSE[40]

VSS_AXG_SENSE[40]

R667 0/J_8

C670

C666

10u/6.3V_6

10u/6.3V_6

C334

C320

1u/6.3V_4

1u/6.3V_4

S3 ST UFF NO_ STUFF
enable -
disable -

R5347/R6362

20111024 from +1.5VSUS change to +1.5V_CPU

1

Q65
2N7002K

R751
100K/J_4

C462

C457

C445

2

IVY Bridge Processor (GRAPHIC POWER) (CPU)

U47G

+VCC_GFX

AA46

VAXG[1]

AB47

VAXG[2]

AB50

C657

10u/6.3V_6

C327
1u/6.3V_4

C455
10u/6.3V_6

C454
10u/6.3V_6

C451
1u/6.3V_4

C410
1u/6.3V_4

R386 100/J_4

R388 100/J_4

CPU_VCCPLL

C668
1u/6.3V_4

10u/6.3V_6

C322
1u/6.3V_4

C669
1u/6.3V_4

C672

R738
*1K/F_4

R748
*1K/F_4

2

C792

+

470u/2V_7343

C458
10u/6.3V_6

C450
10u/6.3V_6

C443
1u/6.3V_4

C403
1u/6.3V_4

TP56

TP57

+

C656
330u/2V_7343

C335
1u/6.3V_4

R5347/R6362

change to 1K/F_4

+

C662
*330u/2.5V_352 8

+VCCSA

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

Ivy Bridge

20111107 stuff Q5010 and un-stuff R5347/R362.

4.5A

MAINON_G[3,41]

GRAPHICS

LINES

1.8V RAIL

SA RAIL

POWER

SENSE

R362 *0_1206

R365 *0_1206

Q64 AO4496

8
7

5

4

MAIND

MAINON_G

SM_VREF

VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]

DDR3 - 1.5V RAILS

VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

VCCDQ[1]
VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

1
2
36

C779
470P/50V_4

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]

+1.5V_CPU+1.5VSUS

2

1

CAD Note: +VDDR_REF_CPU should
have 10 mil trace width

AY43

+VDDR_REF_CPU

+1.5V_CPU

AJ28
AJ33
AJ36
AJ40
AL30

10u/6.3V_6

AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38

10u/6.3V_6

AR26
AR28
AR30
AR32
AR34
AR36

C397

AR40
AV41

1u/6.3V_4

AW26
BA40
BB28
BG33

C439
1u/6.3V_4

AM28
AN26

C378 1u/6.3V_4

BC43

R373 *51/J_4

BA43

R372 *51/J_4

R674 *100 /F_4

U10

SNB_IVB# N.A at SNB EDS #27637 0.7v1

R723 *10K /J_4
C777 *33n/1 0V_4

D48

R728 0/J_4

D49

R374 *10K /J_4

R377
220/J_8

3

Q32
2N7002K

1

C396

C333

C380

10u/6.3V_6

10u/6.3V_6

C411

C440

C414

*10u/6.3V_6

*10u/6.3V_6

C361

C437

1u/6.3V_4

1u/6.3V_4

C329

C389

1u/6.3V_4C339

1u/6.3V_4

+1.5V_CPU

+VCCSA

201201117 C767 for Intel fw issue,
if solve need un-stuff.

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Ivy Bridge 4/5 (POWER)

Ivy Bridge 4/5 (POWER)

Ivy Bridge 4/5 (POWER)

Date: Sheet of

Monday, January 0 7, 2013

Date: Sheet of

Monday, January 0 7, 2013

Date: Sheet of

Monday, January 0 7, 2013

1

05

CPU VDDQ

IVY 45W: 5A

Spec

330uF/6mohm x 1
10uF x 8
1uF x 10

C441

C387

10u/6.3V_6

10u/6.3V_6

C775

+

330u/2V_7343

C362

C379

1u/6.3V_4C347

1u/6.3V_4

C438

C360

1u/6.3V_4

1u/6.3V_4

+1.5V_CPU

VCCSA_SENSE [39]

VCCSA_VID0 [39]
VCCSA_VID1 [39]

For IV Bridge

VID[1]

VID[0]

0
0
1
1

For SN Bridge

VID[1]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

+VCCSA

0.9V

0

0.8V

1

0.725V

0

0.675V

1

+VCCSA

0.9V0

0.8V

1

ZQK

ZQK

ZQK

465

465

465

1A

1A

1A

5

4

3

2

1

IVY Bridge Processor (GND) (CPU)

U47H

A13

VSS[1]

D D

C C

B B

A A

A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

AM13
AM20
AM22
AM26
AM30
AM34

A9

VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

Ivy Bridge

VSS

5

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

R375
*0/J_4

U47I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46
D50
D54
D58

E25
E29

E35
E40
F13
F15
F19
F29
F35
F40
F55
G48
G51

G61
H10
H14
H17
H21

H53
H58

K11
K21
K51

M11
M15

J49
J55

L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

D6

E3

G6

H4

K8

J1

VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]

Ivy Bridge

VSS

G48：no stuff for IVY

Processor Strapping

CFG2
(PCI-E Static x16 Lane Reversal)

CFG3
(PCI-E Static x4 Lane Reversal)

CFG4
(DP Presence Strap)

CFG7
(PEG Defer Training)

4

M4

VSS[251]

M58

VSS[252]

M6

VSS[253]

N1

VSS[254]

N17

VSS[255]

N21

VSS[256]

N25

VSS[257]

N28

VSS[258]

N33

VSS[259]

N36

VSS[260]

N40

VSS[261]

N43

VSS[262]

N47

VSS[263]

N48

VSS[264]

N51

VSS[265]

N52

VSS[266]

N56

VSS[267]

N61

VSS[268]

P14

VSS[269]

P16

VSS[270]

P18

VSS[271]

P21

VSS[272]

P58

VSS[273]

P59

VSS[274]

P9

VSS[275]

R17

VSS[276]

R20

VSS[277]

R4

VSS[278]

R46

VSS[279]

T1

VSS[280]

T47

VSS[281]

T50

VSS[282]

T51

VSS[283]

T52

VSS[284]

T53

VSS[285]

T55

VSS[286]

T56

VSS[287]

U13

VSS[288]

U8

VSS[289]

V20

VSS[290]

V61

VSS[291]

W13

VSS[292]

W15

VSS[293]

W18

VSS[294]

W21

VSS[295]

W46

VSS[296]

W8

VSS[297]

Y4

VSS[298]

Y47

VSS[299]

Y58

VSS[300]

Y59

VSS[301]

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

VSS_NCTF_10

NCTF

VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

The CFG signals have a default value of '1' if not terminated on the board.

1 0

Normal Operation

Normal Operation

Disable; No physical DP attached to eDP

PEG train immediately following
xxRESETB de assertion

3

IVY Bridge Processor (RESERVED, CFG) (CPU)

U47E

TP72
TP79

CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

TP45
TP71

TP53
TP48

TP51

TP52
TP55

1
0

11: 1x16 - Device 1 functions 1 and 2 disabled
10: (Default)2x8, 2x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: 1x8,2x4,2x4 - Device 1 functions 1 and 2 enabled

Lane Reversed

Lane Reversed

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

CFG6

CFG5

AU19
AU21
BD21
BD22
BD25
BD26
BG22

BG26

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

BE22

RSVD23
RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

Ivy Bridge

R753 *1K/F_4

R752 1K/F_4

RESERVED

CFG[6:5] (PCIE Port Bifurcation Straps)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

RSVD28
RSVD29

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

CFG2

0

CFG3

0
0

CFG4

CFG7

1

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

BE7 SA_DIMM_VREFDQ
BG7 SB_DIMM_VREFDQ

BE7
BG7

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

N14P-GV2

R743 1K/F_4

R742 1K/F_4

R741 1K/F_4

R376 *1K/F_4

Ivy Bridge 5/5 (GND)

Ivy Bridge 5/5 (GND)

Ivy Bridge 5/5 (GND)

R678 *1K/J_4

SMDDR_VREF_DQ0_M3 [13,14]
SMDDR_VREF_DQ1_M3 [15]

R679 *1K/J_4

processor signal balls BF3 and BG4 for
Ivy Bridge 4-core and balls BE7
and BG7 for Ivy Bridge 2-core

for M3 solution
need R5265/R5266,
W/O M3 then NC

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQK

ZQK

ZQK

1

06

466

466

466

1A

1A

1A

5

4

3

2

1

CPT/PPT (DMI,FDI,PM) (CLG)

U38C

DMI_COMP
DMI_BIAS

SUSACK#_ R

SYS_PWROK_R

EC_PWROK_R

APWROK _R

SUSWARN#_R

PM_BATLOW #

PM_RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

Panther Point_ R1P0

+3V_S5

+3V_S5

+3V_S5

DSW

+3V_S5

+3V_S5

DMI

FDI

+3V

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

DMI_RXN0[2]
DMI_RXN1[2]
DMI_RXN2[2]
DMI_RXN3[2]

D D

20121219：SUSACK# connect to Pin79 of EC (GPJ3)

PCH_SUSACK#[34]

SYS_PWROK

C C

PWROK_ EC

PM_DRAM_P WRGD[3]

PCH_RSMRST#[34 ]

PCH_SUSW ARN#[34]

DNBSWON#[34]

ACPRESENT[35]

DMI_RXP0[2]
DMI_RXP1[2]
DMI_RXP2[2]
DMI_RXP3[2]

DMI_TXN0[2]
DMI_TXN1[2]
DMI_TXN2[2]
DMI_TXN3[2]

DMI_TXP0[2]
DMI_TXP1[2]
DMI_TXP2[2]
DMI_TXP3[2]

R543 49.9/F_4

+1.05V_V TT

R550 750/F_4

R604 0/J_4

XDP_DBRST#[3]

R591 0/J_4

R614 *0/J_4

R615 0/J_4

20121219：SUSWARN# connect to Pin78 of EC (GPJ2)

C206 *1 U/10V_4

R611 0/J_4

R3

R612 *0 /J_4

PM_DRAM_P WRGD

PCH_RSMRST#

R836 0/J_4

R198 0/J_4

ACPRESENT

XDP_DBRST#

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

+3V_S5

SLP_SUS#

PMSYNCH

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DPWROK_R

PCIE_W AKE#_LAN

CLKRUN#

PCH_SUSCL K

SLP_A#

SLP_SUS#

SLP_LAN#

DSWVREN [8]

R169 0/J_4

R616 0/J_4

TP30

TP32

TP34

TP29

FDI_TXN0 [2]
FDI_TXN1 [2]
FDI_TXN2 [2]
FDI_TXN3 [2]
FDI_TXN4 [2]
FDI_TXN5 [2]
FDI_TXN6 [2]
FDI_TXN7 [2]

FDI_TXP0 [2]
FDI_TXP1 [2]
FDI_TXP2 [2]
FDI_TXP3 [2]
FDI_TXP4 [2]
FDI_TXP5 [2]
FDI_TXP6 [2]
FDI_TXP7 [2]

FDI_INT [2]
FDI_FSYNC0 [2]
FDI_FSYNC1 [2]
FDI_LSYNC0 [2]
FDI_LSYNC1 [2]

CLKRUN# [27,34]

LPCPD# [27 ]

SUSC# [34]

SUSB# [34]

SLP_SUS# [1 1,34]

PM_SYNC [3]

DPWROK [34]

PCIE_LAN_WAKE # [28]

20120914 Add for TPM LPCPD#

INT_LVDS_B LON[24]
INT_LVDS_DI GON[24]

INT_LVDS_B RIGHT[24]

Close to PCH

DAC_IREF

R139
1K/F_4

The required series-resistors are:

‧‧‧‧

Direct Connect - 33 Ω

‧‧‧‧

Docking Topology - 20 Ω

CPT/PPT (LVDS,DDI)

U38D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48
AM47

AK47
AJ48

AN47
AM49

AK49
AJ47

AF40
AF39

AH45
AH47

AF49
AF45

AH43
AH49

AF47
AF43

N48
P49
T49

T39
M40

M47
M49

T43
T42

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

Panther Point_ R1P0

LVDS

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_INTN

SDVO_INTP

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLK­INT_HDMICLK+

DisplayPort D

HDMI_DDCCLK_SW [25]
HDMI_DDCDATA_ SW [25]

HDMI_HP [25]

INT_HDMITX2N [25]
INT_HDMITX2P [25]
INT_HDMITX1N [25]
INT_HDMITX1P [25]
INT_HDMITX0N [25]
INT_HDMITX0P [25]
INT_HDMICLK- [25]
INT_HDMICLK+ [25]

DDPC_CTRLCLK [23]
DDPC_CTRLDAT [2 3]

INT_DP_AUXDN [23]
INT_DP_AUXDP [23]

[23]

DP_HPD_Q

DP_TXN0 [23]
DP_TXP0 [23]
DP_TXN1 [23]
DP_TXP1 [23]
DP_TXN2 [23]
DP_TXP2 [23]
DP_TXN3 [23]
DP_TXP3 [23]

INT. HDMI

DisplayPort C

07

B B

PCH Pull-high/low (CLG)

Follow CRB 1.5 to pull
up 1K ohm to +3V

CLKRUN#

R275 8.2K/J_4

XDP_DBRST#

R283 1K/F_4
R271 *1K/J_4

PCH_RSMRST#

R547 10K/J_4

DPWROK_R

R174 10K/J_4

SYS_PWROK

R577 *10K/J_4

A A

20120706:Speed up 250ms to boot up
R1,R2,R3 for EC power on 250 ms

20121004(EC Anda)：：：：Chage trigger pin from +0.75V_ON to APWROK；；；；R2 change to 100K

APWROK[34]

+3V

CRB 1.0 use 1K

PM_RI#
PM_BATLOW #
PCIE_W AKE#_LAN
SLP_LAN#
SUSWARN#_R
ACPRESENT

PM_DRAM_P WRGD

ACPRESENT would need a pull-up to DSW well if DSW
mode is supported on platform

R1

R607 0/J_4

5

R2

R609 10K/J_4
R242 8.2K/J_4
R618 10K/J_4
R208 *10K/J_4
R196 10K/J_4
R180 *10K/J_4

Follow Z09 NO STUFF

R586 200/F_4

APWROK _R

R608
100K/J_4

System PWR_OK (CLG)

+3V_S5

to PCH Pin12, XDP and EE debug

SYS_PWROK[3]

SYS_PWROK

4

U41

4

TC7SH08FU

IMVP_PWRGD PU +3V
PWROK_EC PD

+3V_S5

so AND gate output dont need PD again

C631

0.1u/10V _4

2
1

PWROK_ EC

3 5

R599
100K/J_4

R576 *0/J_4

PWROK_ EC

+3V_S5

C598
*0.1U/10V _4

U40

2

IMVP_PW RGD_R

[34]

4

*TC7SH08

R554 0/J_4

1

3 5

IMVP_PW RGD [3,4 0]
GFX_PW RGD [34,40 ]

20111128 add 0ohm to passed IMVP_PERGD

include GFX_PWRGD to SYS_PWROK for PCH check

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

3

2

Monday, January 07, 2013

PROJECT :

PCH 1/6 (DMI/FDI/VIDEO)

PCH 1/6 (DMI/FDI/VIDEO)

PCH 1/6 (DMI/FDI/VIDEO)

ZQK

ZQK

ZQK

1

1A

1A

1A

467

467

467

5

RTC (RTC)

20MIL

R665 0/J_6

+3VPCU

D D

20MIL

HDA Bus (CLG)

PCH JTAG Debug (CLG)

C C

R663
1K/J_4

12

CN14
RTC_SOCKET

R621
51/J_4

VCCRTC_1

20MIL

Q70

MMBT3904

PCH_AZ_CODEC_SYNC[30]

PCH_AZ_CODEC_RST#[30]

PCH_AZ_CODEC_SDOUT[30]

+3V_S5

R289
210/F_4

R272
100/F_4

PCH_AZ_CODEC_BITCLK[30]

PCH Dual SPI (CLG)

+3V_RTC

R672 20K/J_4

C650

D30

30MIL

R673 20K/J_4

BAT54C

C647
1u/6.3V_4

1 3

VCCRTC_3 VCCRTC_4VCCRTC_2

R809 4.7K/J_4

2

ML1220 Coin type
AHL03001424 FDK (SAY) 15mAH
AHL03017100 Panasonic (MAT) 17mAH

R302

R294

210/F_4

210/F_4

XDP_TMS_VT
PCH_XDP_TDO_VT
PCH_XDP_TDO
XDP_TCLK_VT

R292

R303

100/F_4

100/F_4

1u/6.3V_4

C651
1u/6.3V_4

R163 33/J_4
R153 33/J_4
R166 33/J_4
R529 33/J_4

(Default for WIN8)

RTC_RST#

12

J2

*SHORT_ PAD1

SRTC_RST#

12

J1

*SHORT_ PAD1

R811 4.7K/J_4

68.1K/F_4

150K/F_4

C141 *22p/50V_4

ACZ_BITCLK_R
ACZ_SYNC_CODEC
ACZ_RST#_R
ACZ_SDOUT_R

+5V_S5

R808

R810

W25Q32BVSSIG / AKE391P0N00----->4MB
W25Q16BVSSIG / AKE38FP0N01----->2MB

R661 0/J_6

PCH_SPI_CLK_R2
PCH_SPI_SI_R2
PCH_SPI_SO_R2

C636
*22p/50V_4

R654 3.3K/J_4

R560 33/J_4
R551 33/J_4
R566 33/J_4

R589 3.3K/J_4

R555 33/J_4
R552 33/J_4
R558 33/J_4

Layout Notes:
Place Series Resistors close to Flash ROM

PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

R584 0/J_4

5

+3V_PCH_ME

PCH_SPI_CS1#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

+3V_S5

R652 33/J_4
R653 33/J_4
R655 33/J_4

PCH_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R

Layout Notes:
Place Series Resistors close to Flash ROM

B B

A A

PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

Layout Notes:
Place Series Resistors close to Flash ROM

C601 *22p/50V_4

+3V_PCH_ME

PCH_SPI_CLK_EC[34]

PCH_SPI_SI_EC[34]

PCH_SPI_SO_EC[34]

SPI_CS0#_UR_ME[34]

U44

1

CE#

6

SCK

5

SI

2

SO

3

WP#

ROM-2M_ME

U39

1

CE#

6

SCK

5

SI

2

SO

3

WP#

ROM-4M_EC

PCH_SPI_CS1#

SPI_CS0#_UR_ME

+3V_PCH_ME

VDD

HOLD#

VSS

VDD

HOLD#

VSS

8

7

R656 3.3K/J_4

4

8

7

R570 3.3K/J_4

4

R596 47K/J_4

+3V_PCH_ME

+3V_PCH_ME

C621

0.1u/10V_4

+3V_PCH_ME

C640

0.1u/10V_4

4

3

PCH2 (CLG)

C591 18p/50V_4

C595 18p/50V_4

Add MOSFET to separate CODEC SYNC signal

+5V

R133 0/J_4

ACZ_SYNC_CODEC

CRB 1.0

R143
1M/J_4

2

1

12

Y4

32.768KHZ

+3V_RTC

ZRH use 2N7002D

3

Q17
2N7002K

PCH_AZ_CODEC_SDIN0[30]

SYS_COM_REQ[23]

XDP_TCLK_VT[3]
XDP_TMS_VT[3]

PCH_XDP_TDO_VT[3]

R549
10M/J_4

R173 1M/J_4

SPKR[30]

TP12

TP35

RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

ACZ_BITCLK_R
ACZ_SYNC_R

SPKR

ACZ_RST#_R

TP24

ACZ_SDOUT_R

PCH_GPIO33

SYS_COM_REQ

XDP_TCLK_VT
XDP_TMS_VT
PCH_XDP_TDO_VT
PCH_XDP_TDO

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_SI
PCH_SPI_SO

PCH Strap Table

Pin Name

Strap description

No reboot mode setting PWROKSPKR

GNT3# / GPIO55 Top-Block Swap Override

INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up

GNT1# / GPIO51

GPIO19

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

HDA_SDO Flash Descriptor Security RSMRST

DF_TVS

GPIO28

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO15

DSWVREN DSW

NV_ALE Intel Anti-Theft HDD protection

4

Intel ME Crypto Transport Layer
Security (TLS) cipher suite
internal PD

DEEP S4/S5 well
On Die DSW VR Enable

Only for Interposer

Sampled

Configuration

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

PWROK

PWROK

0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

GPIO19GNT1#

11

PWROK

00

0 = effect (default)(weak pull-down 20K)

1 = overridden

PWROK

0 = Set to Vss (weak pull-down 20K)

1 = Set to Vcc

0 = Disable

1 = Enable (weak pull-up 10K)

0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V

RSMRST

0 = Disable (Default)

1 = Enable

High = Enable (Default)

Low = Disable

PWROK 0 = Disable (Internal pull-down 20kohm)

3

2

CPT/PPT (HDA,JTAG,SATA) (CLG)

U38A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

Panther Point_R1P0

Boot Location

SPI

*

LPC

RTCIHDA

JTAG

SPI

[34]

+3V_RTC

+3V
+3V

+3V_RTC

+3V_S5

LPC

FWH4 / LFRAME#

+3V

LDRQ1# / GPIO23

SATA 6G

+3V

SATA

+3V_S5

SATAICOMPO

SATA3RCOMPO

SATA0GP / GPIO21
SATA1GP / GPIO19

+3V

ME_WR#

R606 2.2K/J_4
R613 1K/J_4

R299 *1K/J_4

+3V_S5

R557 330K/J_4

+1.8V

C38

FWH0 / LAD0

A38

FWH1 / LAD1

B37

FWH2 / LAD2

C37

FWH3 / LAD3

D36
E36

LDRQ0#

K36
V5

SERIRQ

AM3

SATA0RXN

AM1

SATA0RXP

AP7

SATA0TXN

AP5

SATA0TXP

AM10

SATA1RXN

AM8

SATA1RXP

AP11

SATA1TXN

AP10

SATA1TXP

AD7

SATA2RXN

AD5

SATA2RXP

AH5

SATA2TXN

AH4

SATA2TXP

AB8

SATA3RXN

AB10

SATA3RXP

AF3

SATA3TXN

AF1

SATA3TXP

Y7

SATA4RXN

Y5

SATA4RXP

AD3

SATA4TXN

AD1

SATA4TXP

Y3

SATA5RXN

Y1

SATA5RXP

AB3

SATA5TXN

AB1

SATA5TXP

Y11
Y10

SATAICOMPI

AB12
AB13

SATA3COMPI

AH1

SATA3RBIAS

P3

SATALED#

V14
P1

R291 *1K/J_4

R508 *1K/J_4

R564 330K/J_4

R507 *1K/J_4
R627 *1K/J_4

R164 1K/J_4

R622 1K/J_4

R597 *1K/J_4

2

R536 0/J_4

+1.8V

PCH_DRQ#0
PCH_DRQ#1

TP14
TP9

R634 10K/J_4

TP31

UM77 SATA port 1,3 disable.

SATA_COMP

R219 37.4/F_4

SATA3_COMP

R210 49.9/F_4

SATA3_RBIAS

R633 750/F_4

SATA_ACT#

BBS_BIT0

SPKR

R553 *330K/J_4

R628 10K/J_4
R222 10K/J_4
R643 *10K/J_4

20120919 FOLLOW Z09 NO STUFF

PCI_GNT3# [9]

PCH_INVRMEN

BBS_BIT1 [9]

BBS_BIT0

ACZ_SDOUT_R

DF_TVS [10]
H_SNB_IVB# [3]

PLL_ODVR_EN [10]

ACZ_SYNC_R

PCH_GPIO15 [10]

DSWVREN [7]

NV_ALE [9]

1

08

LPC_LAD0 [26,27,34]
LPC_LAD1 [26,27,34]
LPC_LAD2 [26,27,34]
LPC_LAD3 [26,27,34]

LPC_LFRAME# [26,27,34]

Follow CRB 1.5 to use 10K ohm pull high

SERIRQ [27,34]

TP69

Used as GPIO only. at chklist 1.2

Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]

ME_WR default EC setting folating

for future CPU, Sandy Bridge NC
DF_TVS needs to be pulled up to VccDFTERM power rail
through 2.2 kOhm ±5% - R8361 change to 0 or not??

Needs to be pulled High for Chief River platform
chklist 2.0

+3V

SATA_RXN0 [27]
SATA_RXP0 [27]
SATA_TXN0 [27]
SATA_TXP0 [27]

SATA_RXN1 [26]
SATA_RXP1 [26]
SATA_TXN1 [26]
SATA_TXP1 [26]

DG recommended that AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.

+1.05V_VTT

+3V
+3V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

SATA HDD

mSATA

SATA0GP/GPIO21
SATA4GP/GPIO16
SATA5GP/GPIO49
If these pins are unused use 8.2k
to 10k pull-up to +Vcc3_3 or 8.2k
to 10k pull-down to ground

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PCH 2/6 (SATA/RTC/HDA/LPC)

PCH 2/6 (SATA/RTC/HDA/LPC)

PCH 2/6 (SATA/RTC/HDA/LPC)

ZQK

ZQK

ZQK

1

1A

1A

1A

468

468

468

5

CPT/PPT (PCI,USB,NVRAM) (CLG)

U38E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

D D

Layout Notes:
USB3 TX AC cap place at connector side, AC cap to
connector < 400mils

C C

PCLK_TPM[27]

CLK_LPC_DEBUG[26 ]

CLK_PCI_EC[34]

B B

PLTRST#(CLG) PCI/USBOC# Pull-up(CLG)

PCI_PLTRST#

DDRIII Memory down strap (CLG)

A A

R574 RAMID@15K/F_4
R567 *RAMID@15K/F_4
R200 RAMID@15K/F_4
R581 RAMID@15K/F_4

Vender

Hynix

Elpida

USB30 Port1: EXT USB3.0 Port
USB30 Port3: Mini DP port

USB30_RX1-[31]
USB30_RX3-[23]
USB30_RX1+[31]
USB30_RX3+[23]
USB30_TX1-[31]
USB30_TX3-[23]
USB30_TX1+[31]
USB30_TX3+[23]

BBS_BIT1[8]

BOARD_ID2[10,32]

PCI_GNT3#[8]

DGPU_PWR_EN[42]

DGPU_HOLD_RST#[16]

PCI_PLTRST#[3,34]

CLK_PCI_FB CLK_PCI_FB_R

R132 *100K/J_4

DGPU_PWR_EN

+3V

2
1

U42

3 5

TC7SH08FU

R658 *0/J_4

RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3

Q PN

RAM_IDn

0000

AKD5JGST400

0001

AKD5JGST407 EDJ4216 EFBG-GNL-F

0010

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

REQ1#_GPIO50
REQ2#_GPIO52
REQ#3

BOARD_ID2

MPC_PWR_CTRL#
DGPU_PWR_EN
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH

TP33

PCI_PLTRST#

PCLK_TPM_R

R91 22/J_4
R122 22/J_4

CLK_LPC_DEBUG_R

R116 22/J_4

CLK_PCI_775_R

R138 22/J_4

R137 10K/J_4

20120522：follow CRB to modify power plan to +3V
check list 2.0：When connected to the processor the PLTRST# signal
should be level shifted to 1.05V.

C634

0.1u/10V_4

4

PLTRST#

R575 *RAMID@10K/J_4
R569 RAMID@10K/J_4
R203 *RAMID@10K/J_4
R582 *RAMID@10K/J_4

Mfr. PN

EDJ4216EBBG-DJ- F

5

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

TP21
TP22
TP23
TP24

USB3.0

USB30_RX1N

TP25

USB30_RX2N

TP26

USB30_RX3N

TP27

USB30_RX4N

TP28

USB30_RX1P

TP29

USB30_RX2P

TP30

USB30_RX3P

TP31

USB30_RX4P

TP32

USB30_TX1N

TP33

USB30_TX2N

TP34

USB30_TX3N

TP35

USB30_TX4N

TP36

USB30_TX1P

TP37

USB30_TX2P

TP38

USB30_TX3P

TP39

USB30_TX4P

TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PME#
PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

Panther Point_R1P0

PLTRST# [16,26,27,28,34]

RSVD

PCI

+3V
+3V
+3V

+3V
+3V
+3V

+3V
+3V
+3V
+3V

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

B21

M20

AY16

BG46

BE28
BC30

TP23

BE32
BJ32

TP62

BC28
BE30

TP18

BF32

BG32

TP61

AV26
BB26

TP27

AU28
AY30

TP16

AU26
AY26

TP28

AV28

AW30

TP19

K40
K38
H38

G38
C46

C44
E40

D47
E42
F46

G42
G40
C42
D44

K10

PCI_PME#

C6

H49
H43

J48
K42
H40

+3V

R624
100K/J_4

+3V_S5

Freq.

1333MHz
1600MHz

USB2.0

USB

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25
RSVD26

RSVD27
RSVD28

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

4

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8
AY5

BA2
AT12

BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29

USB port6/7 may not be available on all PCH sku

N28

(HM55 support 12port only)

M28
L30
K30
G30

TP21

E30

TP25

C30
A30
L32
K32
G32
E32
C32
A32

C33

USB_BIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

RAM_ID0

L16

USB_OC4#

A16

RAM_ID1

D14

RAM_ID2

C14

RAM_ID3

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC4#

MPC Switch Cont rol

MPC_PWR_CTRL#

MPC_PWR_CTRL#

EV@: For Optimize SKU
IV@: For UMA SKU

+3V

R115 EV@10K/J_4
R123 *IV@10K/J_4

+3V

R642 EV@10K/J_4
R626 *IV@10K/J_4

+3V

R144 *IV@1K/J_4
R145 EV@100K/F_4

4

NV_ALE [8]

USBP0- [31]
USBP0+ [31]
USBP1- [31]
USBP1+ [31]
USBP2- [23]
USBP2+ [23]
USBP3- [24]
USBP3+ [24]
USBP4- [31]
USBP4+ [31]

USBP8- [24]
USBP8+ [24]

USBP10- [26]
USBP10+ [26]

UM77 USB port 6,7,12,13 disable.

R539 22.6/F_4

USB_OC0# [31]

R587 10K/J_4
R201 10K/J_4
R561 10K/J_4
R206 10K/J_4

Low = MPC ON
High = MPC OFF (Default)

R129 *1K/J_4

SKU_ID1

MB USB WITH 3.0 PORT
MB USB 2.0 Port

Mini DP WITH 3.0 PORT
Touch Panel
DB USB 2.0 Port

Camera

BT+WL

+3V_S5

SKU_ID0 [10]

DGPU_PW_CTRL# [10]

USB Port1 can be used on debug mode

XHCI for USBP0-3

EHCI1

USB Port9 can be used on debug mode

1001：(BIOS) Use port1 is enough

EHCI2

20110908 WLAN support S3 wake up function.

Wireless

LAN

+3V

SKU_ID1
(GPIO64)

0

0

1

1

RP1

10

9
8
7 4

10K_10P8R

SKU_ID0
(GPIO16)

+3V

1
2
3

56

VGA H/W
Signal

0

1

0

UMA+GPU

1

PCI_PIRQA#

R149 8.2K/J_4

PCI_PIRQB#

R152 8.2K/J_4

PCI_PIRQC#

R159 8.2K/J_4

PCI_PIRQD#

R155 8.2K/J_4

REQ2#_GPIO52 REQ#3
EXTTS_SNI_DRV1_PCH

dGPU_PW_CTRL#
(GPIO68)
CTL : dGPU_VRON

UMA Only

dGPU Only

Switchable
(Mux)

Optimize
(Muxless)

dGPU_PW_CTRL#
1 = GPU power is control by H/W (pure Discrete SKU)
0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize)

1

0 or 1

0

0

3

PCIE port 1 for commeral model S3 can't weak up.

PCIE_RX8-[26]
PCIE_RX8+[26]

Wireless

LAN

PCIE_TX8-[26]
PCIE_TX8+[26]

PCIE_RXN3_LAN[28]
PCIE_RXP3_LAN[28]
PCIE_TXN3_LAN[28]
PCIE_TXP3_LAN[28]

UM77/HM70 will disable 5~8 PC IE ports

CLK_PCIE_WLAN#[2 6]
CLK_PCIE_WLAN[26 ]

CLK_PCIE_WLAN_REQ#[26]

CLK_PCIE_LANN[28]
CLK_PCIE_LANP[28]

CLK_PCIE_LAN_REQ#[28]

CLK_PCIE_XDPN[3]
CLK_PCIE_XDPP[3]

CLK_REQ/Strap Pin(CLG) SMBus(EC) (CLG) SMBus(PCH) (CLG)

+3V_S5

DGPU_HOLD_RST#
MPC_PWR_CTRL#REQ1#_GPIO50

Setup
Menu

UMA

Hidden

UMA boot

CLK_BUF_BCLKN

GPU

Hidden

dGPU/SG

UMA

UMA/SG

3

GPU boot

UMA boot

UMA boot

CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M

2

1

CPT/PPT (PCI-E,SMBUS,CLK)

U38B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

+3V_S5

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

+3V

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

+3V

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

+3V_S5

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

+3V_S5

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

+3V_S5

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

+3V_S5

PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N

CLKOUT_PCIE7P

+3V_S5

PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

Panther Point_R1P0

+3V_S5

2

AB49
AB47

TP60

AA48
AA47

AB42
AB40

TP10

TP17

AK14
AK13

PCIE_CLKREQ4#
CLK_PCIE_WLAN_REQ#
PCIE_CLKREQ0#
PCIE_CLKREQ3#
CLK_PCIE_LAN_REQ#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
PCIE_CLKREQ_PEG#_R

PCIE_CLKREQ1#
PCIE_CLKREQ2#

R535 10K/J_4
R530 10K/J_4

R183 10K/J_4
R192 10K/J_4
R190 10K/J_4
R191 10K/J_4
R249 10K/J_4
R247 10K/J_4
R141 10K/J_4

J2

M1

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

E6

V40
V42

T13
V38

V37
K12

PCIE_CLKREQ0#

PCIE_CLKREQ1#

PCIE_CLKREQ2#

PCIE_CLKREQ3#

PCIE_CLKREQ4#

CLK_PCIE_REQ6#

CLK_PCIE_REQ7#

R216 10K/J_4 R659
R205 10K/J_4
R648 10K/J_4
R620 10K/J_4
R276 10K/J_4
R300 10K/J_4
R228 10K/J_4
R301 10K/J_4

+3V

R630 10K/J_4
R632 10K/J_4

CLOCK TERMINATION for FCIM
(Full Clock Integration Mode )

+3V_S5

PCI-E*

+3V_S5

2ND_MBCLK[19,34]

2ND_MBDATA[19,34]

R218 10K/J_4
R625 2.2K/J_4
R649 2.2K/J_4
R231 2.2K/J_4
R221 2.2K/J_4
R595 10K/J_4

+3V_S5

SMBALERT# / GPIO11

+3V_S5

SML0ALERT# / GPIO60

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

+3V_S5

SML1CLK / GPIO58

+3V_S5

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

+3V_S5

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLOCKS

CLKOUT_DMI_P

CLKIN_GND1_N

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_PCILOOPBACK

+3V

CLKOUTFLEX0 / GPIO64

+3V

CLKOUTFLEX1 / GPIO65

+3V

CLKOUTFLEX2 / GPIO66

+3V

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

+3V_S5

5

2
6

2N7002DW

R215 *0/J_4
R220 *0/J_4

20120712：Add 0ohm reserved for two sides of
SMBUS since they are the same power plane
(CRB no level shift)

SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R

20111122 add fo r Touch pad in terrupt pin fr om GPIO13 to GP IO11.

E12

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

R559

2.2K/J_4

Q57

43

1

SMBALERT#

H14

SMB_PCH_CLK

C9

SMB_PCH_DAT

A12

DRAMRST_CNTRL_PCH

C8

SMB_ME0_CLK

G12

SMB_ME0_DAT

C13

SML1ALERT#_R

E14

SMB_ME1_CLK

M16

SMB_ME1_DAT

M7

CL_CLK1

T11

CL_DATA1

P10

CL_RST1#

M10

PCIE_CLKREQ_PEG#_R

AB37
AB38

AV22
AU22

AM12
AM13

BF18

CLK_BUF_PCIE_3GPLLN

BE18

CLK_BUF_PCIE_3GPLLP

BJ30

CLK_BUF_BCLKN

BG30

CLK_BUF_BCLKP

G24

CLK_BUF_DREFCLKN

E24

CLK_BUF_DREFCLKP

AK7

CLK_BUF_DREFSSCLKN

AK5

CLK_BUF_DREFSSCLKP

K45

CLK_PCH_14M

H45

CLK_PCI_FB

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

SKU_ID1

F47

CLK_FLEX1

H47
K49

R592

2.2K/J_4

SMB_ME1_CLK

SMB_ME1_DAT

SMBALERT# [32]
SMB_PCH_CLK [23,26]
SMB_PCH_DAT [23,26]

DRAMRST_CNTRL_PCH [4]

TP68

CL_CLK1 [26]

CL_DATA1 [26]

CL_RST1# [26]

R308 EV@0/J_4

CLK_PCIE_VGAN [16]
CLK_PCIE_VGAP [16]

CLK_CPU_BCLKN [3]
CLK_CPU_BCLKP [3]

CLK_DPLL_SSCLKN [3]
CLK_DPLL_SSCLKP [3]

R504 9 0.9/F_4

TP8

TP59

S5 S0

SMB_PCH_DAT

SMB_PCH_CLK

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.05V_VTT

+3V

5

2
6

2N7002DW

PCH 3/6 (PCIE/USB/CLK/SMB)

PCH 3/6 (PCIE/USB/CLK/SMB)

PCH 3/6 (PCIE/USB/CLK/SMB)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

1

For LAN

For EC

XTAL25_IN

XTAL25_OUT

20120201 Change CAP from 27P to 10P.

BOARD_ID4 [10,24]

R645

4.7K/J_4
Q60

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PEG_A_CLKREQ# [16]

C564 10p/50V_4

R511
1M/J_4

C565 10p/50V_4

4.7K/J_4

43

1

ZQK

ZQK

ZQK

09

Y3
25MHz_XTAL

2 4

1 3

CLK_SDATA [13,15,32 ]

CLK_SCLK [1 3,15,32]

469

469

469

1A

1A

1A

5

4

3

2

1

CPT/PPT (GPIO,VSS_NCTF,RSVD) (CLG)

U38F

S_GPIO

R278 100/J_4

SIO_EXT_SMI#[34]

D D

C C

B B

SATA2GP/SATA3GP : When Unused as GPIO or SATA*GP - Use

8.2K-10K pull-down to ground by chklist 2.0
NOTE: The internal pull-down is disabled after PLTRST#
deasserts.
NOTE: This signal should not be pulled high when strap is
sampled.

A A

2011/09/01 add select resistor

TACH5_GPIO69

LVDS = Pull HIGH
eDP = Pull LOW

SIO_EXT_SCI#[34]
TP_INT_PCH[24]

PCH_GPIO15[8]

SKU_ID0[9]

DGPU_PW ROK[20]

PLL_ODVR_EN[8]

DGPU_VRON[20,43]

TP36

R510 1K/J_4

5

SIO_EXT_SMI#
BOARD_ID1
SIO_EXT_SCI#

TP_INT_PCH

SMIB

DGPU_PW ROK
SCLOCK_GPIO22
PCH_GPIO24
WK_GPIO27
PLL_ODVR_EN
STP_PCI#
DGPU_VRON
DMI_OVRVLTG
FDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP
CRIT_TEMP_REP#
SV_DET

R298 100K/J_4

FDI TERMINATION
VOLTAGE OVERRIDE

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

Panther Point_R1P0

20120607：follow CRB pull down

FDI_OVRVLTG SCLOCK_GPIO22

LOW - Tx, Rx terminated
to same voltage

4

+3V_S5

+3V_S5

DSW
+3V_S5

+3V

+3V_S5

+3V
+3V
+3V
+3V

+3V

+3V

+3V

+3V_S5

+3V

+3V

+3V
+3V

+3V
+3V

+3V

R290 *1K/J_4

+3V
+3V
+3V
+3V

+3V_S5

GPIO

NCTF

+3V +3V

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

PROCPWRGD

THRMTRIP#

CPU/MISC

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

A20GATE

PECI

RCIN#

INIT3_3V#

DF_TVS

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

G_SENSOR_ID

C40
B41
C41
A40

R524 1.5K/F_4

P4

SIO_A20GATE

AU16

EC_PECI_R

P5

SIO_RCIN#

AY11
AY10

PCH_THRMTRIP#

T14
AY1

AH8
AK11
AH10
AK10

P37

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

R268 10K/J_4
R250 *1K/J_4

3

TACH5_GPIO69

DGPU_PW _CTRL# [9]

BOARD_ID3

+3V

R212 *0/J_4

R225 390/J_4

High = Disable (Default)
Low = Enable

SIO_A20GATE [34]

EC_PECI [3,34]

SIO_RCIN# [34]
H_PWRGOOD [3]
PM_THRMTRIP# [3]

DF_TVS [8]

USB3.0 IC CTL

LOW = USB3.0 IC

SMIB

R623 10K/J_4

SV_SET_UP

High = Strong (Default)

TEST_SET_UP

SGPIO

S_GPIO

MFG-TEST

MFG_MODE

GPIO Pull-up/Pull-down (CLG)

20120625

：：：：

<PCH_GPIO24>Follow CRB to pull up 10K ohm

GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.

+3V_S5

+3V

R273 10K/J_4

R248 *1K/J_4

+3V

R285 1K/J_4
R284 *1K/J_4

R644 10K/J_4
R629 *1K/J_4

2

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

+3V

10

+3V_S5

PCH_GPIO24
PLL_ODVR_EN

SIO_EXT_SMI#
SIO_EXT_SCI#

STP_PCI#
SIO_A20GATE
SIO_RCIN#
CRIT_TEMP_REP#

20111017 un-stuff R5126 for DSW

DMI TERMINATION
VOLTAGE OVERRIDE

R229 *10K/J_4

+3V_S5

R280 *10K/J_4

R631 10K/J_4
R162 10K/J_4
R99 *10K/J_4 R105 10K/J_4
R520 10K/J_4
R506 *10K/J_4

WK_GPIO27

DGPU_PW ROK

Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)

DMI_OVRVLTG

high VDDR=+1.35V_SUS for DDR3L
Low VDDR =+1.5V_SUS(default)

assign to VID for VDDR control

SV_DET

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

BOARD_ID4

BOARD_ID2[9,32]
BOARD_ID4[9,24]

High Low

GDDR5 DDR3

Disable on board memory Enable on board memory

Pin8 of SYNAPTICS and ELAN are NC pin
Default is pull high

BIOS maybe will use EEPROM detection

No touch panel

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

PROJECT :

PCH 4/6 (GPIO/MISC)

PCH 4/6 (GPIO/MISC)

PCH 4/6 (GPIO/MISC)

R252 *10K/J_4
R307 10K/J_4

R509 10K/J_4
R148 10K/J_4

R647 *10K/J_4
R270 10K/J_4
R288 10K/J_4
R635 10K/J_4

R185 10K/J_4
R181 *10K/J_4

R131 *10K/J_4

R279 *200K/F_4

R274 100K/J_4

R646 *10K/J_4
R151 *10K/J_4

R522 *10K/J_4
R505 10K/J_4

Touch panel

ZQK

ZQK

ZQK

1

+3V

+3VPCU

+3V

4610

4610

4610

+3V

1A

1A

1A

5

4

3

2

1

PCH5(CLG)

20111018 change for DSW

+1.05V_VTT

3

ZQK

ZQK

ZQK

11

+5VCC_S5
+3VCC_S5

20111018 change for DSW

+5V
+3V

+3VCC_S5

+3V

4611

4611

4611

1A

1A

1A

CPT/PPT (POWER) (CLG)

POWER

+1.05V_VTT

R135 0/J_8

D D

+1.05V_VTT +1.05V_VCCAPLL_EXP

L30 *1uH/25mA_6

+1.05V_VTT

R165 0/J_8

R172 0/J_6

C C

VccDMI needs to be powered by the same 1.05 V voltage source as
the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/
VCC reference plane.

B B

A A

+1.05V_VTT

R108 0/J_6

+1.5V

R130 *0/J_6

VccCORE =1.3 A(60mils)

+1.05V_VCCCORE

C184

C156

C173
1u/6.3V_4

+1.05V_VTT

C590
*10u/6.3V_6

1u/6.3V_4

R182 0/J_6

1u/6.3V_4

VccIO =2.925 A(140mils)

C161

C187

1u/6.3V_4

R540 0/J_8

+1.05V_VTT

+VCCAFDI_VRM

VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1

1.5V (Mobile)

5

C166

1u/6.3V_4 C157

1u/6.3V_4

C172

C201

10u/6.3V_6

1u/6.3V_4

+3V_VCC_EXP+3V

C583

0.1u/10V_4

+VCCAFDI_VRM

R605 *0/J_8

R556 0/J_8

+1.1V_VCC_DMI

+1.1V VCC_DMI witdth >= 20mils.

C169

4.7u/6.3V_6

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

+1.05V_VCCDPLL_FDI

AA23
AC23
AD21
AD23

AF21

AF23
AG21
AG23
AG24
AG26
AG27
AG29

AJ23

AJ26

AJ27

AJ29
AJ31

AN19

BJ22

AN16
AN17

AN21
AN26
AN27

AP21
AP23
AP24
AP26
AT24

AN33
AN34

BH29

AP16

BG6

AP17

AU20

U38G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]

VCCIO[25]
VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

Panther Point_R1P0

U48

VCCADAC

U47

VSSADAC

CRTLVDS

AK36

VCCALVDS

AK37

VCC CORE

VCCIO

FDI

VSSALVDS

AM37

VCCTX_LVDS[1]

AM38

VCCTX_LVDS[2]

AP36

VCCTX_LVDS[3]

AP37

VCCTX_LVDS[4]

V33

VCC3_3[6]

V34

VCC3_3[7]

AT16

VCCVRM[3]

AT20

VCCDMI[1]

DMI

DFT / SPI HVCMOS

AB36

VCCCLKDMI

AG16

VCCDFTERM[1]

AG17

VCCDFTERM[2]

AJ16

VCCDFTERM[3]

AJ17

VCCDFTERM[4]

V1

VCCSPI

20120105 change power plant to +3V for power saving.

+3V_VCCME_SPI +3V_S5

Reserve +3V_S5 to VCCSPI for EC 795 co-layout

+3V

R89 * 0/J_6
R81 1/F_4

4

VccADAC =1mA(8mils)

C567

10u/6.3V_6

When Dis sku and eDP , LVDS power can short to GND

R93 0/J_6
C85

0.1u/10V_4

+VCCAFDI_VRM

C120

C131

*10u/6.3V_6

1u/6.3V_4

R568 0/J_8

C203

0.1u/10V_4

+3V_VCCME_SPI

C635
1u/6.3V_4

+3V

R638 *0/J_6
R637 0/J_6

L8 10uH/100mA_8

C566

C562

0.01u/25V_4

0.1u/10V_4

+3V+3V_VCC_GIO

VCCDMI = 42mA(10mils)

+1.1V_VCC_DMI

+VCCAFDI_VRM

L12 *10uH/100mA_8

+1.8V+VCCP_NAND

VCCSPI = 20mA(8mils)

+VCCA_DAC_1_2

+VCC_DMI_CCI +1.05 V_VTT+1.1V_VCC_DMI_CCI

L26 180ohm/1.5A

C561
10u/6.3V_6

20120104 change power plant from +3V_S5 to +3VPCU.

+1.05V_VTT

R197 0/J_4

C182

20120216 remove R168 for power plant chnge to +1.05V_VTT.

1u/6.3V_4

+1.1V VCC_DMI witdth >= 20mils.

VCCCLKDMI = 20mA(8mils)

R124 *1/F_4
R125 0/J_4

VCCPNAND = 190 mA(15mils)

20120216 remove R172 for power plant chnge to +1.05V_VTT.

VCCRTC<1mA(8mils)

+3V_SUS_CLKF33

C86

C77

1u/10V_4

4.7u/6.3V_6

+3V

+3VPCU

+1.05V_VTT

L29 *10uH/100mA_8

VCCME(+1.05V) = ??A(??mils)

+1.05V_VTT

R204 0/J_6

+1.05V_VTT

R213 0/J_6

R158 0/J_6

R157 0/J_6

+1.05V_VTT

R209 *0/J_6

+1.05V_VTT

R585 0/J_4

+3V_RTC

L27 10uH/100mA_8

+1.05V_VTT

L28 10uH/100mA_8

3

R104 *0/J_8

+1.05V_VTT

C219
*0.1u/10V_4

C176
*1u/6.3V_4

C619

0.1u/10V_4

C587

0.1u/10V_4

+1.05V_VCCA_A_DPL

C569
1u/6.3V_4

+1.05V_VCCA_B_DPL

C571
1u/6.3V_4

+VCCACLK

+VCCPDSW

PCH_VCCDSW

+3V_SUS_CLKF33

+VCCDPLL_CPY

+VCCSUS1

+VCCRTCEXT

+VCCAFDI_VRM

+1.05V_VCCA_A_DPL
+1.05V_VCCA_B_DPL

+VCCDIFFCLK
+VCCDIFFCLKN

+V1.05V_SSCVCC

+VCCSST

+V1.05M_VCCSUS

+VTT_VCCPCPU

R269 0/J_4 C151

+VCCAPLL_CPY_PCH

VccASW =1.01 A(60mils)

C204
1u/6.3V_4

C143
1u/6.3V_4

C142
1u/6.3V_4

C209
*1u/6.3V_4

+1.05V_VTT

C589
*10u/6.3V_6

+1.05V_VCCASW

1u/6.3V_4

VCCDSW3_3= 3mA

C253

0.1u/10V_4

R170 0/J_6

C180

C179

1u/6.3V_4

1u/6.3V_4

C167

C159

10u/6.3V_6

10u/6.3V_6

C200 0.1u/10 V_4

+VCCAFDI_VRM

65mA(10mils)
8mA(8mils)

VCCDIFFCLKN= 55mA(18mils)
VCCSSC= 95mA(10mils)

C190 0.1u/10 V_4

1mA(8mils)

C618

C616

0.1u/10V_4

4.7u/6.3V_6

C586

C585

1u/6.3V_4

0.1u/10V_4

+

C563
220u/2.5V_3528

+

C574
220u/2.5V_3528

CPT/PPT (POWER) (CLG)

POWER

U38J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23
W24
W26
W29
W31
W33

N16

Y49

BD47
BF47

AF17
AF33
AF34
AG34

AG33

V16

T17
V19

BJ8

A22

2

Panther Point_R1P0

Clock and Miscellaneous

VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA
VCCADPLLB

VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1]
DCPSUS[2]

V_PROC_IO

CPURTC

VCCRTC

+5V_S5 +5VCC_S5 +3VCC_S5

SLP_SUS#[7,34]

VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]

VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]

VCC3_3[1]
VCC3_3[8]

PCI/GPIO/LPCMISC

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]
VCCIO[13]

VCCIO[6]

VCCAPLLSATA

SATA USB

VCCVRM[1]

VCCIO[2]
VCCIO[3]
VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

HDA

R521 *0/J_4

1

R515

C568

100K/J_4

*0.33u/10V_6

20111018 ADD DSW Cricuit
20111030 modify cuirucit.

+1.05V_VCCIO

N26
P26
P28
T27
T29

T23

+3V_VCCPUSB

T24
V23
V24
P24

+3V_VCCAUBG

T26

+VCCAUPLL

M26

+5V_PCH_VCC5REFSUS

AN23

+VCCA_USBSUS

AN24

+3V_VCCPSUS

P34

+5V_PCH_VCC5REF

N20
N22
P20

+3V_VCCPSUS

P22

AA16
W16

+3V_VCCPCORE

T34

C130

0.1u/10V_4

AJ2

AF13

AH13

+1.05V_VCC_IO

AH14

AF14
AK1

+V1.1LAN_VCCAPLL

VCCVRM= 114mA(15mils)

AF11

+VCCAFDI_VRM

AC16
AC17
AD17

T21

V21

T19

P32

+V3.3A_1.5A_HDA_IO

C139
*1u/6.3V_4

3

Q51
AO3413

2

R514
0/J_6

+1.05V_VTT

R178 0/J_6

1u/6.3V_4

R193 0/J_6

C186
*1u/6.3V_4

+3V

L31 *10uH/100mA_8
C638

*10u/6.3V_6

+1.05V_VTT

C202
1u/6.3V_4

R146 0/J_6

R179 0/J_4

C160

0.1u/10V_4

+3V_S5

C570
*0.33u/10V_6

6

215

Q55
2N7002DW

20111117 change mose footprint to dual type.

4 3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet o f

Monday, January 07, 2013

Date: Sheet o f

Monday, January 07, 2013

Date: Sheet o f

Monday, January 07, 2013

VCCSUS3_3 = 119mA(15mils)

+3VCC_S5

R537 0/J_6

C582

0.1u/10V_4

R545 0/J_6

C181

0.1u/10V_4

C155

0.1u/10V_4

C105
1u/6.3V_4

C594
1u/10V_4

C188

0.1u/10V_4

C637

0.1u/10V_4

C224
1u/10V_4

+1.05V_VTT

20111018 change for DSW

+1.05V_VTT

VCC5REFSUS=1mA

R532 10/F_4

D24 RB500V-40

V5REF= 1mA

R117 10/F_4

D6 RB500 V-40

R548 0/J_6

VCCSUS3_3 = 119mA(15mils)

R202 0/J_6

VCCPCORE = 28mA(10mils)

+3V

R267 0/J_6

??mA(??mils)

+1.05V_VTT

VCCME = 1.01A(60mils)

VCCSUSHDA= 10mA(8mils)

+3V_S5

R531 *0/J_4

1

R518
100K/J_4

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PCH 5/6 (POWER)

PCH 5/6 (POWER)

PCH 5/6 (POWER)

1

Q54
AO3413

R546
0/J_6

5

4

3

2

1

PCH6(CLG)

ZQK

ZQK

ZQK

12

4612

4612

4612

1A

1A

1A

IBEX PEAK-M (GND) (CLG)

U38H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

D D

C C

B B

A A

5

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

Panther Point_R1P0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

4

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

U38I

AY4
AY42
AY46

AY8

B11
B15
B19
B23
B27
B31
B35
B39

B7

F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38

BB4
BB46
BC14
BC18

BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46

BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28

BD3
BF30
BF38
BF40

BF8

BG17
BG21
BG33
BG44

BG8

BH11
BH15
BH17
BH19

H10

BH27
BH31
BH33
BH35
BH39
BH43

BH7

D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42

D8

E18

E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34

F3

Panther Point_R1P0

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

H46

VSS[259]

K18

VSS[260]

K26

VSS[261]

K39

VSS[262]

K46

VSS[263]

K7

VSS[264]

L18

VSS[265]

L2

VSS[266]

L20

VSS[267]

L26

VSS[268]

L28

VSS[269]

L36

VSS[270]

L48

VSS[271]

M12

VSS[272]

P16

VSS[273]

M18

VSS[274]

M22

VSS[275]

M24

VSS[276]

M30

VSS[277]

M32

VSS[278]

M34

VSS[279]

M38

VSS[280]

M4

VSS[281]

M42

VSS[282]

M46

VSS[283]

M8

VSS[284]

N18

VSS[285]

P30

VSS[286]

N47

VSS[287]

P11

VSS[288]

P18

VSS[289]

T33

VSS[290]

P40

VSS[291]

P43

VSS[292]

P47

VSS[293]

P7

VSS[294]

R2

VSS[295]

R48

VSS[296]

T12

VSS[297]

T31

VSS[298]

T37

VSS[299]

T4

VSS[300]

W34

VSS[301]

T46

VSS[302]

T47

VSS[303]

T8

VSS[304]

V11

VSS[305]

V17

VSS[306]

V26

VSS[307]

V27

VSS[308]

V29

VSS[309]

V31

VSS[310]

V36

VSS[311]

V39

VSS[312]

V43

VSS[313]

V7

VSS[314]

W17

VSS[315]

W19

VSS[316]

W2

VSS[317]

W27

VSS[318]

W48

VSS[319]

Y12

VSS[320]

Y38

VSS[321]

Y4

VSS[322]

Y42

VSS[323]

Y46

VSS[324]

Y8

VSS[325]

BG29

VSS[328]

N24

VSS[329]

AJ3

VSS[330]

AD47

VSS[331]

B43

VSS[333]

BE10

VSS[334]

BG41

VSS[335]

G14

VSS[337]

H16

VSS[338]

T36

VSS[340]

BG22

VSS[342]

BG24

VSS[343]

C22

VSS[344]

AP13

VSS[345]

M14

VSS[346]

AP3

VSS[347]

AP1

VSS[348]

BE16

VSS[349]

BC16

VSS[350]

BG28

VSS[351]

BJ28

VSS[352]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

3

2

Monday, January 07, 2013

PROJECT :

PCH 6/6 (GND)

PCH 6/6 (GND)

PCH 6/6 (GND)

1

DDR ON BOARD RAM (DDR)

Checklist 2.0:
M3 has to be no stuff on Chief River

SMDDR_VREF_DQ0_M3[6,14]

A A

B B

M_A_CLK0

M_A_CLK0#

C C

Place these Caps near Memory Down

+1.5VSUS

C420
1u/6.3V_4

+1.5VSUS

C802
1u/6.3V_4

+1.5VSUS

C431

D D

1u/6.3V_4

+1.5VSUS

C671
1u/6.3V_4

1

R694 *M3@0/J_6

M_A_A[15:0][4,14]

SO-DIMMB SPD Address is 0XA4
SO-DIMMB TS Address is 0X34

DDR3_DRAMRST#[4,14,15]

C485

1.6P/50V_4

R265

R266

30/F_4

30/F_4

C244

0.1u/10V_4

C745
1u/6.3V_4

C684
1u/6.3V_4

C290
1u/6.3V_4

C274
1u/6.3V_4

1

C278
1u/6.3V_4

C768
1u/6.3V_4

C789
1u/6.3V_4

C417
1u/6.3V_4

C741
1u/6.3V_4

C661
1u/6.3V_4

C673
1u/6.3V_4

C688
1u/6.3V_4

M_A_BS#0[4,14]
M_A_BS#1[4,14]
M_A_BS#2[4,14]

M_A_CLK0[4]

M_A_CLK0#[4]

M_A_CKE0[4]

M_A_ODT0[ 4]

M_A_CS#0[4]
M_A_RAS#[4,14]
M_A_CAS#[4,14]

M_A_WE#[4,14]

Should be 240
Ohms +-1%

M_A_DQSP[7:0][4,14]

M_A_DQSN[7:0][4,14]

M_A_DQ[63:0][4,14]

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQSP0
M_A_DQSP1

M_A_DQSN0
M_A_DQSN1

R255
240/F_4

1 2

C746

C470

1u/6.3V_4

1u/6.3V_4

C251

C398

1u/6.3V_4

1u/6.3V_4

C293

C783

1u/6.3V_4

1u/6.3V_4

C682

C771

1u/6.3V_4

1u/6.3V_4

C653
1u/6.3V_4

C689
1u/6.3V_4

C252
1u/6.3V_4

C250
1u/6.3V_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

2

U19

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C421
1u/6.3V_4

C436
1u/6.3V_4

C473
1u/6.3V_4

C432
1u/6.3V_4

2

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

+1.5VSUS

+1.5VSUS

+1.5VSUS

+1.5VSUS

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

C793
1u/6.3V_4

C739
1u/6.3V_4

C752
1u/6.3V_4

C767
1u/6.3V_4

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

BYTE0_0-7
BYTE1_8-15

M_A_DQ6
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ0

M_A_DQ8
M_A_DQ15
M_A_DQ14
M_A_DQ11
M_A_DQ13
M_A_DQ10
M_A_DQ9
M_A_DQ12

+1.5VSUS

+1.5VSUS

C633

C687

1u/6.3V_4

1u/6.3V_4

C686

C665

1u/6.3V_4

1u/6.3V_4

C285

C675

1u/6.3V_4

1u/6.3V_4

C287

C728

1u/6.3V_4

1u/6.3V_4

Should be 240
Ohms +-1%

C809
1u/6.3V_4

C642
1u/6.3V_4

C488
1u/6.3V_4

C639
1u/6.3V_4

3

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

DDR3_DRAMRST#

M_A_ZQ2M_A_ZQ1

R323
240/F_4

1 2

C785
1u/6.3V_4

C459
1u/6.3V_4

C685
1u/6.3V_4

C284
1u/6.3V_4

3

1u/6.3V_4

C772
1u/6.3V_4

C649
1u/6.3V_4

C632
1u/6.3V_4

M8

M7

M2
M3

H1
N3

P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

N8

J7
K7
K9

K1
L2
J3
K3
L3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

U21

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C644
1u/6.3V_4

C315
1u/6.3V_4

C256
1u/6.3V_4

C646
1u/6.3V_4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

C667
1u/6.3V_4

C674
1u/6.3V_4

C294
1u/6.3V_4

C258
1u/6.3V_4

BYTE2_16-23
BYTE3_24-31

E3

M_A_DQ19

F7

M_A_DQ22

F2

M_A_DQ18

F8

M_A_DQ16

H3

M_A_DQ21

H8

M_A_DQ20

G2

M_A_DQ23

H7

M_A_DQ17

D7

M_A_DQ28

C3

M_A_DQ25

C8

M_A_DQ30

C2

M_A_DQ27

A7

M_A_DQ24

A2

M_A_DQ26

B8

M_A_DQ29

A3

M_A_DQ31

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

C763
10u/6.3V_6

+1.5VSUS

C764
10u/6.3V_6

+1.5VSUS

C780
10u/6.3V_6

+1.5VSUS

C681
10u/6.3V_6

4

+1.5VSUS

+1.5VSUS

4

C663
10u/6.3V_6

C314
10u/6.3V_6

C786
10u/6.3V_6

C736
10u/6.3V_6

Should be 240
Ohms +-1%

C283
10u/6.3V_6

C289
10u/6.3V_6

C735
10u/6.3V_6

C723
10u/6.3V_6

C304
10u/6.3V_6

C690
10u/6.3V_6

C691
10u/6.3V_6

C280
10u/6.3V_6

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

DDR3_DRAMRST#

M_A_ZQ3

R697
240/F_4

1 2

C801
10u/6.3V_6

C489
10u/6.3V_6

C643
10u/6.3V_6

C483
10u/6.3V_6

5

U23

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

RAM _DDR3

+

C742

330u/2V_7343

C781

+

*150u/6.3V_3528

5

100-BALL
SDRAM DDR3

BYTE4_32-39
BYTE5_40-47

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

+SMDDR_VREF_DIMM

C602

0.1u/10V_4

+1.5VSUS

R226
1K/F_4

+SMDDR_VREF_DIMM

R232
1K/F_4

WP =1 : WRITE DISABLE

C725

0.1u/10V_4

C245

0.1u/10V_4

CLK_SCLK[9,15,32]
CLK_SDATA[9,15,32]

+3V

M_A_DQ42
M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ45
M_A_DQ40
M_A_DQ43
M_A_DQ47

M_A_DQ36
M_A_DQ38
M_A_DQ35
M_A_DQ37
M_A_DQ32
M_A_DQ39
M_A_DQ33
M_A_DQ34

+1.5VSUS

+1.5VSUS

C703

0.1u/10V_4

+SMDDR_VREF_DIMM

R227 *0/J_6C418

CLK_SCLK
CLK_SDATA

R321 *0/J_4

6

Should be 240
Ohms +-1%

C717

0.1u/10V_4

+SMDDR_VREF

R322
*0/J_4

6

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

DDR3_DRAMRST#

1 2

C493

0.1u/10V_4

U45

6

SCL

5

SDA

7

WP

*M24C02-WMN6TP

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP7
M_A_DQSP6

M_A_DQSN7
M_A_DQSN6

M_A_ZQ4

R724
240/F_4

VCC
GND

0.1u/10V_4

A0
A1
A2

U26

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

C481

0.1u/10V_4

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

SMDDR_VREF_DQ0

C714

0.1u/10V_4

CRB Add

DEEPS3_EC[4,14,15]

SPD address= A0 hex (for MD devices)

+3V

R666 *1K/F_4

MD0_SA0
MD0_SA1

+3V

R662 *1K/F_4

C286
*0.1u/10V_4

1
2
3

8
4

7

BYTE6_48-55
BYTE7_56-63

E3

M_A_DQ60

F7

M_A_DQ61

F2

M_A_DQ63

F8

M_A_DQ57

H3

M_A_DQ62

H8

M_A_DQ56

G2

M_A_DQ58

H7

M_A_DQ59

D7

M_A_DQ53

C3

M_A_DQ55

C8

M_A_DQ52

C2

M_A_DQ50

A7

M_A_DQ49

A2

M_A_DQ54

B8

M_A_DQ48

A3

M_A_DQ51

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C715

0.1u/10V_4

1

Q21

2

*AP2302GN

MD0_SA0
MD0_SA1

7

8

+1.5VSUS

+1.5VSUS

SMDDR_VREF_DQ0+SMDDR_VREF_DIMM

C711

0.1u/10V_4C720

change to 1K/F_4

3

R668 1K/F_4
R664 1K/F_4

C710

C713

0.1u/10V_4

0.1u/10V_4

+1.5VSUS

R224
1K/F_4

SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M3

R230
1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

C480

C712

0.1u/10V_4

0.1u/10V_4

R214 *0/J_6

C223

0.1u/10V_4

CHA0

SA0SA1

00
CHA1
CHB0

1100

CHB1

1 1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZQK

ZQK

ZQK

8

+SMDDR_VREF

13

4613

4613

4613

1A

1A

1A

DDR ON BOARD RAM (DDR)

Checklist 2.0:
M3 has to be no stuff on Chie f River

SMDDR_VREF_DQ0_M3[6,13]

A A

B B

M_A_CLK1

M_A_CLK1#

C C

1

R246 *M3@0/J_6

M_A_A[15:0][4,13]

SO-DIMMB SPD Ad dress is 0XA4
SO-DIMMB TS Add ress is 0X34

M_A_BS#0[4,13]
M_A_BS#1[4,13]
M_A_BS#2[4,13]

M_A_CLK1[4 ]

M_A_CLK1#[4]

M_A_CKE1[4]

M_A_ODT1[4]
M_A_CS#1[4 ]
M_A_RAS#[4,13]
M_A_CAS#[4,13]

M_A_WE#[4,13]

DDR3_DRAMRST#[4,13,15]

Should be 240
Ohms +-1%

C484

1.6P/50V_4

R254

R253

30/F_4

30/F_4

C243

0.1u/10V_4

M_A_DQSP[7:0][4,13]

M_A_DQSN[7:0][4,13]

M_A_DQ[63:0][4,13]

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

R671
240/F_4

1 2

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQSP0
M_A_DQSP1

M_A_DQSN0
M_A_DQSN1

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

2

U43

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

RAM _DDR3

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE0_0-7
BYTE1_8-15

E3

M_A_DQ3

F7

M_A_DQ6

F2

M_A_DQ0

F8

M_A_DQ2

H3

M_A_DQ5

H8

M_A_DQ4

G2

M_A_DQ1

H7

M_A_DQ7

D7

M_A_DQ15

C3

M_A_DQ8

C8

M_A_DQ11

C2

M_A_DQ14

A7

M_A_DQ12

A2

M_A_DQ9

B8

M_A_DQ10

A3

M_A_DQ13

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

3

SMDDR_VREF_DQ0

DDR3_DRAMRST#

M_A_ZQ6M_A_ZQ5

1 2

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP2
M_A_DQSP3

M_A_DQSN2
M_A_DQSN3

R688
240/F_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

U46

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

4

BYTE2_16-23
BYTE3_24-31

E3

M_A_DQ22

F7

M_A_DQ19

F2

M_A_DQ17

F8

M_A_DQ18

H3

M_A_DQ20

H8

M_A_DQ23

G2

M_A_DQ16

H7

M_A_DQ21

D7

M_A_DQ25

C3

M_A_DQ28

C8

M_A_DQ27

C2

M_A_DQ30

A7

M_A_DQ31

A2

M_A_DQ29

B8

M_A_DQ26

A3

M_A_DQ24

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

5

+SMDDR_VREF_DIMM
SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP5
M_A_DQSP4

M_A_DQSN5
M_A_DQSN4

DDR3_DRAMRST#

M_A_ZQ7

R718
240/F_4

1 2

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

U48

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

BYTE4_32-39
BYTE5_40-47

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

+SMDDR_VREF_DIMM

C716

0.1u/10V_4

+1.5VSUS

R572
1K/F_4

+SMDDR_VREF_DIMM

R573
1K/F_4

M_A_DQ44
M_A_DQ46
M_A_DQ41
M_A_DQ42
M_A_DQ47
M_A_DQ45
M_A_DQ40
M_A_DQ43

M_A_DQ38
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ39
M_A_DQ33
M_A_DQ34
M_A_DQ32

C693

0.1u/10V_4

+SMDDR_VREF_DIMM

C603

0.1u/10V_4

6

+1.5VSUS

+1.5VSUS

Should be 240
Ohms +-1%

C721

0.1u/10V_4

+SMDDR_VREF

R571 *0/J_6

C726

0.1u/10V_4

+SMDDR_VREF_DIMM

SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK1
M_A_CLK1#
M_A_CKE1

M_A_ODT1
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP7
M_A_DQSP6

M_A_DQSN7
M_A_DQSN6

DDR3_DRAMRST#

M_A_ZQ8

R765
240/F_4

1 2

C507

0.1u/10V_4

C680

0.1u/10V_4

CRB Add

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

U49

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

RAM _DDR3

C702

0.1u/10V_4

DEEPS3_EC[4,13,15]

7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

SMDDR_VREF_DQ0

C249

0.1u/10V_4

1

2

BYTE6_48-55
BYTE7_56-63

E3

M_A_DQ61

F7

M_A_DQ63

F2

M_A_DQ57

F8

M_A_DQ60

H3

M_A_DQ59

H8

M_A_DQ58

G2

M_A_DQ56

H7

M_A_DQ62

D7

M_A_DQ55

C3

M_A_DQ53

C8

M_A_DQ50

C2

M_A_DQ52

A7

M_A_DQ54

A2

M_A_DQ48

B8

M_A_DQ51

A3

M_A_DQ49

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C506

0.1u/10V_4

change to 1K/F_4

3

Q56
*AP2302GN

+1.5VSUS

+1.5VSUS

C733

0.1u/10V_4

+1.5VSUS

8

14

SMDDR_VREF_DQ0+SMDDR_VREF_DIMM

C719

0.1u/10V_4

C492

0.1u/10V_4

+SMDDR_VREF

R562
1K/F_4

R563
1K/F_4

C724

C254

0.1u/10V_4

0.1u/10V_4

SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M3

C600

0.1u/10V_4

R565 *0/J_6

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

1

2

3

4

5

6

7

Monday, January 07, 2013

PROJECT :

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

DDR3 MEMORY DOWN X 16

ZQK

ZQK

ZQK

8

1A

1A

1A

4614

4614

4614

5

DDR3 DIMM-A (DDR)

M_B_A[15:0][4]

D D

M_B_BS#0[4]
M_B_BS#1[4]
M_B_BS#2[4]
M_B_CS#0[4]
M_B_CS#1[4]
M_B_CLK0[4]
M_B_CLK0#[4]
M_B_CLK1[4]
M_B_CLK1#[4]
M_B_CKE0[4]
M_B_CKE1[4]
M_B_CAS#[4]
M_B_RAS#[4]

C C

B B

M_B_WE#[4]

CLK_SCLK[9,13,32]

CLK_SDATA[9,13,32]

M_B_ODT0[4]
M_B_ODT1[4]

M_B_DQSP[7:0][4]

M_B_DQSN[7:0][4]

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1

CLK_SCLK
CLK_SDATA

M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7

Place these Caps near SO_DIMM-A

+1.5VSUS

C740
10u/6.3V_6

A A

+3V

C478

2.2u/6.3V_6

C709
10u/6.3V_6

C476

0.1u/16V_4

5

C747
10u/6.3V_6

+0.75V_DDR_VTT

C495
1u/6.3V_4

C679

0.1u/16V_4

C511
1u/6.3V_4

C692

0.1u/16V_4

C704

0.1u/16V_4

C513
1u/6.3V_4

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

4

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDR3-DIMM1_H=5.2_RVS

C718

0.1u/16V_4

C512
1u/6.3V_4

PC2100 DDR3 SDRAM SO-DIMM

C494
*10u/6.3V_6

4

(204P)

C729

0.1u/16V_4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

C761

+

*150u/6.3V_3528

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ51
M_B_DQ48
M_B_DQ49
M_B_DQ55
M_B_DQ50
M_B_DQ56
M_B_DQ60
M_B_DQ62
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ59
M_B_DQ63

R400
*10K/J_4

DIMM1_SA0 DIMM1_SA1

R401
10K/J_4

3

M_B_DQ[63:0] [4]

SMDDR_VREF_DQ1_M3[6]

+SMDDR_VREF_DIMM_A

+SMDDR_VREF

Intel M1 solution

SMDDR_VREF_DQ1_M3

CRB Add

+3V

R406
10K/J_4

R409
*10K/J_4

3

2

+1.5VSUS

2.48A

+3V

DDR3_DRAMRST#[4,13,14]

R281 *M3@0/J_6

+1.5VSUS +1.5VSUS

R277 *0/J_6

Q22

2

*AP2302GN

3

1

DEEPS3_EC[4,13,14]

TP80

+SMDDR_VREF_DQ1

20110817 change to 1K/F_4

R296
1K/F_4

+SMDDR_VREF_DQ1

R286
1K/F_4

C255
470P/50V_4

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=5.2_RVS

R355 *0/J_6

C257

0.1u/16V_4

PC2100 DDR3 SDRAM SO-DIMM

C270

2.2u/6.3V_6

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

GND
GND

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

205
206

20110817 change to 1K/F_4

R353
1K/F_4

R350
1K/F_4

1

+SMDDR_VREF_DIMM_A

C750
470P/50V_4

C749

0.1u/16V_4

15

+0.75V_DDR_VTT

C373

2.2u/6.3V_6

20121203：：：：Add 39pF for ESD

SA0SA1

+1.5VSUS +0.75V_DDR_VTT

CHA0
CHA1
CHB0
CHB1

1
1 1

00
10

C848

39P/50V_4

C849

39P/50V_4

0

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR3 DIMMA-RSV H=5.2

DDR3 DIMMA-RSV H=5.2

DDR3 DIMMA-RSV H=5.2

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

2

Monday, January 07, 2013

PROJECT :

ZQK

ZQK

ZQK

1A

1A

1A

4615

4615

1

4615

1

+1.05V_GFX

To be placed no further from the GPU
than bewteen BGA and Power supply

place near balls

place under BGA

A A

+1.05V_GFX

To be placed no further from the GPU
than bewteen BGA and Power supply

place near balls

place under BGA

1000mA

C207 EV@22u/6.3V_8
C208 EV@22u/6.3V_8
C171 EV@10u/6.3V_6
C183 EV@10u/6.3V_6
C158 EV@4.7u/6.3V_6

C154 EV@1u/6.3V_4

C226 EV@22u/6.3V_8
C225 EV@22u/6.3V_8
C246 EV@10u/6.3V_6
C247 EV@10u/6.3V_6
C178 EV@4.7u/6.3V_6
C149 EV@1u/6.3V_4
C148 EV@1u/6.3V_4

2500mA

1001：&(>##%'$-<+,!!L
<+,："#B< ##%'$1 

B B

：&(>##%'$I-<+,!!L


PLACE NEAR TO GPU BALLS

PLACE UNDER GPU BALLS

C C

：&(>##%'$-<+,!!L
<+,："#B< ##%'$1 

+3V_GFX

L8/M8/K8/J8 0.4MM = 16mils

PLACE NEAR TO GPU L8/M8

+3V_GFX

C144 EV@4.7u/6.3V_6

C152 *EV@1u/6.3V_4

C153 EV@0.1u/10V_4

D D

C59 EV@0.1u/10V_4
C65 *EV@0.1u/10V_4

PLACE UNDAER GPU BALLS L8/M8

1

2

Layout Notes:
+1.05_GFX trace width = 250mils

U35A

AG19

PEX_IOVDD_1

AG21

2

AG22
AG24

AH21
AH25

AG13
AG15
AG16
AG18
AG25

AH15
AH18
AH26
AH27
AJ27
AK27
AL27

AM28

AN28

AC6

AJ28

AL11

AJ4
AJ5

C15
D19
D20
D23
D26
H31

V32

T8

J8

K8

L8

M8

PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13

VDD33_1
VDD33_2
VDD33_3
VDD33_4

EV@N14P_GV2

M,B'8N

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS

3

PEX_RX0

PEX_RX0_N

PEX_RX1

PEX_RX1_N

PEX_RX2

PEX_RX2_N

PEX_RX3

PEX_RX3_N

PEX_RX4

PEX_RX4_N

PEX_RX5

PEX_RX5_N

PEX_RX6

PEX_RX6_N

PEX_RX7

PEX_RX7_N

PEX_RX8

PEX_RX8_N

PEX_RX9

PEX_RX9_N

PEX_RX10

PEX_RX10_N

PEX_RX11

PEX_RX11_N

PEX_RX12

PEX_RX12_N

PEX_RX13

PEX_RX13_N

PEX_RX14

PEX_RX14_N

PEX_RX15

PEX_RX15_N

PEX_TX0

PEX_TX0_N

PEX_TX1

PEX_TX1_N

PEX_TX2

PEX_TX2_N

PEX_TX3

PEX_TX3_N

PEX_TX4

PEX_TX4_N

PEX_TX5

PEX_TX5_N

PEX_TX6

PEX_TX6_N

PEX_TX7

PEX_TX7_N

PEX_TX8

PEX_TX8_N

PEX_TX9

PEX_TX9_N

PEX_TX10

PEX_TX10_N

PEX_TX11

PEX_TX11_N

PEX_TX12

PEX_TX12_N

PEX_TX13

PEX_TX13_N

PEX_TX14

PEX_TX14_N

PEX_TX15

PEX_TX15_N

PEX_REFCLK

PEX_REFCLK_N

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT_N

PEX_WAKE

PEX_RST_N

PEX_CLKREQ_N

PEX_TERMP

TESTMODE

PEX_PLLVDD

PEX_PLL_HVDD

PEX_SVDD_3V3

3.3V_AUX_NC

VDD_SENSE

GND_SENSE

3

AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27

AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25

AL13
AK13

AJ26
AK26

AJ11
AJ12

AK12

AP29

AK11

AG26
AH12

AG12

P8

L4

L5

PEG_TX8_C
PEG_TX#8_C
PEG_TX9_C
PEG_TX#9_C
PEG_TX10_C
PEG_TX#10_C
PEG_TX11_C
PEG_TX#11_C
PEG_TX12_C
PEG_TX#12_C
PEG_TX13_C
PEG_TX#13_C
PEG_TX14_C
PEG_TX#14_C
PEG_TX15_C
PEG_TX#15_C

PEG_RX8_C
PEG_RX#8_C
PEG_RX9_C
PEG_RX#9_C
PEG_RX10_C
PEG_RX#10_C
PEG_RX11_C
PEG_RX#11_C
PEG_RX12_C
PEG_RX#12_C
PEG_RX13_C
PEG_RX#13_C
PEG_RX14_C
PEG_RX#14_C
PEG_RX15_C
PEG_RX#15_C

PEX_TSTCLK
PEX_TSTCLK#

PEGX_WAKE
PEGX_RST#

PEX_CLKREQ#

PEX_TERMP
TESTMODE

4

C629 EV@0.22u/10V_4
C628 EV@0.22u/10V_4
C611 EV@0.22u/10V_4
C612 EV@0.22u/10V_4
C627 EV@0.22u/10V_4C147 EV@1u/6.3V_4
C626 EV@0.22u/10V_4
C610 EV@0.22u/10V_4
C609 EV@0.22u/10V_4
C624 EV@0.22u/10V_4
C625 EV@0.22u/10V_4
C608 EV@0.22u/10V_4
C607 EV@0.22u/10V_4
C623 EV@0.22u/10V_4
C622 EV@0.22u/10V_4
C605 EV@0.22u/10V_4
C606 EV@0.22u/10V_4

C197 EV@0.22u/10V_4
C198 EV@0.22u/10V_4
C216 EV@0.22u/10V_4
C217 EV@0.22u/10V_4
C214 EV@0.22u/10V_4
C215 EV@0.22u/10V_4
C195 EV@0.22u/10V_4
C196 EV@0.22u/10V_4
C213 EV@0.22u/10V_4
C212 EV@0.22u/10V_4
C194 EV@0.22u/10V_4
C193 EV@0.22u/10V_4
C192 EV@0.22u/10V_4
C191 EV@0.22u/10V_4
C211 EV@0.22u/10V_4
C210 EV@0.22u/10V_4

R186 *EV@200/F_4

0815 change R53 to 1% tolerance

R590 EV@2.49K/F_4
R195

PEX_PLLVDD

C185 EV@4.7u/6.3V_6
C145 EV@1u/6.3V_4
C163 EV@0.1u/10V_4

C72 EV@0.1u/10V_4
C89 EV@4.7u/6.3V_6
C99 EV@4.7u/6.3V_6

4

EV@10K/F_4

GPU_VCCP_SENSE [43]
GPU_VSSP_SENSE [43]

TP26

Place near BGA

PLACE UNDAER BALLS

5

PEG_TX8 [2]
PEG_TX#8 [2]
PEG_TX9 [2]
PEG_TX#9 [2]
PEG_TX10 [2]
PEG_TX#10 [2]
PEG_TX11 [2]
PEG_TX#11 [2]
PEG_TX12 [2]
PEG_TX#12 [2]
PEG_TX13 [2]
PEG_TX#13 [2]
PEG_TX14 [2]
PEG_TX#14 [2]
PEG_TX15 [2]
PEG_TX#15 [2]

PEG_RX8 [2]
PEG_RX#8 [2]
PEG_RX9 [2]
PEG_RX#9 [2]
PEG_RX10 [2]
PEG_RX#10 [2]
PEG_RX11 [2]
PEG_RX#11 [2]
PEG_RX12 [2]
PEG_RX#12 [2]
PEG_RX13 [2]
PEG_RX#13 [2]
PEG_RX14 [2]
PEG_RX#14 [2]
PEG_RX15 [2]
PEG_RX#15 [2]

CLK_PCIE_VGAP [9]
CLK_PCIE_VGAN [9]

R207 EV@0_6

+3V_GFX

PLACE NEAR BALLS

5

6

Layout Notes:
Place decoupling CAPs close to GPU

PLTRST#[9,26,27,28,34]

DGPU_HOLD_RST#[9]

20120813: EC control PEGX_RST#

0817 RSVD R46 and C49 for GV2 co-layout sDDR3

PEX_PLLVDD : 0.3MM = 12mils (150mA)

+1.05V_GFX

C199
*EV@1u/6.3V_4

AH12/AG12 need 210mA of +3V_GFX

8mils width
(0.2MM)

6

PEX_CLKREQ#

7

+3V_GFX+3V_GFX

R580
EV@10K/F_4

2
1

U16

EV@MC74VHC1G08DFT2G

2

1

+3V

3 5

0816 follow Z09 to isolate CLK_REQ#

3

Q58
EV@2N7002K

C218

EV@0.1u/10V_4

4

PEGX_RST#

R199
EV@100K/F_4

8

PEG_A_CLKREQ# [9]

PU at page 9

PEGX_RST# [19]

PEX_RST timing

I/O 3.3V

PEX_RST

Trise >= 1uS Tfail <=500nS

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DGPU 1/5 (PEG)

DGPU 1/5 (PEG)

DGPU 1/5 (PEG)

7

PROJECT :

ZQK

ZQK

ZQK

16 46Monday, January 07, 2013

16 46Monday, January 07, 2013

16 46Monday, January 07, 2013

8

16

1A

1A

1A

1

2

3

4

5

6

7

8

U35B

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FB_VREF_NC

FBA_WCK01
FBA_WCK23
FBA_WCK45
FBA_WCK67

FBA_WCKB01
FBA_WCKB23
FBA_WCKB45
FBA_WCKB67

RSVD

GND_PROBE

L28

VMA_DQ0

M29

VMA_DQ1

L29

VMA_DQ2

M28

VMA_DQ3

N31

VMA_DQ4

P29

VMA_DQ5

R29

VMA_DQ6

P28

VMA_DQ7

J28

VMA_DQ8

H29

VMA_DQ9

J29

VMA_DQ10

H28

VMA_DQ11

G29

VMA_DQ12

E31

VMA_DQ13

E32

VMA_DQ14

F30

VMA_DQ15

C34

VMA_DQ16

D32

VMA_DQ17

B33

VMA_DQ18

C33

VMA_DQ19

F33

VMA_DQ20

F32

VMA_DQ21

H33

VMA_DQ22

H32

VMA_DQ23

P34

VMA_DQ24

P32

VMA_DQ25

P31

VMA_DQ26

P33

VMA_DQ27

L31

VMA_DQ28

L34

VMA_DQ29

L32

VMA_DQ30

L33

VMA_DQ31

AG28

VMA_DQ32

AF29

VMA_DQ33

AG29

VMA_DQ34

AF28

VMA_DQ35

AD30

VMA_DQ36

AD29

VMA_DQ37

AC29

VMA_DQ38

AD28

VMA_DQ39

AJ29

VMA_DQ40

AK29

VMA_DQ41

AJ30

VMA_DQ42

AK28

VMA_DQ43

AM29

VMA_DQ44

AM31

VMA_DQ45

AN29

VMA_DQ46

AM30

VMA_DQ47

AN31

VMA_DQ48

AN32

VMA_DQ49

AP30

VMA_DQ50

AP32

VMA_DQ51

AM33

VMA_DQ52

AL31

VMA_DQ53

AK33

VMA_DQ54

AK32

VMA_DQ55

AD34

VMA_DQ56

AD32

VMA_DQ57

AC30

VMA_DQ58

AD33

VMA_DQ59

AF31

VMA_DQ60

AG34

VMA_DQ61

AG32

VMA_DQ62

AG33

VMA_DQ63

R30

VMA_CLK0

R31

VMA_CLK0#

AB31

VMA_CLK1

AC31

VMA_CLK1#

15mils width

R28

FBA_DEBUG

AC28

FBA_DEBUG1

H26
R32

AC32
K31

L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

E1
K27
U27
F1
F2
J27
H27
H25

TP5

FB_CLAMP
+FB_PLLAVDD

+FB_PLLAVDD
FBVDDQ_SENSE_NC
FB_GND_SENSE_NC

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

Layout Notes: PLACE CLOSE TO GPU BALLS

+1.5V_GFX

U30

FBA_CMD0 (FBA_CMD25)

T31

FBA_CMD1 (FBA_CMD23)

U29

FBA_CMD2

R34

FBA_CMD3 (FBA_CMD0)

R33

FBA_CMD4 (FBA_CMD10)

U32

FBA_CMD5 (FBA_CMD26)

U33

FBA_CMD6 (FBA_CMD14)

U28

FBA_CMD7

V28

FBA_CMD8 (FBA_CMD1)

V29

FBA_CMD9 (FBA_CMD22)

V30

FBA_CMD10 (FBA_CMD20)

U34

FBA_CMD11 (FBA_CMD24)

U31

FBA_CMD12 (FBA_CMD18)

V34

FBA_CMD13 (FBA_CMD9)

V33

FBA_CMD14 (FBA_CMD29)

Y32

FBA_CMD15 (FBA_CMD8)

AA31

FBA_CMD16 (FBA_CMD27)

AA29

FBA_CMD17 (FBA_CMD15)

AA28

FBA_CMD18 (FBA_CMD11)

AC34

FBA_CMD19 (FBA_CMD16)

AC33

FBA_CMD20 (FBA_CMD28)

AA32

FBA_CMD21 (FBA_CMD3)

AA33

FBA_CMD22 (FBA_CMD17)

Y28

FBA_CMD23 (FBA_CMD5)

Y29

FBA_CMD24 (FBA_CMD4)

W31

FBA_CMD25 (FBA_CMD21)

Y30

FBA_CMD26 (FBA_CMD6)

AA34

FBA_CMD27 (FBA_CMD13)

Y31

FBA_CMD28 (FBA_CMD19)

Y34

FBA_CMD29 (FBA_CMD12)

Y33

FBA_CMD30

V31

FBA_CMD31 (NC)

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

AA27

FBVDDQ_1

AA30

FBVDDQ_2

AB27

FBVDDQ_3

AB33

FBVDDQ_4

AC27

FBVDDQ_5

AD27

FBVDDQ_6

AE27

FBVDDQ_7

AF27

FBVDDQ_8

AG27

FBVDDQ_9

B13

FBVDDQ_10

B16

FBVDDQ_11

B19

FBVDDQ_12

E13

FBVDDQ_13

E16

FBVDDQ_14

E19

FBVDDQ_15

H10

FBVDDQ_16

H11

FBVDDQ_17

H12

FBVDDQ_18

H13

FBVDDQ_19

H14

FBVDDQ_20

H15

FBVDDQ_21

H16

FBVDDQ_22

H18

FBVDDQ_23

H19

FBVDDQ_24

H20

FBVDDQ_25

H21

FBVDDQ_26

H22

FBVDDQ_27

H23

FBVDDQ_28

H24

FBVDDQ_29

H8

FBVDDQ_30

H9

FBVDDQ_31

L27

FBVDDQ_32

M27

FBVDDQ_33

N27

FBVDDQ_34

P27

FBVDDQ_35

R27

FBVDDQ_36

T27

FBVDDQ_37

T30

FBVDDQ_38

T33

FBVDDQ_39

V27

FBVDDQ_40

W27

FBVDDQ_41

W30

FBVDDQ_42

W33

FBVDDQ_43

Y27

FBVDDQ_44

EV@N14P_GV2

[MEMORY I/F A]

(FBA_DEBUG) FBA_DEBUG0

+

C1 *EV@330u/2.5V_3528

+

C6 EV@330u/2V_7343

(NC) FBA_DEBUG1

FBA_CMD_RFU0
FBA_CMD_RFU1

FBA_WCK01_N
FBA_WCK23_N
FBA_WCK45_N
FBA_WCK67_N

FBA_WCKB01_N
FBA_WCKB23_N
FBA_WCKB45_N
FBA_WCKB67_N

FB_DLL_AVDD

FBA_PLL_AVDD

FBVDDQ_PROBE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

VMA_WDQS0
VMA_WDQS1
VMA_WDQS2
VMA_WDQS3
VMA_WDQS4
VMA_WDQS5
VMA_WDQS6
VMA_WDQS7

VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7

+1.5V_GFX

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

TP13

VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7

FBA_CMD[30:0][21]

A A

VMA_DM[7..0][21]

DBI

B B

VMA_WDQS[7..0][21]

EDC

VMA_RDQS[7..0][21]

0816 follow DG to place caps

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS

C C

0.1u x 6
stuff x4

1u x 6
stuff x4

4.7u x 6
stuff x4

10u x 4
stuff x2

D D

22u x 4
stuff x2

PLACE UNDER GPU BALLS

+1.5V_GFX

C55 EV@0.1u/10V_4
C53 EV@0.1u/10V_4
C32 EV@0.1u/10V_4
C54 EV@0.1u/10V_4
C58 *EV@0.1u/10V_4
C136 *EV@0.1u/10V_4

C30 EV@1u/6.3V_4
C31 EV@1u/6.3V_4
C51 EV@1u/6.3V_4
C52 EV@1u/6.3V_4
C44 *EV@1u/6.3V_4
C43 *EV@1u/6.3V_4

C581 EV@4.7u/6.3V_6
C119 EV@4.7u/6.3V_6
C60 EV@4.7u/6.3V_6
C134 EV@4.7u/6.3V_6
C96 *EV@4.7u/6.3V_6
C57 *EV@4.7u/6.3V_6

C68 EV@10u/6.3V_6
C81 EV@10u/6.3V_6
C110 *EV@10u/6.3V_6
C584 *EV@10u/6.3V_6

C538 EV@22u/6.3V_8
C125 EV@22u/6.3V_8
C536 *EV@22U/6.3V_8
C537 *EV@22U/6.3V_8

PLACE NEAR TO GPU BALLS

FBC_CMD[30:0][22]

VMC_DM[7..0][22]

VMC_WDQS[7..0][22]

VMC_RDQS[7..0][22]

VMA_CLK0 [21]
VMA_CLK0# [21]
VMA_CLK1 [21]
VMA_CLK1# [21]

R76 *EV@60.4/F_4
R154 *EV@60.4/F_4

0815 no stuff follow CRB

GC6 connect to EC

R472 EV@0/J_4
R473 EV@10K/J_4

C6218 close ball K27 35mA

C61 EV@0.1u/10V_4

TP4
TP58

R84 EV@40.2/F_4
R77 EV@42.2/F_4
R70 EV@51.1/F_4

L9 EV@PBY160808T-30Y-N_6
C64 EV@22u/6.3V_8

C67 EV@0.1u/10V_4
C63 *EV@0.1u/10V_4

R1
R2

0813
sDDR3
R1=42.2/F
R2=51.1/F

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

TP82

VMC_DM0
VMC_DM1
VMC_DM2
VMC_DM3
VMC_DM4
VMC_DM5
VMC_DM6
VMC_DM7

VMC_WDQS0
VMC_WDQS1
VMC_WDQS2
VMC_WDQS3
VMC_WDQS4
VMC_WDQS5
VMC_WDQS6
VMC_WDQS7

VMC_RDQS0
VMC_RDQS1
VMC_RDQS2
VMC_RDQS3
VMC_RDQS4
VMC_RDQS5
VMC_RDQS6
VMC_RDQS7

+1.5V_GFX

EC_FB_CLAMP [19,20,34]

+1.5V_GFX

RSVD 330u, ZQS have one

1

2

3

4

D13
E14
F14
A12
B12
C14
B14

G15

F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18

B18
G18
G17

F17

D16

A18

D17

A17

B17

E17

E11

E3
A3

C9
F23
F27
C30
A24

D10

D5

C3

B9
E23
E28
B30
A23

D9

E4

B2

A9
D22
D28
A30
B23

5

U35C

FBB_CMD0 (FBC_CMD25)
FBB_CMD1 (FBC_CMD23)
FBC_CMD2
FBB_CMD3 (FBC_CMD0)
FBB_CMD4 (FBC_CMD10)
FBB_CMD5 (FBC_CMD26)
FBB_CMD6 (FBC_CMD14)
FBC_CMD7
FBB_CMD8 (FBC_CMD1)
FBB_CMD9 (FBC_CMD22)
FBB_CMD10 (FBC_CMD20)
FBB_CMD11 (FBC_CMD24)
FBB_CMD12 (FBC_CMD18)
FBB_CMD13 (FBC_CMD9)
FBB_CMD14 (FBC_CMD29)
FBB_CMD15 (FBC_CMD8)
FBB_CMD16 (FBC_CMD27)
FBB_CMD17 (FBC_CMD15)
FBB_CMD18 (FBC_CMD11)
FBB_CMD19 (FBC_CMD16)
FBB_CMD20 (FBC_CMD28)
FBB_CMD21 (FBC_CMD3)
FBB_CMD22 (FBC_CMD17)
FBB_CMD23 (FBC_CMD5)
FBB_CMD24(FBC_CMD4)
FBB_CMD25 (FBC_CMD21)
FBB_CMD26 (FBC_CMD6)
FBB_CMD27 (FBC_CMD13)
FBB_CMD28 (FBC_CMD19)
FBB_CMD29 (FBC_CMD12)
FBC_CMD30
FBC_CMD31 (NC)

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

+1.05V_GFX

MEMORY I/F C

PLACE NEAR TO GPU BALLS
PLACE UNDER GPU BALLS

+FB_PLLAVDD = 0.3mm 12mils
U27+H17 62mA

FBC_D00
FBC_D01
FBC_D02
FBC_D03
FBC_D04
FBC_D05
FBC_D06
FBC_D07
FBC_D08
FBC_D09
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_CLK0

FBC_CLK0_N

FBC_CLK1

FBC_CLK1_N

(FBC_DEBUG) FBB_DEBUG0

(NC) FBB_DEBUG1

FBB_CMD_RFU0
FBB_CMD_RFU1

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

6

G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26

D12
E12
E20
F20

G14
G20

C12
C20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

H17

EV@N14P_GV2

VMC_DQ0
VMC_DQ1
VMC_DQ2
VMC_DQ3
VMC_DQ4
VMC_DQ5
VMC_DQ6
VMC_DQ7
VMC_DQ8
VMC_DQ9
VMC_DQ10
VMC_DQ11
VMC_DQ12
VMC_DQ13
VMC_DQ14
VMC_DQ15
VMC_DQ16
VMC_DQ17
VMC_DQ18
VMC_DQ19
VMC_DQ20
VMC_DQ21
VMC_DQ22
VMC_DQ23
VMC_DQ24
VMC_DQ25
VMC_DQ26
VMC_DQ27
VMC_DQ28
VMC_DQ29
VMC_DQ30
VMC_DQ31
VMC_DQ32
VMC_DQ33
VMC_DQ34
VMC_DQ35
VMC_DQ36
VMC_DQ37
VMC_DQ38
VMC_DQ39
VMC_DQ40
VMC_DQ41
VMC_DQ42
VMC_DQ43
VMC_DQ44
VMC_DQ45
VMC_DQ46
VMC_DQ47
VMC_DQ48
VMC_DQ49
VMC_DQ50
VMC_DQ51
VMC_DQ52
VMC_DQ53
VMC_DQ54
VMC_DQ55
VMC_DQ56
VMC_DQ57
VMC_DQ58
VMC_DQ59
VMC_DQ60
VMC_DQ61
VMC_DQ62
VMC_DQ63

VMC_CLK0
VMC_CLK0#
VMC_CLK1
VMC_CLK1#

FBC_DEBUG
FBC_DEBUG1

R184 *EV@60.4/F_4
R188 *EV@60.4/F_4

FBA_CMD2
FBA_CMD3
FBA_CMD5
FBA_CMD18
FBA_CMD19

FBC_CMD2
FBC_CMD3
FBC_CMD5
FBC_CMD18
FBC_CMD19

0815 confirm with ZQS (sDDR3)

VMA_DQ[63:0]
VMC_DQ[63:0]

VMC_CLK0 [22]
VMC_CLK0# [22]
VMC_CLK1 [22]
VMC_CLK1# [22]

R78 EV@10K/F_4
R74 EV@10K/F_4
R114 EV@10K/F_4
R544 EV@10K/F_4
R538 EV@10K/F_4

R25 EV@10K/F_4
R26 EV@10K/F_4
R63 EV@10K/F_4
R370 EV@10K/F_4
R407 EV@10K/F_4

0815 no stuff follow CRB

1012(FAE)：Reserve +FB_PLLAVDD evan without CH-B

+FB_PLLAVDD

C94 EV@0.1u/10V_4

C107 close to ball H17

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

PROJECT :

DGPU 2/5 (Memory)

DGPU 2/5 (Memory)

DGPU 2/5 (Memory)

+1.5V_GFX

17

VMA_DQ[63:0] [21]
VMC_DQ[63:0] [22]

ZQK

ZQK

ZQK

17 46Monday, January 07, 2013

17 46Monday, January 07, 2013

17 46Monday, January 07, 2013

8

1A

1A

1A

1

2

3

4

5

6

7

8

18

U35D

AH8

IFPAB_PLLVDD

AG8

IFPA_IOVDD

AG9

AJ8

AF7

AG7

AF6

AG6

AF8
AN2

AB8

AC7
AC8

AD6

AG10

AP9

AP8

IFPB_IOVDD

IFPAB_RSET

IFPC_PLLVDD
IFPD_PLLVDD

IFPC_IOVDD
IFPD_IOVDD

IFPC_RSET
IFPD_RSET

IFPEF_PLLVDD

IFPE_IOVDD
IFPF_IOVDD

IFPEF_RSET

DACA_VDD

DACA_VREF

DACA_RSET

A A

B B

C C

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1318MILS

[IFPA/B_LVDS]

[IFPC/D_TMDS]

[IFPE/F_DP]

[DACA/B_CRT]

IFPA_TXC_N
IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N

IFPB_TXC_N
IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N

IFPC_AUX_I2CW_SCL

IFPC_AUX_I2CW_SDA_N

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA_N

IFPE_AUX_I2CY_SCL

IFPE_AUX_I2CY_SDA_N

IFPF_AUX_I2CZ_SCL

IFPF_AUX_I2CZ_SDA_N

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC
DACA_VSYNC

NV_PLLVDD 0.3MM=12mils 78mA

+1.05V_GFX

L14 EV@160808-30Y

C140

EV@22u/6.3V_8

NV_PLLVDD

C137

EV@0.1u/10V_4

AD8

PLLVDD

PLACE UNDER GPU BALLSPLACE NEAR TO GPU BALLS

AE8 : 71mA

D D

+1.05V_GFX

1

GPU_SP_PLLVDD 0.3MM=12mils

L15 EV@160808-0180P

C165

C168

EV@22u/6.3V_8

EV@4.7u/6.3V_6

PLACE NEAR TO GPU BALLS

2

AD7 : 41mA

SP_VID_PLLVDD

C138

C164

EV@0.1u/10V_4

EV@0.1u/10V_4

PLACE UNDER GPU BALLS

3

AE8

AD7

EV@N14P_GV2

SP_PLLVDD

VID_PLLVDD

[XTAL IN]

4

XTAL_OUTBUFF

IFPA_TXC
IFPA_TXD0
IFPA_TXD1
IFPA_TXD2
IFPA_TXD3

IFPB_TXC
IFPB_TXD4
IFPB_TXD5
IFPB_TXD6
IFPB_TXD7

IFPC_L0

IFPC_L0_N

IFPC_L1

IFPC_L1_N

IFPC_L2

IFPC_L2_N

IFPC_L3

IFPC_L3_N

IFPD_L0

IFPD_L0_N

IFPD_L1

IFPD_L1_N

IFPD_L2

IFPD_L2_N

IFPD_L3

IFPD_L3_N

IFPE_L0

IFPE_L0_N

IFPE_L1

IFPE_L1_N

IFPE_L2

IFPE_L2_N

IFPE_L3

IFPE_L3_N

IFPF_L0

IFPF_L0_N

IFPF_L1

IFPF_L1_N

IFPF_L2

IFPF_L2_N

IFPF_L3

IFPF_L3_N

I2CA_SCL

I2CA_SDA

XTAL_IN

XTAL_OUT

XTAL_SSIN

AN6
AM6
AN3
AP3
AM5
AN5
AK6
AL6
AH6
AJ6

AH9
AJ9
AP5
AP6
AL7
AM7
AM8
AN8
AL8
AK8

AG3
AG2
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4

AK3
AK2
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5

AB3
AB4
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5

AF3
AF2
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1

AK9
AL10
AL9

AM9
AN9

R4

EV_CRTDCLK

R5

EV_CRTDDAT

H3

CLK_27M_VGA_2

H2

XTALOUT

J4

R79 EV@10K/F_4

H1

R492 EV@10K/F_4

5

R107 EV@2.2K_4
R106 EV@2.2K_4

C548 EV@10p/50V_4

R481
*EV@1M/J_4

C554 EV@10p/50V_4

6

CLK_27M_VGA_2

Y2
EV@27MHZ

2 4

XTALOUT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DGPU 3/5 (Display)

DGPU 3/5 (Display)

DGPU 3/5 (Display)

7

ZQK

ZQK

ZQK

18 46Monday, January 07, 2013

18 46Monday, January 07, 2013

18 46Monday, January 07, 2013

8

1A

1A

1A

1

U35E

A A

[MIOA]

[MIOB]

B B

AM10

JTAG_TCK

TP63

JTAG_TMS

TP65

JTAG_TDIJTAG_TDI

TP67

JTAG_TDO

TP66

JTAG_TRST#

TP64

R118 EV@2.2K_4
R119 EV@2.2K_4

R121 EV@2.2K_4

C C

R120 EV@2.2K_4

N13P_SCL
N13P_SDA

DGPU_EDIDCLK
DGPU_EDIDDATA

GFx_SCL
GFx_SDA

AP11

AM11

AP12
AN11

R7
R6

R2
R3

T4
T3

K4
K3

JTAG_TCK

[MISC_GPIO/I2C/JTAG/THER]

JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N

I2CB_SCL
I2CB_SDA

I2CC_SCL
I2CC_SDA

I2CS_SCL
I2CS_SDA

THERMDP
THERMDN

&#

J2

N14x others

N14M-GE/GL

GPIO8 VGA thrmtrip# => inform EC
over temperature protect

D D

VGA_OVT#

+3V_GFX

R516 *EV@0_4

1

Q47 EV@2N7002K

40.2K

NC

R501 EV-D@40.2K/ F_4

R3

3

2

R194 EV@0/J_4

0816 dGPU_OTP# = EC control

1

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

dGPU_OTP# [34]

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

J1

MULTISTRAP_REF_GND

EV@N14P_GV2

PEGX_RST# [ 16]

+3V_GFX

[MISC2_ROM]

GPU_ALERT#

R786 *EV@0_4

2

1001：Remove 3V3MISC by FAE Nelson suggesLon
FAE：Please use +3V_GFX to instead 3V3MISC power rail

VGPU_PSI
VGA_OVT#
JTAG_TMS
JTAG_TDI
GPIO12_ACIN
GPU_ALERT#
JTAG_TCK
JTAG_TRST#

FB_CLAMP_MON

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

M7

GPIO6

3DVision

N8

GPIO7

M1

VGA_OVT#

GPIO8

M2

GPU_ALERT#

GPIO9

L1

GPIO10

M5

GPIO11

N3

GPIO12_ACIN

GPIO12

M4

VGPU_PSI

GPIO13

HPD_A

N4

GPIO14

HPD_C

P2

GPIO15

FRM_LCK

R8

GPIO16

HPD_D

M6

GPIO17

HPD_E

R1

GPIO18

HPD_F or HDP_B

P3

GPIO19

P4

GPIO20

P1

GPIO21

H4

ROM_SCLK

H6
H5

ROM_SI

ROM_SI

H7

ROM_SO

ROM_SO

L2

L3

0817 CEC is NC for GK107

CEC

3

Q50
EV@2N7002K

2

R189 EV@0/J_4

GPIO9 for ADPS circuit to infrom EC
NV dGPU VPS Alert

0816 dGPU_ALT# = EC control

2

1

ROM_SCLK
ROM_CS_N

BUFRST_N

3

Logical Strap Bit Mapping

4.99K
10K
15K
20K

24.9K

30.1K

34.8K

45.3K

+3V_GFX

R127 EV@0/J_4

1

R111

EV@10K/F_4

+3V_GFX

U14

4

*EV@MC74VHC1G08DFT2G

3

ROM_SI
ROM_SO
ROM_SCLK

R100 EV@10K/F_4
R512 EV@10K/F_4
R593 *EV@10K/F_4
R578 *EV@10K/F_4
R142 EV@10K/F_4
R513 EV@10K/F_4
R594 *EV@10K/F_4
R579 EV@10K/F_4

3

1

R90 EV @0/J_4

Q14
EV@2N7002K

2

+3V_GFX

LCD_BL_PWM
LCD_VCC
LCD_BLEN
RSVD

FB_CLAMP_REQ#_R

VGPU_PWMVID [43]
VGPU_PSI [43]

PSI stuff 10k at GPU side ready, remove power page of pu 10k

RSVD
RSVD

GPIO20/21 available on N14P-GV2

GPIO12 HW throttle
over power protect

GPIO12_ACIN

dGPU_ALT# [34]

PEGX_RST#

4

PU-VDD PD

1000 0000
1001 0001

00101010
1011 0011
1100

0100
1101

0101
1110 0110
1111

0111

+3V_GFX

R61
*EV-D@4.99K/F_4

R72
EV-D@10K/F_4

0817：FB_CLAMP have PD, EC programing to avoid leakage
0928 FAE Nelson：Add a MOS to avoid power leakage issue pin 2 connect to +3V_GFX power rail

EC_FB_CLAMP [17,20,34]

3

Q13
*EV@2N7002K

2

0816 EC programing GPI

+3V_GFX

0816 dGPU_OPP# = EC control

3

1

Q16
EV@2N7002K

2

GPIO12 AC detect
AC high
DC low

2
1

3 5

0815 RSVD VGPU TALERT#
to throttle GPU power

R58
EV-D@4.99K/F_4

R69
*EV-D@10K/F_4

R52
EV-D@4.99K/F_4

R64
*EV-D@15K/F_4

dGPU_OPP# [34]

GPU_THAL# [43]

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

R101

*EV@10K/F_4

+3V

4

Logical

Strapping Bit3

FB_1

PCI_DEVIDE[4]
RAMCFG[3]

3GIO_PADCFG[3]
PCI_DEVID[3] PCI_DEVID[1]
SOR3_EXPOSED
RESERVED PCIE_MAX SPEED DP_PL L_VDD33

R500

EV-D@45.3K/F_4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

R502

*EV-D@10K/F_4

FB_CLAMP_TGL_REQ# [34]

0928 FAE Nelson：Please add 10k pull up to +3V
on FB_CLAMP_REQ# signal also

SMBus (VGA)

2ND_MBCLK[9,34]

[9,34]

2ND_MBDATA

EC/S5

Strapping Bit2

FB_0

SUB_VENDOR
RAMCFG[2]

3GIO_PADCFG[2]
PCI_DEVID[2]
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
PCIE SPEED

CHANGE GEN3

+3V_GFX

R80

R50

*EV-D@34.8K/F_4

*EV-D@4.99K/F_4

R51

EV-D@45.3K/F_4

R86
EV-D@15K/F_4

1001：Remove 3V3MISC by FAE Nelson suggesLon
FAE：Please use +3V_GFX to instead 3V3MISC power rail

Q18

5

43

2
6

1

EV@2N7002DW

5

LogicalLogical

Strapping Bit1

SMB_ALT_ADDR

PCI_DEVID[5]
RAMCFG[1]
USER[1]
3GIO_PADCFG[1] 3GIO_PADCF G[0]

R497
*EV-D@10K/F_4

R53

*EV-D@34.8K/F_4

R496

R65

EV-D@45.3K/F_4

EV-D@4.99K/F_4

+3V_GFX

R128

R136

EV@10K/F_4

EV@10K/F_4

VGA/+3V_GFX

5

GFx_SCL

GFx_SDA

Logical

Strapping Bit0

VGA_DEVICE

PEX_PLL_EN_TERM
RAMCFG[0]
USER[0]USER[3] USER[2]

PCI_DEVID[0]

A.ROM_SI - Memeory strap
B.ROM_SO - 5K pull high
D.STRAP 0 - 45k pull high
E.STRAP 1 ：GV2- 45K pull down
GT - 5K pull down
F.STRAP 3 - 5k pull down

C2.For N14P-GV2+SDDR3 sku
N14P-GV2 QS device ID=0x1292 'This is QS device ID

1.ROM_SCLK =5K pull high

2.STRAP2= 15k pull down

3.STRAP4=45 pull down 'For N14P-GV2 QS

N14P-GT device ID=0x0FE4

1.ROM_SCLK =15K pull down

2.STRAP2= 25k pull down

3.STRAP4=45K pull down

Strap

Vender

Hynix

0110

1000

1292

XXXX

1111

0110

0010

0000

0111

AKD5PGSTL05

AKD5MGWTW17

6

STRAP3
Optimus ---> 4.99k PD
Discrete only ---> 15K PD

Resistor P/N

4.99K---> CS24992FB26
10K ---> CS31002FB26
15K ---> CS31502FB24
20K ---> CS32002FB29

24.9K---> CS32492FB16

30.1K---> CS33012FB18

34.8K---> CS33482FB22

45.3K---> CS34532FB18

Q PN

MT41K256M16HA-107G:E0001

H5TQ2G63DFR-11C

6

Mfr. PN

Freq.

900MHzMicron

900MHz

GPU

N14P-GT1 & GV2

N14P-GT

7

N14M-GE device ID is 0x1140
N14M-GE is use binary strap setting

A.ROM_SI - 10K pull down
B.ROM_SO - 10K pull down
F.STRAP 3 - 10k pull down

Micron：MT41K256M16HA-107G:E (QPN = AKD5PGSTL05)
strap= 0xD =(0x1101)
STRAP 3&2&0 =10K Pull high
STRAP 1= 10K Pull down

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DGPU 4/5 (MIO/GPIO)

DGPU 4/5 (MIO/GPIO)

DGPU 4/5 (MIO/GPIO)

Date: Sheet of

Date: Sheet of

7

Date: Sheet of

8

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZQK

PROJECT :

ZQK

PROJECT :

ZQK

19 46Monday, January 07, 2013

19 46Monday, January 07, 2013

19 46Monday, January 07, 2013

8

19

1A

1A

1A

1

+VGPU_CORE

A A

B B

C C

for meet Power down sequence
for +3V_GFX

+VGPU_CORE

+1.5V_GFX

U35F

AA12

VDD_001

AA14

VDD_002

AA16

VDD_003

AA19

VDD_004

AA21

VDD_005

AA23

VDD_006

AB13

VDD_007

AB15

VDD_008

AB17

VDD_009

AB18

VDD_010

AB20

VDD_011

AB22

VDD_012

AC12

VDD_013

AC14

VDD_014

AC16

VDD_015

AC19

VDD_016

AC21

VDD_017

AC23

VDD_018

M12

VDD_019

M14

VDD_020

M16

VDD_021

M19

VDD_022

M21

VDD_023

M23

VDD_024

N13

VDD_025

N15

VDD_026

N17

VDD_027

N18

VDD_028

N20

VDD_029

N22

VDD_030

P12

VDD_031

P14

VDD_032

P16

VDD_033

P19

VDD_034

P21

VDD_035

P23

VDD_036

R13

VDD_037

R15

VDD_038

R17

VDD_039

R18

VDD_040

R20

VDD_041

R22

VDD_042

T12

VDD_043

T14

VDD_044

T16

VDD_045

T19

VDD_046

T21

VDD_047

T23

VDD_048

U13

VDD_049

U15

VDD_050

U17

VDD_051

U18

VDD_052

U20

VDD_053

U22

VDD_054

V13

VDD_055

V15

VDD_056

V17

VDD_057

V18

VDD_058

V20

VDD_059

V22

VDD_060

W12

VDD_061

W14

VDD_062

W16

VDD_063

W19

VDD_064

W21

VDD_065

W23

VDD_066

Y13

VDD_067

Y15

VDD_068

Y18

VDD_069

Y17

VDD_070

Y20

VDD_071

Y22

VDD_072

EV@N14P_GV2

D3 EV@RB500V-40

D2 *EV@RB500V-40

20120911: D6002 no stuff when GC6 support.

HWPG_1.5VGFX
VGPU_PWRGD

PU at page 43

D D

1

2
1

U12 EV@MC74VHC1G08DFT2G

R103 *EV@0_4

+3V

3 5

[GPU VDD]

4

2

+3V_GFX

C87

*EV@0.1u/10V_4

2

XVDD_001
XVDD_002
XVDD_003
XVDD_004
XVDD_005
XVDD_006
XVDD_007
XVDD_008
XVDD_009
XVDD_010
XVDD_011
XVDD_012
XVDD_013
XVDD_014
XVDD_015
XVDD_016
XVDD_017
XVDD_018
XVDD_019
XVDD_020
XVDD_021
XVDD_022
XVDD_023
XVDD_024
XVDD_025
XVDD_026
XVDD_027
XVDD_028
XVDD_029
XVDD_030
XVDD_031
XVDD_032
XVDD_033
XVDD_034
XVDD_035
XVDD_036
XVDD_037
XVDD_038

U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8

1.05V_GFX_EN [42]

FBVDDQ_EN[42]

3

U35G

A2

GND_1

AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19

AB21
AB23

AB28
AB30
AB32

AC13
AC15
AC17
AC18

AA13
AC20
AC22

AE28

AE30

AE32

AE33

AH10

AA15
AH13
AH16
AH19

AH22
AH24
AH28
AH29
AH30
AH32
AH33

AK10

AL12

AL14

AL15

AL17

AL18

AL20

AL21

AL23

AL24

AL26

AL28

AL30

AL32

AL33
AM13

AM16
AM19
AM22
AM25

AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34

AP33

AB2

A33

AB5
AB7

AE2

AE5
AE7

AH2

AH5
AH7

AJ7

AK7

AL2

AL5

AN1

AN4
AN7
AP2

B10
B22
B25
B28
B31
B34

C10
C13
C19
C22
C25
C28

C7

GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84

B1

GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91

B4

GND_92

B7

GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100

EV@N14P_GV2

[GPU GND]

0816 GC6 need system 3V to control FBVDDQ

+3V

5

4

R83
EV@100K/F_4

3

3

U11 EV@74AHC1G32GW

4

GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199

GND_200
GND_OPT_1
GND_OPT_2

C71
EV@0.1u/10V_4

2
1

VGPU_PWRGD_R

4

D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11

C16
W32

EC_FB_CLAMP [17,19,34]

R82 EV@0/J_4
R87 *EV@0_4

C70 *EV@0.1u/10V_4

5

+VGPU_CORE

+

C596
EV@330u/2V_7343

Power request ESR

PLACE UNDER GPU BALLS

+VGPU_CORE

4.7uF x 15 population x10

C102

EV@4.7u/6.3V_6

+VGPU_CORE

C83

EV@4.7u/6.3V_6

PLACE NEAR TO GPU BALLS

+VGPU_CORE

+

EV@330u/2.5V_3528

+VGPU_CORE

C92

*EV@22u/6.3V_8

R187

+1.05V_GFX

R167

+1.5V_GFX

20120914: H/W Add for HWPG_1.5VGFX
20121018: Circuit combination

5

C617

EV@4.7K/J_4

EV@4.7K/J_4

VGPU_PWRGD [43]

DGPU_VRON [10,43]

C100

EV@4.7u/6.3V_6

C104

EV@4.7u/6.3V_6

47u x1 22u x7

C128
EV@47u/6.3V_8

0817 RSVD more NVVDD caps by NV DG

C93

*EV@22u/6.3V_8

DGPU_POK2

C175
*EV@1000P/50V_4

DGPU_POK4

C146
*EV@1000P/50V_4

6

PLACE UNDER GPU BALLS

+VGPU_CORE

0.1uF x 8 population x 4

C90 EV@0.1u/10V_4
C98 EV@0.1u/10V_4
C91 EV@0.1u/10V_4
C108 EV@0.1u/10V_4
C97 *EV@0.1u/10V_4
C116 *EV@0.1u/10V_4
C107 *EV@0.1u/10V_4
C115 *EV@0.1u/10V_4

C117

EV@4.7u/6.3V_6

C113

*EV@4.7u/6.3V_6

C74

*EV@22u/6.3V_8

stuff x 1

C599

EV@22u/6.3V_8

2

Q20

1 3

EV@MMBT3904-7-F

DGPU_POK_Q

2

1 3

Q19
EV@MMBT3904-7-F

6

C129

EV@4.7u/6.3V_6

C121

*EV@4.7u/6.3V_6

4.7u x6
stuff x 5

C597
EV@4.7u/25V_8

C73

*EV@22u/6.3V_8

DGPU_PGOK-1

DGPU_POK_Q

R176
*EV@0_4

7

LAYOUT NOTES:
UNDAER: WITHIN 150MILS
NEAR: WITHIN 1378MILS

C103

EV@4.7u/6.3V_6

C101

*EV@4.7u/6.3V_6

330u x1
RSVD by DG

C132

EV@4.7u/25V_8

C592

*EV@22u/6.3V_8

C88

EV@4.7u/6.3V_6

C122

*EV@4.7u/6.3V_6

C111
EV@4.7u/25V_8

+3V

R161
EV@4.7K/J_4

C123
EV@1000P/50V_4

C124

*EV@22u/6.3V_8

2

C69

EV@4.7u/6.3V_6

C133

*EV@4.7u/6.3V_6

C112

EV@4.7u/25V_8

C127

*EV@4.7u/25V_8

+3V_GFX

R140
EV@4.7K/J_4

Q15

1 3

EV@DTC144EUA

0814 POWER GD connect to EC

+3V

R59
EV@4.7K/J_4

C49
EV@1000p/50V_4

+3V_GFX

R43
EV@4.7K/J_4

2

Q5

1 3

EV@DTC144EUA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DGPU 5/5 (Power/Ground)

DGPU 5/5 (Power/Ground)

DGPU 5/5 (Power/Ground)

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

R49
EV@100K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

C82

EV@4.7u/6.3V_6

C588
EV@4.7u/25V_8

R147
EV@100K/F_4

HWPG_1.5VGFX

ZQK

ZQK

ZQK

8

20

DGPU_PWROK [10]

20 46Monday, January 07, 2013

20 46Monday, January 07, 2013

20 46Monday, January 07, 2013

8

1A

1A

1A

5

4

3

2

1

VMA_DQ[63..0][17]

VMA_DM[7..0][17]

VMA_WDQS[7..0][17]

VRAM1

VREFC_VMA1
VREFD_VMA1

FBA_CMD9[17]

D D

FBA_CMD11[17]
FBA_CMD8[17]
FBA_CMD25[17]
FBA_CMD10[17]
FBA_CMD24[17]
FBA_CMD22[17]
FBA_CMD7[17]
FBA_CMD21[17]
FBA_CMD6[17]
FBA_CMD29[17]
FBA_CMD23[17]
FBA_CMD28[17]
FBA_CMD20[17]
FBA_CMD4[17]
FBA_CMD14[17]

FBA_CMD12[17]
FBA_CMD27[17]
FBA_CMD26[17]

VMA_CLK0[17]
VMA_CLK0#[17]
FBA_CMD3[17]

FBA_CMD2[17]

C C

FBA_CMD0[17]
FBA_CMD30[17]
FBA_CMD15[17]
FBA_CMD13[17]

FBA_CMD5[17]

Should be 240
Ohms +-1%

B B

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

VMA_CLK0
VMA_CLK0#
FBA_CMD3

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

VMA_WDQS0
VMA_RDQS0

VMA_DM0
VMA_DM1

VMA_WDQS1
VMA_RDQS1

FBA_CMD5

VMA_ZQ1

R73
EV@243/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8

VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VMA_RDQS[7..0][17]

VMA_DQ2
VMA_DQ7
VMA_DQ1
VMA_DQ4
VMA_DQ3
VMA_DQ6
VMA_DQ0
VMA_DQ5

VMA_DQ8
VMA_DQ12
VMA_DQ11
VMA_DQ14
VMA_DQ9
VMA_DQ13
VMA_DQ10
VMA_DQ15

+1.5V_GFX

Should be 240
Ohms +-1%

VREFC_VMA1
VREFD_VMA1

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

VMA_CLK0
VMA_CLK0#
FBA_CMD3

FBA_CMD2
FBA_CMD0
FBA_CMD30
FBA_CMD15
FBA_CMD13

VMA_WDQS2
VMA_RDQS2

VMA_DM2
VMA_DM3

VMA_WDQS3
VMA_RDQS3

FBA_CMD5

CHANNEL A: 1024MB DDR3

VRAM3

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

VMA_ZQ2 VMA_ZQ3

R498
EV@243/F_4

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

E3

VMA_DQ20

F7

VMA_DQ16

F2

VMA_DQ21

F8

VMA_DQ18

H3

VMA_DQ23

H8

VMA_DQ17

G2

VMA_DQ22

H7

VMA_DQ19

D7

VMA_DQ30

C3

VMA_DQ24

C8

VMA_DQ28

C2

VMA_DQ25

A7

VMA_DQ29

A2

VMA_DQ27

B8

VMA_DQ31

A3

VMA_DQ26

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5V_GFX

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

VMA_CLK1[17]

VMA_CLK1#[17]

FBA_CMD19[17]

FBA_CMD18[17]
FBA_CMD16[17]

Should be 240
Ohms +-1%

VREFC_VMA3
VREFD_VMA3

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

VMA_CLK1
VMA_CLK1#
FBA_CMD19

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

VMA_WDQS4
VMA_RDQS4

VMA_DM4
VMA_DM5

VMA_WDQS5
VMA_RDQS5

FBA_CMD5 FBA_CMD5

R533
EV@243/F_4

VRAM2

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

Micron 900MHz 2G AKD5LZWTW02

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2

VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3

VMA_DQ36

F7

VMA_DQ34

F2

VMA_DQ38

F8

VMA_DQ35

H3

VMA_DQ39

H8

VMA_DQ32

G2

VMA_DQ37

H7

VMA_DQ33

D7

VMA_DQ47

C3

VMA_DQ40

C8

VMA_DQ46

C2

VMA_DQ43

A7

VMA_DQ45

A2

VMA_DQ42

B8

VMA_DQ44

A3

VMA_DQ41

B2

+1.5V_GFX

D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Should be 240
Ohms +-1%

VREFC_VMA3
VREFD_VMA3

FBA_CMD9
FBA_CMD11
FBA_CMD8
FBA_CMD25
FBA_CMD10
FBA_CMD24
FBA_CMD22
FBA_CMD7
FBA_CMD21
FBA_CMD6
FBA_CMD29
FBA_CMD23
FBA_CMD28
FBA_CMD20
FBA_CMD4
FBA_CMD14

FBA_CMD12
FBA_CMD27
FBA_CMD26

VMA_CLK1
VMA_CLK1#
FBA_CMD19

FBA_CMD18
FBA_CMD16
FBA_CMD30
FBA_CMD15
FBA_CMD13

VMA_WDQS7
VMA_RDQS7

VMA_DM7
VMA_DM6

VMA_WDQS6
VMA_RDQS6

VMA_ZQ4

R534
EV@243/F_4

VRAM4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9

VDD#G7

VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2

VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8

VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

21

VMA_DQ61
VMA_DQ59
VMA_DQ63
VMA_DQ58
VMA_DQ60
VMA_DQ57
VMA_DQ62
VMA_DQ56

VMA_DQ55
VMA_DQ49
VMA_DQ54
VMA_DQ48
VMA_DQ52
VMA_DQ50
VMA_DQ53
VMA_DQ51

+1.5V_GFX

+1.5V_GFX

VMA_CLK0

R489
EV@162/F_4

VMA_CLK0#

Fermi : Change to 160 ohm
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

A A

+1.5V_GFX

C615 EV@1u/10V_4
C541 EV@1u/10V_4
C573 EV@1u/10V_4
C542 EV@1u/10V_4

5

+1.5V_GFX

C177 EV@10u/6.3V_6
C613 EV@1u/10V_4
C614 EV@1u/10V_4

C233 EV@1u/10V_4

R88

EV@1.33K/F_4

4

R85
EV@1.33K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA3 VREFD_VMA3

C75

EV@0.1u/10V_4

+1.5V_GFX

C27 EV@1u/10V_4
C550 EV@1u/10V_4
C580 EV@1u/10V_4

C25 EV@1u/10V_4
C556 EV@1u/10V_4C24 EV@1u/10V_4
C170 EV@1u/10V_4
C232 EV@1u/10V_4

R48

EV@1.33K/F_4

R60
EV@1.33K/F_4

C42

EV@0.1u/10V_4

+1.5V_GFX

FBA_CMD17[17]
FBA_CMD1[17]

C572 EV@10u/6.3V_6C231 EV@10u/6.3V_6
C533 EV@10u/6.3V_6
C21 EV@0.1u/10V_4

C234 EV@0.1u/10V_4
C547 EV@0.1u/10V_4

C26 EV@0.1u/10V_4

3

FBA_CMD17
FBA_CMD1

10/14 modify

Fermi : Change to 160 ohm
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

TP11
TP6

VMA_CLK1

R542
EV@162/F_4

VMA_CLK1#

+1.5V_GFX

C84 EV@10u/6.3V_6
C540 EV@10u/6.3V_6

C593 EV@0.1u/10V_4
C552 EV@0.1u/10V_4
C575 EV@0.1u/10V_4C29 EV@1u/10V_4 C577 EV@0.1u/10V_4

2

+1.5V_GFX+1.5V_GFX

R156
EV@1.33K/F_4

C135
EV@0.1u/10V_4

R160

EV@1.33K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

PROJECT :

NN13P-LP DDR3 VRAM 1/2

NN13P-LP DDR3 VRAM 1/2

NN13P-LP DDR3 VRAM 1/2

+1.5V_GFX

R175

EV@1.33K/F_4

1

R171
EV@1.33K/F_4

C162
EV@0.1u/10V_4

ZQK

ZQK

ZQK

1A

1A

1A

4621

4621

4621

5

4

3

2

1

[17]

VMC_DQ[63..0]

[17]

VMC_DM[7..0]

[17]

VMC_WDQS[7..0]

[17]

VMC_RDQS[7..0]

VRAM5

VREFC_VMC1
VREFD_VMC1

[17]

FBC_CMD9

D D

[17]

FBC_CMD11

[17]

FBC_CMD8

[17]

FBC_CMD25

[17]

FBC_CMD10

[17]

FBC_CMD24

[17]

FBC_CMD22

[17]

FBC_CMD7

[17]

FBC_CMD21

[17]

FBC_CMD6

[17]

FBC_CMD29

[17]

FBC_CMD23

[17]

FBC_CMD28

[17]

FBC_CMD20

[17]

FBC_CMD4

[17]

FBC_CMD14

[17]

FBC_CMD12

[17]

FBC_CMD27

[17]

FBC_CMD26

VMC_CLK0[17]
VMC_CLK0#[17]

[17]

FBC_CMD3

[17]

FBC_CMD2

C C

[17]

FBC_CMD0

[17]

FBC_CMD30

[17]

FBC_CMD15

[17]

FBC_CMD13

[17]

FBC_CMD5

Should be 240
Ohms +-1%

B B

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

FBC_CMD12
FBC_CMD27
FBC_CMD26

VMC_CLK0
VMC_CLK0#
FBC_CMD3

FBC_CMD2
FBC_CMD0
FBC_CMD30
FBC_CMD15
FBC_CMD13

VMC_WDQS0
VMC_RDQS0

VMC_DM0
VMC_DM1

VMC_WDQS1
VMC_RDQS1

FBC_CMD5

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

VMC_ZQ1 VMC_ZQ2

R94
EV@243/F_4

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2

VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

E3

VMC_DQ3

F7

VMC_DQ4

F2

VMC_DQ0

F8

VMC_DQ6

H3

VMC_DQ1

H8

VMC_DQ7

G2

VMC_DQ2

H7

VMC_DQ5

D7

VMC_DQ8

C3

VMC_DQ12

C8

VMC_DQ9

C2

VMC_DQ14

A7

VMC_DQ10

A2

VMC_DQ13

B8

VMC_DQ11

A3

VMC_DQ15

B2

+1.5V_GFX

D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Should be 240
Ohms +-1%

VREFC_VMC1
VREFD_VMC1

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

FBC_CMD12
FBC_CMD27
FBC_CMD26

VMC_CLK0
VMC_CLK0#
FBC_CMD3

FBC_CMD2
FBC_CMD0
FBC_CMD30
FBC_CMD15
FBC_CMD13

VMC_WDQS3
VMC_RDQS3

VMC_DM3
VMC_DM2

VMC_WDQS2
VMC_RDQS2

FBC_CMD5

R598
EV@243/F_4

CHANNEL B: 1024MB DDR3

VRAM6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9

VDD#G7

VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

+1.5V_GFX

E3

VMC_DQ27

F7

VMC_DQ31

F2

VMC_DQ25

F8

VMC_DQ28

H3

VMC_DQ24

H8

VMC_DQ30

G2

VMC_DQ26

H7

VMC_DQ29

D7

VMC_DQ17

C3

VMC_DQ22

C8

VMC_DQ18

C2

VMC_DQ23

A7

VMC_DQ19

A2

VMC_DQ21

B8

VMC_DQ16

A3

VMC_DQ20

B2
D9
G7
K2
K8
N1
N9
R1

+1.5V_GFX

R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

[17]

[17]
[17]

VMC_CLK1[17]
VMC_CLK1#[17]
FBC_CMD19

FBC_CMD18
FBC_CMD16

Should be 240
Ohms +-1%

VREFC_VMC3
VREFD_VMC3

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

FBC_CMD12
FBC_CMD27
FBC_CMD26

VMC_CLK1
VMC_CLK1#
FBC_CMD19

FBC_CMD18
FBC_CMD16
FBC_CMD30
FBC_CMD15
FBC_CMD13

VMC_WDQS4
VMC_RDQS4

VMC_DM4
VMC_DM5

VMC_WDQS5
VMC_RDQS5

FBC_CMD5

VRAM7

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

R446
EV@243/F_4

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

VMC_ZQ3 VMC_ZQ4

HYNIX 900MHz 1G AKD5LZWTW02
HYNIX 900MHz 2G AKD5MGWTW16

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2

VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

E3

VMC_DQ38

F7

VMC_DQ32

F2

VMC_DQ36

F8

VMC_DQ35

H3

VMC_DQ39

H8

VMC_DQ34

G2

VMC_DQ37

H7

VMC_DQ33

D7

VMC_DQ44

C3

VMC_DQ40

C8

VMC_DQ46

C2

VMC_DQ42

A7

VMC_DQ45

A2

VMC_DQ43

B8

VMC_DQ47

A3

VMC_DQ41

B2

+1.5V_GFX

D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

Should be 240
Ohms +-1%

VREFC_VMC3
VREFD_VMC3

FBC_CMD9
FBC_CMD11
FBC_CMD8
FBC_CMD25
FBC_CMD10
FBC_CMD24
FBC_CMD22
FBC_CMD7
FBC_CMD21
FBC_CMD6
FBC_CMD29
FBC_CMD23
FBC_CMD28
FBC_CMD20
FBC_CMD4
FBC_CMD14

FBC_CMD12
FBC_CMD27
FBC_CMD26

VMC_CLK1
VMC_CLK1#
FBC_CMD19

FBC_CMD18
FBC_CMD16
FBC_CMD30
FBC_CMD15
FBC_CMD13

VMC_WDQS7
VMC_RDQS7

VMC_DM7
VMC_DM6

VMC_WDQS6
VMC_RDQS6

FBC_CMD5

+1.5V_GFX

R641
EV@243/F_4

VRAM8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL
SDRAM DDR3

EV@VRAM _DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9

VDD#G7

VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2

VDDQ#E9

VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

+1.5V_GFX+1.5V_GFX

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

22

VMC_DQ60
VMC_DQ57
VMC_DQ63
VMC_DQ58
VMC_DQ61
VMC_DQ59
VMC_DQ62
VMC_DQ56

VMC_DQ52
VMC_DQ49
VMC_DQ55
VMC_DQ51
VMC_DQ54
VMC_DQ50
VMC_DQ53
VMC_DQ48

+1.5V_GFX

R519

R245
EV@162/F_4

VMC_CLK0#

Fermi : Change to 160 ohm
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

A A

+1.5V_GFX

C795 EV@1u/10V_4
C833 EV@1u/10V_4
C827 EV@1u/10V_4
C826 EV@1u/10V_4

5

+1.5V_GFX

C19 EV@10u/6.3V_6

C825 EV@10u/6.3V_6
C22 EV@1u/10V_4
C839 EV@1u/10V_4

C56 EV@1u/10V_4
C830 EV@1u/10V_4

+1.5V_GFX

EV@1.33K/F_4

VREFC_VMC1 VREFD_VMC1

R588

EV@1.33K/F_4

C836 EV@0.1u/10V_4
C230 EV@0.1u/10V_4
C229 EV@0.1u/10V_4
C831 EV@0.1u/10V_4
C819 EV@0.1u/10V_4
C486 EV@0.1u/10V_4
C837 EV@0.1u/10V_4
C832 EV@0.1u/10V_4

4

C834

EV@0.1u/10V_4

R31

EV@1.33K/F_4

+1.5V_GFX

R33
EV@1.33K/F_4

C282

EV@0.1u/10V_4

C835 EV@1u/10V_4
C838 EV@1u/10V_4
C319 EV@1u/10V_4
C817 EV@1u/10V_4
C62 EV@1u/10V_4
C471 EV@1u/10V_4
C472 EV@1u/10V_4
C487 EV@1u/10V_4

Fermi : Change to 160 ohm
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)

[17]

FBC_CMD17

[17]

FBC_CMD1

+1.5VSUS

1107

：：：：

Reserve 330uF for 8VRAM power routing

3

VMC_CLK1VMC_CLK0

R18
EV@162/F_4

VMC_CLK1#

FBC_CMD17
FBC_CMD1

+

C840 *EV@330u/2.5V_3528

TP113
TP110

R503
EV@1.33K/F_4

VREFC_VMC3 VREFD_VMC3

C829

R451

EV@1.33K/F_4

2

EV@0.1u/10V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

PROJECT :

N13P-LP DDR3 VRAM 2/2

N13P-LP DDR3 VRAM 2/2

N13P-LP DDR3 VRAM 2/2

R332

EV@1.33K/F_4

R251
EV@1.33K/F_4

1

C828
EV@0.1u/10V_4

ZQK

ZQK

ZQK

1A

1A

1A

4522

4522

4522

5

mini DP ML (DPP)

+5V

R41
SW@1M/J_4

D D

SYS_COM_REQ

R792
SW@10K/J_4

R791
SW@100K/F_4

ESD Protect (EMC)

C C

DP_TXP0[7]
DP_TXN0[7]

DP_TXP1[7]
DP_TXN1[7]

Layout Notes:
Place decoupling CAPs close to Connector

B B

C8 0.1u/10V_4
C7 0.1u/10V_4

C9 0.1u/10V_4
C10 0.1u/10V_4

R75
SW@1M/J_4

R787 SW@10K/J_4

SMB_PCH_DAT[9,26]

C821
1u/6.3V_4

R790 SW@10K/J_4

6

215

SMB_PCH_CLK[9,26]

Q68
SW@2N7002DW

4 3

U2

1

1

10

INT_DPTX2P
INT_DPTX3P

INT_DPTX3N

DP_AUXN
DP_AUXP

CONFIG_2CNN CONFIG_2CNN
CONFIG_1CNN

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

U29

1

1

10

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

U1

1

INT_DPTX0P INT_DPTX0P
INT_DPTX0N

INT_DPTX1P

1

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

10

Close to DP connector

CONFIG_1P

R778 SW @0_4

CONFIG_2P

R835 SW@5.1M/ J_4

R779 SW @0_4

10

INT_DPTX2NINT_DPTX2N

9

INT_DPTX2P

9

7

INT_DPTX3P

7

6

INT_DPTX3N

6

10

DP_AUXN

9

DP_AUXP

9

7

7

6

CONFIG_1CNN

6

10
9

INT_DPTX0N

9

7

INT_DPTX1P

7

6

INT_DPTX1NINT_DPTX1N

6

Q45

5

2
6

SW@2N7002DW

Q46

5

2
6

SW@2N7002DW

INT_DPTX0N
INT_DPTX0P

INT_DPTX1N
INT_DPTX1P

43

1

43

1

4

R793
SW@100K/F_4

R789
SW@100K/F_4

R774 0/J_4
L34

443

1

1

*DLW21HN900SQ2L_C

R773 0/J_4

R776 0/J_4
L35

443

1

1

*DLW21HN900SQ2L_C

R775 0/J_4

3

Layout Notes:
Place near Pin13 and Pin14

LB_CHARGE_OFF
LB_CHG_DELAY1#

TP2

R782 NSW@0_4
R785 NSW@5.1M/J_4
R783 NSW@0_4
R784 NSW@1M/J_4

DP_TXP2_CR
DP_TXN2_CR

DP_TXN3_CR

CONFIG_2CNN_C
CONFIG_1CNN_C

C527
SW@0.1u/10V_4

DP_TXP2_C
DP_TXN2_C

USB30_TX3+_C
USB30_TX3-_C

DP_TXP3_C
DP_TXN3_C

USB3_SEL
CONFIG_1P

CONFIG_2P
FCH_USB2_P0_R

FCH_USB2_N0_R

USB2_SEL

USB2_MUX_DIS
USB3_MUX_DIS

DP_HPD_OUT

48

B0P

47

B0N

44

C0P

43

C0N

46

B1P

45

B1N

42

C1P

41

C1N

7

SS_SEL_IN

35

BDP

36

BDM

37

CDP

38

CDM

12

HS_SEL_IN

9

HS_OE#_IN

8

SS_OE#_IN/NC

32

HS_OE#_OUT

34

SS_OE#_OUT

21

CHRG_OFF

22

CHRG_DELAY

23

SLEEP

17

HPD_OUT

57

PAD

CONFIG_1CNNCONFIG_1P

DP_HPD_CDP_HPD_Q

R460 NSW@0_4
R459 NSW@0_4

R458 NSW@0_4
R457 NSW@0_4

C815 SW@2200p/50V_4
C816 SW@2200p/50V_4

SS_SEL

HS_SEL

56

VCC13VCC14VCC40VCC

NC149NC250NC3

NC454NC555NC6

51

INT_DPTX2P
INT_DPTX2N

INT_DPTX3PDP_TXP3_CR
INT_DPTX3N

CONFIG_1CNNFCH_USB2_P0_R

SEL/OE# polarity Control

+3V

R23 *10K/J_4
R22 *10K/J_4

+3V

R447 *10K/J_4
R24 *10K/J_4

+3V

R67 *10K/J_4
R54 *10K/J_4

+3V

R68 *10K/J_4
R55 *10K/J_4

3

INT_DPTX0N_R

2

INT_DPTX0P_R

2

3

INT_DPTX1N_R

2

INT_DPTX1P_R

2

USB2_SEL

USB3_SEL

USB2_MUX_DIS

USB3_MUX_DIS

DP_TXP2[7]
DP_TXN2[7]

USB30_TX3+[9]
USB30_TX3-[9]

DP_TXP3[7]
DP_TXN3[7]

USB30_RX3+[9]

USB30_RX3-[9]

USBP2+[9]

USBP2-[9]

DP_HPD_Q[7]

DP_TXP2_C
DP_TXN2_C

DP_TXP3_C
DP_TXN3_C

FCH_USB2_N0_R CONFIG_2CNN

C534
SW@10u/6.3V_6

C546 0.1u/10V_4
C545 0.1u/10V_4

C40 SW@0.1u/10V_4
C39 SW@0.1u/10V_4

C544 0.1u/10V_4
C543 0.1u/10V_4

R56 SW@0/J_4
R57 SW@0/J_4

R777 SW@0/J_4

R788 SW@0/J_4

CONFIG_2CNN

LB_PWR_RTN

R468 NSW@0_4
R467 NSW@0_4

R466 NSW @0_4
R465 NSW@0_4

C813 SW@2200p/50V_4
C814 SW@2200p/50V_4

NC0

24

4

52

53

2

C23
SW@0.1u/10V_4

1

U7

VCC/NC

VCC/NC

A0P

A0N

A1P

A1N

ADM
ADP

net name change to DP_HPD_C

MODE_LED

HPD_IN

AUX_N

HS_SEL_OUT
SS_SEL_OUT

CONFIG_2
CONFIG_1

CONFIG_1_PU
CONFIG_2_PU

SYS_COM_REQ

RST

TEST

GND33GND

GND

SW@(X)HD3SS2521_NB

39

+3V

Q69

3

IN

NSW@AP2331SA-7

30mil

500mA (Max.)

2
3

5
6

10
11

15
16

18

19
20

28
29

26
27

25

30
31

OUT
GND

C529
SW@0.1u/10V_4

INT_DPTX2P
INT_DPTX2N

INT_DPTX3P
INT_DPTX3N

CONFIG_2CNN
CONFIG_1CNN

DP_HPD_C

USB2_SEL
USB3_SEL

CONFIG_2P
CONFIG_1P

CONFIG_PU
Dongle_POWEREN#

R780 SW@0/J_4

TP3

1
2

C16
SW@0.1u/10V_4

DP HPD (DPP)

R781 SW@10K/J_4

R456 SW@100K/J_4

R32 SW@3.3K/J_4
R42 SW@3.3K/J_4

R66 SW@47K/J_4

C522

0.1u/10V_4

+3V

Connect to HS_SEL_IN(pin12)
Connect to SS_SEL_IN(pin7)

SYS_COM_REQ [8]

C38
SW@2200p/50V_4

LB_PWR_RTN
LB_PWR_CNN

C822
10u/6.3V_6

C15
SW@0.1u/10V_4

+5V

2

Q39

1

2N7002K

R450 *0/J_4

DP_AUXNDP_AUXN_R

CONFIG_PU

+3V

C823

0.1u/10V_4

1

CONFIG_PU

+3V

C17
SW@0.1u/10V_4

DP_HPD

+3V

1

2

3

CN4

1

GND

2

HPD

3

LANE0_P

4

CONFIG1

5

LANE0_N

6

CONFIG2

7

GND

8

GND

9

LANE1_P

10

LANE3_P

11

LANE1_N

12

LANE3_N

13

GND

14

GND

15

LANE2_P

16

AUX_CH_P

17

LANE2_N

18

AUX_CH_N

19

GND

20

DP_PWR

mDP

Q10
SW@AO3409

R805 SW@0/J_6

C528
SW@0.1u/10V_4

3

R20 100/J_4

R21

12

1M/J_4

+3V

1

2

Q9
SW@AO3409

3

MINI DP connector (DPP)

DP_HPD
INT_DPTX0P_R
CONFIG_1CNN
INT_DPTX0N_R
CONFIG_2CNN

INT_DPTX1P_R
INT_DPTX3P
INT_DPTX1N_R
INT_DPTX3N

INT_DPTX2P
DP_AUXP
INT_DPTX2N
DP_AUXN

C824
10u/6.3V_6

23

SHELL1
SHELL2
SHELL3
SHELL4

21
22
23
24

mDP AUX (DPP)

20121018：：：：Follow Intel DG to exchange pin1/6 of Q41

R495 2. 2K/J_4

+3V

DDPC_CTRLDAT[7]

R475 100K/F_4

A A

INT_DP_AUXDN[7]

INT_DP_AUXDP[ 7]

R490 *100K/F_4

+3V

C555 0.1u/10V_4

C551 0.1u/10V_4

R479 *100K/F_4

5

4 3

1

INT_DP_AUXDN_C

INT_DP_AUXDP_C

Q41

2N7002DW

DP_AUXP

4 3

1

2N7002DW

+3V

R494

2.2K/J_4

R476
NSW@100K/F_4

DP_AUXN

DP_DDI_EN

DDPC_CTRLCLK [7]

5

2
6

5

2
6

+3V

Q42

DP_AUX_EN

+5V

R493

R491

10K/F_4

10K/F_4

DP_AUX_EN

CONFIG_1P

DP_CAD

4

5

2
6

R62

2N7002DW

1M/F_4

Low

DP signal (AC couple)

High

TMDS signal (DC couple)

Q43

43

1

Behavior

2 1

D36
SMAJ20A

LB_PWR_RTN

52

1

3

4

Q48
SW@FDMC4435BZ

LB_PWR_RTN_M

R528
SW@20K/J_4

R800
SW@2K/F_4

3

1

4

3

2

Q53
SW@ME2N7002E

3

+5V

52

1

Q49
SW@FDMC4435BZ

4

R541
SW@100K/F_4

+3V

3 5

U36
SW@TC7SH08FU

Dongle_POWEREN#

C578
SW@0.1u/10V_4

2
1

LB_CHARGE_OFF

Q44

5

43

2
6

1

SW@2N7002DW

R499 *SW@100K/F_4

+3V

C579 SW@0.1u/10V_4

U37

1

5

2

Dongle_POWEREN#

4 3

SW@NL17SZ04DFT2G

LB_PWR_RTN

2

R799
SW@100K/F_4

D35
SMAJ20A

2 1

LB_CHARGE_OFF

+3VLB_PWR_CNN

R34
SW@100K/J_4

1 2

+3V

R488
SW@10K/F_4

52

4

Q7
SW@FDMC4435BZ

3

1

LB_PWR_CNN_M

R801 SW@2K/F_4

3

2

Q12
SW@ME2N7002E

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Mini DP

Mini DP

Mini DP

PROJECT :

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

4

R71
SW@20K/F_4

52

3

1

ZQK

ZQK

ZQK

Q6
SW@FDMC4435BZ

23 46Monday, January 07, 2013

23 46Monday, January 07, 2013

23 46Monday, January 07, 2013

1A

1A

1A

1

eDP Power (LDS)

C227

1u/6.3V_4

A A

INT_LVDS_DIGON[7]

R244 0/J_4

eDP Backlight Control (LDS)

INT_LVDS_BLON[7]

B B

R319 0/J_4

R312

100K/J_4

2N7002DW

Q25

+3V

R243
100K/J_4

+3V

5

2

1st: AL002821000 (BCD)
2nd: AL003512000 (ANC)

U18

6

IN

4

IN

3

ON/OFF

AP2821KTR-G1

R320

R314

10K/J_4

10K/J_4

BL#

6

2

1

4 3

OUT
GND
GND

1
2
5

1 3

BL_ON

LCDVCC1

C242
*0.1u/10V_4

+3VPCU

R313
*100K_4

2

Q24
DTC144EUA

3

D10
RB500V-40

R583 0/J_8
C248
*2.2u/6.3V_6

LID#,EC intrnal PU

C620

0.1u/10V_4

LID# [31,34]

EC_FPBACK# [34]

4

LCDVCC

C630

0.01u/25V_4

C604

22u/6.3V_8

5

eDP (LDS)

MAX 4 lane signals

Touch Panel

6

Layout Notes:
Place decoupling CAPs close to Connector

EDP_TXP3[2]
EDP_TXN3[2]

EDP_TXP2[2]
EDP_TXN2[2]

eDP

CCD

USBP3+[9]
USBP3-[9]

EDP_TXP1[2]
EDP_TXN1[2]

EDP_TXP0[2]
EDP_TXN0[2]

EDP_AUXP[2]
EDP_AUXN[2]

USBP8+[9]

USBP8-[9]

COLOR_ENG[34]

1

*DLW21HN900SQ2L_C

1

*TPL@DLW21HN900SQ2L_C

VIN

LCDVCC

+3V
+5V

C260 0.1u/10V_4
C261 0.1u/10V_4

C262 0.1u/10V_4
C263 0.1u/10V_4

C264 0.1u/10V_4
C265 0.1u/10V_4

C266 0.1u/10V_4
C267 0.1u/10V_4

C268 0.1u/10V_4
C269 0.1u/10V_4

R241 0/J_4

L18

3

443

2

1

2

R233 0/J_4

R234 TPL@0/J_4

L19

3

443

2

1

2

R235 TPL@0/J_4

R316 0_6
R315 0_6

R295 0_6
R311 TPL@0_6

R794 *0/J_4

EDP_HPD[2]

+3V

EDP_TXP3_C
EDP_TXN3_C

EDP_TXP2_C
EDP_TXN2_C

EDP_TXP1_C
EDP_TXN1_C

EDP_TXP0_C
EDP_TXN0_C

R305 100K/J_4

eDP_AUXP_C
eDP_AUXN_C

R306 100K/J_4

7

LCD_VIN

LCDVCC

CCD_PWR

TP_PWR

LVDS_BRIGHT
BL_ON

EDP_HPD

USBP8+_R
USBP8-_R

USBP3+_R
USBP3-_R

TP_GND

R309
TPL@0_6

Reserve for GND noise

TP_INT

BOARD_ID4[9,10]

CN8

G_5

40
39
38
37
36
35
34
33
32

G_4

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

G_1
9
8
7
6
5
4
3
2
1

G_0

CVS5402M1RA-NH

8

G_6

24

Inform BIOS that it is touch panel or not

C C

CCD_PWR VIN

C276

C272

*10p/50V_4

1000p/50V_4

Touch Panel interrupt signal：

eDP Brightness Control (LDS)

D D

1

From PCH

1001：：：：Un-stuff 0.1uF to prevent backlight
flicker issue when reduce brightness

INT_LVDS_BRIGHT[7]

2

R318 0/J_4

3

LVDS_BRIGHT

C281
*0.1u/10V_4

R317
*100K/J_4

4

1016：Exchange Q59 pin 1 & 3 direction to prevent leakage

+3V_S5

R610
*TPL@10K/J_4

TP_INT_PCH[10]

TP_INT_PCH TP_INT

5

+3V +3V

3

2

Q59

TPL@2N7002K

1

6

R639
*TPL@10K/J_4

+3V+3V_S5

C275

C271

1000p/50V_4

4.7u/25V_8

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

TP_PWR

ZQK

ZQK

ZQK

24 46Monday, January 07, 2013

24 46Monday, January 07, 2013

24 46Monday, January 07, 2013

C277
TPL@1000p/50V_4

8

C273
*TPL@10p/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

eDP/CAMERA/LID

eDP/CAMERA/LID

eDP/CAMERA/LID

1A

1A

1A

5

HDMI Cost Reduced level shift (HDM) HDMI connector (HDM)

INT_HDMITX2N[7]
INT_HDMITX2P[7]

INT_HDMITX1N[7]
INT_HDMITX1P[7]

D D

INT_HDMITX0N[7]
INT_HDMITX0P[7]

INT_HDMICLK+[7]
INT_HDMICLK-[7]

Layout Notes:
Place decoupling CAPs close to Connector

C C

C524 0.1u/10V_4
C523 0.1u/10V_4

C526 0.1u/10V_4
C525 0.1u/10V_4

C12 0.1u/10V_4
C11 0.1u/10V_4

C13 0.1u/10V_4
C14 0.1u/10V_4

*100K/F_4

+3V

R19

INT_HDMITX0N_C
INT_HDMITX0P_C

INT_HDMICLK+_C
INT_HDMICLK-_C

2

12

3

1

R15
680/J_4

Q1

2N7002K

12

4

R14
680/J_4

INT_HDMITX2N_C
INT_HDMITX2P_C

INT_HDMITX1N_C

INT_HDMITX1P_C

12

12

R12

R13

680/J_4

680/J_4

12

R443
680/J_4

12

R444
680/J_4

12

R441
680/J_4

12

R442
680/J_4

3

+5V

Q3

3

IN

AP2331SA-7

OUT

GND

1
2

C2
*220p/50V_4

2

D1

*5V/30V/0.2p_4

HDMI_MB_HP

12

RV1

*5V/30V/0.2p_4

INT_HDMITX2P_C
INT_HDMITX2N_C

INT_HDMITX1P_C
INT_HDMITX1N_C

INT_HDMITX0P_C
INT_HDMITX0N_C

INT_HDMICLK+_C
INT_HDMICLK-_C

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

HDMI_5V

R11 0/J_4

R17
20K/J_4

*1000p/50V_4

HP_DET_CN

C4

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

C3
*1000p/50V_4

1

CN2

SHELL1

D2+

SHELL3
D2 Shield
D2­D1+
D1 Shield
D1­D0+
D0 Shield
D0­CK+
CK Shield
CK­CE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET

SHELL4

SHELL2

ABA-HDM-022-P05

20
22

23
21

25

HDMI DDC (HDM)

+3V

+3V

R463

2.2K/J_4

R462

2.2K/J_4

B B

HDMI_DDCCLK_SW[7]

A A

HDMI_DDCDATA_SW[7]

R470 0/J_4

R469 0/J_4

5

HDMI_DDCCLK_COM HDMI_DDCCLK_MB

+3V

Q38

2

BSN20

1

+3V

Q37

2

BSN20

1

4

+5V

D20

RB500V-40

R439

3

RB500V-40

3

2.2K/J_4

Follow CRB 1.0 change to 2.2K

+5V

D19

R438

2.2K/J_4

Follow CRB 1.0 change to 2.2K

HDMI_DDCDATA_MBHDMI_DDCDATA_COM

EMI (EMC)

INT_HDMITX2P_C

R435 *100/F_4

INT_HDMITX1P_C

R436 *100/F_4

INT_HDMITX0P_C

R9 *100/F_4

INT_HDMICLK+_C

R10 *100/F_4

3

INT_HDMITX2N_C

INT_HDMITX1N_C

INT_HDMITX0N_C

INT_HDMICLK-_C

HDMI-detect (HDM)

HDMI_HP[7]

2

+3V

R16
1M/J_4

2

Q4

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

3

HDMI_MB_HP

2N7002K

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

HDMI

HDMI

HDMI

ZQK

ZQK

ZQK

1

25 46Monday, January 07, 2013

25 46Monday, January 07, 2013

25 46Monday, January 07, 2013

1A

1A

1A

1

mSATA Redriver (HDD)

RD_POWER

A A

A_PRE0

R818 *RD@4.7K/J_4

A_PRE1

R817 *RD@4.7K/J_4

R842 *ASM@0/J_4

B_PRE0

R816 *RD@4.7K/J_4

B_PRE1

R815 *RD@4.7K/J_4

R843 *ASM@0/J_4

TEST

R814 *RD@4.7K/J_4

+1.5V RD_POWER

B B

R827 PS8@0/J_4

R838 ASM@0/J_4

+3V

C868 ASM@0.1u/10V_4
C869 ASM@0.1u/10V_4
C870 ASM@0.1u/10V_4
C871 ASM@0.1u/10V_4

Closed to ASM1466 Power Pin

C C

SATA_TXP1[8]
SATA_TXN1[8]

SATA_RXN1[8]
SATA_RXP1[8]

D D

C862 RD@0.01u/25V_4
C864 RD@0.01u/25V_4

C865 RD@0.01u/25V_4
C863 RD@0.01u/25V_4

C867
ASM@10u/6.3V_6

1

Pre-emphasis level setting for Channel A,

3.3V tolerant. Internally pulled down at
~150K次
[A_PRE1, A_PRE0] ==
00: no pre-emphasis
01: 2dB pre-emphasis is selected
10: 3.5dB pre-emphasis is selected
11: 5dB pre-emphasis is selected

Pre-emphasis level setting for Channel B,

3.3V tolerant. Internally pulled down at
~150K次
[B_PRE1, B_PRE0] ==
00: no pre-emphasis
01: 2dB pre-emphasis is selected
10: 3.5dB pre-emphasis is selected
11: 5dB pre-emphasis is selected

Chip test mode enable, internally pulled down at ~150K次
L: Normal operation
H: Test mode enable
For SATA/SAS PHY test, this pin should be pulled to High

RD_POWERRD_POWER

SATA_TXP1_ C
SATA_TXN1_C

SATA_RXN1_ C
SATA_RXP1 _C

RD_POWER

C860
RD@0.1u/10V_4

C861
PS8@0.01 u/25V_4

2

R812

*PS8@4.99K/F_4

R839 ASM@0/J_4

U51

1

A_INp

2

A_INn

3

GND

4

B_OUTn

5

B_OUTp

R840 ASM@4.7K/J_4

C855

*PS8@1u/6.3V_4

SATA_TXP1
SATA_TXN1

SATA_RXN1
SATA_RXP1

2

Note:
REXT can be left open or connected to VDD with default
swing setting

RD_POWER

TEST

A_PRE1

B_PRE1

REXT

20

19

18

17

16

VDD

TEST

REXT

A_PRE1

VDD6EN7B_PRE08A_PRE09I2C_EN#

B_PRE0

R819 NRD@0/J_4
R820 NRD@0/J_4

R821 NRD@0/J_4
R822 NRD@0/J_4

15

B_PRE1

A_OUTp
A_OUTn

RD@PS8521A/ASM1466

10

A_PRE0

I2C_EN

R841
ASM@2K/F_ 4

SATA_TXP1_ PS

14

SATA_TXN1_P S

13

GND

12

B_INn

11

SATA_RXN1_ PS

B_INp

SATA_RXP1 _PS

R813 ASM@4.7K/J_4

SATA_TXP1_ R
SATA_TXN1_R

SATA_RXN1_ R
SATA_RXP1 _R

3

MINI-CARD WLAN(MPC)

+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA

BT_POWE RON[34]

CL_RST1#[9]
CL_DATA1[9]

CL_CLK1[9]

Layout Notes:
Place decoupling CAPs close to Connector

PCIE_TX8+[9]
PCIE_TX8-[9]

PCIE_RX8+[9]
PCIE_RX8-[9]

CLK_PCIE_WLAN[9]
CLK_PCIE_WLAN#[9]

R737 0/J_4
R732 *0 /J_4
R730 *0 /J_4
R727 *0 /J_4

C769 0.1u/10V _4
C765 0.1u/10V _4

CLK_PCIE_WLAN_REQ#_R

mSATA (HDD)

R828 RD@0/J_4
R829 RD@0/J_4

R830 RD@0/J_4
R831 RD@0/J_4

RD_POWER

R823 NRD@0/J_4
R824 NRD@0/J_4

R825 NRD@0/J_4
R826 NRD@0/J_4

3

SATA_TXP1_ PS_R
SATA_TXN1_P S_R

SATA_RXN1_ PS_R
SATA_RXP1 _PS_R

CLK_LPC_ DEBUG[9]

SATA_TXP1_ PS_R
SATA_TXN1_P S_R

SATA_RXN1_ PS_R
SATA_RXP1 _PS_R

SATA_TXP1_ PS_R
SATA_TXN1_P S_R

SATA_RXN1_ PS_R
SATA_RXP1 _PS_R

PLTRST#[9,16,27,28,34]

Close to connector

C854 0.01u/25V_4
C853 0.01u/25V_4

C852 0.01u/25V_4
C851 0.01u/25V_4

CL_RST1#_WLAN
CL_DATA1_WLAN
CL_CLK1_ WLAN

+WL_VDD

PCIE_TX8+_C
PCIE_TX8-_C

PCIE_W AKE#_R

4

Check LED signal. (active high or low)

H=5.2mm

CN13

51

+3V

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

LTS_AAA-PCI-092-P05

R771 0/J_8

+3V_SATA

10u/6.3V _6

C811

53

+3.3V

+1.5V
LED_WPAN#
LED_WLAN#

LED_WWAN#

USB_D+

USB_D-

SMB_DATA

SMB_CLK

+1.5V

+3.3Vaux

PERST#

W_DISABLE#

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

+3.3V

GND54GND

0.1u/10V _4

GND

GND

GND

GND

GND

GND

H=4.95mm

CN22

Debug

R434 0/J_4
R433 0/J_4

SATA_TXP1_ PS_C
SATA_TXN1_P S_C

SATA_RXN1_ PS_C
SATA_RXP1 _PS_C

4

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

SATA_Tp0

31

SATA_Tn0

29

GND

27

GND

25

SATA_Rn0

23

SATA_Rp0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

LTS_AAA-PCI-092-P05

53

LED_WPAN#
LED_WLAN#

LED_WWAN#

W_DISABLE#

5

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

C520

+3.3V
+1.5V

USB_D+
USB_D-

SMB_DATA

SMB_CLK

+1.5V

+3.3Vaux

PERST#

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V
+3.3V

GND54GND

5

GND

GND

GND

GND

GND

GND

0.1u/10V _4

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

+WL_VDD
+1.5V_Mini1 _VDD

TP41

WLAN_CLK_SDATA
WLAN_CLK_SCLK

C521

+1.5V_Mini1 _VDD
+WL_VDD

+1.5V_Mini1 _VDD
+WL_VDD

R704 *0 /J_4
R701 0/J_4

RF_EN [34]

R706 *0 /J_4

LAYOUT NOTE:
CLOSE TO CONNECTOR

rating = 1000mA @ 128G

+3V_SATA

Debug

A_LFRAME#_R

R432 0/J_4

A_LAD3_R

R431 0/J_4

A_LAD2_R

R430 0/J_4

A_LAD1_R

R429 0/J_4

A_LAD0_R

R428 0/J_4

USBP10+ [9]
USBP10- [9]

IOAC_LANPWR#[34]

WLAN_O FF [34]

R1
R2
R3

6

+3VPCU

20120217 reserve R648 PU 100k.

PLTRST#
IOAC_PCIE RST#

LPC_LFRAME# [8,27 ,34]
LPC_LAD3 [8,27,34]
LPC_LAD2 [8,27,34]
LPC_LAD1 [8,27,34]
LPC_LAD0 [8,27,34]

6

20120221 add R1 for PLTRST#.
20120216 add R2/R3 un-stuff for iRST reserve.

LAYOUT NOTE:
CLOSE TO CONNECTOR

Q63 AO3413

1

R708
*100K/J_4

IOAC_PCIE RST# [28,34]
PCIERST# [28,34]

20111122 change to PMOS

3

2

+3V_WL AN

Leakage circuit (MPC)

SMB_PCH_DAT[9,23]

SMB_PCH_CLK[9,23]

CLK_PCIE_WLAN_REQ#[9]

[34]

WAKE_ SRC_1

7

1

Mini card +3V power enable

High

Mini card +3V power disable

R721 0/J_8

C773
10u/6.3V _6

+WL_VDD

C787

0.1u/10V _4

+1.5V_Mini1 _VDD

500mA for +1.5V

C766

C784

*0.1u/10V_4

*1000p/5 0V_4

20120105 Change power plant for leakage issue.

2N7002DW

S5

S5

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

7

Monday, January 07, 2013

5

4 3

2
6

1

Q30

20120105 Change power plant for leakage issue.

2N7002DW

5

4 3

2
6

1

Q28

R342 *0/J_4
R347 *0/J_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Mini Card/mSATA

Mini Card/mSATA

Mini Card/mSATA

+3V_S5

+3V_S5

8

C762
*0.1u/10V_4

R692 *0 /J_8

C722
*10u/6.3V_6

+WL_VDD

R361

4.7K/J_4

+WL_VDD

R341

4.7K/J_4

8

26

+WL_VDD

C707
*0.1u/10V_4

+1.5V

R358

4.7K/J_4

IOAC

WLAN_CLK_SDATA

WLAN_CLK_SCLK

R348

4.7K/J_4

IOAC

CLK_PCIE_WLAN_REQ#_R

PCIE_W AKE#_R

ZQK

ZQK

ZQK

4626

4626

4626

1A

1A

1A

1

2

3

MAIN SATA HDD (HDD) TPM (TPM)

4

27

A A

B B

CN11

SATA_HDD

R352 0_8

19

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

1

1

+5V_HDD

SATA_RXP0_C
SATA_RXN0_C

SATA_TXN0_C
SATA_TXP0_C

+5V

C732

*100u/6.3V_1206

C388

+

10u/6.3V_6

Layout Notes:
Place decoupling CAPs close to Connector

C694 0.01u/25V_4
C683 0.01u/25V_4

C677 0.01u/25V_4
C676 0.01u/25V_4

SATA_RXP0 [8]
SATA_RXN0 [8]

SATA_TXN0 [8]
SATA_TXP0 [8]

C358
*0.1u/25V_4

C359
*0.1u/25V_4

+5V_HDD

C386

0.01u/25V_4

C357

0.01u/25V_4

CN17

CLKRUN#[7,34]

PLTRST#[9,16,26,28,34]

+3V_S5

+3V

SERIRQ[8,34]

LPCPD#[7]
LPC_LAD0[8,26,34]
LPC_LAD1[8,26,34]

LPC_LFRAME#[8,26,34]

PCLK_TPM[9]

LPC_LAD2[8,26,34]
LPC_LAD3[8,26,34]

R410 TPM@0/J_4

C794 TPM@0.1u/10V_4

R412 TPM@0/J_4
R411 TPM@0/J_4

R408 TPM@0/J_4
C508 TPM@10p/50V_4

SERIRQ_R
LPCPD#_R

PCLK_TPM_C

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

TPM@TPM_CONN

3/5VPCU reset switch (CLG)

SW3

2

C C

3/5V_SW

3
14

5

6

C812

0.1u/16V_4

12

D33
*14V/38V/100P_4

SYS_SHDN# [3,36,41]

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

Date: Sheet of

PROJECT :

SATA-HDD/ TPM

SATA-HDD/ TPM

SATA-HDD/ TPM

4

ZQK

ZQK

ZQK

1A

1A

1A

27 46Monday, January 07, 2013

27 46Monday, January 07, 2013

27 46Monday, January 07, 2013

LAN/Card reader (LAN)

5

(1.5A) 60 mils

C307 10p/50V_4

R335
*1M/J_4

D D

C C

Y1

25MHz_XTAL

SP5[29]
SP6[29]
SP7[29]
SP8[29]
SP9[29]
SP10[29]

SP12[29]
SP13[29]

C306 10p/50V_4

2 4

1 3

CARD_3V3[29]

LAN_XTALI

LAN_XTAL2

VDD10

VDD10

VDD33
VDD33

SP5
SP6
SP7
SP8
SP9
SP10

SP12
SP13

X'tal 25MHz

R329 2.49K/F_4

MDI0+
MDI0-

MDI1+
MDI1­MDI2+
MDI2-

MDI3+
MDI3-

R797 0/J_6

CARD_3V3

Leakage circuit (LAN)

S0

CLK_PCIE_LAN_REQ#_Q

B B

S5

PCIE_LAN_WAKE#[7]

LAN_WAKE#[34]

R803 *0/J_4
R804 0/J_4

+3V_S5

+3VPCU

LANPWR#[34]

C866

0.1u/10V_4

+3V

R349
10K/J_4

R351 *0/J_4
R346 *0/J_4

R336 *0/J_8

1

R324
*100K_4

VDD33

VDD10
VDD33

U22

65

GND

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MIDP2

7

MDIN2

8

AVDD10

9

MDIP3

10

MDIN3

11

AVDD33

12

DVDD33

13

Card_3V3

14

SD_D7/xD_RDY

15

SD_D6/MS_INS#/xD_RE#

16

SD_D5/xD_CE#

2N7002DW

4 3

1

Q29

Q26 AO3413

LAN_XTALI
LAN_XTAL2

LAN_RESET

SP5
SP6
SP7
SP8
SP9
SP10

5

2
6

2

+3V_S5

3

R334 0/J_6
R333 0/J_6

63

62

61

59

64

RSET

AVDD33

AVDD10

AVDD33

CKXTAL260CKXTAL1

RTL8411BA-CG

SD_CMD/MS_D6/xD_D321SD_D3/MS_D2/xD_D222SD_D2/xD_D723GND24HSIP25HSIN26REFCLK_P27REFCLK_N28EVDD1029HSOP30HSON

SD_D4/xD_WE#17SD_D1/MS_CLK/xD_D618SD_D0/MS_D7/xD_D519SD_CLK/MS_D3/xD_D4

20

58

55

51

57

54

52

53

AVDD33

XD_CD#

DVDD10

VDD33/18

MS_D0/xD_D156MS_D4/xD_D0

SD_CD#/MS_D5/xD_ALE

S5

CLK_PCIE_LAN_REQ# [9]

40 mils

VDD33

50 mils

VDDREG

SP13

R330 *0/J_4

LED0/SPICSB

GPO_NC
LED1/SPICLK/EESK

50

49

GPO

LED0/SPICSB

LED1/SPISCK

REGOUT
VDDREG
VDDREG

ENSWREG_H

SDA/SPIDI

LED3/SPIDO

SCL/LED_CR

DVDD10

LANWAKEB

DVDD33

ISOLATEB

PERSTB

CLKREQB

SD_WP/MS_D1/xD_WP#

MS_BS/xD_CLE

VDD33/18

GND

31

32

PCIE_RXN3_C
PCIE_RXP3_C

PCIE_TXN3_C
PCIE_TXP3_C

VDD33+3V

R340
10K/J_4

PCIE_LAN_WAKE#_Q

PCU

4

If use RTL8411BAR, unstuff R330

VDD33/18VDD33-18

VDD10

10/31 modify

TP81

R331 10K/J_4

TP37

Power source mode:
Pin45 :Pull-up VDD33 for SWR mode
Pull-down for LDO mde

(1.5A) 70 mils

48

REGOUT

47
46
45

ENSWREG

44
43
42
41
40
39
38
37
36
35
34
33

IOAC_PCIERST#[26,34]

EVDD10

Layout Notes:
Place decoupling CAPs close to LAN Chip

1012
1016

R337 0/J_4

SDA/SPIDI

LED3/SPIDO/EEDO_NC
SCL/LED_CR_NC

PCIE_LAN_WAKE#_Q

R798 0/J_6

ISOLATEB
CLK_PCIE_LAN_REQ#_Q

SP12

VDD33/18

PCIERST#[26,34]

PLTRST#[9,16,26,27,34]

C385 0.1u/10V_4
C384 0.1u/10V_4

C383 0.1u/10V_4
C382 0.1u/10V_4

：：：：

LAN request pin power domain need to sync with ISOLATEB pin

：：：：

Exchange Q29 pin 3 & 4 to prevent leakage issue

VDDREG

TP38
TP40
TP39

VDD10
VDD33

R802 *0/J_4
R796 *0/J_4
R795 0/J_4

For Support DC IOAC .

PCIE_RXN3_LAN [9]
PCIE_RXP3_LAN [9]

CLK_PCIE_LANN [9]
CLK_PCIE_LANP [9]

PCIE_TXN3_LAN [9]
PCIE_TXP3_LAN [9]

VDD33

3

2

1

Transformer (LAN)

RJ45-TX0+
RJ45-TX0-

RJ45-TX1-

RJ45-TX3-

RJ45-TX3+

RJ45-TX2­RJ45-TX2+

28

R47 0/J_4

L7

MDI0+

MDI0-

MDI1+

MDI1-

+3V

R345
1K/J_4

R343
15K/F_4

MDI3-

MDI3+

MDI2-

MDI2+

C558 *6.8P/50V_4
C557 *6.8P/50V_4
C560 *6.8P/50V_4
C559 *6.8P/50V_4

C45 *6.8P/50V_4
C48 *6.8P/50V_4
C47 *6.8P/50V_4

Reserver for EMI

443

1

1

2

*HCMC0805-371MFS

R46 0/J_4

R45 0/J_4

L6

443

1

1

2

*HCMC0805-371MFS

R44 0/J_4

C20 0.01u/25V_4

R484 0/J_4

L24

443

1

1

2

*HCMC0805-371MFS

R485 0/J_4

R486 0/J_4

L25

443

1

1

2

*HCMC0805-371MFS

R487 0/J_4

3
2

3
2

3
2

3
2

MDI3+
MDI2+
MDI1+
MDI0+

MDI3­MDI2­MDI1­MDI0-

TX0P_R
TX0N_R

TX1P_R
TX1N_R

TX3N_R
TX3P_R

TX2N_R
TX2P_R

U9

1

TD+

2

TD-

8

TCT

7

TCT

TRANSFORMER
U8

6

TCT

5

TCT

3

TD+
TD-4MX-

TRANSFORMER

U30

1

TD+

2

TD-

8

TCT

7

TCT

TRANSFORMER
U31

6

TCT

5

TCT

3

TD+
TD-4MX-

TRANSFORMER

6

MX+

5

MX-

3

MCT

4

MCT

1

MCT

2

MCT

8

MX+

7

6

MX+

5

MX-

3

MCT

4

MCT

1

MCT

2

MCT

8

MX+

7

X-TX0P
X-TX0N

X-TX1P RJ45-TX1+
X-TX1N

X-TX3N
X-TX3P

TERM0

X-TX2N
X-TX2P

R471
75/F_8

TERM9

R448

C535

*SUG@1M_8

220p/3KV_1808C46 *6.8P/50V_4

1

HCMC0805-371MFS

1

HCMC0805-371MFS

1

HCMC0805-371MFS

1

HCMC0805-371MFS

D22

*SUG@BS201N

1 2

R30 *0/J_4
L2

443
1

2

R29 *0/J_4

R28 *0/J_4
L1

443
1

2

R27 *0/J_4

R452 *0/J_4
L22

443
1

2

R453 *0/J_4

R454 *0/J_4
L23

443
1

2

R455 *0/J_4

3
2

3
2

3
2

3
2

RJ45 CONNECTOR (LAN)

RJ45-TX0+

RJ45-TX0­RJ45-TX1+
RJ45-TX2+

RJ45-TX2-

RJ45-TX1­RJ45-TX3+

RJ45-TX3-

CN1

1
2
3
4
5
6
7
8

RJ45

9

9

10

10
0+
0­1+
2+
2­1­3+
3-

11

11

12

12

40 milsMax current is 1400mA

C317

4.7u/6.3V_6

C352

0.1u/10V_4

C318

0.1u/10V_4

10 mils

VDD33/18

C302

C303

*0.1u/10V_4

*4.7u/6.3V_6

Place close to pin 53

1012

：：：：

REGOUT

L20

(1.5A) 60 mils

Place Close pins-- 48

C311

0.1u/10V_4

VDD10

(1.5A) 60 mils

Place Close to LAN chip, for VDD33 pins-- 3, 8, 41, 52, 61

4

Change choke from 2.2uH to 4.7uH by FAE

VDD10

4.7uH/680mA

C312

0.1u/10V_4

C316

0.1u/10V_4

C301

4.7u/6.3V_6

C727

0.1u/10V_4

C300

0.1u/10V_4

R356

C330

0.1u/10V_4

0/J_6

EVDD10

C390
1u/6.3V_4

Close to Pin29

3

30 mils

C381

0.1u/10V_4

SURGE (LAN)

MDI1­MDI0-

MDI0+

MDI3­MDI3+ RJ45-TX3+
MDI2­MDI2+

U10

1

1

8

2

2

7

3

3

6

445

*[e-mail]

U34

1

1

8

2

2

7

3

3

6

445

*[e-mail]

U3

1

8
7
6
5

8
7
6
5

RJ45-TX1­RJ45-TX1+MDI1+
RJ45-TX0­RJ45-TX0+

RJ45-TX3­RJ45-TX2-

RJ45-TX2+

2

*[e-mail]

*[e-mail]

2
3

1
2
3

1
2
3
445

1
2
3
445

8

8

7

7

6

6

5

U28

8

8

7

7

6

6

5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

LAN-RTL8411/CARD READER

LAN-RTL8411/CARD READER

LAN-RTL8411/CARD READER

1

ZQK

ZQK

ZQK

1A

1A

28 46Monday, January 07, 2013

28 46Monday, January 07, 2013

28 46Monday, January 07, 2013

1A

C309

0.1u/10V_4

C343

0.1u/10V_4

VDD33

C351

0.1u/10V_4

C371
*4.7u/6.3V_6

Place close to pin 33

If use RTL8411BAR, unstuff C303/C302

VDDREG

Power-on Strapping

SDA/SPIDI

R338 1.5K/F_4

Close to Chip

A A

VDD33

keep routing trace at least 50 mil

C313

0.1u/10V_4

C341

0.1u/10V_4

C310

0.1u/10V_4

Place connect to Pin46/47Place Close to LAN chip, for VDD33 pins-- 11, 12, 39, 58, 63, 64

5

A

B

C

D

E

SD/MMC CARD READER (MMC)CARD READER CONNECTOR (MMC)

Share Pin

SD_D7 xD_RDY

SP1
SP2

SD_D6

SP3

SD_D5

SP4

4 4

SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16

SD_D4
SD_D1
SD_D0
SD_CLK
SD_CMD
SD_D3
SD_D2

SD_WP
SD_CD#

MS_INS# xD_RE#

MS_CLK
MS_D7
MS_D3
MS_D6
MS_D2

MS_BS
MS_D1
MS_D5
MS_D4
MS_D0

xD_CE#
xD_WE#
xD_D6
xD_D5
xD_D4
xD_D3
xD_D2
xD_D7
xD_CLE
xD_WP#
xD_ALE
xD_D0
xD_D1
xD_CD#

SP5[28]
SP6[28]
SP7[28]
SP8[28]

SP9[28]
SP10[28]

SP12[28]
SP13[28]

CARD_3V3[28]

R699 0/J_4
R700 0/J_4
R698 0/J_4
R689 0/J_4

R685 0/J_4
R687 0/J_4

R703 0/J_4
R690 0/J_4

CARD_3V3

SP5=SD_D1=MS_CLK=XD_D6

SP6=SD_D0=MS_D7=XD_D5

SP7=SD_CLK=MS_D3=xD_D4

SP8=SD_CMD=MS_D6=xD_D3

SP9=SD_D3=MS_D2=XD_D2

SP10=SD_D2=XD_D7

SP12=SD_WP=MS_D1=XD_WP#

SP13=SD_CD#=MS_D5=XD_ALE

SP13=SD_CD#=MS_D5=XD_ALE

SP12=SD_WP=MS_D1=XD_WP#

SP10=SD_D2=XD_D7

SP5=SD_D1=MS_CLK=XD_D6

SP6=SD_D0=MS_D7=XD_D5

SP7=SD_CLK=MS_D3=xD_D4

SP8=SD_CMD=MS_D6=xD_D3

SP9=SD_D3=MS_D2=XD_D2

CARD_3V3

10 mils

CARD_3V3

C708

4.7u/6.3V_6

11
10

9
8
7
6
5
4
3
2
1

CARD/DET
W/P
DATA2
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
CD/DATA3

GND

GND

13

12

SD-CARD

CN12

29

EMI

SP5=SD_D1=MS_CLK=XD_D6

SP7=SD_CLK=MS_D3=xD_D4

3 3

C751
*6P/50V_4

C734
*6P/50V_4

Place close to connector

2 2

1 1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CARD READER CONNECTOR

CARD READER CONNECTOR

CARD READER CONNECTOR

Date: Sheet of

Date: Sheet of

A

B

C

D

Date: Sheet of

PROJECT :

ZQK

ZQK

ZQK

1A

1A

1A

29 46Monday, January 07, 2013

29 46Monday, January 07, 2013

29 46Monday, January 07, 2013

E

5

Codec (ADO)

D D

+1.5V

R364
0_6

+1.5VAVDD2

C425

C428

10u/6.3V_6

0.1u/10V_4

Place next to p in 40

ADOGND

C416
10u/6.3V_6

C415
10u/6.3V_6

C413

0.1u/10V_4

R363 0_6

C412

0.1u/10V_4

R359 0_6

C423
10u/6.3V_6

Place next to p in 46

+5V

C C

+5V

+5VA

R769
*10K_4

R371
*10K_4

ADOGND

Layout Note:
Place close to Codec

+5VPVDD1

C419

C422

10u/6.3V_6

0.1u/10V_4

Place next to p in 41

+5VPVDD2

C427

0.1u/10V_4

Need check AMP
PD PIN level

C778
10u/6.3V_6

SPK-1

Spilt by DGND

R366 0_6

+3V

ADOGNDADOGND

L_SPK+
L_SPK­R_SPK­R_SPK+

COMBO_MICJD

DIGITAL

C430

0.1u/10V_4

HP

+3V

C433

+

2.2u/6.3V_6

DIGITAL

ANALOG

PD#

+3VDVDD

R733 0_6

37
38
39
40
41
42
43
44
45
46
47
48

49

C426
10u/6.3V_6

EAPD#

HP-L
HP-R

2.2u/6.3V_6

+3VCPVDD

C782

0.1u/10V_4

36

U25

CPVDD

CBP
AVSS2
LDO2-CAP
AVDD2
PVDD1
SPK-L+
SPK-L­SPK-R­SPK-R+
PVDD2
PDB
SPDIFO/GPIO2

GND

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BIT-CLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

Place next to p in 1

DMIC_DATA

DMIC

B B

DMIC_CLK

4

3

2

1

HEADPHONE/Mic combo (AMP)

30

MIC2-VREFO

C796

C456

C797

0.1u/10V_4

2.2u/6.3V_6

C434

+

R806

R807

0/J_4

*0/J_4

Place next to p in 28

C464 10u/6.3V_6

close to pin 27

ANALOG

35

CBN

CPVEE

HP-OUT-R

VREF

HP-OUT-L

MIC1-VREFO-L

AVDD1

LDO1-CAP

MIC2-VREFO

MIC1-VREFO-R

MONO-OUT

AVSS1

LINE2-L
LINE2-R
LINE1-L
LINE1-R

MIC1-R
MIC1-L
MIC2-R
MIC2-L

JDREF
Sense B
Sense A

ADOGND

24
23
22
21
20
19
18
17
16
15
14
13

25

26

27

28

29

30

31

32

33

34

ANALOG

ALC3225

12

DIGITAL

C791
10u/6.3V_6

close to pin 7

ACZ_SDIN0_R

C442 *22p/50V_4

1.6Vrms

PCBEEP BEEP_1

C461 1u/35V_6 R393 47K/J_ 4

R381 33/J_4

*10u/6.3V_6

ADOGND

ADOGND

Place next to p in 26

L_SPK2
R_SPK2

MIC2-R

MIC2-L

R399 20K/F_4

close to pin 15

PCBEEP dont cou pling any sign als if possibl e
8/17 separate P CBEEP to Digit al from Realte k suggestion

C466
100p/50V_4

1 2

5.5V/25V/410P_4

+3VDVDDIO

C452

0.1u/10V_4

Place next to p in 9

R398 39.2K/F_4

close to pin 13

D34

R380 0_6
C448
10u/6.3V_6

ADOGND

R394

4.7K/J_4

C460 *100p/50V_4

+5VA

C477

C469

10u/6.3V_6

0.1u/10V_4

ADOGND

combo MIC

HPOUT_JDSENSEA

BEEP_2

D14 RB500V-40

D13 RB500V-40

PCH_AZ_CODEC_RST# [8]

<20121018>Add D 34 for ESD

PCH_AZ_CODEC_SYNC [8]

+3V

PCH_AZ_CODEC_SDIN0 [8]

PCH_AZ_CODEC_BITCLK [8]
PCH_AZ_CODEC_SDOUT [8]

SPK-2

MIC2-R MIC2_MIC

20121009: FAE Vic request to change 0 ohm to 1K ohm

20121205: FAE Vic request to change 47 ohm to 56 ohm

Internal Speaker (AMP)

Pin1 - Pin6: DGND
Pin7 - Pin12: AGND
Thermal Pad: DGND

SPKR [8]

PCBEEP_EC [34]

Layout Note:
Place very close to U5001

R_SPK2+

R425 0_6

R_SPK2-

R424 0_6

L_SPK2-

R421 0_6

L_SPK2+

R420 0_6

20120910: ALC3225 has a internal MOSFET

C4292.2u/6.3V_6

MIC2-L

HP-L

R383 56/F_4

HP-R HP-R-1

R392 56/F_4

R_SPK2

L_SPK2

+5VA

C501

*68p/50V_4

C4242.2u/6.3V_6

C510 1u/16V_6

C479 1u/16V_6

R418 *20K/F_4

C500

*68p/50V_4

C497

*68p/50V_4

MIC2-VREFO

R369 1K/J_4

R382 0/J_6
R402 0/J_6

C804

0.1u/10V_4

close to U5001

R415 0 _6

R414
*0/J_6

R770 * 22K/F_4

C496

*68p/50V_4

2.2K/J_4

22K/F_4

+5V

C509 1u/16V_6

C490 1u/16V_6R404 0_6

ADOGND

R729

R731

ADOGND

R768 0 _6

C808
10u/6.3V_6

R403
*0/J_6

R_SPK+
R_SPK­L_SPK­L_SPK+

COMBO_MICJD

12

D11

*14V/38V/100P_4

ADOGND

12

D12

*14V/38V/100P_4

+5V_AMP

U27

9

INPUT-R

7

EAPD#

PD#

10

INPUT-L

8

BYP

ALC1001-CGT

C810

2.2u/6.3V_6

Layout Note:
Place very close to U5001

ADOGND

40mil for each signal

R427 0_6
R426 0_6
R423 0_6
R422 0_6

C776

10u/6.3V_6

ADOGND

12

D16

*14V/38V/100P_4

ADOGNDADOGND ADOGND

4

PVDD13PVDD2

OUT-RP
OUT-RN

OUT-LN

OUT-LP

G1
G2

GND

13

C502

C503

*68p/50V_4

*68p/50V_4

COMBO_MIC

HPL_SYSHP-L-1
HPR_SYS
HPOUT_JD

6
5

2
1

11
12

R_SPK+_2
R_SPK-_2
L_SPK-_2
L_SPK+_2
R_SPK+_1
R_SPK-_1
L_SPK-_1
L_SPK+_1

C499

*68p/50V_4

12

R_SPK2+
R_SPK2-

L_SPK2­L_SPK2+

R72622K/F_4

Combo Jack

CN15

4
3
1

2
5
6 7

R2

NC
NC
0
0

SIT_2SJ3052-005111F

R3

0
NC
0
NC

D17

*14V/38V/100P_4

Output Gain Table

R1

NC
0
NC
0

G1
G2

20120928：：：：Follow ME & PDC pin define

C498

*68p/50V_4

R4

0
0
NC
NC

L_SPK+_2
L_SPK-_2
L_SPK+_1
L_SPK-_1
R_SPK-_2
R_SPK+_2
R_SPK-_1
R_SPK+_1

G1
G2

ADOGND

Gain (Differential)

11dB
14dB
19dB
25dB

+5VA

R767

*0/J_4

R1 R2

R405
0/J_4

R3 R4

ADOGND

CN21

1
2
3
4
5
6
789

10

SPK CN

R766
*0/J_4

R764
0/J_4

INT DMIC (AMP)

Power(ADO) Mute(ADO)

+5V

A A

L21 UPB201209T-310Y-N/6A/31ohm_8

+5VA

DGND plane AGND plane

5

R772 *0/J_4
R716 0/J_4

R763 0/J_4
R360 0/J_4
R419 *0/J_4
C788 *1000p/50V_ 4
C803 *1000p/50V_ 4

ADOGND

Tied at one point only under
the codec or near the codec

4

+3V

0V : Power down Class D SPK amplifer

R725

3.3V : Power up Class D SPK amplifer

*10K/J_4

D32 RB500V -40

D31 RB500V -40

AMP_MUTE# [34]

PCH_AZ_CODEC_RST#

3

+3V

CN19

4
3
2

6

1

5

DMIC

12

D15

TVS/6pF_4

12

D18

TVS/6pF_4

R417 0/J_4

C482
*22p/50V_4

R416 0/J_4
C505
*22p/50V_4

2

DMIC_DATADMIC_DATA_R

DMIC_CLKDMIC_CLK_RPD# AMP_MUTE#

Quanta Computer Inc.

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PROJECT :

PROJECT :

Size Document Num ber Rev

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Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

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PROJECT :

REALTEK ALC3225

REALTEK ALC3225

REALTEK ALC3225

1

ZQK

ZQK

ZQK

1A

1A

30 4 6Monday, January 07, 2013

30 4 6Monday, January 07, 2013

30 4 6Monday, January 07, 2013

1A

5

USB3.0 (USB)

2012-06-15
Active High:
1st: AL002820003 (BCD)
2nd: AL007534001 (Promate)
3rd: AL002511002 (DDS)

USB_BC_EN

D D

C C

USB30_RX1-[9]
USB30_RX1+[9]

Layout Notes:
Place close to L6008

USB30_TX1-[9]
USB30_TX1+[9]

Layout Notes:
Place decoupling CAPs close to Connector

B B

USB_OC0#[9]

+5VPCU

USBP0-_R
USBP0+_R

USB3_RXN1_R
USB3_RXP1_R

USB3_TXN1_R
USB3_TXP1_R

C34

*1.6P/50V_4

C35 0.1u/10V_4
C36 0.1u/10V_4

C37 1u/6.3V_4
U6

2

IN1

OUT3

IN23OUT2

OUT1

4

EN

1

GND

AP2820AMMTR-G1

USBP0-_C
USBP0+_C

C33

*1.6P/50V_4

USB3_TXN1_C
USB3_TXP1_C

8
7
6

5

OC#

U4

1

GND

2

2

3

3

*RClamp0582N

U5

1

1

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

*DLW21HN900SQ2L_C

*DLW21HN900SQ2L_C

1

*DLW21HN900SQ2L_C

+5V_S5 -> +5VPCU for battery
mode can charger when enter S4/S5

USBPWR0

10

R40 0/J_4
L5

443

1

1

R39 0/J_4

R35 0/J_4

L3

1

1
443

R36 0/J_4

R37 0/J_4
L4

1
443

R38 0/J_4

+

C539
100u/6.3V_1206

6
5
4

9
7

6

2

2

2

C18
470P/50V_4

6

USBPWR0

5
4

10
9

7
6

3

USBP0-_R

2

USBP0+_R

2

USB3_RXN1_R

3

USB3_RXP1_R

2

USB3_TXN1_R

3

USB3_TXP1_R

C531

*1.6P/50V_4

Layout Notes:
Place close to L6009

USBP0-_R
USBP0+_R

USB3_RXN1_R
USB3_RXP1_R

USB3_TXN1_R
USB3_TXP1_R

USB2.0 (USB)

+5V_S5

C291 1u/6.3V_4

U20

2

IN1
IN23OUT2

4

USBON#

EN#

1

GND

AP2820CMMTR-G1

A A

USBP1+[9]

USBP1-[9]

USB_OC0#

1

*DLW21HN900SQ2L_C

R112 0/J_4
L11

1
443

R113 0/J_4

Active Low:
1st: AL007534000 (Promate)
2nd: AL002820001 (BCD)
3rd: AL002501000 (DDS)

8

OUT3

7
6

OUT1

5

OC#

2

USBP1+_CN

2

3

USBP1-_CN

5

USBP1-_CN
USBP1+_CN

C50
1000p/50V_4

12

D5
*5V/30V/0.2p_4

USBP1

+

C292
100u/6.3V_1206

12

C530

0.1u/10V_4

C532

*1.6P/50V_4

D4
*5V/30V/0.2p_4

4

USB 3.0 Connector

CN3

1

VBUS

1

2

D-

2

3

D+

3

4

4

GND

5

SSRX-

5

6

6

SSRX+

7

7

GND

8

8

SSTX-

9

SSTX+

9

11111010131312

12

AUSB0006-P001A

USBP0-_R
USBP0+_R
USB3_RXN1_R
USB3_RXP1_R

USB3_TXN1_R
USB3_TXP1_R

4

1 2

RV3 *5V/30V/0.2p_4

1 2

RV2 *5V/30V/0.2p_4
RV4 *5V/30V/0.2p_4

1 2

RV5 *5V/30V/0.2p_4

1 2

1 2

RV6 *5V/30V/0.2p_4

1 2

RV7 *5V/30V/0.2p_4

CN6

1

VDD

GND6

2

D-

GND5

3

D+

4

GND1

GND7
GND8

USB2.0

3

2

1

USB Charger to 3.0 (USB)

CB

Name

DCP,Auto S4~S5

USB data Apple DeviceMax Current

SDP
CDP

YES
YES

State

S0~S3

NO

500mA
1500mA
1800mA

500mAS0~S3
500mA
1800mA

SELCDP FuncionFuncion

0

X
1
1

DCP autodetect with mouse/keyboard wakeup

0

S0 charging with SDP only

1

S0 charging with CDP or SDP only (depending on external device)

31

CH@: Default stuff

System status(CB)
> Hi: S0 Charging with CDP/SDP.

USBP0- [9]

USBP0+ [9]

4

USB_BC_EN

> Lo: S3,DCP autodetect.

MAINON [34,37,38,41]

USB_CHG_MODE [34]

+5VPCU

C28 CH@0.1u/10V_4
C41 *CH@10u/6.3V_6

+5VPCU

BC_CEN

[34]

USBP0-_C

USBP0+_C

USB_CHG_EN

R477

CH@4.7K_4

R478

*CH@4.7K_4

Pull high CDP/SDP autodetect.
Pull Low SDP only.

CEN:SLG55584A----pull up
SLG55584----pull low

Battery Status, EC GPO control it.
> Hi: S0 and S3~S5 Battery over 30%
> Lo: S3~S5/ Battery under 30%

BC_CEN

U32

1

CEN

2

DM

3

DP

4

SELCDP

CH@SLG55584A

R483 *NCH@0_4
R482 *NCH@0_4

8

CB1

7

TDM

6

TDP

5

VDD

9

Thermal Pad

R480 CH@47K_4

USB_CHG_EN

R464 *CH@0_4
R461 CH@0_4

+3VPCU

C553 *CH@0.1u/10V_4

2
1

U33

3 5

R474 *NCH@0_4

CH@TC7SH08FU

I/O board (USB)

+5V_S5

C189 1u/6.3V_4

U17

2

IN1
IN23OUT2

3

4

EN#

1

GND

AP2820CMMTR-G1

USB_OC0#

R217 0/J_4

L17

1

*DLW21HN900SQ2L_C

R211 0/J_4

USBON#[34]

USBP4+[9]

USBP4-[9]

6
5

7
8

443
1

OUT3
OUT1

OC#

2

8
7
6

5

3

USBP4+_R

2

USBP4-_R

C222

0.1u/10V_4

USBP4

[24,34]

USBP4-_R
USBP4+_R

NBSWON#[34]

LID#

*5V/30V/0.2p_4

12

D9

2

+3VPCU

CN7

1

13

2

14
3
4
5
6
7
8
9
10
11
12

USB/B CONN

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PROJECT :

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Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

INT&EXT USB

INT&EXT USB

INT&EXT USB

ZQK

31 46Monday, January 07, 2013

31 46Monday, January 07, 2013

1

31 46Monday, January 07, 2013

1A

1A

1A

5

K/B (KBC) TOUCHPAD BOARD CONN (TPD)

CN18

26

MY0[34]
MY1[34]
MY2[34]
MY3[34]
MY4[34]
MY5[34]
MY6[34]

D D

C C

MY7[34]
MY8[34]
MY9[34]
MY10[34]
MY11[34]
MY12[34]
MY13[34]
MY14[34]
MY15[34]

[34]

MY16

[34]

MY17
MX7[34]
MX6[34]
MX5[34]
MX4[34]
MX3[34]
MX2[34]
MX1[34]
MX0[34]

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0

25

28

24

27
23
22
21
20

20121005 SWAP keyboard pin-define

19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

KB_CONN

4

7 8
5

6

3

4

1

2

CP1 *100p/50Vx4

7 8
5

6

3

4

1

2

CP2 *100p/50Vx4

7 8
5

6

3

4

1

2

CP3 *100p/50Vx4

7 8
5

6

3

4

1

2

CP6 *100p/50Vx4

7 8
5

6

3

4

1

2

CP4 *100p/50Vx4

7 8
5

6

3

4

1

2

CP5 *100p/50Vx4
C515 *100p/50V_4

C514 *100p/50V_4

+3VPCU

RP2 10K_10P8R

10

9

MX7

8

MX6

7 4

MX5
MX4

3

MX5
MX4
MX3
MX2

MY1
MY0
MX7
MX6

MY5
MY4
MY3
MY2

MY9
MY8
MY7
MY6

MY13
MY12
MY11
MY10

MY17
MY16
MY15
MY14

MX1
MX0

1

MX0

2

MX1

3

MX2
MX3

56

+3V
+5V

TPCLK[34]

TPDATA[34]

C475

*0.01u/16V_4

R391 0/J_4
R397 *0/J_4

R389
10K/J_4

C474

*0.01u/16V_4

R390
10K/J_4

R759 0/J_4
R758 0/J_4

SMBALERT#[9]

+3V
+5V

L32 0_6
L33 *0/J_6

3

Q36

*2N7002K

+3V

2

2

C798

0.1u/10V_4

50mil

CLK_SDATA[9,13,15]

CLK_SCLK[9,13,15]

BOARD_ID2[9,10]

Pin8 of SYNAPTICS and ELAN are NC pin

1

+TPVDD

R757 0/J_4
R756 0/J_4

TP_INT#_D

TPCLK_R
TPDATA_R

CLK_SDATA_R

CLK_SCLK_R

R837 *0/J_4

CN16

1
2
3
4
5
6
789

TP CN

1

32

10

KB_BL LED (KBC)

B B

+5V +5V

C504 *KBL@2.2u/10V_6

R413
KBL@10K/J_4

[34]

KEY_BL_EN

A A

2

Q35

KBL@DTC144EUA

1 3

5

1

Q34
KBL@AO3413

2

3

C465
KBL@4.7u/6.3V_6

R760 KBL@0/J_4
C799
KBL@0.01u/25V_4

+5V_KB_R+5V_KB

CN20

1
2

5

346

KBL@KB_backlight

4

FAN1 For CPU (THM)

[34]

CPUFAN1

FAN2 For GPU (THM)

[34]

CPUFAN2

3

+3V

R339
1K/J_4

2

1 3

Q27
MMBT3904-7-F_200MA

+3V

R445
1K/J_4

2

1 3

Q2
MMBT3904-7-F_200MA

+5V

R696
10K/J_4

[34]

FANSIG1

FAN_PWM_CN1

30mil

+5V

R437
10K/J_4

[34]

FANSIG2

FAN_PWM_CN2

30mil

+5V

+3V

R695

R691
0/J_8

10K/J_4

+5V

+3V

R440
10K/J_4

+5V_FAN1

R449
0/J_8

+5V_FAN2

2

CN10

345
2
1

CN5

345
2
1

FAN1

FAN2

6

6

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Date: Sheet of

Date: Sheet of

PROJECT :

KB/TP/FAN

KB/TP/FAN

KB/TP/FAN

ZQK

1A

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32 46Monday, January 07, 2013

32 46Monday, January 07, 2013

1

32 46Monday, January 07, 2013

1A

LED(UIF)

5

4

3

2

1

HOLE(OTH)

33

Power LED

D D

PWRLED#[34]
SUSLED#[34]

Battery

R6 *1M_4
R5 *1M_4

R2 100/J_4
R1 150/J_4

R7 *1M_4
R8 *1M_4

+3V_S5

3
4

LED1 BATTERY LED

+3VPCU

Blue

Amber

+3V_S5

+3VPCU

2
1

+3VPCU

HOLE5

*hg-c236d118p2

8
9

123

67
5
4

HOLE1

*hg-c236d118p2

67
5

8

4

9

123

HOLE6

*HG-TE382X675BC236D118NPTPB

67
5

8

4

9

123

HOLE11

*hg-c236d118p2

8
9

123

HOLE9

*hg-c236d118p2

8
9

123

HOLE21

67
5
4

67
5
4

*hg-c236d118p2

67
5

8

4

9

123

HOLE17

*hg-te394x315be394x313d244p2

45
3

6

1

2

HOLE22

*hg-e394x325d165p2

45
3

6

1

2

Blue

BATLED0#[34]
BATLED1#[34]

C C

R3 100/J_4
R4 150/J_4

3
4

LED2 BATTERY LED

Amber

2
1

BATT Enable short pad

HOLE13

*h-te236x236bc236d165p2

23

1

HOLE19

*h-te236x236bc236d158p2

23

1

3

Lid Switch

SW2

2
14

Stitching cap (EMC)

BATT_EN# [35]

VIN VIN VIN VIN VIN

C806
*0.1u/25V_4

+VCC_GFX

B B

C790
*0.1u/25V_4

+5VPCU +5VPCU +5VPCU

C305
*0.1u/25V_4

A A

C491
*0.1u/25V_4

+1.05V_VTT +1.05V_VTT +1.05V_VTT +1.05V_VTT

C235
*0.1u/25V_4

+1.05V_VTT

C807
*0.1u/25V_4

C659
*0.1u/25V_4

C205
*0.1u/25V_4

C805
*0.1u/25V_4

C549
*0.1u/25V_4

VIN

+5VPCU

+5V_S5

C259
*0.1u/25V_4

C5
*0.1u/25V_4

C308
*0.1u/25V_4

C800
*0.1u/25V_4

+VCC_GFX

+1.05V_VTT

C576
*0.1u/25V_4

+VGPU_CORE

C288
*0.1u/25V_4

+5V_S5

+1.05V_VTT

+VGPU_CORE

+1.05V_VTT

C820
*1000p/50V_4

C228
*0.1u/25V_4

VIN

C818
*1000p/50V_4

HOLE3

*hg-c276d118p2

8
9

123

HOLE7
FBAJ2003010

1

*spad-e858x1268

12345

PAD1

67
5
4

HOLE10
FBAJ2003010

6

1

HOLE12

*hg-c276d118p2

8
9

123

HOLE14
*H-TC150BC217D150P2

1

HOLE8

*HG-C236D118P2

67
5
4

HOLE15
*H-TC150BC217D150P2

67
5

8

4

9

123

1

HOLE4
FBAJ2005010

1

HOLE16
*H-TC150BC217D150P2

1

HOLE18
FBAJ2005010

1

HOLE23

*HG-C236D118P2

8
9

123

HOLE20
*h-c91d91n

1

67
5
4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZQK

ZQK

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

LED/ Hole

LED/ Hole

LED/ Hole

ZQK

1A

1A

33 46Monday, January 07, 2013

33 46Monday, January 07, 2013

33 46Monday, January 07, 2013

1

1A

5

EC(KBC)

+3VPCU_EC and +3V_RTC
minimum trace width 12mils.

R223 2.2_6

+3VPCU

D D

+3VPCU

C C

Please do not place any
pull-up resistor
on GPG0, GPG2, and GPG6
(Reserved
hardware strapping).

B B

1 2

39P/50V_4

D7

R168

SDMK0340L-7-F

100K_4

1 2

2 1

WRST#

C126
1U/6.3V_4

CLK_PCI_EC

R150
*22_4

Layout Notes:
Place Series Resistors close to ITE8587

C118
*10p/50V_4

R527
*10K_4

SUSON[37]

100K/J_4

PCH_SPI_SI_EC
PCH_SPI_SO_EC

R526
*10K_4

C850

R832

[19]

L16
BLM11A05S/0.2A/120ohm_6

C79

0.1u/10V_4

LPC_LAD0[8,26,27]
LPC_LAD1[8,26,27]
LPC_LAD2[8,26,27]
LPC_LAD3[8,26,27]

CLK_PCI_EC[9]

LPC_LFRAME#[8,26,27]

SIO_A20GATE[10]

[8,27]

SIO_EXT_SMI#[10]

SIO_EXT_SCI#[10]

SIO_RCIN#[10]
+0.75V_ON[37]

BT_POWERON[26]

[7]

PWROK_EC

[32]

KEY_BL_EN

AMP_MUTE#[30]

COLOR_ENG[24]

DPWROK[7]

SLP_SUS#[7,11]

LAN_WAKE#[28]

FB_CLAMP_TGL_REQ#

PCBEEP_EC[30]

PCH_SPI_CLK_EC[8]

SPI_CS0#_UR_ME[8]

PCH_SPI_SI_EC[8]

PCH_SPI_SO_EC[8]

BATLED1#[33]

[4]

EC_DRAMRST_CNTRL

12 mils

C174

0.1u/10V_4

PLTRST#[9,16,26,27,28]

SERIRQ

MAINON[31,37,38,41]

LID#[24,31]

D/C#[35]

MY16[32]
MY17[32]

+3VPCU_EC

MY0[32]
MY1[32]
MY2[32]
MY3[32]
MY4[32]
MY5[32]
MY6[32]
MY7[32]
MY8[32]

MY9[32]
MY10[32]
MY11[32]
MY12[32]
MY13[32]
MY14[32]
MY15[32]

TP7

C220

0.1u/10V_4

+3V

R834 100K/J_4

PROCHOT_EC

HWPG

R134 10K_4

C80

0.1u/10V_4

R126 0_6

C150

0.1u/10V_4

ECAGND

C114

0.1u/10V_4

C106

0.1u/10V_4

10

9
8

7
22
13

6
17

126

5
15
23
14

4
16

119
123

80

104

33
88
81
87

109
108

71
72
73
35
34

107

95
94

105
101
102
103

56
57
32

100
106

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55

MX0[32]
MX1[32]
MX2[32]
MX3[32]
MX4[32]
MX5[32]
MX6[32]
MX7[32]

4

+A3VPCU

12 mils

+3V_RTC

+3VPCU_EC

C221

0.1u/10V_4

+3V_EC

U15

LAD0/GPM0(X)
LAD1/GPM1(X)
LAD2/GPM2(X)
LAD3/GPM3(X)
LPCRST#/WUI4/GPD2(Up)
LPCCLK/GPM4(X)
LFRAME#/GPM5(X)

LPCPD#/WUI6/GPE6(Dn)
GA20/GPB5(X)

SERIRQ/GPM6(X)
ECSMI#/GPD4(Up)
ECSCI#/GPD3(Up)
WRST#
KBRST#/GPB6(X)
PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT

CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn)

DAC4/DCD0#/GPJ4(X)
DSR0#/GPG6(X)
GINT/CTS0#/GPD5(Up)
PS2DAT1/RTS0#/GPF3(Up)
DAC5/RIG0#/GPJ5(X)
PS2CLK1/DTR0#/GPF2(Up)
TXD/SOUT0/GPB1(Up)
RXD/SIN0/GPB0(Up)

ADC5/DCD1#/WUI29/GPI5(X)
ADC6/DSR1#/WUI30/GPI6(X)
ADC7/CTS1#/WUI31/GPI7(X)
RTS1#/WUI5/GPE5(Dn)
PWM7/RIG1#/GPA7(Up)
DTR1#/SBUSY/GPG1/ID7(Dn)
CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)

FSCK/GPG7
FSCE#/GPG3
FMOSI/GPG4
FMISO/GPG5

KSO16/SMOSI/GPC3(Dn)
KSO17/SMISO/GPC5(Dn)
PWM6/SSCK/GPA6(Up)

SSCE0#/GPG2(X)
SSCE1#/GPG0(X)

KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15

C95

0.1u/10V_4

11

114

VCC

VSTBY26VSTBY50VSTBY92VSTBY

LPC

CIR

EXTERNAL SERIAL FLASH

SPI ENABLE

KBMX

KSI0/STB#58KSI1/AFD#59KSI2/INIT#60KSI3/SLIN#61KSI462KSI563KSI664KSI7

121

VSTBY

UART port

65

3

74

VBAT

+3VPCU_ECPLL

127

AVCC

IT8587

1

L13
BLM11A05S/0.2A/120ohm_6

VSTBY

VSS

C78

0.1u/10V_4

84

82

EGCS#/WUI26/GPE2(Dn)83EGCLK/WUI27/GPE3(Dn)

VSS27VSS49VSS

91

EGAD/WUI25/GPE1(Dn)

VSS

113

L10

BLM11A05S/0.2A/120ohm_6

dGPU_OPP#

R517 AC@0_4

20

19

97

WUI41/GPH5/ID5(Dn)98WUI42/GPH6/ID6(Dn)99WUI19/GPH3/ID3(Dn)96WUI40/GPH4/ID4(Dn)

L80LLAT/WUI7/GPE7(Up)

L80HLAT/BAO/WUI24/GPE0(Dn)

GPIO

+3VPCU_EC

(For PLL Power)

93

PECI/SMCLK2/WUI22/GPF6(Up)

SMDAT2/WUI23/GPF7(Up)

PS2CLK0/TMB0/CEC/GPF0(Up)

PS2DAT0/TMB1/GPF1(Up)

SM BUS

PS2CLK2/WUI20/GPF4(Up)
PS2DAT2/WUI21/GPF5(Up)

CLKRUN#/WUI16/GPH0/ID0(Dn)

PS/2

PWM

TACH1A/TMA1/GPD7(Dn)

TMRI0/WUI2/GPC4(Dn)
TMRI1/WUI3/GPC6(Dn)

WAKE UP

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn)

A/D D/A

DAC2/TACH0B/GPJ2(X)
DAC3/TACH1B/GPJ3(X)

CLOCK

VCORE

VSS

AVSS

12

75

122

C109

0.1u/10V_4

ECAGND

3

1008

DNBSWON# [7]

SB_ACDC [35]
dGPU_OPP# [19]

S5_ON [36,41]
IOAC_LANPWR# [26]

WAKE_SRC_1

LANPWR#
USB_CHG_MODE

USB_CHG_EN

CLKRUN# [7,27]

SMCLK0/GPB3(X)
SMDAT0/GPB4(X)
SMCLK1/GPC1(X)
SMDAT1/GPC2(X)

PWM0/GPA0(Up)
PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
PWM5/GPA5(Up)

TACH0A/GPD6(Dn)

PWRSW/GPE4(Up)
RI1#/WUI0/GPD0(Up)
RI2#/WUI1/GPD1(Up)

ADC0/GPI0(X)
ADC1/GPI1(X)
ADC2/GPI2(X)
ADC3/GPI3(X)

ADC4/WUI28/GPI4(X)

TACH2/GPJ0(X)

GPJ1(X)

CK32KE/GPJ7

CK32K/GPJ6

IT8587E/EX

：：：：

Change Power rail from +3VPCU to +3VPCU_EC

[26]

[28]

[31]

[31]

110
111
115
116
117
118

85
86
89
90

24
25
28
29
30
31

47
48

120
124

125
18
21

112

66
67
68
69
70

76
77
78
79

2
128

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
EC_PECR_R

C76 10u/6.3V_6

TP114

R833

100K/J_4

R96 43_4

ECAGND

MBCLK [35]
MBDATA [35]

2ND_MBCLK [9,19]

2ND_MBDATA [9,19]

EC_PECI [3,10]

EC_FPBACK# [24]

WLAN_OFF [26]

USBON# [31]
TPCLK [32]
TPDATA [32]

PWRLED# [33]
ME_WR# [8]
SUSLED# [33]
BATLED0# [33]

[32]

CPUFAN1

[32]

CPUFAN2

[32]

FANSIG1

[32]

FANSIG2
ACIN [35]

TEMP_MBAT [35]

NBSWON# [31]

SUSB# [7]
SUSC# [7]

PCH_RSMRST#

RF_EN [26]
ICMNT [35]

[7]

APWROK

dGPU_ALT# [19]

dGPU_OTP# [19]

EC_FB_CLAMP [17,19,20]

PCH_SUSWARN# [7]

PCH_SUSACK# [7]

IOAC_PCIERST# [26,28]
VRON [40]

[7]

Input only

SM BUS ARRANGEMENT TABLE

SM Bus 1

Battery

SM Bus 2

PCH/VGA

2

S5_ON

R177 10K_4

dGPU_OPP#

R95 *10K_4

SM BUS PU(KBC)

MBCLK
MBDATA

2ND_MBCLK
2ND_MBDATA

PROCHOT_EC

2

R525
100K_4

HWPG(KBC)

HWPG_VCCSA[39]

HWPG_1.8V[41]
HWPG_VTT[38,39]
HWPG_1.5V[37]
SYS_HWPG[36]

GFX_PWRGD[7,40]

1

R102 4.7K_4
R92 4.7K_4

R98 4.7K_4
R97 4.7K_4

3

Q52

2N7002K

1

D28 RB500V-40
D27 *RB500V-40
D26 *RB500V-40
D29 *RB500V-40
D23 *RB500V-40
D25 *BAS316

+3VPCU

+3V_GFX

+3VPCU

+3V_S5

H_PROCHOT# [3,35,40]

+3V

R523

10K/J_4

HWPG

2
1

R109
*100K/J_4

+3V

U13

3 5

*TC7SH08FU

4

C66
*0.1u/10V_4

PCIERST# [26,28]

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

KBC IT8587

KBC IT8587

KBC IT8587

ZQK

ZQK

ZQK

34 46Monday, January 07, 2013

34 46Monday, January 07, 2013

1

34 46Monday, January 07, 2013

1A

1A

1A

For test only

A A

3
5

6

Power Switch

SW1

2

NBSWON#

14

5

4

iRST

20120217 reserve iRST function.

PCI_PLTRST#[3,9]

3

IOAC_PCIERST#

R110

*100K/J_4

5

CN9

1
2
3
4

Power conn

D D

C C

ACIN[34]

ACPRESENT[7]

SB_ACDC[34]

[33]

BATT_EN#

B B

PJ1

89
7

BATT_EN#

6
5

50458-00801-V01

4
3
2
1

10

A A

PU6

1

CH1

2

VN
CH23CH3

*IP4223-CZ6

Add ESD diode base on EC FAE suggestion

PR134

*0_4

CH4

VP

PR26
0_4

PC30

0.1u/50V_6

BATT_EN#

PR115
100_4

6

MBDATA

5
4

MBCLKTEMP_MBAT

5

PR25
*0_4

PC192

0.1u/50V_6

PC122

*100p/50V_4

PR130
100_4

PC86

*47p/50V_4

+3VPCU

PC31

2200p/50V_6

+3VPCU

PR33
*10K_4

PR127
100_4

PR31
100K_4

6

1

PC92
47p/50V_4

MBCLK [34]

MBDATA [34]

2

TEMP_MBAT

PR32

PC25

100K_4

0.1u/25V_4

5

PQ4
2N7002DW

4 3

BAT-V

TEMP_MBAT [34]

PR129
1M_4

+3VPCU

4

VA1

PC29

0.1u/50V_6

PD2
1N4148WS

recommend 200mA at least.

PR110
0_6

+3VPCU

PR141
10K_4

PR139
*10K_4

PR158
316K/F_4

2

24737_BM#

PQ52
*2N7002K

4

3

1

MBDATA

MBCLK

PR157
*100K_4

PR156
100K/F_4

PC112

68n/10V_4

PR153
10K/F_4

PR114
20_1206

PR154
0_4

PR155
0_4

24737_BM#

24737_CMPOUT

PC114

0.01u/25V_4

2 1

24737_ILIM

ICMNT[34]

PD7
SMAJ20A

PR152

63.4K/F_4

24737_ACDET

24737_VCC

PC89

0.47u/25V_6

24737_CMPIN

PR143
*100K_4

PC28

0.1u/50V_6

PC99

0.1u/50V_6

6

20

5

8

9

11

3

10

4

PR148

1.62K/F_4

ACDET

VCC

ACOK#

SDA

SCL

BM#

CMPOUT

ILIM

CMPIN

PR43
220K_4

PR41
220K_4

0.1u/50V_6

2

BQ24737RGRR

IOUT

7

PC113
100p/50V_4

3

PC98

ACP

3

PQ9
AOL1413

1
3

4

1 6

PU9

GND

GND22GND24GND23GND

21

24737_CMPOUT

2
3

1

ACN

25

PQ8

IMD2AT108

24737_ACP

24737_ACN

PC96

0.1u/50V_6

REGN

BTST

HIDRV

PHASE

LCDRV

PGND

SRP

SRN

PR140

*0_4

5
4

16

24737_REGN

17

24737_BST

18

24737_DH

19

24737_LX

15

14

13

12

For battery reverse

Limit set on 60W/3.16A

PR224

*100K_4

52

PR131
10_6

PR135

7.5_6

2

VA2

PD1
SBR1045SP5-13

1
2

PR42

0_4

PR116
0_6

24737_SRP

24737_SRN

+3V

3

PQ51
2N7002K

1

3

PC85
1u/16V_6

PD3
RB500V-40

PC84
47n/50V_6

0.1u/25V_4

PC111

0.1u/25V_4

0.1u/25V_4

H_PROCHOT# [3,34,40]

1 2

D/C# [34]

PQ46

MDV1528

PQ47
MDV1595S

PC116

PC115

2

PR45

0.01/F_0612

4

4

2

VIN

PR46
0_4

24737_ACN

24737_ACP

PR44
0_4

52

3

52

3

2200p/50V_6

1

1

PC174

PR85
*4.7_6

PC66
*680p/50V_6

PC67

0.1u/50V_6

PL10

6.8uH_7X7X3

24737_SRP
24737_SRN

VIN

PR72
0_4

PC72

4.7u/25V_8

PR76

0.01/F_0612

1 2

REGN MAX voltage 6.5V
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
=0.793V for 3.965A current limit

Pin10 ILIM=0.793V
Rsr = 0.01ohm

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Charger(BQ24737RGRR)

Charger(BQ24737RGRR)

Charger(BQ24737RGRR)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

PQ12
AOL1413

4

3

2

1

PC55

10u/25V_1206

ZQK

ZQK

ZQK

35 46Monday, January 07, 2013

35 46Monday, January 07, 2013

35 46Monday, January 07, 2013

35

52

PR104
10K_4

BAT-V24737_DL

10u/25V_1206

1
3

PC71
2200p/50V_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PR75
0_4

PR105
33K/F_4

PQ13
2N7002K

PC48

2200p/50V_6

1

PC52

1A

1A

1A

5

4

3

2

1

MAIND

D D

+5VPCU

VIN

+

+5VPCU
5 Volt +/- 5%

12

MAIND [5,37,41]

PC183
47u/25V_6X4.5

PC121

4.7u/25V_8

TDC : 7A
PEAK : 9A
OCP : 10A
Width : 280mil

PL16

2.2uH_7X7X3

C C

+

PC191

220u/6.3V_6X4.2

OCP:10A

L(ripple current)
=(9-5)*5/(2.2u*0.3M*9)
=3.367A
Iocp=10-(3.367/2)=8.32A

B B

Vth=(8.32A*14mOhm)+1mV=117.43mV
R(Ilim)=(117.43mV*8)/10uA
=93.944K

PC193

0.1u/50V_6

PR133
15K/F_4

PR138
10K/F_4

PR236
*4.7_6

PC184
*680p/50V_6

+15V

PC124

0.1u/50V_6

SYS_SHDN#

PC187
2200p/50V_6

MDV1528

MDV1595S

PR162
22_8

PQ55

PQ54

+15V_ALWP

SYS_SHDN# [3,27,41]

PR123
0_6

7

PGOOD

20

EN1

16

DRVH1

17

VBST1

18

SW1

15

DRVL1

2

VFB1

14

VO1

10/15 change

VL

PC97 10u/6.3V_6

13

VREG5

CS11CS2

VCLK

19

51225_CS1

51225_VCLK

PR232 97.6K/F_4

+3VPCU

SYS_HWPG[34]

SYS_SHDN#

PR144
0_4

52

4

3

1

PC108

PR146

0.1u/50V_6

52

4

3

1

1/F_6

PR113
0_4

51225_EN1
51225_DH1
51225_VBST1
51225_SW1
51225_DL1
51225_FB1

PR221
*100K/F_4

RDSon=14mohm RDSon=14mohm

PD4
1PS302

PD5
1PS302

2

1

2

1

PC125

0.1u/50V_6

PC109

0.1u/50V_6

3

3

PC110

0.1u/50V_6

PR147
0_6

51225_VIN

12

VIN

PU8

TPS51225RUKR

5

26

51225_CS2

PR227 86.6K/F_4

3V_LDO

PC93 0.1u/25V_4

3

VREG3

PR118
0_6

PC95 4.7u/6.3V_6

EN2

DRVH2

VBST2

SW2

DRVL2

VFB2

GND
GND

GND23GND24GND25GND

PR230
10K/F_4

6
10
9
8
11
4
21
22

SYS_SHDN#
51225_DH2
51225_VBST2
51225_SW2
51225_DL2
51225_FB2

PR112

1/F_6

OCP:9A

L(ripple current)
=(9-3.3)*3.3/(2.2u*0.355M*9)
~2.676A
Iocp=9-(2.676/2)=7.66A
Vth=(7.66A*14mOhm)+1mV=108.27mV
R(Ilim)=(108.27mV*8)/10uA
=86.614K

PC82

0.1u/50V_6

36

VIN

PC177
2200p/50V_6

52

PQ48

4

4

MDV1528

3

1

PL14

2.2uH_7X7X3

52

PQ50
MDV1595S

3

1

PR117
*4.7_6

PC88
*680p/50V_6

PC81

4.7u/25V_8

+3VPCU

3.3 Volt +/- 5%
TDC : 5.5A
PEAK : 7.5A
OCP : 9A
Width : 220mil

PR125

6.49K/F_4

PR122
10K/F_4

PC176

0.1u/50V_6

+3VPCU

+

PC181
220u/6.3V_6X4.2

9/10 change9/10 change

PR103
22_8

PQ15
2N7002K

+15VVIN

3

2

1

+5V_S5+3V_S5

PR120
1M_6

A A

S5_ON[34,41]

10/11 change

3

2

PQ16

PR108

2N7002K

1

5

1M_6

PR126
22_8

3

2

1

PQ17
2N7002K

3

2

1

PR93
1M_6

PQ14

2N7002K

4

VIN

PR97
*1M_6

S5D MAIND MAIND S5D

PC68
*2.2n/50V_4

4

3

+5VPCU

52

PQ39

MDV1528Q

1

+5V_S5

TDC : 1.5A
PEAK : 2A
Width : 80mil

+5VPCU

52

4

3

1

TDC : 2.5A
PEAK : 3.4A
Width : 100mil

3

PQ56

MDV1528Q

+3VPCU

52

4

+5V

MDV1528Q

3

1

TDC : 1.7A
PEAK : 2.3A
Width : 80mil

+3VPCU

3

PQ19

+3V +3V_S5

2

PQ18
AO3404

1

TDC : 1.2A
PEAK : 1.6A
Width : 50mil

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SYSTEM 5V/3V (TPS51225)

SYSTEM 5V/3V (TPS51225)

SYSTEM 5V/3V (TPS51225)

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQK

ZQK

ZQK

36 46Monday, January 07, 2013

36 46Monday, January 07, 2013

36 46Monday, January 07, 2013

1

1A

1A

1A

5

4

3

2

1

TDC : 0.75A
PEAK : 1A
Width : 40mil

D D

TDC : 0.38A
PEAK : 0.5A

+SMDDR_VREF

Width : 20mil

PC56

0.22u/10V_4

+3V

PR92

100K/F_4

PC54

51216_S551216_S3

20

17

16

19

18

26

51216_REF

PR203
10K/F_4

PR81

69.8K/F_4

C C

HWPG_1.5V[34]

MAINON[31,34,38,41]

SUSON[34]

PR96

*0_4

PR94

0_4
PR205

200K/F_4

52.3K/F_4

10/11 change

51216_S3

51216_S5

51216_MODE

51216_TRIP 51216_DRVL

VREF=1.8V

PR89
*0_4

0.1u/10V_4

B B

+0.75V_ON[34]

PR95
0_4

OCP=20A

A A

L ripple current
=(19-1.5)*1.5/(0.36u*400k*19)
=9.594A
Vtrip=20-(9.594/2)*4.3mohm
=0.065372V
Rlimit=0.065372/10uA*8=52.297Kohm

5

PGOOD

S3

S5

MODE

TRIP

PAD

+0.75V_DDR_VTT

PC64
10u/6.3V_6

22

PAD21PAD

REFIN8REF

6

51216_REFIN

5

VTTREF

TPS51216RUKR

VDDQSNS

9

PC53

0.01u/25V_4

4

PU5

25

4

PC65
10u/6.3V_6

1

VTTGND

PAD

24

37

Close to IC

Greater than or equal 40mil

+5VPCU

PC63

12

14

15

13

11

10

10u/6.3V_6

51216_DRVH

51216_VBST

51216_SW

PR86

2_6

2

3

VTT

VTTSNS

VLDOIN

V5IN

DRVH

VBST

SW

DRVL

PGND

GND

PAD23PAD

7

PR91
0_6

Mode Frequency Discharge mode

200K 400K Tracking Discharge

100K 300K Tracking Discharge

S0

S3 (mainon off)

S4/S5

PC57
1u/10V_4

PQ45

RJK03J6DPA

4

PC59

0.1u/50V_6

4

PQ44

RJK03K5DPA

RDSon=4.3mohm

S3 S5
1
0

1
1

3

5

213

5

213

PC168

2200p/50V_4

PR198
*4.7_6

PC154
*680p/50V_6

ON

4.7u/25V_8

PL13

0.36uH_10X10X4PR204

ON ON
ON ON
OFF

OFF OFF0 0

PC61

PC60

4.7u/25V_8

Close to output cap

VTTREF+1.5VSUS

OFF

2

PC156

0.1u/50V_6

VIN

+1.5VSUS

1.5 Volt +/- 5%
TDC : 14A
PEAK : 18A
OCP : 20A
Width : 560mil

+1.5VSUS

+

PC165

330u/2.5V_6X4.2

MAIND[5,36,41]

+

PC173

330u/2.5V_6X4.2

2

+1.5VSUS

3

1

PQ41
AO3404

+1.5V

TDC : 0.38A
PEAK : 0.5A
Width : 20mil

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZQK

ZQK

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR 1.5V(TPS51216)

DDR 1.5V(TPS51216)

DDR 1.5V(TPS51216)

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ZQK

37 46Monday, January 07, 2013

37 46Monday, January 07, 2013

37 46Monday, January 07, 2013

1

1A

1A

1A

5

4

3

2

1

VIN

D D

+5V_S5+3V

PC129
2200p/50V_4

PC133

4.7u/25V_8

PC131

4.7u/25V_8

+1.05V

1.05 Volt +/- 2%

38

TDC : 14A
PEAK : 17A

PR11
100K_4

HWPG_VTT[34,39]

MAINON[31,34,37,41]

C C

OCP=20A
L ripple current
=(19-1.05)*1.5/(0.68u*500k*19)
=2.918A
Vtrip=20-(2.918/2)*4.3mohm
=0.07972V

B B

Rlimit = 0.07972/10uA*8=63.781Kohm

PR169
0_4

*0.1u/10V_4

PC8

PR176
10_6

PC14
1u/6.3V_4

+3V_S5

PR171
1K/F_4

PC10

0.1u/10V_4

51219_EN
51219_V5
51219_MODE

51219_TRIP

PR175

64.9K/F_4

PR172
0_4

16

PGOOD

14

EN

9

V5

15

MODE

6

TRIP

VREF=2V

51219_REF

PR170
*10K/F_4

PR173
*11K/F_4

22

PU2

TPS51219RTER

VREF1REFIN

3

2

51219_GSNS

51219_REFIN

PC12 0.01u/25V_4

OCP : 20A
Width : 560mil

+1.05V_VTT

VCCP_SENSE [5]

VSSP_SENSE [5]

1

8

G1

S1/D2

G2

2

PQ25

D1D1D1

S2S2S2

FDMS3660S

567

9

51219_SW

PL6

0.68uH_7X7X3

PR4
*4.7_6

PC5
*680p/50V_6

Close to output cap

PR17
*100_4

PR13
*100_4

PR14
0_4

PR12
0_4

PC132

0.1u/50V_6

+

PC134

330u/2V_7343

PAD17PAD18PAD19PAD20PAD21PAD

11

DH

13

BST

12

SW

10

DL

8

PGND

GND

VSNS4GSNS

COMP

5

51219_VSNS

7

PC17

0.01u/16V_4

PC19 1n/50V_4

PC13 1n/50V_4

PR9
0_6

PR10
2_6

PR18
10_4

PR15
10_4

51219_DH

PC11

0.1u/25V_6

51219_SW
51219_DL

RDSon 4.3mOhm

RC filter is for improve
Jitter performance.

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+1.05V (TPS51219)

+1.05V (TPS51219)

+1.05V (TPS51219)

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

1

ZQK

ZQK

ZQK

1A

1A

1A

38 46Monday, January 07, 2013

38 46Monday, January 07, 2013

38 46Monday, January 07, 2013

5

4

3

2

1

39

+3V

D D

PC166

0.1u/10V_4

+5V_S5

PC171

+3V

PR90

C C

HWPG_VCCSA[34]

HWPG_VTT[34,38]

B B

PR84 0_6

PR87 0_6

PR210
0_4

PC170

*0.1u/10V_4

*100K_4

VCCSA_VID0[5]

VCCSA_VID1[5]

2.2u/6.3V_6

PC172
1u/6.3V_4

PR209
1K_4

PR208
1K_4

PR211

0_6

51461_FILT

51461_EN

18

17

16

13

14

15
25

V5DRV

V5FILT

PGOOD

EN

VID0

VID1
AGND

PR82
*33K/F_4

24

6

51461_MODE

22

VIN

VIN23VIN

PU12
TPS51463

GND1VREF2COMP3SLEW4VOUT

MODE

51461_VREF

PC162

0.22u/10V_4

3.3n/50V_4

21

PGND

PR199 4.99K/F_4

PC163

20

PGND

51461_SLEW

PC164

0.01u/16V_4

19

PGND

5

PC167
10u/10V_8

BST

SW

SW

SW

SW

SW

12

11

10

9

8

7

PC58
10u/10V_8

51461_BST

51461_SW

PC169

0.1u/50V_6

PL11

0.47uH_7X7X3

+VCCSA

+VCCSA

0.9 Volt +/- 2%
TDC : 3A
PEAK : 4A
Width : 120mil

PR202
100/F_4

PC51 10u/6.3V_6

PC161 0.1u/50V_6

PC160 10u/6.3V_6

PC158 10u/6.3V_6

PC159 10u/6.3V_6

51461_VOUT

PC50 10u/6.3V_6

PC49 10u/6.3V_6

PR201
0_4

VCCSA_SENSE [5]

PR200
*10K/F_4

VID0 +VCCSA

A A

0 0

1
1 1

default 0.9V

5

VID1

10
0 0.775V

4

0.9V

0.85V

0.75V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZQK

ZQK

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

VCCSA(TPS51463)

VCCSA(TPS51463)

VCCSA(TPS51463)

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

ZQK

1A

1A

1A

39 46Monday, January 07, 2013

39 46Monday, January 07, 2013

39 46Monday, January 07, 2013

1

5

4

3

2

1

+VCC_CORE

PC74

PR80

*330p/50V_4

*10_4

*0_4

100K/F_4

PR223

*499/F_4

PR79 0_4
PR78 0_4

PR132

200K/F_4

PR228

30.1K/F_4

PR235

PR111

1.91K/F_4

VR_SVID_ALERT#
VR_SVID_DATA
VR_SVID_CLK

1.91K/F_4

PR225

*22.6K/F_4

20K/F_4

PR226

+3V_S5+3V+1.05V_VTT

PR216

PC175

1u/6.3V_4

*100K/F_4

PR240
0_4

PR243
0_4

100K/F_4_4250NTC

PR77
*10_4

Close to the
CPU side.

51650_VREF

51650_VREF

PR98

4.7K/F_4

PR213

200K/F_4

PR217

PR220

30K/F_4

75K/F_4

PR231 *0_4

VR_SVID_CLK[5]
VR_SVID_ALERT#[5]
VR_SVID_DATA[5]

+VCC_GFX

PR244
*10_4

PR245
*10_4

Close to the
CPU side.

PR142

15.8K/F_4

PR233

Place NTC close to the
GFX_CORE Hot-Spot.

PC73
*0.01u/50V_4

PR214

PR218

PC105

*330p/50V_4

PC104
*0.01u/50V_4

52.3K/F_4

51650_COCP-R

75K/F_4

51650_CF-IMAX

51650_GOCP-R

51650_SLEW
51650_GF-IMAX
51650_GSKIP#

51650_VRON

VR_SVID_CLK
VR_SVID_ALERT#
VR_SVID_DATA

51650_VREF

1.7V
Thermal shutdown
setting 104C

PR100

15.8K/F_4

PR212
100K/F_4_4250NTC

Place NTC close to the
VCORE Hot-Spot.

4

PC180
1u/6.3V_4

2

3
13
22
24
33
15
16
17
23
21
18
19
20

51650_VREF

COCP-R
CF-IMAX
GOCP-R
SLEW
GF-IMAX
GSKIP
V3R3
VR_ON
CPGOOD
GPGOOD
VR_HOT
VCLK
ALERT
VDIO

51650_VREF

51650_GVFB

51650_VREF

PC75 47p/50V_4

PR99 6.65K/F_4

51650_CVFB

51650_CGFB

51650_CCOMP

8

9

10

11

12

14

CVFB

VREF

CGFB

CCSN3

CCOMP

PU7

TPS51650RSLR

GGFB25GVFB26GCOMP27GCSN128GCSP129GCSP230GCSN231GTHERM

51650_GGFB

51650_GCSN1

51650_GCSP1

+3V

PR145 5.49K/F_4

PC102 100p/50V_4

+3V_S5

CCSP27CCSP3

32

51650_GTHERM

6

GPWM134GPWM235CPWM3

51650_GPWM1

PC103

0.1u/10V_4

+5V_S5

PR137

PC76

10K/F_4

CTHERM

VBAT

V5

V5DRV

CDH1

CBST1

CSW1

CDL1
CDL2

CSW2

CBST2

CDH2
PGND

PAD49TPAD150TPAD251TPAD352TPAD453TPAD554TPAD655TPAD756TPAD857TPAD958TPAD1059TPAD1160TPAD1261TPAD1362TPAD1463TPAD1564TPAD16

65

51650_GSKIP#
51650_GPWM1

PR222
0_6

37
48
43
47
46
45
44
41
40
39
38
42

0.1u/10V_4

51650_VBAT
51650_V5
51650_V5DRV
51650_CDH1
51650_CBST1
51650_CSW1
51650_CDL1

51650_CBST3

51650_CTHERM

51650_CCSP1

51650_CCSN1

1

4

CCSP1

CCSN15CCSN2

36

3

PU10

1

BST

2

SKIP

3

PWM
GND4DRVL

12

PAD

13

PAD

14

PAD

TPS51601DRBR

PR102

PC79

PR239

2.2/F_6

PC188

0.22u/25V_6

DRVH

SW

VDD
PAD

PAD
PAD

10/F_6

2.2u/6.3V_4

8
7
6
5
9
10
11

+3V

VCC_SENSE[5]

D D

C C

VRON[34]
IMVP_PWRGD[3,7]
GFX_PWRGD[7,34]
H_PROCHOT#[3,34,35]

B B

VSS_SENSE[5]

Parallel

PR107 0_4

PC94

43p/50V_4

VCC_AXG_SENSE[5]
VSS_AXG_SENSE[5]

PR136

PR229

Parallel

PC87

0.1u/10V_4

+1.05V_VTT

PR119

54.9/F_4

Close to VR

PR124

130/F_4

PR121

*75/F_4

+5V_S5

PR106
*0_4

A A

51650_VRON 51650_CTHERM51650_GTHERM

PR219
100K/F_4

VR_ON PU to 5V for test mode

5

51650_CBST1

51650_CSW1

51650_CDH1

51650_CDL1

0_6

PR128

PC90

4.7u/6.3V_6

51650_CDH3
51650_CSW3

PC120
1u/10V_4

51650_CDL3

PR238
*0_4

PR237
*0_4

PR109

2.2/F_6

PC83

0.22u/25V_6

Close to the
VR side.

+5V_S5

51650_CCSP1

51650_CCSN1

51650_GCSP1

51650_GCSN1

G1

1

S1/D2

8

G2

G1

1

S1/D2

8

G2

Close to the
VR side.

2

2

D1D1D1

9

PQ49

FDMS3660S

S2S2S2

567

PC70
*0.1u/25V_4

PC69
*0.1u/25V_4

for faster response

2

D1D1D1

9

PQ53

FDMS3660S

S2S2S2

567

PC107
*0.1u/25V_4

PC106
*0.1u/25V_4

12

0.1u/50V_6

PC179

51650_CSW1

PC78

22n/16V_4

Close with
phase1 inductor

12

PC185

0.1u/50V_6

51650_CSW3

PC100

22n/16V_4

Close with
AXG inductor

PC182

4.7u/25V_8

PR101

2.2_6

PC77

2200p/50V_6

PC117

4.7u/25V_8

2.2_6

PR149

PC119

2200p/50V_6

12

PL12

0.24uH_7X7X4

1 2

3

PR207

28.7K/F_4

PR206

PR215

100K/F_4_4250NTC

PC80

4.7u/25V_8

4

PR83 0_4

PR88 16.9K/F_4

187K/F_4

12

+

2200p/50V_4

PC178

DCR=1mOhm

PC155

PC157

0.1u/10V_4

10u/6.3V_6

PC91
15u/25V_7343

+

PC62

330u/2V_7343

+VCC_CORE
TDC : 16A
PEAK : 33A
OCP : 40A
Width : 1320mil

VCORE Load Line :

2.9mV/A

AXG

12

PL15

0.24uH_7X7X4

1 2

3

PR241

26.1K/F_4

PR242

PR234

100K/F_4_4250NTC

4.7u/25V_8

4

PR151 0_4

PR150 14.3K/F_4

*191K/F_4 PC118

12

+

PC101
15u/25V_7343

PC186

2200p/50V_4

DCR=1mOhm

PC189

PC190

0.1u/10V_4

10u/6.3V_6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCC_CORE/+VGFX (TPS51650)

+VCC_CORE/+VGFX (TPS51650)

+VCC_CORE/+VGFX (TPS51650)

Monday, January 07, 2013

Monday, January 07, 2013

Monday, January 07, 2013

+VCC_GFX

+

PC123

+VCC_GFX

330u/2V_7343

TDC : 21.5A
PEAK : 33A
OCP : 38A
Width : 1320mil

GFX_CORE Load Line :

-3.9mV/A for GT2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

VIN

+VCC_CORE

VIN

ZQK

ZQK

ZQK

40

40 46

40 46

40 46

1A

1A

1A

5

4

3

2

1

10/11 change

+3VPCU

PR19
*100K/F_4

PC18

VIN

PC24
10u/6.3V_6

+3V

D D

[34]

HWPG_1.8V

MAINON[31,34,37,38]

C C

0_4

PR21

PR181

100K/F_4

PC20
1000p/50V_4

*100p/50V_4

Thermal protection

PR20
10K/F_4

PC21
1200p/50V_4

PD6
DA2J10100L

PR184
1M_6

2

PC22

0.1u/25V_4

1

PR178
121K/F_4

PQ31
AO3409

PU3 TPS54318RTER

16

VIN

1

VIN

2

VIN

14

PWRGD

15

EN

7

COMP

8

RT/CLK

9

SS

22

PC16

0.01u/25V_4

PAD17PAD18PAD19PAD20PAD21PAD

BOOT

VSNS

GND
GND

AGND

10

PH

11

PH

12

PH

PR16

13
6

0_6

PC15

3
4
5

0.1u/50V_6

PL1

1uH_7X7X3

54318_VSNS

V0=0.8*(R1+R2)/R2

PR22
100K/F_4

PR23

78.7K/F_4

R1

R2

+1.8V

1.8 Volt +/- 5%
TDC : 0.9A
PEAK : 1.22A
Width : 40mil

PC9

PC6

10u/6.3V_6

0.1u/25V_4

+1.8V

PC7

10u/6.3V_6

41

1

PU11A
BA10393F

3

PC141

0.1u/50V_6

PR183
0_6

PR185
200K_6

PC142

0.1u/50V_6

SYS_SHDN# [3,27,36]

VIN

3

2

PQ34
2N7002K

1

MAINON

MAINON_G

PR163
*100K/F_6

3

2

PQ20
2N7002K

1

PR161
1M_4

PR160
1M_4

PR159
22_8

3

2

PQ21
2N7002K

1

3

2

1

PR164
22_8

PQ22
2N7002K

+1.5V

PR165
22_8

3

2

PQ23
2N7002K

1

+15V+5V+3V

PR166
1M_4

MAIND

3

2

PQ24
2N7002K

1

PC126
*2200p/50V_4

MAIND [5,36,37]MAINON_G[3,5]

2

PR188

1.74K/F_4

VLVL

S5_ON

DTC144EUA

PR187
200K/F_4

2.469V

PR186
200K/F_4

PQ32

1 3

84

3

+

2

-

S5_ON[34,36]

B B

PR189

10K_6_NTC

3

2

S5_ON

PQ33
2N7002K

1

10/11 change

A A

LM393_PIN2

5

+

7

6

-

PU11B
BA10393F

For EC control thermal protection (output 3.3V)

5

4

3

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

+1.8V/Discharge/Thermal

+1.8V/Discharge/Thermal

+1.8V/Discharge/Thermal

ZQK

ZQK

ZQK

1

1A

1A

1A

4641

4641

4641

5

4

3

2

1

10/1 Change

PC143
*2.2n/50V_4

4

+1.5VSUS

5

213

+1.5V_GFX
TDC : 4.43A
PEAK : 5.9A
Width : 180mil

PQ36
RJK03K5DPA

+1.5V_GFX

VIN

PR57
1M_4

D D

FBVDDQ_EN[20]

PR64
0_4

PC35
*1u/10V_4

PQ11
PDTC143TT

PR60
1M_4

2

12

PR59
100K_4

1 3

PR190
22_8

3

2

PQ35
2N7002K

1

+15V+1.5V_GFX

PR40
1M_4

dGPU_D2

3

2

PQ10
2N7002K

1

42

10/5 Reserve switching power for +1.5V_GFX

C C

OCP=7.5A
L ripple current
=(19-1.5)*1.5/(2.2u*290k*19)
=2.165A
Vtrip=7.5-(2.165/2)*14mohm
=0.0898V
Rlimit=0.0898/10uA*8=71.873Kohm

VIN

PR37
1M_4

B B

1.05V_GFX_EN[20]

DGPU_PWR_EN[9]

A A

5

PR34
0_4

PC26
*1u/10V_4

PR179
0_4

PC135
*1u/10V_4

PR174
100K_4

2

12

PR35
100K_4

10/1 Change

12

PR36
1M_4

PQ5

1 3

PDTC143TT

VIN

PR177
1M_4

3

2

1

PQ29
2N7002K

PR180
1M_4

4

3

2

1

3

2

1

PR39
22_8

PQ7
2N7002K

PR182
22_8

PQ30
2N7002K

+15V+1.05V_GFX

PR38
1M_4

dGPU_D1

3

2

PQ6
2N7002K

1

+15V+3V_GFX

PR24
1M_4

dGPU_D

3

2

PQ1
2N7002K

1

PC27
*2.2n/50V_4

PC23
*2.2n/50V_4

4

2

+1.05V_VTT

52

PQ3

MDV1528Q

3

1

+3VPCU

3

PQ2
AO3404

1

+3V_GFX
TDC : 0.76A
PEAK : 1A
Width : 40mil

+1.05V_GFX

+3V_GFX

3

+1.05V_GFX
TDC : 2.3A
PEAK : 3A
Width : 100mil

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

2

Monday, January 07, 2013

PROJECT :

+VGPU_CORE(UP1642PQAG)

+VGPU_CORE(UP1642PQAG)

+VGPU_CORE(UP1642PQAG)

ZQK

ZQK

ZQK

42 46

42 46

1

42 46

1A

1A

1A

5

4

3

2

1

+5V_S5+3V

VIN

12

+

2

D D

3

1

PR48 0_4

PR47 0_4

PR70 0_4

PR52 0_4

PR192

5.1K/F_4

R6

C1

+3V_S5

R2

R3

R4

R5

PC145

2700p/50V_4

PR191 *1K/F_4

+3V

PR67 10K_4

PR50

20K/F_4

PR49

2K/F_4

PR56

18K/F_4

0_4

PR58

1642_FBRTN

DGPU_VRON[10,20]

VGPU_PSI[19]

C C

B B

VGPU_PWRGD[20]

VGPU_PWMVID[19]

PQ40

2N7002K

2

PR195
10K_4

PR193

*10K_4

100K_4

PR194

PR51
20K/F_4

PR62

2.2_6
PR196

66.5K/F_4

PC37

1u/6.3V_4

PC36

R1

PC40

0.1u/25V_4

PC44

*0.1u/25V_4

*0.1u/25V_4

1642_TON

1642_PVCC

1642_EN

1642_PSI

1642_PGOOD

1642_VID

1642_VREF

1642_REFADJ

1642_REFIN

1642_COMP

1642_FB

PR63

16.2K/F_4

PC39

4700p/25V_4

9

21

3

4

16

5

8

6

7

12

11

10

TON

PVCC

EN

PSI

PGOOD

VID

VREF

REFADJ

REFIN

COMP

FB

FBRTN

PU4

UP1642RQAG

DSBL/ISEN1

TALERT#/ISEN2

GND/PWM3

TSNS/ISEN3

PAD

25

Add 3 GND VIAs
for thermal pad

UGATE1

BOOT1

PHASE1

LGATE1

UGATE2

BOOT2

PHASE2

LGATE2

2

1

24

15

23

17

18

19

14

20

22

13

1642_UGATE1

1642_BOOT1

1642_PHASE1

1642_ISEN1

1642_LGATE1

1642_UGATE2

1642_BOOT2

1642_PHASE2

GPU_THAL#

1642_LGATE2

1642_TSNS

PR66

2.2/F_6

PR53

2.2/F_6

PC33

0.22u/25V_6

PC45

0.22u/25V_6

PR54
10K/F_4

RDSon 2.2mohm

PR74
10K/F_4

RDSon 2.2mohm

PQ37

D1D1D1

G1

1

S1/D2

9

1642_PHASE1

8

G2

S2S2S2

FDMS3660S

567

2

PQ42

D1D1D1

G1

1

S1/D2

9

1642_PHASE2

8

G2

S2S2S2

FDMS3660S

567

PC38

PC147

4.7u/25V_8

0.1u/50V_6

DRC=0.78mohm

PL8 0.36uH_10X10X4

PR55

2.2_6

PC34

1000p/50V_6

PC151

0.1u/50V_6

PC146

PC150

4.7u/25V_8

DRC=0.78mohm

PL9 0.36uH_10X10X4

PR73

2.2_6

PC47

1000p/50V_6

PC152

PC148

0.1u/10V_4

PC42

0.1u/10V_4

PC46
15u/25V_3528

4.7u/25V_8

+VGPU_CORE

+VGPU_CORE

+

1 Volt +/- 5%
TDC : 45A

PC41

PC144

10u/6.3V_6

PEAK : 58A

330u/2V_7343

OCP : 70A
Width : 1800mil

VIN

4.7u/25V_8

+VGPU_CORE

+

PC153

PC149

10u/6.3V_6

330u/2V_7343

43

+VGPU_CORE

PC43

PR28

PR27

0_4

GPU_VCCP_SENSE[16]

GPU_VSSP_SENSE[16]

A A

5

GPU_VCCP_SENSE_R

PR29

0_4

*100_4

PR30
*100_4

33p/50V_4

PR61
1K/F_4

1642_FBRTN

4

+3V

Place NTC close to the
VGPU Hot-Spot.

3

PR68
10K/F_4

GPU_THAL#

PR69
10K/F_4

1642_PVCC 1642_ISEN1

PR71

15.8K/F_4

1642_VREF 1642_TSNS

PR197
100K/F_4_4250NTC

GPU_THAL# [19]

PR65

*1.33K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

Monday, January 07, 2013

Date: Sheet of

2

Monday, January 07, 2013

PROJECT :

+VGPU_CORE(UP1642PQAG)

+VGPU_CORE(UP1642PQAG)

+VGPU_CORE(UP1642PQAG)

1

ZQK

ZQK

ZQK

43 46

43 46

43 46

1A

1A

1A

5

4

3

2

1

DGPU_PWROK

D D

GPIO17

GPIO3

+3VPCU

DGPU_PWR_EN

MOSFET

+3V_GFX

+1.5V_VRAM

44

PCH

C C

GPIO35

VIN

DGPU_VRON

PWM
uP1642PQAG

+VGPU_CORE

VGPU_PWRGD

EC_FB_CLAMP

+1.5VSUS

FBVDDQ_EN

MOSFET

+1.5V_GFX

HWPG_1.5VGFX

+1.05V_VTT

1.05V_GFX_EN

+1.05V_GFX

MOSFET

Power Sequence

B B

+3V_GFX

+VGPU_CORE

+1.5V_GFX

IFPx_IOVDD (+1.05V_GFX)

PEX_VDD (+1.05V_GFX)

A A

All rails must be powered off within 10 ms from the first rail powering off.

5

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Power Sequence

Power Sequence

Power Sequence

ZQK

ZQK

ZQK

44 46Monday, January 07, 2013

44 46Monday, January 07, 2013

44 46Monday, January 07, 2013

1

1A

1A

1A

5

4

3

2

1

39

SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.

SLP_S4#(SUSC#):
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components
when system transitions to S4 or S5 state.

D D

AC Adapter

Battery

BATT Charger

PU9

10

1

VIN

Always System power

Regulator

PU8

3

NBSWON#

2

+3VPCU

+5VPCU

SUSON(SUSD)

4

30ms

5

S5_ON
(S5D)

7

PCH_RSMRST#

8

DNBSWON#

+5VPCU

MOS

PQ39

+3VPCU

MOS

PQ18

+5V_S5

6

+3V_S5

RSMRST#

PWRBTN#

13

SUSC#

MAINON(MAIND)

MAIND

MAIND

C C

MAIND

+3VPCU

MDV1528Q-PQ19

+5VPCU

MDV1528Q-PQ56

+1.5VSUS

+3V

+5V

+1.5V

16

19

VRON

EC

100ms

SUSB#

22

PWROK_EC

9

SLP_S4#

SLP_S3#

23

SYS_PWROK

PCH

SYS_PWROK

AO3404-PQ41

MAINON

MAINON

+3VPCU

VR-PU3

VIN

VR-PU2

+1.8V

+1.05V_VTT

14

PROCPWRGD

PLTRST#

HWPG_VTT

B B

VIN

Regulator

PU2

+VCCSA

17

SYS_HWPG

24 25

H_PWRGOOD PCI_PLTRST#

18

15

19

VRON

(From EC)

VIN

VR-PU7

+VCC_CORE

+VCC_GFX

HWPG_1.8V

20

15

HWPG_VTT

HWPG_VCCSA

21

HWPG

UNCOREPWRGOOD

RESET#

IMVP_PWRGD

HWPG_1.5V

21

A A

MAINON

SUSON

VIN

Regulator

PU5

+0.75V_DDR_VTT

+SMDDR_VREF

+1.5VSUS

12

IMVP_PWRGD

CPU

11

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZQK

PROJECT :

ZQK

PROJECT :

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

power sequence block diagram

power sequence block diagram

power sequence block diagram

Date: Sheet o f

Date: Sheet o f

5

4

3

2

Date: Sheet o f

1

ZQK

1A

1A

1A

45

45

45

46Monday, January 07, 20 13

46Monday, January 07, 20 13

46Monday, January 07, 20 13

5

4

3

2

1

Model

Date

CHANGE LIST

1.Change C774 from 0.1uF to 39pF for ESD

1203

2.Add C841~C850 39pF for ESD

3.Change U19,U21,U23,U26,U43,U46,U48,U49 PN from AKD5JGST404 to AKD5JGST407

1.Change LED1/LED2 PN：BEB00028ZA0；FP：led19-123-y2st1d-c30-2t-4p

1205

D D

2.Change R383/R392 from 47 ohm to 56 ohm

1206 1.Change SW2 PN： DHPATE2CK03；FP：sw-ate-2ck-v-tr-4p

1.Delete PL2/PL3/PL4/PL5

1210

2.Add RTC charge circiut and modify CN14 PN and FP (DFHS02FS032/ml1220-smt)

3.Update CN4 FP to "dp-adis0022-p001a-20p-smt"

1.Add mSATA re-driver circuit

1211

2.Change CN22 PN & FP as same as CN13

1212 1.Modify Hole4 FP to H-TC197BC142D142P2

2.Change mSATA redriver power rail to +1.5V

1.Add R828~R831 for co-layout

1213

2.Add N14M-GE binary strap setting information

1214 1.Change USB DB power to 4 pins

2.Change CN4 PN to DFTD20FR001

1.Update Hole6/Hole17/Hole22 FP

C C

2.Add C866 by FAE suggestion

3.Change C706 from 10uF to 4.7uF

1217

4.Add pull down 100K by EC-Anda command (R832/R833/R834)

5.Change TEMP_MBAT fromPJ1 pin 5 to pin 6 (BATT_EN#) , then pin 6 is NC pin

6.Un stuff PR96

7.Add R835 and change R785 to 5.1M ohm

8.Mark R746 to NSW@ due to pin18 of U7 has internal +3V

1.SUSLED# power from +3V_S5 to +3V_PCU (for Deep S3)

ZQK

1219

2.Change eDP connector CN8 PN and FP (DFHS40FS095 / gs12401-1011-40p-r-nh-smt)

1.Add net PCH_SUSWARN# connect to Pin78 of EC (GPJ2)

1220

2.Add net PCH_SUSACK# connect to Pin79 of EC (GPJ3)

1221 1.Change PR191 PU voltage from +3V to +3V_S5

1.Unstuff PR28/PR30

1224

2.Reserve R837

1225 1.Change PU4 PN from AL001642000 to AL001642001

B B

1226 1.Change U15 PN from AJ085870F03 to AJ085870F04
1228 1.Co-layout mSATA re-driver IC-U51 (PS8521A & ASM1466)

1.Unstuff PR191 (Already PU on HW side)

0102

2.Reserve R842/R843
0103 1.SWAP EC pin：BATLED1# change to pin32 ; ME_WR# change to pin25
0104 1.Change U38 PN from AJ0QPRG0T03 to AJSLJ8C0T05
0107 1.Update Hole6/Hole17 FP

2.Update Pad1 PN to FBZRK011010

3.Update Hole4 PN to FBAJ2005010

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZQK

PROJECT :

ZQK

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Change list

Change list

Change list

5

ZQK

46 46Monday, January 07, 2013

46 46Monday, January 07, 2013

46 46Monday, January 07, 2013

DOC NO.

1A

1A

1A

PROJECT MODEL :

PART NUMBER: DRAWING BY: REVISON:

4

ZQK

3

APPROVED BY:

DATE:

2

1