Quanta NL6 Schematic

5

www.schematic-x.blogspot.com

4

3

2

1

NL6

01

Intel Bay Trail-M Platform Block Diagram

D D

DDR3L 1333
Memory down

DDR3L

2 Channel 1Rx16

PAGE 11,12

eMMC

SDIN8DE2-16G

MMC

PAGE 21

C C

SD card

SDIO

PAGE 16

1.8V BIOS+TXE
SPI ROM(64Mb)

W25Q64FWSSIG

SPI Interface

PAGE 6

B B

TPM

SLB9655TT1.2
FW4.32GOOG

TI KBC

TM4E1G31H6ZRB

Package : BGA-157

Size : 9.1 x 9.1 (mm)

PAGE 22

Thermal IC

PAGE 27

Keyboard

TMP432A

A A

PAGE 26

5

PAGE 26

SKUA QC N2930
Up to 1.83 GHz SR1SG(FCBGA) P/N: AJ0QG9UUT01

SKUB DC N2830
Up to 2.17 GHz SR1SG(FCBGA) P/N: AJ0QG9VUT01

DDI 1

32.768KHz

Intel Bay Trail-M

Power : TDP 7.5 Watt

Package : FCBGA 1170

Size : 25 x 27 (mm)

Int

Audio Codec

MAX98090

Package : TQFN-40

Size : 5 x 5 (mm)

PAGE 24

Speaker

MIC SW

TS3A225E

DMIC

PAGE 2~10

I2S+I2C(PORT1)

PCIE Gen 2 x 1 LaneLPC Interface

M.2 LGA 1216-S3

PAGE 24

CCD Integrated

4

PAGE 6

25 Mhz
PAGE 6

DDI 0

I2C Interface

USB 3.0 Interface

USB 2.0 Interface

Port1 Port0

Video Codec

PAGE 20

PAGE 24

Combo Jack
Headphone + MIC

PAGE 24

X4 LANES

USB Charger

Port0

TPS2546

PAGE 25

Port3

NGFF M.2 2230-E

WLAN / BT Combo

PCIE CLK PORT 0PCIE CLK PORT 1

PAGE 20

PAGE 24

Port0

USB3.0 Port x 1

Port2

CCD

PAGE 17

LTE UART COEXISTENCE

3

PAGE 25

Daughter Board

PAGE 16

eDP

PAGE 17

HDMI Conn PAGE 19

Track Pad

PAGE 26 PAGE ?

ALS

ILS29035
CCD Integrated

Port1

USB Hub

PAGE 17

GL852G-OHG12

USB Hub -2

NGFF M.2 3042-B

USB Hub -1

USB Charger

TPS2546

LTE

USB2.0 Port x 1

2

Port5Port4Port0

Touch Screen

MXT1664S

In touch panel PCBA

BQ24715

Batery Charger

NB670/NB671

PP3300_DSW/PP5000

ISL95833HRTZ-T

+VCC_CORE/+VCC_GFX

Discharger

BOM value option:
CHB@-==>DDR Single channel or dual channel
EDP@ =>4 Lane eDP
TS@ =>Touch screen
SX@ => S0IX
NSX@=> Non S0ix
VC@ =>Video codec
LTE@ => LTE
GD@ =>Google debug

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

TPS51216

PP1350

TLV62150ARGTR

PP1050_PCH

TLV62130ARGTR

PP1000_PCH_S5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Intel Block Diagram

Intel Block Diagram

Intel Block Diagram

NL6

NL6

NL6

1

1A

1A

1A

411

411

411

5

M_A_A[15:0](12)

D D

M_A_DM0(12)
M_A_DM1(12)
M_A_DM2(12)
M_A_DM3(12)
M_A_DM4(12)
M_A_DM5(12)
M_A_DM6(12)
M_A_DM7(12)

M_A_RAS#(12)
M_A_CAS#(12)
M_A_WE#(12)

M_A_BS0(12)
M_A_BS1(12)
M_A_BS2(12)

M_A_CS#0(12)

C C

1023 unstuff R28 by
Intel request

1121 remove R28,R25,C35

M_A_DRAMRST#(12)

PP1350

B B

A A

R344

4.7K/F_4

CPU_VREF

R348

4.7K/F_4

GND GND

SLP_S4#(6,11,14)

C242

0.1U/10V_4

SLP_S4#

PP3300_PCH_S5

R151

4.7K_4

DRM_PWOK_C1

34

5

Q40A
PJ4N3KDW

GND

5

R195
10K_4

2

PP1350

GND

GND

DRAM_PWROK

61

Q40B

PJ4N3KDW

M_A_CKE0(12)

M_A_ODT0(12)

M_A_CLKP0(12)
M_A_CLKN0(12)

R23 23.2/F_4
R19 29.4/F_4
R18 162/F_4

R178 0_4

R15 100K/F_4
R16 100K/F_4

GND

4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CS#0

M_A_CKE0

M_A_ODT0

M_A_CLKP0
M_A_CLKN0

M_A_DRAMRST#

CPU_VREF

ICLK_DRAM_TERMN_0
ICLK_DRAM_TERMN_1

SOC_DRAM_PWROK
SOC_VCCA_PWROK

DRAM_RCOMP0
DRAM_RCOMP1
DRAM_RCOMP2

SOC_DRAM_PWROK

C102
*1u/10V_4

4

R191 0_4

U14A

K45

DRAM0_MA_00

H47

DRAM0_MA_11

L41

DRAM0_MA_22

H44

DRAM0_MA_33

H50

DRAM0_MA_44

G53

DRAM0_MA_55

H49

DRAM0_MA_66

D50

DRAM0_MA_77

G52

DRAM0_MA_88

E52

DRAM0_MA_99

K48

DRAM0_MA_1010

E51

DRAM0_MA_1111

F47

DRAM0_MA_1212

J51

DRAM0_MA_1313

B49

DRAM0_MA_1414

B50

DRAM0_MA_1515

G36

DRAM0_DM_00

B36

DRAM0_DM_11

F38

DRAM0_DM_22

B42

DRAM0_DM_33

P51

DRAM0_DM_44

V42

DRAM0_DM_55

Y50

DRAM0_DM_66

Y52

DRAM0_DM_77

M45

DRAM0_RAS

M44

DRAM0_CAS

H51

DRAM0_WE

K47

DRAM0_BS_00

K44

DRAM0_BS_11

D52

DRAM0_BS_22

P44

DRAM0_CS_0

P45

DRAM0_CS_2

C47

DRAM0_CKE_00

D48

RESERVED_D48

F44

DRAM0_CKE_22

E46

RESERVED_E46

T41

DRAM0_ODT_0

P42

DRAM0_ODT_2

M50

DRAM0_CKP_0

M48

DRAM0_CKN_0

P50

DRAM0_CKP_2

P48

DRAM0_CKN_2

P41

DRAM0_DRAMRST

AF44

DRAM_VREF

AH42

ICLK_DRAM_TERMN

AF42

ICLK_DRAM_TERMN_AF42

AD42

DRAM_VDD_S4_PWROK

AB42

DRAM_CORE_PWROK

AD44

DRAM_RCOMP_00

AF45

DRAM_RCOMP_11

AD45

DRAM_RCOMP_22

AF40

RESERVED_AF40

AF41

RESERVED_AF41

AD40

RESERVED_AD40

AD41

RESERVED_AD41

VLV_M_D/BGA

REV = 1.15

+1.35V_SUS
+1.35V_SUS

ph

EC_PWROK(27)

PP1350_PGOOD (31)

?
VLV_M_D

1 OF 13

EC_PWROK

3

3

DRAM0_DQ09_C32

DRAM0_DQ_1010
DRAM0_DQ_1111
DRAM0_DQ_1212
DRAM0_DQ_1313
DRAM0_DQ_1414
DRAM0_DQ_1515
DRAM0_DQ_1616
DRAM0_DQ_1717
DRAM0_DQ_1818
DRAM0_DQ_1919
DRAM0_DQ_2020
DRAM0_DQ_2121
DRAM0_DQ_2222
DRAM0_DQ_2323
DRAM0_DQ_2424
DRAM0_DQ_2525
DRAM0_DQ_2626
DRAM0_DQ_2727
DRAM0_DQ_2828
DRAM0_DQ_2929
DRAM0_DQ_3030
DRAM0_DQ_3131
DRAM0_DQ_3232
DRAM0_DQ_3333
DRAM0_DQ_3434
DRAM0_DQ_3535
DRAM0_DQ_3636
DRAM0_DQ_3737
DRAM0_DQ_3838
DRAM0_DQ_3939
DRAM0_DQ_4040
DRAM0_DQ_4141
DRAM0_DQ_4242
DRAM0_DQ_4343
DRAM0_DQ_4444
DRAM0_DQ_4545
DRAM0_DQ_4646
DRAM0_DQ_4747
DRAM0_DQ_4848
DRAM0_DQ_4949
DRAM0_DQ_5050
DRAM0_DQ_5151
DRAM0_DQ_5252
DRAM0_DQ_5353
DRAM0_DQ_5454
DRAM0_DQ_5555
DRAM0_DQ_5656
DRAM0_DQ_5757
DRAM0_DQ_5858
DRAM0_DQ_5959
DRAM0_DQ_6060
DRAM0_DQ_6161
DRAM0_DQ_6262
DRAM0_DQ_6363

DRAM0_DQSP_00
DRAM0_DQSN_00
DRAM0_DQSP_11
DRAM0_DQSN_11
DRAM0_DQSP_22
DRAM0_DQSN_22
DRAM0_DQSP_33
DRAM0_DQSN_33
DRAM0_DQSP_44
DRAM0_DQSN_44
DRAM0_DQSP_55
DRAM0_DQSN_55
DRAM0_DQSP_66
DRAM0_DQSN_66
DRAM0_DQSP_77
DRAM0_DQSN_77

PP3300_PCH_S5

4.7K_4

DRM_PWOK_C2

34

5

Q28A

PJ4N3KDW

GND

DRAM0_DQ_00
DRAM0_DQ_11
DRAM0_DQ_22
DRAM0_DQ_33
DRAM0_DQ_44
DRAM0_DQ_55
DRAM0_DQ_66
DRAM0_DQ_77
DRAM0_DQ_88

R205
10K_4R147

?

PP1350

2

M36
J36
P40
M40
P36
N36
K40
K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51
L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51

J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51

61

PJ4N3KDW

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQSP0
M_A_DQSN0
M_A_DQSP1
M_A_DQSN1
M_A_DQSP2
M_A_DQSN2
M_A_DQSP3
M_A_DQSN3
M_A_DQSP4
M_A_DQSN4
M_A_DQSP5
M_A_DQSN5
M_A_DQSP6
M_A_DQSN6
M_A_DQSP7
M_A_DQSN7

Q28B

M_A_DQ[63:0] (12)

M_A_DQSP0 (12)
M_A_DQSN0 (12)
M_A_DQSP1 (12)
M_A_DQSN1 (12)
M_A_DQSP2 (12)
M_A_DQSN2 (12)
M_A_DQSP3 (12)
M_A_DQSN3 (12)
M_A_DQSP4 (12)
M_A_DQSN4 (12)
M_A_DQSP5 (12)
M_A_DQSN5 (12)
M_A_DQSP6 (12)
M_A_DQSN6 (12)
M_A_DQSP7 (12)
M_A_DQSN7 (12)

SOC_VCCA_PWROK

C90
*0.1U/10V_4

GND

1128 place C90 to close SoC ball

2

1

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

2

Friday, April 25, 2014

PROJECT :

Valley 1/9 (DDRA)

Valley 1/9 (DDRA)

Valley 1/9 (DDRA)

NL6

NL6

NL6

1A

1A

1A

412

412

1

412

5

4

3

2

1

?
VLV_M_D

2 OF 13

DRAM1_DQ_00
DRAM1_DQ_11
DRAM1_DQ_22
DRAM1_DQ_33
DRAM1_DQ_44
DRAM1_DQ_55
DRAM1_DQ_66
DRAM1_DQ_77
DRAM1_DQ_88

DRAM1_DQ_99
DRAM1_DQ_1010
DRAM1_DQ_1111
DRAM1_DQ_1212
DRAM1_DQ_1313
DRAM1_DQ_1414
DRAM1_DQ_1515
DRAM1_DQ_1616
DRAM1_DQ_1717
DRAM1_DQ_1818
DRAM1_DQ_1919
DRAM1_DQ_2020
DRAM1_DQ_2121
DRAM1_DQ_2222
DRAM1_DQ_2323
DRAM1_DQ_2424
DRAM1_DQ_2525
DRAM1_DQ_2626
DRAM1_DQ_2727
DRAM1_DQ_2828
DRAM1_DQ_2929
DRAM1_DQ_3030
DRAM1_DQ_3131
DRAM1_DQ_3232
DRAM1_DQ_3333
DRAM1_DQ_3434
DRAM1_DQ_3535
DRAM1_DQ_3636
DRAM1_DQ_3737
DRAM1_DQ_3838
DRAM1_DQ_3939
DRAM1_DQ_4040
DRAM1_DQ_4141
DRAM1_DQ_4242
DRAM1_DQ_4343
DRAM1_DQ_4444
DRAM1_DQ_4545
DRAM1_DQ_4646
DRAM1_DQ_4747
DRAM1_DQ_4848
DRAM1_DQ_4949
DRAM1_DQ_5050
DRAM1_DQ_5151
DRAM1_DQ_5252
DRAM1_DQ_5353
DRAM1_DQ_5454
DRAM1_DQ_5555
DRAM1_DQ_5656
DRAM1_DQ_5757
DRAM1_DQ_5858
DRAM1_DQ_5959
DRAM1_DQ_6060
DRAM1_DQ_6161
DRAM1_DQ_6262
DRAM1_DQ_6363

DRAM1_DQSP_00
DRAM1_DQSN_00
DRAM1_DQSP_11
DRAM1_DQSN_11
DRAM1_DQSP_22
DRAM1_DQSN_22
DRAM1_DQSP_33
DRAM1_DQSN_33
DRAM1_DQSP_44
DRAM1_DQSN_44
DRAM1_DQSP_55
DRAM1_DQSN_55
DRAM1_DQSP_66
DRAM1_DQSN_66
DRAM1_DQSP_77
DRAM1_DQSN_77

?REV = 1.15

BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44
BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53
AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51

BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51

M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQSP0
M_B_DQSN0
M_B_DQSP1
M_B_DQSN1
M_B_DQSP2
M_B_DQSN2
M_B_DQSP3
M_B_DQSN3
M_B_DQSP4
M_B_DQSN4
M_B_DQSP5
M_B_DQSN5
M_B_DQSP6
M_B_DQSN6
M_B_DQSP7
M_B_DQSN7

M_B_A[15:0](13)

D D

M_B_DM0(13)
M_B_DM1(13)
M_B_DM2(13)
M_B_DM3(13)
M_B_DM4(13)
M_B_DM5(13)
M_B_DM6(13)
M_B_DM7(13)

M_B_RAS#(13)
M_B_CAS#(13)
M_B_WE#(13)

M_B_BS0(13)
M_B_BS1(13)
M_B_BS2(13)

C C

1023 unstuff R29 by
Intel request

M_B_CS#0(13)

M_B_CKE0(13)

M_B_ODT0(13)

M_B_CLKP0(13)
M_B_CLKN0(13)

1121 remove R29,R26,C36

M_B_DRAMRST#(13)

B B

M_B_A0 M_B_DQ0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CS#0

M_B_CKE0

M_B_ODT0

M_B_CLKP0
M_B_CLKN0

M_B_DRAMRST#

AY45
BB47

AW41

BB44
BB50

BC53

BB49
BF50

BC52

BE52
AY48
BE51

BD47

BA51
BH49
BH50

BD38
BH36
BC36
BH42

AT51
AM42

AK50

AK52

AV45

AV44

BB51

AY47

AY44

BF52

AT44

AT45

BG47

BE46

BD44

BF48

AP41

AT42

AV50

AV48

AT50

AT48

AT41

U14B

DRAM1_MA_00
DRAM1_MA_11
DRAM1_MA_22
DRAM1_MA_33
DRAM1_MA_44
DRAM1_MA_55
DRAM1_MA_66
DRAM1_MA_77
DRAM1_MA_88
DRAM1_MA_99
DRAM1_MA_1010
DRAM1_MA_1111
DRAM1_MA_1212
DRAM1_MA_1313
DRAM1_MA_1414
DRAM1_MA_1515

DRAM1_DM_00
DRAM1_DM_11
DRAM1_DM_22
DRAM1_DM_33
DRAM1_DM_44
DRAM1_DM_55
DRAM1_DM_66
DRAM1_DM_77

DRAM1_RAS
DRAM1_CAS
DRAM1_WE

DRAM1_BS_00
DRAM1_BS_11
DRAM1_BS_22

DRAM1_CS_0
DRAM1_CS_2

DRAM1_CKE_00
RESERVED_BE46
DRAM1_CKE_22
RESERVED_BF48

DRAM1_ODT_0
DRAM1_ODT_2

DRAM1_CKP_0
DRAM1_CKN_0

DRAM1_CKP_2
DRAM1_CKN_2

DRAM1_DRAMRST

VLV_M_D/BGA

M_B_DQ[63:0] (13)

M_B_DQSP0 (13)
M_B_DQSN0 (13)
M_B_DQSP1 (13)
M_B_DQSN1 (13)
M_B_DQSP2 (13)
M_B_DQSN2 (13)
M_B_DQSP3 (13)
M_B_DQSN3 (13)
M_B_DQSP4 (13)
M_B_DQSN4 (13)
M_B_DQSP5 (13)
M_B_DQSN5 (13)
M_B_DQSP6 (13)
M_B_DQSN6 (13)
M_B_DQSP7 (13)
M_B_DQSN7 (13)

3

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

5

4

3

2

Friday, April 25, 2014

PROJECT :

Valley 2/9 (DDRB)

Valley 2/9 (DDRB)

Valley 2/9 (DDRB)

NL6

NL6

NL6

1A

1A

1A

413

413

1

413

5

4

3

2

1

U14C

INT_HDMITX2P(19) EDP_TXP0 (17)
INT_HDMITX2N(19)
INT_HDMITX1P(19)
INT_HDMITX1N(19)

D D

C C

B B

INT_HDMITX0P(19)
INT_HDMITX0N(19)
INT_HDMICLK+(19)
INT_HDMICLK-(19)

INT_HDMI_HPD(19)

HDMI_DDCDATA_SW(19)

HDMI_DDCCLK_SW(19)

R442
402/F_4

R184 *0_4_S
R183 *0_4_S

GND GND

TP5
TP4

INT_HDMITX2P
INT_HDMITX2N
INT_HDMITX1P
INT_HDMITX1N
INT_HDMITX0P
INT_HDMITX0N
INT_HDMICLK+
INT_HDMICLK-

INT_HDMI_HPD
HDMI_DDCDATA_SW

HDMI_DDCCLK_SW

SOC_DDIO_RCOMP
SOC_DDIO_RCOMP_P

SOC_PIN_AM3
SOC_PIN_AM2

GPIO_NC13
GPIO_NC14

INTD_DSI_TE

BTM Strapping Table

Pin Name Strap description

GPIO_SO_SC_56

LPE_I2S2_FRM

GPIO_SO_SC_65

A A

DDI0_DDCDATA

DDI1_DDCDATA

Top Swap (A16 Override)

BIOS Boot Selection

ecurity Flash Descriptors

S

DDI0 Detect

DDI1 Detect

Sampled

PWROK

PWROK

PWROK

PWROK

PWROK

AV3
AV2
AT2
AT3
AR3
AR1
AP3
AP2

AL3
AL1

D27
C26

C28
B28

C27
B26

AK13

AK12
AM14
AM13

AM3
AM2

T2

T3
AB3
AB2

Y3

Y2

W3
W1

V2

V3

R3

R1
AD6
AD4
AB9
AB7

Y4

Y6

V4

V6
A29
C29

AB14

B30
C30

0 = Top address bit is unchanged

+1.0V_SX

DDI0_TXP_0

+1.0V_SX

DDI0_TXN_0

+1.0V_SX

DDI0_TXP_1

+1.0V_SX

DDI0_TXN_1

+1.0V_SX

DDI0_TXP_2

+1.0V_SX

DDI0_TXN_2

+

VLV_M_D/BGA

REV = 1.15

1.0V_SX

+1.0V_SX
+1.0V_SX

+1.0V_SX

+1.8V

+1.8V
+1.8V

+1.8V
+1.8V
+1.8V

DDI0_TXP_3
DDI0_TXN_3

DDI0_AUXP
DDI0_AUXN

DDI0_HPD
DDI0_DDCDATA

DDI0_DDCCLK
DDI0_VDDEN

DDI0_BKLTEN
DDI0_BKLTCTL

DDI0_RCOMP
DDI0_RCOMP_P
RESERVED_AM14
RESERVED_AM13
VSS_AM3
VSS_AM2

RESERVED_T2
RESERVED_T3
RESERVED_AB3
RESERVED_AB2
RESERVED_Y3
RESERVED_Y2
RESERVED_W3
RESERVED_W1
RESERVED_V2
RESERVED_V3
RESERVED_R3
RESERVED_R1
RESERVED_AD6
RESERVED_AD4
RESERVED_AB9
RESERVED_AB7
RESERVED_Y4
RESERVED_Y6
RESERVED_V4
RESERVED_V6
GPIO_S0_NC13
GPIO_S0_NC14_C29
RESERVED_AB14
GPIO_S0_NC12
RESERVED_C30

Configuration Note

1 = Top address bit is inverted

0 = LPC

1 = SPI

0 = Override

1 = Normal operation

0 = DDI0 not detected

1 = DDI0 detected

0 = DDI0 not detected

1 = DDI0 detected

GPIO_SO_NC_13

5

4

?
VLV_M_D

+1.0V_SX
+1.0V_SX

+1.8V

+1.8V

DDI1_DDCDATA

+1.8V

DDI1_DDCCLK

+1.8V
+1.8V

DDI1_BKLTEN

+1.8V

DDI1_BKLTCTL

RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13

VGA_DDCCLK

VGA_DDCDATA

RESERVED_T7

RESERVED_T9
RESERVED_AB13
RESERVED_AB12

RESERVED_Y12
RESERVED_Y13
RESERVED_V10

RESERVED_V9

RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14
RESERVED_T13

RESERVED_T6

RESERVED_T4

RESERVED_P14

RESERVED_K34

GPIO_S0_NC26
GPIO_S0_NC25
GPIO_S0_NC24
GPIO_S0_NC23
GPIO_S0_NC22
GPIO_S0_NC21
GPIO_S0_NC20
GPIO_S0_NC18
GPIO_S0_NC17
GPIO_S0_NC16

3 OF 13

GPIO_S0_NC15

GPIO_S0_SC_56(7)

I2S_LRCLK(5)

SOC_OVERRIDE#(27)

Pull up +1.8V at HDMI side

AG3

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI1_HPD

DDI1_VDDEN

VSS_AH3
VSS_AH2

VGA_RED

VGA_BLUE

VGA_GREEN

VGA_IREF
VGA_IRTN

VGA_HSYNC
VGA_VSYNC

?

PP1800_PCH GND

R58 *0_4_S

HDMI_DDCDATA_SW

PP1800_PCH GND

PP1800_PCH GND

3

EDP_TXP0

AG1

EDP_TXN0

AF3

EDP_TXP1

AF2

EDP_TXN1

AD3

EDP_TXP2

AD2

EDP_TXN2

AC3

EDP_TXP3

AC1

EDP_TXN3

AK3

EDP_AUXP

AK2

EDP_AUXN

K30

EDP_HPD_L

P30

DDI1_DDCDATA

G30
N30

SOC_DISP_ON_C

J30

SOC_EDP_BLON_C

M30

SOC_DPST_PWM_C

AH14
AH13
AF14
AF13
AH3

SOC_PIN_AH3

AH2
BA3

AY2
BA1
AW1
AY3

BD2
BF2

BC1
BC2

T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6
T4
P14

K34
D32
N32
J34
K28
F28
F32
D34
J28
D28
M32
F34

GPIO_S0_SC_56

R128 *10K_4

I2S_LRCLK

R372 10K_4

I2S_DOUT(5)

DDI1_DDCDATA

R386 2.2K_4 R388 *10K_4

GPIO_NC13

R62 *10K_4

R452 *0_4_S

SOC_PIN_AH2

R457 *0_4_S

CRT_R
CRT_B
CRT_G
SOC_VGA_IREF
SOC_VGA_IRTN

CRT_HSYNC
CRT_VSYNC

VGA_DDCCLK
VGA_DDCDATA

XDP_GPIO_S0_NC19

XDP_GPIO_S0_NC23
XDP_GPIO_S0_NC22
XDP_GPIO_S0_NC21
XDP_GPIO_S0_NC20
XDP_GPIO_S0_NC18
XDP_GPIO_S0_NC17
XDP_GPIO_S0_NC16
XDP_GPIO_S0_NC15

R434 *10K_4

R369 *10K_4

I2S_DOUT

SOC_OVERRIDE_NM

R76 *10K_4

R63 10K_4

EDP_TXN0 (17)
EDP_TXP1 (17)
EDP_TXN1 (17)
EDP_TXP2 (17)
EDP_TXN2 (17)
EDP_TXP3 (17)
EDP_TXN3 (17)

EDP_AUXP (17)
EDP_AUXN (17)

SOC_DISP_ON_C (15)
SOC_EDP_BLON_C (15)
SOC_DPST_PWM_C (15)

TP19
TP20
TP16
TP17
TP22

TP49
TP48

R180 *0_4_S
R197 *0_4_S

3

2

1

XDP_GPIO_S0_NC19 (11)

XDP_GPIO_S0_NC23 (11)
XDP_GPIO_S0_NC22 (11)
XDP_GPIO_S0_NC21 (11)
XDP_GPIO_S0_NC20 (11)
XDP_GPIO_S0_NC18 (11)
XDP_GPIO_S0_NC17 (11)
XDP_GPIO_S0_NC16 (11)
XDP_GPIO_S0_NC15 (11)

GNDPP1800_PCH

Q6

2N7002K

GND

1029 unstuff R128, using SoC internal PU

029 unstuff R372, using SoC internal PU

1
1115 stuff R372, system can't boot if un-stuff R372 on

proto1.5 board, need intel double confirm before proto2

GND

1029 unstuff R386, using SoC internal PU
1115 stuff R386, it is required for eDP to be detected

HPD output high
SOC active Low

2

PP1800_PCH

R146

10K_4

EDP_HPD_L

3

2

Q32

2N7002K

GND GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

EDP_HPD

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Valley 3/9 (Display)

Valley 3/9 (Display)

Valley 3/9 (Display)

R459
100K/F_4

EDP_HPD (17)

NL6

NL6

NL6

1

4

1A

1A

1A

414

414

414

5

4

3

2

1

PP1800_PCH

R215 *10K_4

R198 *10K_4

D D

C C

SATA_DEVSLP_C

SATA_LED_R_N

1025 Delete complete SSD(connector and caps), unstuf
and add test points on SATA signals

TP34
TP36

TP37
TP38

R409 49.9/F_4

GND

R131 *0_4_S
R139 *0_4_S

R204 *0_4_S

R408
402/F_4

GND

SOC_KBC_SCI(14)

EMMC_CLK(21)

EMMC_D0(21)
EMMC_D1(21)
EMMC_D2(21)
EMMC_D3(21)
EMMC_D4(21)
EMMC_D5(21)
EMMC_D6(21)
EMMC_D7(21)

EMMC_CMD(21)

EMMC_RST#(21)

0217 reserve C377 on SD CLK for EMI

SD3_CLK

C377
*33P/50V_4

B B

SD3_CLK(16)

SD3_D1(16)
SD3_D2(16)
SD3_D3(16)
SD3_CD#(16,18)
SD3_CMD(16)

TP23

SDIO3_PWR_EN#(16)

SD3_CLK
SD3_D0
SD3_D1
SD3_D2
SD3_D3
SD3_CD#
SD3_CMD
SDMMC3_1P8_EN
SDIO3_PWR_EN#

R403 49.9/F_4

GND

f R215

SATA_TXP0_SSD
SATA_TXN0_SSD

SATA_RXP0_SSD
SATA_RXN0_SSD

ICLK_SATA_TERMP
ICLK_SATA_TERMN

SATA_GP0
SATA_DEVSLP_C
SATA_LED_R_N

SATA_RCOMP_DP
SATA_RCOMP_DN

EMMC_CLK
EMMC_D0

EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7

EMMC_CMD
EMMC_RST#

EMMC_RCOMP

SDIO3_RCOMP

U14D

BF6

SATA_TXP_0

BG7

SATA_TXN_0

AU16

SATA_RXP_0

AV16

SATA_RXN_0

BD10

SATA_TXP1

BF10

SATA_TXN_1

AY16

SATA_RXP_1

BA16

SATA_RXN_1

BB10

ICLK_SATA_TERMP

BC10

ICLK_SATA_TERMN

BA12

SATA_GP0

AY14

SATA_GP1

AY12

SATA_LED

AU18

SATA_RCOMP_P_AU18

AT18

SATA_RCOMP_N_AT18

AT22

MMC1_CLK

AV20

MMC1_D0

AU22

MMC1_D1

AV22

MMC1_D2

AT20

MMC1_D3

AY24

MMC1_D4

AU26

MMC1_D5

AT26

MMC1_D6

AU20

MMC1_D7

AV26

MMC1_CMD

BA24

MMC1_RST

AY18

MMC1_RCOMP

BA18

SD2_CLK

AY20

SD2_D0

BD20

SD2_D1

BA20

SD2_D2

BD18

SD2_D3_CD

BC18

SD2_CMD

AY26

SD3_CLK

AT28

SD3_D0

BD26

SD3_D1

AU28

SD3_D2

BA26

SD3_D3

BC24

SD3_CD#

AV28

SD3_CMD

BF22

SD3_1P8EN

BD22

SD3_PWREN

BF26

SD3_RCOMP

V

LV_M_D/BGA

+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V
+1.8V/+3.3V

REV = 1.15

+1.8V
+1.8V
+1.8V

+1.8V

+1.8V
+1.8V

?
VLV_M_D

+1.0V
+1.0V

+1.8V
+1.8V
+1.8V
+1.8V

PCIE_RCOMP_P_AP14_AP14

PCIE_RCOMP_N_AP13_AP13

+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V+1.8V/+3.3V
+1.8V/1.5V

+1.8V

4 OF 13

+1.8V

RESERVED_AV10

HDA_LPE_RCOMP

LPE_I2S2_DATAOUT

LPE_I2S2_DATAIN

+1.0V

PCIE_TXP_0
PCIE_TXN_0

PCIE_RXP_0
PCIE_RXN_0

PCIE_TXP_1
PCIE_TXN_1

PCIE_RXP_1
PCIE_RXN_1

PCIE_TXP_2
PCIE_TXN_2

PCIE_RXP_2
PCIE_RXN_2

PCIE_TXP_3
PCIE_TXN_3

PCIE_RXP_3
PCIE_RXN_3

VSS_BB7
VSS_BB5

PCIE_CLKREQ_0
PCIE_CLKREQ_1
PCIE_CLKREQ_2
PCIE_CLKREQ_3

SD3_WP_BD5

RESERVED_BB4
RESERVED_BB3

RESERVED_AV9

HDA_RST

HDA_SYNC

HDA_CLK
HDA_SDO
HDA_SDI0
HDA_SDI1

HDA_DOCKRST

HDA_DOCKEN
LPE_I2S2_CLK

LPE_I2S2_FRM

RESERVED_P34
RESERVED_N34

RESERVED_AK9
RESERVED_AK7

PROCHOT

AY7

PCIE_TX0+_WLAN_C

AY6

PCIE_TX0-_WLAN_C

AT14

PCIE_RX0+_WLAN

AT13

PCIE_RX0-_WLAN

AV6

PCIE_TX1+_IMAGE_C

AV4

PCIE_TX1-_IMAGE_C

AT10

PCIE_RX1+_IMAGE

AT9

PCIE_RX1-_IMAGE

AT7
AT6

AP12
AP10

AP6
AP4

1213 swap CLKREQ_WLAN and CLKREQ_IMAGE for

AP9

CLKREQ and CLK pins are aligned

AP7
BB7

VSS_BB7

BB5

VSS_BB5

BG3

PCIE_CLKREQ_WLAN#

BD7

PCIE_CLKREQ_IMAGE#

BG5

PCIE_CLKREQ_LAN#

BE3

PCIE_CLKREQ3#

BD5

SD3_WP

AP14

SOC_PCIE_COMP

AP13

SOC_PCIE_COMN

BB4
BB3
AV10
AV9

BF20

HDA_RCOMP

BG22

ACZ_RST#

BH20

ACZ_SYNC

BJ21

ACZ_BCLK

BG20

ACZ_SDOUT

BG19

PCH_AZ_CODEC_SDIN0

BG21
BH18

DET_TRIGGER

BG18

HDA_DOCKEN#

BF28

I2S_BCLK

BA30

I2S_LRCLK

BC30

I2S_DOUT

BD28

I2S_DIN

P34
N34

AK9
AK7

C24

SOC_PROCHOT#

?

C336 0.1U/10V_4
C341 0.1U/10V_4

C322 0.1U/10V_4
C328 0.1U/10V_4

R123 *0_4_S

R96 71.5/F_4
R103 *0_4_S

R455 *0_4_S
R462 *0_4_S

TP18
TP15

SD3_WP (16)

R410 49.9/F_4

TP6
TP10
TP7
TP8
TP9

DET_TRIGGER (24)
AJACK_MICPRES_L (24)SD3_D0(16)

R383 *0_4_S
R375 *0_4_S
R381 *0_4_S
R379 *0_4_S

H_PROCHOT#

R414 *0_4_S
R553 *0_4

1021 un-stuff R553

PCIE_TX0+_WLAN (20)
PCIE_TX0-_WLAN (20)

PCIE_RX0+_WLAN (20)
PCIE_RX0-_WLAN (20)

PCIE_TX1+_IMAGE (20)
PCIE_TX1-_IMAGE (20)

PCIE_RX1+_IMAGE (20)
PCIE_RX1-_IMAGE (20)

PCIE_CLKREQ_WLAN# (20)
PCIE_CLKREQ_IMAGE# (20)

GND

I2S_BCLK_R (24)
I2S_LRCLK_R (24)
I2S_DOUT_R (24)
I2S_DIN_R (24)

PP1000_PCH

H_PROCHOT# (18,27,33)
IMVP7_PROCHOT# (28)
ALERT# (23)

GND

PCIE_CLKREQ_IMAGE#
PCIE_CLKREQ_WLAN#
I2S_DOUT

R431
402/F_4

5

PP1800_PCH

R152 10K_4
R148 10K_4
R364 *10K_4

1029 unstuff R364,
using SoC internal PU

0 = LPC
1 = SPI

I2S_LRCLK
I2S_DOUT

Security Flash Descriptors
0 = Override
1 = Normal Operation

Need check to see if MOSFET
isolation needed or not

I2S_LRCLK (4)
I2S_DOUT (4)

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

5

4

3

2

Friday, April 25, 2014

PROJECT :

Valley 4/9 (SD/PCIE/SATA)

Valley 4/9 (SD/PCIE/SATA)

Valley 4/9 (SD/PCIE/SATA)

NL6

NL6

NL6

1A

1A

1A

415

415

1

415

C105 12P/50V_4

GND

GND

C106 12P/50V_4

1121 by X'tal vender suggestion,

D D

change C105/C106 from 15pF to 12pF

PP1800_PCH

C C

PP1800_PCH_S5

1025 add level shifter for
LTE SUSCLK

B B

XTAL25_OUT

1

2

Y3

25MHZ +-10PPM

4

3

XTAL25_IN

1031 remove R417, PRDY should
be direct connection between
SoC and XDP by intel request

1128 add a connection and name to
KBD_IRQ#, besides add pulled high resistor

R150 10K_4

R117 *10K_4
R108 10K_4
R122 10K_4
R111 10K_4

5

R188
1M_4

SOC_JTAG2_TDO
PCH_WAKE#
TRACKPAD_INT#
TOUCH_INT#

XTAL25_IN
XTAL25_OUT

R466 4.02K/F_4
R467 47.5/F_4

GND

CLK_PCIE_WLANN(20)
CLK_PCIE_WLANP(20)

CLK_PCIE_IMAGEN(20)
CLK_PCIE_IMAGEP(20)

I2S_MCLK(24)

KBD_IRQ#(27)
SRT_CRST#(11)

XDP_H_TCK(11)

XDP_H_TRST#(11)

XDP_H_TMS(11)
XDP_H_TDI(11)

XDP_H_TDO(11)

XDP_H_PRDY#(11)

XDP_H_PREQ#_C(11)

MUX_AUD_INT1#(24)

R107 *0_4_S

R424 *0_4_S

WIFI_DISABLE#(15)

GND

PCH_WAKE_L(27)

TRACKPAD_INT#(26)

TOUCH_INT#(15)

LTE_WAKE#(15)

PMC_SUSCLK1(15)

SOC_KBC_SMI(14)

ICLK_ICOMP
ICLK_RCOMP

CLK_PCIE_WLANN
CLK_PCIE_WLANP

CLK_PCIE_IMAGEN
CLK_PCIE_IMAGEP

I2S_MCLK

KBD_IRQ#KBD_IRQ#
SRT_CRST#

XDP_H_TCK
XDP_H_TRST#
XDP_H_TMS
XDP_H_TDI
XDP_H_TDO
XDP_H_PRDY#
XDP_H_PREQ#_C

SOC_SPI_CS#
SOC_SPI_MISO

SOC_SPI_MOSI
SOC_SPI_CLK

PCH_WAKE#
TRACKPAD_INT#
TOUCH_INT#
LTE_WAKE#
SOC_JTAG2_TDO
PMC_SUSCLK1
PCH_SPI_WP_D
SOC_GPOI7

MUX_AUD_INT1#
WIFI_DISABLE#

R402 49.9/F_4

RTC Clock 32.768KHz

RTC Circuitry(RTC)

PP3300_RTC

A A

R116 *0_6_S

30mils

+3V_RTC

R138

20K/F_4

R130

20K/F_4

C85
1u/6.3V_4

GND

5

GND

GND

C89
1u/6.3V_4

C84
1u/6.3V_4

SOC_RTEST#

SRT_CRST#

4

SOC_GPIO_RCOMP

RTC_X1

R161

10M_4

RTC_X2

4

AH12
AH10

AD14
AD13

AD10
AD12

AM10

AT34

AD9

AF6
AF4

AF9
AF7

AK4
AK6

AM4
AM6

AM9

BH7
BH5
BH4
BH8
BH6

BJ9
C12

D14

G12

F14
F12

G16

D18
F16

C23
C21
B22
A21
C22

B18
B16
C18
A17
C17
C16
B14
C15

C13
A13
C19

N26

U14E

ICLK_OSCIN
ICLK_OSCOUT

RESERVED_AD9
ICLK_ICOMP

ICLK_RCOMP
RESERVED_AD10

RESERVED_AD12
PCIE_CLKN_00

PCIE_CLKP_00
PCIE_CLKN_11

PCIE_CLKP_11

PCIE_CLKN_22
PCIE_CLKP_22

PCIE_CLKN_33
PCIE_CLKP_33

RESERVED_AM10
RESERVED_AM9

PMC_PLT_CLK_00
PMC_PLT_CLK_11
PMC_PLT_CLK_22
PMC_PLT_CLK_33
PMC_PLT_CLK_44
PMC_PLT_CLK_55
ILB_RTC_RST

TAP_TCK
TAP_TRST
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY
TAP_PREQ
RESERVED

PCU_SPI_CS_00
PCU_SPI_CS_11
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK

GPIO_S5_0
GPIO_S5_1
GPIO_S5_2
GPIO_S5_3
GPIO_S5_4
GPIO_S5_5
GPIO_S5_6
GPIO_S5_7

GPIO_S5_8
GPIO_S5_9
GPIO_S5_10

GPIO_RCOMP

VLV_M_D/BGA

REV = 1.15

12

Y2

32.768KHZ

?
VLV_M_D

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V
+1.8V_S5

+1.8V
+1.8V
+1.8V
+1.8V

+1.8V
+1.8V
+1.8V
+1.8V

+1.8V_S5

+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5 +1.0V

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

SPI ROM needs power in S3/S5 for the TXE (Trusted execution engine).

C9115P/50V_4

C9215P/50V_4

GND

+3V_RTC

+3V_RTC
+3V_RTC

5 OF 13

PP1800_PCH
PP1800_PCH_S5

+1.0V
+1.0V

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V
+1.8V
+1.8V
+1.8V

R158 *0_6
R157 *0_6_S

PP3300_PCH_S5

3

SIO_UART1_RXD
SIO_UART1_TXD
SIO_UART1_RTS
SIO_UART1_CTS

SIO_UART2_RXD
SIO_UART2_TXD
SIO_UART2_RTS
SIO_UART2_CTS

PMC_SUSPWRDNACK

PMC_SUSCLK0_G24

PMC_SLP_S0IX

PMC_SLP_S4
PMC_SLP_S3

GPIO_S514_J20

PMC_ACPRESENT

PMC_WAKE_PCIE_0

PMC_BATLOW
PMC_PWRBTN

PMC_RSTBTN
PMC_PLTRST

GPIO_S517_J24

PMC_SUS_STAT

ILB_RTC_TEST

PMC_RSMRST

PMC_CORE_PWROK

ILB_RTC_X1
ILB_RTC_X2

ILB_RTC_EXTPAD

SVID_ALERT

SVID_DATA

SVID_CLK

SIO_PWM_00
SIO_PWM_11

GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30

SIO_SPI_CS
SIO_SPI_MISO
SIO_SPI_MOSI

SIO_SPI_CLK

1

PP1800_PCH_S5

SPI_WP_ME

SPI_HOLD_ME

3

AU34
AV34
BA34
AY34

BF34
BD34
BD32
BF32

D26
G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18

C11

B10
B7

C9
A9
B8

B24
A25
C25

AU32
AT32

K24
N24
M20
J18
M18
K18
K20
M22
M24

AV32
BA28
AY28
AY30

Q29 PJA138K

2

R136 10K_4

ALS_INT#
TOUCH_INT_L_DX

SIO_UART2_RXD
SIO_UART2_TXD

PMC_SUSPWRDNACK
PMC_SUSCLK0
SLP_S0IX#
SLP_S4#
SLP_S3#

ACPRESENT
SOC_PMC_WAKE#
PMC_BATLOW#
SOC_PWRBTN#
SOC_REST_BTN#
SOC_PLTRST#

PMC_SUS_STAT#

SOC_RTEST#

SOC_RSMRST#
CORE_PWROK

RTC_X1
RTC_X2
BRTC_EXTPAD

SVID_ALERT#_SOC
SVID_DATA_SOC
SVID_CLK_SOC

SIO_PWM1

XDP_GPIO_DFX0
XDP_GPIO_DFX1
XDP_GPIO_DFX2
XDP_GPIO_DFX3
XDP_GPIO_DFX4
XDP_GPIO_DFX5
XDP_GPIO_DFX6
XDP_GPIO_DFX7
XDP_GPIO_DFX8

SIO_SPI_CS#
SIO_SPI_MISO
SIO_SPI_MOSI
SIO_SPI_CLK

PP1800_PCH_ME

3

PCH_SPI_WP_D

R133 0_4
R513 0_4

1

2

2

ALS_INT# (17)
TOUCH_INT_L_DX (15)

TP31
TP33

PMC_SUSPWRDNACK (14)
PMC_SUSCLK0 (15)
SLP_S0IX# (14)
SLP_S4# (2,11,14)
SLP_S3# (11,14)

ACPRESENT (15)
SOC_PMC_WAKE# (15)

SOC_PWRBTN# (11,14)
SOC_REST_BTN# (11,18)

SUS STAT OUTPUT PORT

R448 *0_4_S

C101 0.1U/10V_4

R90 20/F_4
R84 16.9/F_4
R81 0_4

0206 Disconnect SPI SIO I/F

TP67
TP68
TP69
TP70

R488 *3.3K/F_4

R500 3.3K/F_4

near SPI ROM as possible

Q272N7002K

3

PCH_SPI_WP_D

SPI_WP_ME

SOC_PLTRST# (11,14)
PMC_SUS_STAT# (14)

SOC_RTEST# (11)

SOC_RSMRST# (11,14)
CORE_PWROK_R (11,27)

SPEC 512177 INPUT PORT

VR_SVID_ALERT#
VR_SVID_DATA
VR_SVID_CLK

TP32

XDP_GPIO_DFX0 (11)
XDP_GPIO_DFX1 (11)
XDP_GPIO_DFX2 (11)
XDP_GPIO_DFX3 (11)
XDP_GPIO_DFX4 (11)
XDP_GPIO_DFX5 (11)
XDP_GPIO_DFX6 (11)
XDP_GPIO_DFX7 (11)
XDP_GPIO_DFX8 (11)

PP1800_PCH_ME

C355

0.1U/10V_4

GND

SPI_WP_ME_ROM

SPI_HOLD_ME

PP1800_PCH_ME

GPIO_SPI_WP (18)
SPI_HOLD#_BIOS (18)

To PCH

PCH_SPI_WP_D connect to GPIO58 at GRB

SPI_WP_ME (25,27)

2

GND

VR_SVID_ALERT# (33)
VR_SVID_DATA (33)

VR_SVID_CLK (33)

SPI_WP_ME

U22

8

VCC

Default PD

3

WP#

SPI_HOLD7GND

SPI_FLASH

soic8-7_9-1_27

AKE5EZN0N00

IC FLASH (8P) W25Q64FWSSIG (SOIC)

R501 3.3K/F_4

To debug header

From Screw/EC

O_1.8VA

SPI_SI

SPI_SO

CS#

SPI_SCK

SOC_SPI_CS#

1

PP1800_PCH_S5

PMC_SUSPWRDNACK
SOC_PMC_WAKE#
ACPRESENT
PMC_BATLOW#

SOC_REST_BTN#
TOUCH_INT_L_DX
ALS_INT#

9/6 Add EC_RCIN_L for warm boot,
EC side is OD type

SOC_REST_BTN#

R165 *0_4_S

5
2
1
6

4

SPI_WP_ME_ROM_Q

SOC_SPI_MOSI_R
SOC_SPI_MISO_R
SOC_SPI_CS#_R
SOC_SPI_CLK_R

GND

SPI NOR FLASH

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet

R413 10K_4
R412 10K_4
R397 *2.2K_4
R399 10K_4

R441 10K_4
R363 10K_4
R418 10K_4

DATA, CLK CLOSE TO VR

VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK

R468 *0_4_S

LAYOUT CLOSE TO SPI ROM

3.3V

R472 22/F_4
R487 22/F_4
R503 22/F_4
R480 22/F_4

LAYOUT CLOSE TO SPI ROM

R471 0_4
R479 0_4
R470 0_4
R481 0_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Valley 5/9 (SPI/GPIO/CLK)

Valley 5/9 (SPI/GPIO/CLK)

Valley 5/9 (SPI/GPIO/CLK)

PP1000_PCH

R374

73.2/F_4

PP1800_PCH_ME

C115 0.1u/10V_4

2
1

U1974LVC1G34

3 5

1

PP1800_PCH

ALERT Close to SOC

EC_REST_L (27)

4

SOC_SPI_MOSI
SOC_SPI_MISO
SOC_SPI_CS#
SOC_SPI_CLK

PCH_SPI_SO_R (18)
PCH_SPI_CS0#_R (18)

NL6

NL6

NL6

R88

73.2/F_4

PCH_SPI_SI_R (18)

PCH_SPI_CLK_R (18)

6

R360

73.2/F_4

SPI_WP_ME_ROM

R179
100K_4

of

416

416

416

1A

1A

1A

5

D D

LTE_DISABLE#(15)

M
HUB PORT 1
HUB PORT 2

C C

USB2.0
LTE

B USB3.0
HUB1
CCD
BT

GND

PP1800_PCH_S5

GND

1101 add option BOM R446,R449 for
EC CLK for power saving by Intel
request

B B

PCLK_TPM(22)

R446
*0_4

CLK_PCI_EC(27)

PP1800_PCH

A A

LPC_CLKRUN_L(27)

R120 2.2K_4
R125 2.2K_4
R141 2.2K_4

5

GND

R449 *0_4_S

0217 reserve R483 for CLKRUN# disable

GND

SMB_SOC_DATA
SMB_SOC_CLK
SMB_SOC_ALERTB

R483 *0_4

R185 45.3/F_4
R415 49.9/F_4

USBP0+(25)
USBP0-(25)

USBP1+(23)
USBP1-(23)

USBP2+(17)
USBP2-(17)

USBP3+(20)

USBP3-(20)

R437 1K/F_4
R425 1K/F_4

R97 10K_4
R189 10K_4

R443 45.3/F_4

R436 *0_4

GND

LPC_LAD0(22,27)
LPC_LAD1(22,27)
LPC_LAD2(22,27)
LPC_LAD3(22,27)

LPC_LFRAME#(22,27)

CLK_PCI_EC_R SOC_CLKOUT_1
LPC_CLKRUN_L

SOC_SERIRQ(14)

SOC_CLKRUN#

R115 22/F_4
R112 22/F_4
R109 0_4 R392 TS@4.7K_4

SMB_SOC_DATA(11)

SMB_SOC_CLK(11)

LTE_DISABLE#
RAM_ID0

RAM_ID1
RAM_ID2

RAM_ID3

ICLK_USB_TERMN_0
ICLK_USB_TERMN_1

USB_OC0#(14,25)

USB_OC0#
USB_OC1#

USB_OC1#(14,23)

USB_RCOMP

USB_PLL_MON

USB_HSIC_RCOMP

LPC_RCOMP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
SOC_CLKOUT_0

SOC_CLKRUN#
SOC_SERIRQ

SMB_SOC_DATA
SMB_SOC_CLK
SMB_SOC_ALERTB

4

U14F

G2

GPIO_S5_31

M3

GPIO_S5_32

L1

GPIO_S5_33

K2

GPIO_S5_34

K3

GPIO_S5_35

M2

GPIO_S5_36

N3

GPIO_S5_37

P2

GPIO_S5_38

L3

GPIO_S5_39

J3

GPIO_S5_40

P3

GPIO_S5_41

H3

GPIO_S5_42

B12

GPIO_S5_43

M16

USB_DP0

K16

USB_DN0

J14

USB_DP1

G14

USB_DN1

K12

USB_DP2

J12

USB_DN2

K10

USB_DP3

H10

USB_DN3

D10

ICLK_USB_TERMN_D10

F10

ICLK_USB_TERMN

C20

USB_OC_00

B20

USB_OC_11

D6

USB_RCOMPO

C7

USB_RCOMPI

M13

USB_PLL_MON

B4

USB_HSIC0_DATA

B5

USB_HSIC0_STROBE

E2

USB_HSIC1_DATA

D2

USB_HSIC1_STROBE

A7

USB_HSIC_RCOMP

BF18

LPC_RCOMP

BH16

ILB_LPC_AD_00

BJ17

ILB_LPC_AD_11

BJ13

ILB_LPC_AD_22

BG14

ILB_LPC_AD_33

BG17

ILB_LPC_FRAME

BG15

ILB_LPC_CLK_00

BH14

ILB_LPC_CLK_11

BG16

ILB_LPC_CLKRUN

BG13

ILB_LPC_SERIRQ

BG12

PCU_SMB_DATA

BH10

PCU_SMB_CLK

BG11

PCU_SMB_ALERT

VLV_M_D/BGA

4

REV = 1.15

+1.8V_S5
+1.8V_S5

+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V

+1.8V
+1.8V
+1.8V

?
VLV_M_D

6 OF 13

3

+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V

+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

3

RESERVED_M10

RESERVED_M9
RESERVED_P7

RESERVED_P6

RESERVED_M7

USB3_REXT0

RESERVED_P10
RESERVED_P12

RESERVED_M4
RESERVED_M6

USB3_RXP0

USB3_RXN0

USB3_TXP0
USB3_TXN0

RESERVED_H8
RESERVED_H7

RESERVED_H5
RESERVED_H4

GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61

ILB_8254_SPKR

SIO_I2C0_DATA

SIO_I2C0_CLK

SIO_I2C1_DATA

SIO_I2C1_CLK

SIO_I2C2_DATA

SIO_I2C2_CLK

SIO_I2C3_DATA

SIO_I2C3_CLK

SIO_I2C4_DATA

SIO_I2C4_CLK

SIO_I2C5_DATA

SIO_I2C5_CLK

SIO_I2C6_DATA

SIO_I2C6_CLK

GPIO_S0_SC_092
GPIO_S0_SC_093

2

RAM ID

RAM_ID0

R186 *1K_4
R187 1K_4
R196 1K_4
R212 *1K_4

0220 reserve placeholder R212,R218
f

or additional RAM ID

M10
M9

P7
P6

M7
M12

USB3_P0_REXT

P10
P12

M4
M6

D4
E3

K6
K7

H8
H7

H5
H4

BD12
BC12
BD14
BC14
BF14
BD16
BC16

BH12

BH22
BG23

BG24
BH24

BG25
BJ25

BG26
BH26

BF27
BG27

BH28
BG28

BJ29
BG29

BH30
BG30

?

R440 1.24K/F_4

GND

USB3_RXP0
USB3_RXN0

USB3_TXP0
USB3_TXN0

TRACKPAD_INT_DX
GPIO_S0_SC_56
SOC_UART_TX
SIM_DET_C
EC_IN_RW_C

SOC_UART_RX SOC_UART_TX SOC_UART_RX

I2C_0_SDA_C

R102 22/F_4

I2C_0_SCL_C

R95 22/F_4

I2C_1_SDA_C

R89 22/F_4

I2C_1_SCL_C

R83 22/F_4

I2C_4_SDA_C

R79 22/F_4

I2C_4_SCL_C

R75 22/F_4

I2C_5_SDA_C

R71 TS@22/F_4

I2C_5_SCL_C

R65 TS@22/F_4

I2C_NFC_SDA
I2C_NFC_SCL

USB3_RXP0 (25)
USB3_RXN0 (25)

USB3_TXP0 (25)
USB3_TXN0 (25)

I2C_0_SDA_R (15)
I2C_0_SCL_R (15)

I2C_1_SDA_R (24)
I2C_1_SCL_R (24)

I2C_4_SDA (17)
I2C_4_SCL (17)

I2C_5_SDA (17)
I2C_5_SCL (17)

220 R392,R389,R71,R65 need always to be stuffed even if w/o TS SKU

0

2

RAM_IDVender Freq.
Micron
Hynix

001

AKD5JGSTL02
AKD5JGETW00

Q PN Mfr. PN

MT41K256M16HA-125:E
H5TC4G63AFR-PBA

Micron 010 MT41K128M16JT-125:KAKD5DGSTL02

AKD5MG0TW02
AKD5JGSTL02

101

AKD5JGETW00

TRACKPAD_INT_DX (26)
GPIO_S0_SC_56 (4)

SOC_UART_TX (18)

SIM_DET_C (15)

EC_IN_RW_C (15)

SOC_UART_RX (18)

H5TC2G63FFR-PBAHynix 011
MT41K256M16HA-125:E
H5TC4G63AFR-PBAHynix

Proto1/1.5 stage use H2G & H4G

1212 add new RAMID 101 for single channel SKU

SIM_DET_C
TRACKPAD_INT_DX

Touch pad

udio Codec

A

Light sensor

Touch panel

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

R202 1K_4

RAM_ID1

R203 *1K_4

RAM_ID2

R192 *1K_4

RAM_ID3

R218 *1K_4

R420
*0_4

Un-Stuff for Test Only

I2C_0_SDA_R
I2C_0_SCL_R

I2C_1_SDA_R
I2C_1_SCL_R

I2C_4_SDA
I2C_4_SCL

I2C_5_SDA
I2C_5_SCL

I2C_NFC_SDA
I2C_NFC_SCL

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Valley 6/9 (USB/LPC/I2C)

Valley 6/9 (USB/LPC/I2C)

Valley 6/9 (USB/LPC/I2C)

1

PP1800_PCH_S5

1600MHz000
1600MHz
1600MHz
1600MHz
1600MHzMicron 100
1600MHz

PP1800_PCH

R422 10K_4
R433 10K_4

PP1800_PCH

R438 4.7K_4
R432 4.7K_4

R421 4.7K_4
R416 4.7K_4

R398 4.7K_4
R394 4.7K_4

R389 TS@4.7K_4

R368 *4.7K_4
R367 *4.7K_4

NL6

NL6

NL6

1

Size
4Gb
4Gb
2Gb
2Gb
4Gb
4Gb

7

Total
Size

4GB
4GB
2GB
2GB
2GB
2GB

1A

1A

1A

417

417

417

5

4

3

2

1

8

1031 for layout suggestion by
intel, VSS_AXG_SENSE didn't

D D

+VCC_CORE

+VCC_GFX

connect to VSS_SENSE, will
connect the GND via near
VCC_AXG_SENSE

1031 for layout, add 0hm between
GND and VSS_AXG_SENSE

R373

R458

100/F_4

100/F_4

VCC_SENSE

VSS_SENSE

R382
100/F_4

C C

B B

GND

1030 for core power, change
C271,C281,C280,C278,C273 to 10uF

1206 change C271,C273,C280 to
0603 22uF for ACLL issue

1204 for z-height issue, change
C72,C75,C81 to 0.85mm cap

VSS_AXG_SENSE(33)

PP1350

PP1350

+VCC_CORE

R385 *0_4_S

VCC_SENSE(33)

VCC_AXG_SENSE(33)

VSS_SENSE(33)

R343 *0_4_S

GND

GND

VCC_SENSE
VCC_AXG_SENSE
VSS_SENSEVCC_AXG_SENSE

PP1350_VSM

C231 1U/6.3V_4
C251 1U/6.3V_4
C38 0.1U/10V_4

C271 22u/6.3V_6
C281 10u/6.3V_4
C280 22u/6.3V_6
C278 10u/6.3V_4
C273 22u/6.3V_6

C72 22u/6.3V_8
C83 22u/6.3V_8
C75 22u/6.3V_8
C81 22u/6.3V_8
C79 22u/6.3V_8
C80 22u/6.3V_8
C76 22u/6.3V_8

GND

U14G

P28

CORE_VCC_SENSE_P28

BB8

UNCORE_VNN_SENSE

N28

CORE_VSS_SENSE_N28

AD38

DRAM_VDD_S4_AD38

AF38

DRAM_VDD_S4_AF38

A48

DRAM_VDD_S4

AK38

DRAM_VDD_S4_AK38

AM38

DRAM_VDD_S4_AM38

AV41

DRAM_VDD_S4_AV41

AV42

DRAM_VDD_S4_AV42

BB46

DRAM_VDD_S4_BB46

AA27

CORE_VCC_S0IX_AA27

AA29

CORE_VCC_S0IX_AA29

AA30

CORE_VCC_S0IX_AA30

AC27

CORE_VCC_S0IX_AC27

AC29

CORE_VCC_S0IX_AC29

AC30

CORE_VCC_S0IX_AC30

AD27

CORE_VCC_S0IX_AD27

AD29

CORE_VCC_S0IX_AD29

AD30

CORE_VCC_S0IX_AD30

AF27

CORE_VCC_S0IX_AF27

AF29

CORE_VCC_S0IX_AF29

AG27

CORE_VCC_S0IX_AG27

AG29

CORE_VCC_S0IX_AG29

AG30

CORE_VCC_S0IX_AG30

P26

CORE_VCC_S0IX_P26

P27

CORE_VCC_S0IX_P27

U27

CORE_VCC_S0IX_U27

U29

CORE_VCC_S0IX_U29

V27

CORE_VCC_S0IX_V27

V29

CORE_VCC_S0IX_V29

V30

CORE_VCC_S0IX_V30

Y27

CORE_VCC_S0IX_Y27

Y29

CORE_VCC_S0IX_Y29

Y30

CORE_VCC_S0IX_Y30

AF30

TP_CORE_V1P05_S4

VLV_M_D/BGA

REV = 1.15

?
VLV_M_D

7 OF 13

DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51

DRAM_VDD_S4_BJ48

DRAM_VDD_S4_C51
DRAM_VDD_S4_D44

DRAM_VDD_S4_F49
DRAM_VDD_S4_F52

DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42

DRAM_VDD_S4_V38

DRAM_VDD_S4_Y38

UNCORE_VNN_S3_AA24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AD24
UNCORE_VNN_S3_AF22

UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AG24

UNCORE_VNN_S3_AJ22

UNCORE_VNN_S3_AJ24
UNCORE_VNN_S3_AK22
UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK27
UNCORE_VNN_S3_AK29
UNCORE_VNN_S3_AK30
UNCORE_VNN_S3_AK32

UNCORE_VNN_S3_AM22

TP2_CORE_VCC_S0IX

1031 remove TP44 and TP35 for GND vias adding

BD49
BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38

AA24
AC22
AC24
AD22
AD24
AF22
AF24
AG22
AG24
AJ22
AJ24
AK22
AK24
AK25
AK27
AK29
AK30
AK32
AM22

AA22

PP1350

+VCC_GFX

GND

C69
10U/6.3V_6

C235

1U/6.3V_4

C63

22u/6.3V_8

C65
10U/6.3V_6

C240

1U/6.3V_4

C70

22u/6.3V_8

C236

1U/6.3V_4

C68
10U/6.3V_6

C266
22u/6.3V_6

1030 for Gfx power, change C266,C289,C290
to 10uF and add 2 caps 10uF

1206 change C266,C311,C315 to
0603 22uF for ACLL issue

C64

22u/6.3V_8

C237

1U/6.3V_4

C289
10u/6.3V_4

1030 change C60 power netname
for layout

+VCC_GFX

C290
10u/6.3V_4

C60

22u/6.3V_8

C238

1U/6.3V_4

C311
22u/6.3V_6

1U/6.3V_4

GND

C239

C315
22u/6.3V_6

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

5

4

3

2

Date: Sheet

PROJECT :

Valley 7/9 (Power 1)

Valley 7/9 (Power 1)

Valley 7/9 (Power 1)

NL6

NL6

NL6

1A

1A

1A

of

418

418

1

418

5

C299 1U/6.3V_4

GND

C329 1U/6.3V_4

PP1000_PCH
PP1000_PCH_SX

PP1000_PCH_SX

D D

PP1000_PCH_SX

PP1000_PCH

PP1000_PCH
PP1000_PCH_SX

PP1000_PCH

C C

PP1000_PCH_S5

PP1050_PCH

PP1350_PCH_SX

PP1350_PCH

PP1350_PCH

GND

R378 *0_4_S

R380 *0_4_S

R430 *0_4_S

C295 1U/6.3V_4
C306 1U/6.3V_4

C314 1U/6.3V_4

R54 *0_4_S

R456 *0_4_S

R354 *0_8_S
R384 *0_8_S

R193 *0_6_S

DARM_V1P0_S0IX_PWR_A

GND

DARM_V1P0_S0IX_PWR

GND

DDI_V1P0_S0IX

USB3_V1P0_G3
VIS_V1P0_S0IX_PW

GND

GND

CORE_V1P05
VIS_V1P0_S0IX_PW

GND

GND

USB3_V1P0_G3

GND

CORE_V1P05
UNCORE_V1P35_S0IX

GND

VGA_V1P35_S3
UNCORE_V1P35_S0IX

GND

GND

C256 1U/6.3V_4

C258 1U/6.3V_4
C255 1U/6.3V_4
C254 1U/6.3V_4

C338 0.01U/25V_4
C305 1U/6.3V_4

C308 1U/6.3V_4
C287 1U/6.3V_4

C286 1U/6.3V_4
C284 1U/6.3V_4

C313 1U/6.3V_4
C279 1U/6.3V_4

C334 1U/6.3V_4
C324 1U/6.3V_4

C262 1U/6.3V_4
C259 1U/6.3V_4

C297 1U/6.3V_4
C253 1U/6.3V_4

C339 1U/6.3V_4
C349 1U/6.3V_4

GND

AD35

AF35
AF36
AA36
AJ36
AK35
AK36

AK19
AK21
AJ18

AM16

AN29
AN30
AF16
AF18

AM21
AN21

AN18
AN19

AA33
AF21

AG21

AN25

AC32

AA25

AG32

AF19

AG19

AJ19

AG18
AN16

V32
BJ6

Y35
Y36

U22
V22

Y18

G1

V24
Y22

Y24
M14
U18
U19

Y19

Y32
U36

V36
BD1

U16

4

U14H

SVID_V1P0_S3_V32
VGA_V1P0_S3_BJ6
DRAM_V1P0_S0IX_AD35
DRAM_V1P0_S0IX_AF35
DRAM_V1P0_S0IX_AF36
DRAM_V1P0_S0IX_AA36
DRAM_V1P0_S0IX_AJ36
DRAM_V1P0_S0IX_AK35
DRAM_V1P0_S0IX_AK36
DRAM_V1P0_S0IX_Y35
DRAM_V1P0_S0IX_Y36
DDI_V1P0_S0IX_AK19
DDI_V1P0_S0IX_AK21
DDI_V1P0_S0IX_AJ18
DDI_V1P0_S0IX_AM16
UNCORE_V1P0_G3_U22
UNCORE_V1P0_G3_V22
VIS_V1P0_S0IX_AN29
VIS_V1P0_S0IX_AN30
UNCORE_V1P0_S3_AF16
UNCORE_V1P0_S3_AF18
UNCORE_V1P0_S3_Y18
UNCORE_V1P0_S3_G1
PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21

PCIE_GBE_SATA_V1P0_S3_AN18
SATA_V1P0_S3_AN19
CORE_V1P05_S3_AA33
UNCORE_V1P0_S0IX_AF21
UNCORE_V1P0_S0IX_AG21
VIS_V1P0_S0IX_V24
VIS_V1P0_S0IX_Y22
VIS_V1P0_S0IX_Y24
USB_V1P0_S3_M14
USB_V1P0_S3_U18
USB_V1P0_S3_U19
GPIO_V1P0_S3_AN25
USB3_V1P0_G3_Y19

C3

USB3_V1P0_G3_C3

C5

UNCORE_V1P0_G3_C5

B6

UNCORE_V1P0_G3_B6
CORE_V1P05_S3_AC32
CORE_V1P05_S3_Y32
UNCORE_V1P35_S0IX_F4_U36
UNCORE_V1P35_S0IX_F5_AA25
UNCORE_V1P35_S0IX_F2_AG32
UNCORE_V1P35_S0IX_F3_V36
VGA_V1P35_S3_F1_BD1
UNCORE_V1P35_S0IX_F6
UNCORE_V1P35_S0IX_F1_AG19
ICLK_V1P35_S3_F1_AJ19

ICLK_V1P35_S3_F2
VSSA_AN16
USB_VSSA_U16

REV = 1.15

VLV_M_D/BGA

?
VLV_M_D

8 OF 13

DRAM_V1P35_S0IX_F1_AD36

HDA_LPE_V1P5V1P8_S3_AM32

UNCORE_V1P8_S3_AM30

UNCORE_V1P8_S3_AN32

LPC_V1P8V3P3_S3_AM27

UNCORE_V1P8_G3_U24

USB_V3P3_G3_N18
USB_V3P3_G3_P18

UNCORE_V1P8_S3_U38

VGA_V3P3_S3_AN24

PCU_V1P8_G3_V25

3V_S5

PCU_V3P3_G3_N22

SD3_V1P8V3P3_S3_AN27

VSS_AD16

USB_HSIC_V1P24_G3_V18

VSS_AD18

UNCORE_V1P8_G3_AA18

RTC_VCC_P22

USB_V1P8_G3_N20

PMU_V1P8_G3_U25
CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35

CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33

VSS_A3_A3

VSS_A49_A49

VSS_A5_A5
VSS_A51_A51
VSS_A52_A52

VSS_A6_A6

VSS_B2_B2
VSS_B52_B52
VSS_B53_B53

VSS_BE1_BE1

VSS_BE53_BE53

VSS_BG1_BG1

VSS_BG53_BG53

VSS_BH1_BH1

VSS_BH2_BH2
VSS_BH52_BH52
VSS_BH53_BH53

VSS_BJ2_BJ2
VSS_BJ3_BJ3

VSS_BJ5_BJ5
VSS_BJ49_BJ49
VSS_BJ51_BJ51
VSS_BJ52_BJ52

VSS_C1_C1

VSS_C53_C53

VSS_E1_E1

VSS_E53_E53

RESERVED_F1

PCIE_V1P0_S3_AK18

PCIE_V1P0_S3_AM18

3

AD36
AM32
AM30
AN32
AM27
U24
N18
P18
U38
AN24
V25
N22
AN27
AD16
AD18
V18
AA18
P22
N20
U25
AF33
AG33
AG35
U33
U35
V33
A3
A49
A5
A51
A52
A6
B2
B52
B53
BE1
BE53
BG1
BG53
BH1
BH2
BH52
BH53
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52
C1
C53
E1
E53
F1
AK18
AM18

?

GND

UNCORE_V1P35_S0IX
UNCORE_V1P8_AN32_PWR
LPC_V3P3_PWR

V1P8_S5_PWR
PCU_V3P3_G3_PWR

UNCORE_V1P8_AN32_PWR
LPC_V3P3_PWR
PCU_V1P8_G3_V25
PCU_V3P3_G3_PWR
+VSDIO

VSS_AD18_AD16_PWR
USB_HSIC_V1P24_G3
V1P8_AA18_PEW
RTC_VCC_P22_PWR

V1P8_S5_PWR

CORE_V1P05

C263 1U/6.3V_4
C248 1U/6.3V_4
C260 1U/6.3V_4
C247 1U/6.3V_4
C268 1U/6.3V_4

C249 1U/6.3V_4
R395 *0_4_S
R114 *0_4_S

R555 *0_6_S
R554 *0_6
R407 *0_4_S
R121 *0_4_S

R464 *0_4_S
R453 *0_4_S

R110 *0_4_S
R400 *0_4_S

C270 1U/6.3V_4

C267 1u/6.3V_4
C264 1u/6.3V_4
C261 1u/6.3V_4
C265 0.47u/6.3V_4

C291 1U/6.3V_4
C304 1U/6.3V_4

2

GND

GND
PP1800_PCH

PP3300_PCH

PP1800_PCH_S5
PP1800_PCH
PP3300_PCH_S5
PP3300_PCH

GND
PP1800_PCH_S5

+3V_RTC
PP1800_PCH_S5

GND

GND

PP1000_PCH
GND

R460 *0_4_S
C346 1U/6.3V_4

PP1000_PCH_S5
GND

1

9

B B

A A

PP1350_PCH

GND

C296
1U/6.3V_4

PP1000_PCH

VIS_V1P0_S0IX_PW

22U/6.3V_8

GND

5

1031 remove C285

USB3_V1P0_G3 LPC_V3P3_PWR

C288

C303

1U/6.3V_4

C59
22U/6.3V_8

GND

C300

1U/6.3V_4 C307

0.01U/25V_4

C61
22U/6.3V_8

C301
1U/6.3V_4

C298
1U/6.3V_4

C276
1U/6.3V_4

C309
1U/6.3V_4

C277
1U/6.3V_4

GND

C323
1U/6.3V_4

C272
1U/6.3V_4

C292

0.01U/25V_4

C275

0.01U/25V_4

3

C337

C269

1U/6.3V_4 C332

1U/6.3V_4

V1P8_S5_PWR RTC_VCC_P22_PWR

GND

4

GND

C74
*1U/6.3V_4

V1P8_AA18_PEW

1U/6.3V_4

GND

VSS_AD18_AD16_PWR

GND

+VSDIO

C350
*1U/6.3V_4

PCU_V3P3_G3_PWR

C302

1U/6.3V_4

GND

UNCORE_V1P8_AN32_PWR

C283
1U/6.3V_4

GND

2

1U/6.3V_4

GND

C274

C282

1U/6.3V_4

1U/6.3V_4C62

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet

PROJECT :

Valley 8/9 (Power 2)

Valley 8/9 (Power 2)

Valley 8/9 (Power 2)

C252
1U/6.3V_4

1

GND

NL6

NL6

NL6

C293
1U/6.3V_4

of

C294

0.1U/10V_4

419

419

419

1A

1A

1A

5

4

3

2

1

10

D D

?

U14I

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35

VLV_M_D/BGA

VLV_M_D

9 OF 13

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70

AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40
AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36

?

AG38
AH41

AH45

AJ16
AJ21
AJ25
AJ27
AJ29

AJ30
AJ32
AJ33
AJ35
AJ38

AJ53
AK10
AK14
AK16
AK33
AK41
AK44
AM12
AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40

AH4

AH7
AH9

AJ1

AJ3

M28

REV = 1.15

A11
A15
A19
A23
A27
A31
A35
A39
A43
A47

AA1
AA16
AA19
AA21

AA3
AA32
AA35
AA38
AA53
AB10

AB4
AB41
AB45
AB47

C C

AB48
AB50
AB51

AC16
AC18
AC19
AC21
AC25
AC33
AC35

AB6

REV = 1.15

U14J

VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105

VLV_M_D/BGA

?
VLV_M_D

10 OF 13

VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140

AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1
AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19

?

AT24
AT27
AT30
AT35
AT38

AT47

AT52
AU24
AU30

AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51

AW13
AW19
AW27

AW3

AW35

AY10
AY22
AY32

AT4

AU1
AU3

AV7

REV = 1.15

U14K

VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175

VLV_M_D/BGA

?

VLV_M_D

11 OF 13

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210

?

U14L

AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27
BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38

?

BF30
BF36

BG31
BG34
BG39
BG42
BG45
BG49

BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47

BF4

BJ7
C14
C31
C34
C39
C42
C45
C49
D12
D16
D24
D30
D36
D38
E19
E35

REV = 1.15

VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245

VLV_M_D/BGA

VLV_M_D

12 OF 13

VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280

E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27
H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50

?

K9
L13
L19
L27
L35

M19
M26
M27
M34
M35
M38
M47
M51

N1

N16
N38
N51

P13
P16
P19
P20
P24
P32
P35
P38

P4
P47
P52

P9
T40

U1

U11
U12
U14
U21

U14M

VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315

VLV_M_D/BGA

REV = 1.15

?
VLV_M_D

13 OF 13

VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350

U3
U30
U32
U40
U42
U43
U45
U46
U48
U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9

?

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

5

4

3

2

Friday, April 25, 2014

PROJECT :

Valley 9/9 (GND)

Valley 9/9 (GND)

Valley 9/9 (GND)

NL6

NL6

NL6

1A

1A

1A

4110

4110

1

4110

5

INTEL Debug Port

D D

SOC_RSMRST#(6,14)

C199

*2N7002K
Q54

PCH_PWRBTN_L(14,27)

CORE_PWROK_R(6,27)

SMB_SOC_DATA(7)
SMB_SOC_CLK(7)

XDP_H_TCK(6)

SOC_RTEST# (6)

3

2

*2N7002K
Q55

1

PP1800_XDP_AB PP1800_XDP_CD

*0.1u/10V_4

C C

PP3300_PCH_S5

R528
100K_4

3

XDP_RTEST_L

B B

2

1

APS

CN14

A A

*ACES_88511-180N

1

APS1

1

2

PMC_SLP_S3#

2

3

3

4

4

5

5

6

6

7

7

8

8

9

ILB_RTC_RST#

9

10

10

11
12
13
14
15
16
17
18

PMC_PWRBTN#
PMC_RSTBTN#

5

11
12
13
14
15
16
17
18

R502 *0_6
R512 *0_4

R511 *0_4

R510 *0_4
R509 *0_4
R508 *0_4

XDP_H_PRDY#(6)

XDP_GPIO_DFX1(6)
XDP_GPIO_DFX2(6)

XDP_GPIO_DFX3(6)
XDP_GPIO_DFX4(6)

XDP_GPIO_DFX5(6)
XDP_GPIO_DFX6(6)

XDP_GPIO_DFX7(6)
XDP_GPIO_DFX8(6)

SOC_RSMRST# XDP_RSMRST#

PP3300_PCH_S5

SLP_S3#

SLP_S4#PMC_SLP_S4#

SRT_CRST#
SOC_PWRBTN#
SOC_REST_BTN#

4

XDP_H_PREQ#
XDP_H_PRDY#

XDP_GPIO_DFX1
XDP_GPIO_DFX2

XDP_GPIO_DFX3
XDP_GPIO_DFX4

XDP_GPIO_DFX5
XDP_GPIO_DFX6

XDP_GPIO_DFX7
XDP_GPIO_DFX8

R317 1K_4
R332 *0_4_S

R322 1K_4
R325 0_4

R320 *0_4_S
R319 *0_4_S

SLP_S3# (6,14)

SLP_S4# (2,6,14)

SRT_CRST# (6)

SOC_PWRBTN# (6,14)

4

XDP_PMU_PWRBTN#PCH_PWRBTN_L
XDP_COREPWROKCORE_PWROK_R

XDP_RTEST#XDP_RTEST_L
SMB_XDP_SDASMB_SOC_DATA

SMB_XDP_SCLSMB_SOC_CLK
XDP_H_TCK

3

CN13

GND

1

31

31

OBSFN_A0

3

32

32

OBSFN_A1

5

33

33

GND

7

34

34

OBSDATA_A_0

9

35

35

OBSDATA_A_1

11

36

36

GND

13

37

37

OBSDATA_A_2

15

38

38

OBSDATA_A_3

17

39

39

GND

19

40

40

OBSFN_B0

21

41

41

OBSFN_B1

23

42

42

GND

25

43

43

OBSDATA_B_0

27

44

44

OBSDATA_B_1

29

45

45

GND

31

46

46

OBSDATA_B_2

33

47

47

OBSDATA_B_3

35

48

48

GND

37

49

49

HOOK0

39

50

50

HOOK1

41

51

51

VCC_OBS_AB VCC_OBS_CD

43

52

52

HOOK2

45

53

53

HOOK3

47

54

54

GND

49

55

55

SDA

51

56

56

SCL

53

57

57

TCK1

55

58

58

TCK0

57

59

59

GND

59

60

60

*SEC_BSH-030-01-L-D-A-TR

GND_XDP_PRESENT

GND
OBSFN_C0
OBSFN_C1

GND

OBSDATA_C_0
OBSDATA_C_1

GND

OBSDATA_C_2
OBSDATA_C_3

GND

OBSFN_D_0
OBSFN_D_1

GND

OBSDATA_D_0
OBSDATA_D_1

GND

OBSDATA_D_2
OBSDATA_D_3

GND

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

DBR#/HOOK7

GND

TDO

TRSTn

TDI

TMS

2

30

30

4

29

29

6

28

28

8

27

27

10

26

26

12

25

25

14

24

24

16

23

23

18

22

22

20

21

21

22

20

20

24

19

19

26

18

18

28

17

17

30

16

16

32

15

15

34

14

14

36

13

13

38

12

12

40

11

11

42

10

10

44

9

9

46

8

8

48

7

7

50

6

6

52

5

5

54

4

4

56

3

3

58

2

2

60

1

1

1030 U10 change to 74AUP1G34 and stuff it
1031 N.C U10 pin1
1101 stuff C16

XDP_H_PREQ#_C(6)

3

XDP_H_PREQ#_C

PP1800_PCH_S5 PP1800_XDP_AB
PP1000_PCH_S5

PP1800_PCH PP1800_XDP_CD

XDP_GPIO_S0_NC15
XDP_GPIO_DFX0

XDP_GPIO_S0_NC16
XDP_GPIO_S0_NC17

XDP_GPIO_S0_NC18
XDP_GPIO_S0_NC19

XDP_GPIO_S0_NC20
XDP_GPIO_S0_NC21

XDP_GPIO_S0_NC22
XDP_GPIO_S0_NC23

XDP_PMU_PLTRST# SOC_PLTRST#
XDP_PMU_RSTBTN# SOC_REST_BTN#

XDP_H_TDO
XDP_H_TRST#
XDP_H_TDI
XDP_H_TMS
XDP_PRESENT_N

PP1800_PCH_S5

4

U10

74AUP1G34GW

3 5

R329 *0_4

2
1

R306 1K_4
R307 0_4

R263 *0_4_S

C16

0.1u/10V_4

XDP_H_PREQ#

C15
*0.1u/10V_4

2

R337 *0_6
R334 *0_6

R333 *0_4_S

XDP_GPIO_S0_NC15 (4)

XDP_GPIO_DFX0 (6)

XDP_GPIO_S0_NC16 (4)
XDP_GPIO_S0_NC17 (4)

XDP_GPIO_S0_NC18 (4)
XDP_GPIO_S0_NC19 (4)

XDP_GPIO_S0_NC20 (4)
XDP_GPIO_S0_NC21 (4)

XDP_GPIO_S0_NC22 (4)
XDP_GPIO_S0_NC23 (4)

SOC_PLTRST# (6,14)

SOC_REST_BTN# (6,18)

XDP_H_TDO (6)

XDP_H_TRST# (6)
XDP_H_TDI (6)
XDP_H_TMS (6)

C186 0.1u/10V_4

GND

PLACE C6601 closed to XDP HOOK PIN 54

1031 stuff
R273,R286,R289 for
Intel request

1030 remove PREQ# pulled up resistor R323
1031 put back R323

C160 0.1u/10V_4

GND

PLACE C6866 closed to XDP HOOK PIN48

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

2

Friday, April 25, 2014

XDP_RTEST#

PLACE R295 WITHIN 0.25" FROM XDP PIN

XDP_H_TDO

PLACE R273,R286,R318 WITHIN 1" FROM SoC PIN

XDP_H_TMS
XDP_H_TDI

XDP_H_TCK

XDP_H_TRST#
XDP_PMU_PWRBTN#

PLACE R6866 closed to XDP

PLACE R323 WITHIN 1.1" OF BUFFER PIN

XDP_H_PREQ#

XDP_PMU_RSTBTN#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CPU/PCH XDP

CPU/PCH XDP

CPU/PCH XDP

1

C177
*0.1u/10V_4

R324 1K_4

R295 *51/F_4

R273 *51/F_4
R286 *51/F_4

R318 *51/F_4

R289 *51/F_4
R321 *30K/F_4

R323 *200/F_4

R308 *1K_4

NL6

NL6

NL6

1

11

PP3300_PCH_S5

PP1800_XDP_AB

GND

PP1800_PCH_S5

PP1800_PCH

11 41

11 41

11 41

1A

1A

1A

1

<DDR>

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

M_A_A[15:0](2)

A A

M_A_BS[2:0](2)

M_A_CLKP0(2)
M_A_CLKN0(2)
M_A_CKE0(2)

M_A_ODT0(2)

M_A_CS#0(2)
M_A_RAS#(2)
M_A_CAS#(2)
M_A_WE#(2)

M_A_DQSP1(2) M_A_DQSP3(2)

M_A_DM2(2) M_A_DM0(2)

M_A_DQSN1(2)

B B

endor

M_A_DRAMRST#(2)

P/NV

Hynix

AKD5JGST400

Elpida

C C

DDR3L 1333Mhz 4Gb

DDR3L 1600Mhz 4GbAKD5JGST404

PP1350

C10
10u/6.3V_6

Place these Caps near each X16 Memory Down

C154
1u/6.3V_4

+SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP1

M_A_DM2 M_A_DM0

M_A_DQSN1

M_A_DRAMRST# M_A_DRAMRST#

R315
240/F_4

1 2

Distributed around all DRAM devices (CHA and CHB)

C8

C9

10u/6.3V_6

10u/6.3V_6

C187

C209

1u/6.3V_4

1u/6.3V_4

2

U2

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL
SDRAM DDR3

R

AM _DDR3L

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

C12

C7

10u/6.3V_6

10u/6.3V_6

C161

C155

1u/6.3V_4

1u/6.3V_4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

C11
10u/6.3V_6

C178
1u/6.3V_4

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

BYTE2_16-23

3

BYTE1_8-15

M_A_DQ18

M_A_DQ18 (2)

M_A_DQ16

M_A_DQ16 (2)

M_A_DQ19

M_A_DQ19 (2)

M_A_DQ21

M_A_DQ21 (2)

M_A_DQ22

M_A_DQ22 (2)

M_A_DQ17

M_A_DQ17 (2)

M_A_DQ23

M_A_DQ23 (2)

M_A_DQ20

M_A_DQ20 (2)

M_A_DQ13

M_A_DQ13 (2)

M_A_DQ11

M_A_DQ11 (2)

M_A_DQ9

M_A_DQ9 (2)

M_A_DQ10

M_A_DQ10 (2)

M_A_DQ12

M_A_DQ12 (2)

M_A_DQ15

M_A_DQ15 (2)

M_A_DQ8

M_A_DQ8 (2)

M_A_DQ14

M_A_DQ14 (2)

PP1350 PP1350 PP1350 PP1350

M_A_DQSP0(2)M_A_DQSP2(2)

M_A_DM3(2) M_A_DM7(2)M_A_DM1(2)

M_A_DQSN0(2)M_A_DQSN2(2)
M_A_DQSN3(2) M_A_DQSN7(2)

C188

C218

1u/6.3V_4

1u/6.3V_4

+SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0
M_A_CKE0 M_A_CKE0 M_A_CKE0

M_A_ODT0
M_A_CS#0 M_A_CS#0 M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP0M_A_DQSP2
M_A_DQSP3 M_A_DQSP7

M_A_DQSN0M_A_DQSN2
M_A_DQSN3

M_A_ZQ2M_A_ZQ1

R311
240/F_4

1 2

1205 add 0.1uFx2 on
PP1350 for EMI request

C325

0.1u/10V_4

C326

0.1u/10V_4

U3

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1

VSSQ#D8

VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

4

BYTE0_0-7
BYTE3_24-31

E3

M_A_DQ3

F7

M_A_DQ5

F2

M_A_DQ2

F8

M_A_DQ0

H3

M_A_DQ7

H8

M_A_DQ4

G2

M_A_DQ6

H7

M_A_DQ1

D7

M_A_DQ29

C3

M_A_DQ27

C8

M_A_DQ28

C2

M_A_DQ26

A7

M_A_DQ25

A2

M_A_DQ30

B8

M_A_DQ24

A3

M_A_DQ31

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

5

U4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0

M_A_ODT0
M_A_RAS#

M_A_CAS#
M_A_WE#

M_A_ZQ3

R4
240/F_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

R3
R7

N7

M7

M2
N8
M3

K7
K9

K1

K3

C7

E7
D3

G3
B7

T8
L7

T3
T7

J7

L2
J3

L3

F3

T2
L8

J1
L1
J9
L9

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1

VSSQ#D8

VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

M_A_DQ3 (2)
M_A_DQ5 (2)
M_A_DQ2 (2)
M_A_DQ0 (2)
M_A_DQ7 (2)
M_A_DQ4 (2)
M_A_DQ6 (2)
M_A_DQ1 (2)

M_A_DQ29 (2)
M_A_DQ27 (2)
M_A_DQ28 (2)
M_A_DQ26 (2)
M_A_DQ25 (2)
M_A_DQ30 (2)
M_A_DQ24 (2)
M_A_DQ31 (2)

M_A_DQSP6(2)
M_A_DQSP4(2)

M_A_DM6(2) M_A_DM5(2)
M_A_DM4(2)

M_A_DQSN4(2)

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0

M_A_DQSP6
M_A_DQSP4

M_A_DM6 M_A_DM5
M_A_DM4

M_A_DQSN4

M_A_DRAMRST#

1 2

6

BYTE4_32-39
BYTE6_48-55

E3

M_A_DQ55

F7

M_A_DQ49

F2

M_A_DQ54

F8

M_A_DQ52

H3

M_A_DQ50

H8

M_A_DQ48

G2

M_A_DQ51

H7

M_A_DQ53

D7

M_A_DQ32

C3

M_A_DQ39

C8

M_A_DQ33

C2

M_A_DQ35

A7

M_A_DQ37

A2

M_A_DQ34

B8

M_A_DQ36

A3

M_A_DQ38

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M_A_DQ55 (2)
M_A_DQ49 (2)
M_A_DQ54 (2)
M_A_DQ52 (2)
M_A_DQ50 (2)
M_A_DQ48 (2)
M_A_DQ51 (2)
M_A_DQ53 (2)

M_A_DQ32 (2)
M_A_DQ39 (2)
M_A_DQ33 (2)
M_A_DQ35 (2)
M_A_DQ37 (2)
M_A_DQ34 (2)
M_A_DQ36 (2)
M_A_DQ38 (2)

M_A_DQSP5(2)
M_A_DQSP7(2)

M_A_DQSN5(2)M_A_DQSN6(2)

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0

M_A_DQSP5

M_A_DM7M_A_DM3M_A_DM1

M_A_DQSN5M_A_DQSN6
M_A_DQSN7

M_A_DRAMRST#

1 2

M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_BS0
M_A_BS1
M_A_BS2
M_A_CKE0
M_A_CS#0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0

M_A_ODT0
M_A_RAS#

M_A_CAS#
M_A_WE#

M_A_ZQ4

R309
240/F_4

7

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

R270 36/F_4
R269 36/F_4
R250 36/F_4
R278 36/F_4
R260 36/F_4
R283 36/F_4
R301 36/F_4
R261 36/F_4
R276 36/F_4
R275 36/F_4
R256 36/F_4
R272 36/F_4
R284 36/F_4
R277 36/F_4
R259 36/F_4
R248 36/F_4
R252 36/F_4
R262 36/F_4
R271 36/F_4
R265 36/F_4
R290 36/F_4
R249 36/F_4
R255 36/F_4
R296 36/F_4

U5

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

+DDR_VTT_RUN

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE5_40-47
BYTE7_56-63

E3

M_A_DQ43

F7

M_A_DQ44

F2

M_A_DQ42

F8

M_A_DQ40

H3

M_A_DQ47

H8

M_A_DQ45

G2

M_A_DQ46

H7

M_A_DQ41

D7

M_A_DQ56

C3

M_A_DQ59

C8

M_A_DQ57

C2

M_A_DQ58

A7

M_A_DQ61

A2

M_A_DQ63

B8

M_A_DQ60

A3

M_A_DQ62

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1024 change ODT PU to VTT
by Intel request

M_A_ODT0

M_A_CLKP0

R279 39/F_4

M_A_CLKN0

R280 39/F_4

1023 change cap from

0.2pF to 3.3pF

8

M_A_DQ43 (2)
M_A_DQ44 (2)
M_A_DQ42 (2)
M_A_DQ40 (2)
M_A_DQ47 (2)
M_A_DQ45 (2)
M_A_DQ46 (2)
M_A_DQ41 (2)

M_A_DQ56 (2)
M_A_DQ59 (2)
M_A_DQ57 (2)
M_A_DQ58 (2)
M_A_DQ61 (2)
M_A_DQ63 (2)
M_A_DQ60 (2)
M_A_DQ62 (2)

R305 36/F_4

+DDR_VTT_RUN_A

C230 3.3p/50V_4

C146

0.1u/10V_4

M_A_CLKN0M_A_CLKP0

12

+DDR_VTT_RUN

+DDR_VTT_RUN

C210

C162

C179

C219

C169

C189

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

1u/6.3V_4

C156

C180

C190

C220

C163

1u/6.3V_4

1u/6.3V_4

C148
1u/6.3V_4

1u/6.3V_4

C142
1u/6.3V_4

2

1u/6.3V_4

C181

C221

1u/6.3V_4

1u/6.3V_4

D D

+DDR_VTT_RUN

C145
1u/6.3V_4

1

C152
1u/6.3V_4

C144
1u/6.3V_4

1u/6.3V_4

C212
1u/6.3V_4

+SMDDR_VREF_DIMM

C4
10U/6.3V_6

12

C171

0.047u/25V_4

+SMDDR_VREF_DQ0

C211

1u/6.3V_4

1u/6.3V_4

C164
1u/6.3V_4

12

C13

0.047u/25V_4

12

C175

0.047u/25V_4

12

C173

0.047u/25V_4

Place these Caps near Memory Down CA & DQ pin

12

12

C196

0.047u/25V_4

3

12

C195

0.047u/25V_4

12

C204

0.047u/25V_4

C200

0.047u/25V_4

M1 solution

PP1350

R314

4.7K/F_4

R304

4.7K/F_4

4

5

Vref_CA

+SMDDR_VREF_DIMM

12

C153

0.047u/25V_4

6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

7

Date: Sheet of

M1 solution

PP1350

R330

4.7K/F_4

R327

4.7K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR3L MEMORY DOWNx16 A

DDR3L MEMORY DOWNx16 A

DDR3L MEMORY DOWNx16 A

Friday, April 25, 2014

Friday, April 25, 2014

Friday, April 25, 2014

Vref_DQ

+SMDDR_VREF_DQ0

NL6

NL6

NL6

12 41

12 41

12 41

8

12

C202

0.047u/25V_4

1A

1A

1A

5

<DDR>

+SMDDR_VREF_DIMM

+SMDDR_VREF_DIMM

M_B_A[15:0](3)

D D

M_B_BS[2:0](3)

M_B_CLKP0(3)
M_B_CLKN0(3)

M_B_CKE0(3)

M_B_ODT0(3)
M_B_CS#0(3)
M_B_RAS#(3)
M_B_CAS#(3)
M_B_WE#(3)

M_B_DQSP2(3)
M_B_DQSP3(3)

M_B_DM2(3)
M_B_DM3(3)

M_B_DQSN2(3)
M_B_DQSN3(3)

C C

M_B_DRAMRST#(3)

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_ODT0
M_B_RAS#

M_B_CAS#
M_B_WE#

M_B_DQSP2
M_B_DQSP3

M_B_DM2
M_B_DM3

M_B_DQSN2
M_B_DQSN3

M_B_DRAMRST#

M_B_ZQ1

R5
CHB@240/F_4

1 2

P/NVe ndor

Micron

AKD5JGSTL02 MT41K256M16HA -125:E

AKD5JGST400

Elpida

AKD5JGST404

PP1350

B B

Place these Caps near each X16 Memory Down

C159
CHB@1u/6.3V_4

C168
CHB@1u/6.3V_4

C183
CHB@1u/6.3V_4

C185
CHB@1u/6.3V_4

C184
CHB@1u/6.3V_4

U8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL
SDRAM DDR3

C

HB@RAM _DDR3L

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

C194

C216

CHB@1u/6.3V_4

CHB@1u/6.3V_4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE2_16-23
BYTE3_24-31

E3

M_B_DQ20

F7

M_B_DQ19

F2

M_B_DQ21

F8

M_B_DQ18

H3

M_B_DQ17

H8

M_B_DQ22

G2

M_B_DQ16

H7

M_B_DQ23

D7

M_B_DQ27

C3

M_B_DQ24

C8

M_B_DQ30

C2

M_B_DQ25

A7

M_B_DQ26

A2

M_B_DQ29

B8

M_B_DQ31

A3

M_B_DQ28

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C225
CHB@1u/6.3V_4

C224
CHB@1u/6.3V_4

4

BYTE0_0-7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE1_8-15

E3

M_B_DQ0

F7

M_B_DQ2

F2

M_B_DQ5

F8

M_B_DQ3

H3

M_B_DQ1

H8

M_B_DQ7

G2

M_B_DQ4

H7

M_B_DQ6

D7

M_B_DQ15

C3

M_B_DQ12

C8

M_B_DQ14

C2

M_B_DQ13

A7

M_B_DQ10

A2

M_B_DQ9

B8

M_B_DQ11

A3

M_B_DQ8

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

U9

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ2

R310
CHB@240/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

C

HB@RAM _DDR3L

100-BALL
SDRAM DDR3

M_B_DQ20 (3)
M_B_DQ19 (3)
M_B_DQ21 (3)
M_B_DQ18 (3)
M_B_DQ17 (3)
M_B_DQ22 (3)
M_B_DQ16 (3)
M_B_DQ23 (3)

M_B_DQ27 (3)
M_B_DQ24 (3)
M_B_DQ30 (3)
M_B_DQ25 (3)
M_B_DQ26 (3)
M_B_DQ29 (3)
M_B_DQ31 (3)
M_B_DQ28 (3)

PP1350 PP1350 PP1350 PP1350

M_B_DQSP0(3)
M_B_DQSP1(3)

M_B_DM0(3)
M_B_DM1(3)

M_B_DQSN0(3)
M_B_DQSN1(3)

C166
CHB@1u/6.3V_4

C165
CHB@1u/6.3V_4

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_ODT0
M_B_CS#0M_B_CS#0 M_B_CS#0
M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP0
M_B_DQSP1

M_B_DM0
M_B_DM1

M_B_DQSN0
M_B_DQSN1

M_B_DRAMRST# M_B_DRAMRST#

1 2

3

M_B_DQ0 (3)
M_B_DQ2 (3)
M_B_DQ5 (3)
M_B_DQ3 (3)
M_B_DQ1 (3)
M_B_DQ7 (3)
M_B_DQ4 (3)
M_B_DQ6 (3)

M_B_DQ15 (3)
M_B_DQ12 (3)
M_B_DQ14 (3)
M_B_DQ13 (3)
M_B_DQ10 (3)
M_B_DQ9 (3)
M_B_DQ11 (3)
M_B_DQ8 (3)

2

BYTE6_48-55

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BYTE4_32-39

E3

M_B_DQ53

F7

M_B_DQ55

F2

M_B_DQ49

F8

M_B_DQ54

H3

M_B_DQ52

H8

M_B_DQ50

G2

M_B_DQ48

H7

M_B_DQ51

D7

M_B_DQ35

C3

M_B_DQ32

C8

M_B_DQ39

C2

M_B_DQ33

A7

M_B_DQ38

A2

M_B_DQ37

B8

M_B_DQ34

A3

M_B_DQ36

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M_B_DQ53 (3)
M_B_DQ55 (3)
M_B_DQ49 (3)
M_B_DQ54 (3)
M_B_DQ52 (3)
M_B_DQ50 (3)
M_B_DQ48 (3)
M_B_DQ51 (3)

M_B_DQ35 (3)
M_B_DQ32 (3)
M_B_DQ39 (3)
M_B_DQ33 (3)
M_B_DQ38 (3)
M_B_DQ37 (3)
M_B_DQ34 (3)
M_B_DQ36 (3)

M_B_DQSP5(3)
M_B_DQSP7(3)

M_B_DM5(3)
M_B_DM7(3)

M_B_DQSN5(3)
M_B_DQSN7(3)

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP5
M_B_DQSP7

M_B_DM5
M_B_DM7

M_B_DQSN5
M_B_DQSN7

1 2

M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_BS0
M_B_BS1
M_B_BS2
M_B_CKE0
M_B_CS#0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ4

R316
CHB@240/F_4

U7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ3

R312
CHB@240/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

C

HB@RAM _DDR3L

100-BALL
SDRAM DDR3

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0
M_B_CKE0 M_B_CKE0M_B_CKE0 M_B_CKE0

M_B_ODT0 M_B_ODT0
M_B_CS#0
M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP6(3)
M_B_DQSP4(3)

M_B_DM6(3)
M_B_DM4(3)

M_B_DQSN6(3)
M_B_DQSN4(3)

M_B_DQSP6
M_B_DQSP4

M_B_DM6
M_B_DM4

M_B_DQSN6
M_B_DQSN4

M_B_DRAMRST#

1 2

M8
H1

N3

M_B_A0M_B_A0

P7

M_B_A1

P3

M_B_A2

N2

M_B_A3

P8

M_B_A4

P2

M_B_A5

R8

M_B_A6

R2

M_B_A7

T8

M_B_A8

R3

M_B_A9

L7

M_B_A10

R7

M_B_A11

N7

M_B_A12

T3

M_B_A13

T7

M_B_A14

M7

M_B_A15

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

R297 CHB@36/F_4
R302 CHB@36/F_4
R298 CHB@36/F_4
R292 CHB@36/F_4
R267 CHB@36/F_4
R288 CHB@36/F_4
R300 CHB@36/F_4
R291 CHB@36/F_4
R287 CHB@36/F_4
R264 CHB@36/F_4
R281 CHB@36/F_4
R282 CHB@36/F_4
R299 CHB@36/F_4
R293 CHB@36/F_4
R251 CHB@36/F_4
R247 CHB@36/F_4
R254 CHB@36/F_4
R266 CHB@36/F_4
R303 CHB@36/F_4
R258 CHB@36/F_4
R274 CHB@36/F_4
R257 CHB@36/F_4
R253 CHB@36/F_4
R294 CHB@36/F_4

U6

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

C

HB@RAM _DDR3L

+DDR_VTT_RUN

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

1

BYTE5_40-47
BYTE7_56-63

E3

M_B_DQ41

F7

M_B_DQ46

F2

M_B_DQ44

F8

M_B_DQ42

H3

M_B_DQ40

H8

M_B_DQ47

G2

M_B_DQ45

H7

M_B_DQ43

D7

M_B_DQ59

C3

M_B_DQ61

C8

M_B_DQ63

C2

M_B_DQ60

A7

M_B_DQ58

A2

M_B_DQ56

B8

M_B_DQ62

A3

M_B_DQ57

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1024 change ODT PU to VTT
by Intel request

M_B_ODT0

M_B_CLKP0
M_B_CLKN0

1023 change cap from

0.2pF to 3.3pF

R268 CHB@39/F_4
R285 CHB@39/F_4

M_B_DQ41 (3)
M_B_DQ46 (3)
M_B_DQ44 (3)
M_B_DQ42 (3)
M_B_DQ40 (3)
M_B_DQ47 (3)
M_B_DQ45 (3)
M_B_DQ43 (3)

M_B_DQ59 (3)
M_B_DQ61 (3)
M_B_DQ63 (3)
M_B_DQ60 (3)
M_B_DQ58 (3)
M_B_DQ56 (3)
M_B_DQ62 (3)
M_B_DQ57 (3)

R313 CHB@36/F_4

+DDR_VTT_RUN_B

C228 CHB@3.3p/50V_4

13

+DDR_VTT_RUN

+DDR_VTT_RUN

C147

CHB@0.1u/10V_4

M_B_CLKN0M_B_CLKP0

C167

C223

CHB@1u/6.3V_4

CHB@1u/6.3V_4

C222

C158

CHB@1u/6.3V_4

CHB@1u/6.3V_4

+DDR_VTT_RUN

C141

C149

C150

A A

CHB@1u/6.3V_4

CHB@1u/6.3V_4

CHB@1u/6.3V_4

5

C143
CHB@1u/6.3V_4

CHB@1u/6.3V_4

C182
CHB@1u/6.3V_4

C151
CHB@1u/6.3V_4

CHB@1u/6.3V_4

C1
CHB@10U/6.3V_6

C157
CHB@1u/6.3V_4

C191
CHB@1u/6.3V_4

C215
CHB@1u/6.3V_4

+SMDDR_VREF_DIMM

12

C172
CHB@0.047u/25V_4

+SMDDR_VREF_DQ1

12

C197
CHB@0.047u/25V_4

C192

C193

C214

C170

CHB@1u/6.3V_4

CHB@1u/6.3V_4

C213
CHB@1u/6.3V_4

12

12

C174
CHB@0.047u/25V_4

12

C14
CHB@0.047u/25V_4

C176
CHB@0.047u/25V_4

Place these Caps near Memory Down CA & DQ pin

12

12

C205
CHB@0.047u/25V_4

4

C201
CHB@0.047u/25V_4

12

C198
CHB@0.047u/25V_4

M1 solution

PP1350

Vref_DQ

R331

+SMDDR_VREF_DQ1

CHB@4.7K/F_4

12

C203

NL6

NL6

NL6

13 41Friday, April 25, 2014

13 41Friday, April 25, 2014

13 41Friday, April 25, 2014

CHB@0.047u/25V_4

1A

1A

1A

R328
CHB@4.7K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR3L MEMORY DOWNx16 B

DDR3L MEMORY DOWNx16 B

DDR3L MEMORY DOWNx16 B

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

1

5

PWRON SEQUENCE

9/6 EC table says SERIRQ is OD pin, reserve for debugging
1128 remove R166, because SERIQR of TPM needs 3V
1128 reserve 0 ohm R387/R391 on VCCA and VCCB for debugging

D D

20140210 unstaff R387/R391

PP3300_PCH_S5PP1800_PCH_S5

R391
*0_4

U20

VCCA1VCCB

SOC_SERIRQ(7)

C C

PP1800_PCH
SOC_KBC_SCI(5)
SOC_KBC_SMI(6)

PP1800_PCH_S5

PMC_SUS_STAT#(6)

3

A

2

GND

GND

PMC_SUS_STAT# PCH_SUS_STAT_L

*G2129TL1U

R159 10K_4

R170 10K_4

6

4

B

5

OE

R171 *0_4_S

6
5
4

*74LVC2G07GW
R174 *0_4_S

PP1800_PCH_S5

2

1

Q23 *PJA138K

R387
*0_4

IRQ_SERIRQSOC_SERIRQ

SWITCH_EN

R156 *10K_4

20140210 unstaff U20/R156

U21

1

A1

Y1

2

GND

VCC

A23Y2

R465 *10K_4

3

GNDPP3300_EC

4

IRQ_SERIRQ (22,27)

PP1800_PCH_S5

EC_SCI_L (27)
EC_SMI_L (27)

PP3300_EC
PCH_SUS_STAT_L (27)

PWRON SEQUENCE

SOC_RSMRST#(6,11)

R515 10K_4

SOC_PWRBTN#

SOC_RSMRST#

100K/F_4

PMC_SUSPWRDNACK

SLP_S3#

SLP_S4#

SLP_S0IX#

PP1800_PCH_S5

SOC_PWRBTN#(6,11) PCH_PWRBTN_L (11,27)

SLP_S3#(6,11)

3

PP1800_PCH_S5

1

Q34 PJA138K

R439

GND

PP1800_PCH_S5

2

1

Q46 PJA138K

Q49A PJ4N3KDW

34

5

2

61

Q49B PJ4N3KDW

PP1800_PCH_S5

1

Q45 PJA138K

1022 un-stuff R182 for S5
leakage issue

2

2

3

R4450_4

R491 *10K_4

3

PCH_SLP_S3_L

R517 *10K_4
R523 *10K_4

PCH_SLP_S4_L

R492 *10K_4

3

R182 *30K/F_4

PP3300_EC

PCH_RSMRST_L (27)

PCH_SUSPWRDNACK (27)PMC_SUSPWRDNACK(6)

PCH_SLP_S3_L (27)

PP3300_ECPP1800_PCH_S5

PCH_SLP_S4_L (27)SLP_S4#(2,6,11)

PP3300_EC
PCH_SLP_SX_L (27)SLP_S0IX#(6)

PP3300_PCH_S5

2

1

14

0128 change power rail of
Q35,Q36,Q37,Q44 from PP1800_PCH_S5
to PP1800_PCH for PP1800_PCH
leakage issue in S3 mode

0206 remove/delete SPI_SIO Interface,
Q35,Q36,Q37,Q44,R486,R484,R485,
R483,R426,R429,R427,R428

USB OC

B B

USB_OC0#(7,25)

USB_OC1#(7,23)

A A

USB_OC0#

USB_OC1#

5

PP1800_PCH_S5

2

R99 10K_4

2

3

R86 10K_4

3

1

Q20 PJA138K

PP1800_PCH_S5

1

Q17 PJA138K

Stuffing for notifying EC

PP3300_EC
USB_OC0_L (27)

PP3300_EC
USB_OC1_L (27)

4

PP1800_PCH_S5

2

R143 10K_4

Q30 PJA138K

3

R142
*100K_4

SOC_PLTRST#(6,11)

SOC_PLTRST#

3

1

PP3300_PCH

PLTRST# (20,22,27)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

2

Date: Sheet

PROJECT :

Level Shfiter (SOC_EC)

Level Shfiter (SOC_EC)

Level Shfiter (SOC_EC)

NL6

NL6

NL6

1A

1A

1A

of

4114

4114

1

4114

5

LTE

LTE SUSCLK

PP1800_PCH_S5

LTE_DISABLE

LTE_WAKE#(6)

WIFI SUSCLK

R167 *3G@10K_4

PMC_SUSCLK1(6)

R496 *3G@10K_4

LTE_DISABLE#(7)

*3G@PJ4N3KDW

PP1800_PCH_S5

PMC_SUSCLK0(6)

PP1800_PCH_S5

PP1800_PCH_S5

D D

LTE_WAKE(OD)

C C

LTE_SIM DET

WIFI

B B

2

Q53B

*3G@PJ4N3KDW

PP1800_PCH_S5

R200

3G@10K_4

Q48A

PP1800_PCH

1

R91 *3G@0_4

R49 10K_4

R80 10K_4

WIFI_DISABLE#(6)

U28

NC1VCC

2

A

GND3Y

*3G@74AUP1G07GW

+3V_LTE +3V_LTE

61

*3G@10K_4

34

R73 *3G@0_4

Q41 *3G@PJA138K

WIFI_DISABLE

SOC_PMC_WAKE#(6)

Q16A

WIFI WAKE(OD)

A A

*PJ4N3KDW

SOC_PMC_WAKE# WLAN_WAKE_L

5

0.1u/10V_4

R618
*3G@10K_4

5

+3V_LTE

R619

6 1

5

*3G@PJ4N3KDW

R529 *3G@10K_4

2

3

U29

NC1VCC

2

A

GND3Y

74AUP1G07GW

+WL_VDD

2

Q25B

PJ4N3KDW

+WL_VDD

R622

*10K_4

34

5

*PJ4N3KDW

R59 0_4

PP1800_PCH_S5

+3V_LTE

5

12

C389

4

R163
*3G@10K_4

LTE_SUSCLK (23)

LTE SUSCLK is must required for bruce modem

R521
*3G@10K_4

34

R214 *3G@10K_4

2

Q48B

SIM_DETSIM_DET_C

61

LTE_DISABLE_L (23)

R521can be deleted due to there was pulled up on DB
Q53,R496,R618 can be unstuffed due to not
support in current modules

Q53A
*3G@PJ4N3KDW

+3V_LTE

0218 due to LTE wake is OD/1.8V in
M.2 spec, unstuff R214,Q48, and
stuff 0 ohm R73

0220 unstuff R619

LTE_WAKE_LLTE_WAKE#

0224 reserve R91 0 ohm on SIM_DET line for difference
design of various cards

PP1800_PCH_S5
5

12

C390

0.1u/10V_4

4

+WL_VDD

R113

R621

10K_4

10K_4

34

5

Q25A
PJ4N3KDW

R53 *10K_4

2

6 1

Q16B

LTE_WAKE_L (23)

There is internal pulled up in QRI module to

3.3V, but for more modules , keep stuffing

+3V_LTE

pulled up R529

SIM_DET (23)SIM_DET_C(7)

+WL_VDD

R45
10K_4

WIFI_SUSCLK (20)

0219 for layout smoothly, change
pulled up power rail of level shifter
of WiFi from PP3300_WLAN to
+WL_VDD

RF_EN (20)

+WL_VDD

4

WLAN_WAKE_L (20)

4

HW RESET

PP1800_PCH

Touch Screen

S0

TOUCH_INT_L_DX(6)

TOUCH_INT#(6)

S5

Track Pad

I2C_0_SDA_R(7)

I2C_0_SCL_R(7)

eDP control pin

SOC_EDP_BLON_C(4)

R447 10K_4

PP1800_PCH

PP1800_PCH

PP1800_PCH

2

3

1

EC_IN_RW_C

Q26 *PJA138K

R137 *0_4_S

1023 EC_IN_RW is OD,
remove level shift and PU
to PP1800_PCH

D13

*RB501V-40

R118 *0_4

R533 *0_4

PJ4N3KDW
Q47A

Q47B
PJ4N3KDW

R542 *0_4

R350 *10K_4

R351 *10K_4

SOC_DPST_PWM_C

PP3300_DX

R548

4.7K_4

SOC_EDP_BLON_C_Q

3

2

1

5

2

Q59
PJA138K

34

61

PP1800_PCH

I2C_0_SDA_R

I2C_0_SCL_R I2C_0_SCL

SOC_DISP_ON_C(4)

R357

100K_4

3

EC_IN_RW

TS_INT#TOUCH_INT_L_DX

I2C_0_SDA

R531 2.2K_4
R530 2.2K_4

1

Q4
2N7002K

3

2

1

3

PP3300_DSW

5

2

R556

4.7K_4

Q43

2N7002K

I2C_0_SDA (26)

I2C_0_SCL (26)

R626
10k_4

34

Q69A

R625 *0_4

3

EC_IN_RW (26)EC_IN_RW_C(7)

TS_INT# (17)

PP3300_DX

2

R346 10K_4

SOC_EDP_BLON (17)

S5 Power Good(+3V_S5)

0830 A24

TP_PWRPP1800_PCH

R347
10K_4

61

Q69B

PJ4N3KDW/30V_0.1A-SC70

5/25 DISP_ON power sequence issue

PP3300_DX

SOC_DPST_PWM (17)SOC_DPST_PWM_C(4)

2

PP3300_DSW

R129

R134

4.7K_4

4.7K_4

PP3300_PCH_S5_PG

3

Q24

2

PP3300_PCH_S5

3

2

1

Q21

2N7002K

1

2N7002K

S0iX Power Good

for proto type only, can remove at MP stage if S0ix is not needed

1VS0IX_PG_2

2

PP1000_PCH_SX

SOC_DISP_ON (17)

PP1350_PCH_SX

2

R48 SX@4.7K_4

R34 SX@4.7K_4

AC Detect

1VS0IX_PG_1

C47
*SX@1000P/50V_4

1.35VS0IX_PG_1

C54
*SX@1000P/50V_4

ACPRESENT(6)

Q5
SX@MMBT3904-7-F

1 3

1.35VS0IX_PG_2

2

Q9
SX@MMBT3904-7-F

1 3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

15

PP3300_PCH_S5_PG (27)

R33
SX@4.7K_4

C49
SX@1000P/50V_4

R35
SX@4.7K_4

2

C55
SX@1000P/50V_4

PP1800_PCH_S5

2

1

Q22 PJA138K

Level Shfiter (SOC_DEV)

Level Shfiter (SOC_DEV)

Level Shfiter (SOC_DEV)

Friday, April 25, 2014

Friday, April 25, 2014

Friday, April 25, 2014

1

9/9

PP3300_DX

R31
SX@4.7K_4

PP1000_PCH_SX_PG (27)

2

Q8

1 3

SX@DTC144EUA

9/9

PP3300_DX

R36
SX@4.7K_4

PP1350_PCH_SX_PG (35)

Q7

1 3

SX@DTC144EUA

3

ACINACPRESENT

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

NL6

NL6

NL6

ACIN (26,27,28)

of

1A

1A

1A

4115

4115

4115

5

4

3

2

1

SD/MMC CARD READER CONNECTOR (MMC)

1025 the damping of SDIO change to 0
ohm by Intel request

1025 add PU for SDIO WP by Intel request
1205 R551 changes to 1K to isolate SD

socket and servo/SoC
1205 SD3_WP is 1.8V power rail in SoC,

change external Pulled up power well of

D D

SD3_D3(5)
SD3_CMD(5)
SD3_CLK(5)
SD3_D0(5)
SD3_D1(5)
SD3_D2(5)
SD3_CD#(5,18)

SD3_WP(5)

C C

SDIO3_PWR_EN#(5)

SD3_WP to 1.8V power

R539

4.7K_4

Q58
PJA138K

SD_DAT3
SD_CMD_R
SD_CLK_R
SD_DAT0
SD_DAT1
SD_DAT2
SD_CD#_R
SD_WP_R

R160 10K_4

1202 add
C285 for
U18 input
inrush
current

C285

1u/6.3V_4

SDIO3_PWR_EN

SD3_D3

R489 0_4

SD3_CMD

R507 0_4

SD3_CLK

R526 0_4

SD3_D0

R541 0_4

SD3_D1

R549 0_4

SD3_D2

R550 0_4

SD3_CD#

R551 1K_4

SD3_WP SD_WP_R

R552 0_4

PP3300_DXPP1800_PCH

R154
*4.7K_4

3

2

1

PP1800_PCH

PP3300_DX

U18

5

IN

4

IN

3

ON/OFF

G5243AT11U

1115 U18 footprint
change to 5 pin which
is same as eDP power
switch

OUT

GND

This is full size SD card

CN15

C342

0.1U/10V_4

VCC_SD

11
10

9
8
7
6
5
4
3
2
1

WP
CD
DATA2
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
CD/DATA3

1

2

SD_WP_R
SD_CD#_R
SD_DAT2
SD_DAT1
SD_DAT0

SD_CLK_R

VCC_SD

SD_CMD_R

SD_DAT3

16

NC

17

NC

GND

GND

GND12GND

TAS_5-251301001000-6

14

13

15

1101 correct C351 footprint

C351

4.7U/6.3V_4

VCC_SD

C375
10U/6.3V_4

C373
*33P/50V_4

30mils

C371

0.1U/10V_4

SD_CLK_RSD_WP_R

C374

0.1U/10V_4

C376

0.1U/10V_4

C372
33P/50V_4

16

1211 add pulled up resistors on SDIO data/cmd lines

B B

A A

1212 all Pulled up resistors of SDIO data/cmd to be un-stuffed

VCC_SD

5

R559 *47K_4
R478 *47K_4
R563 *47K_4
R558 *47K_4
R562 *47K_4

SD_CMD_R
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

C397
*33P/50V_4

C394
*33P/50V_4

C395
*33P/50V_4

C396
*33P/50V_4

4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

3

2

Friday, April 25, 2014

PROJECT :

SDIO CardReader

SDIO CardReader

SDIO CardReader

NL6

NL6

NL6

1A

1A

1A

4116

4116

1

4116

1

eDP Power(VGA)

1u/6.3V_4

A A

SOC_DISP_ON(15)

R20 *0_4_S

PP3300_DX

C217

EDP_ON

R21

100K_4

eDP panel control(VGA)

B B

Touch Screen(VGA)

C C

2

1115 correct U11 orcad
symbol, pin5 need
connect to power input

U11

5

IN

4

IN

3

ON/OFF

G5243AT11U

EC_BL_DISABLE_L(27)

SOC_DPST_PWM(15)

SOC_EDP_BLON(15)

OUT

GND

sot23-5

1

2

D2 RB500V-40

3

LCDVCC_1

R17 *0_8_S
C31
*0.1u/10V_4

R341 *0_4_S

R340 2.2K_4

EC_BL_DISABLE#

R339

4

5

6

eDP(VGA)

1029 eDP power

LCDVCC

C28
*2.2u/6.3V_6 4.7u/25V_8

EC_BL_PWM_CONN

EC_BL_EN_CONN

C229

0.1u/10V_4

C227

0.01u/16V_4

R342

C226
*0.1u/10V_4

*100K_4

R338

*0_4_S R6 600,0.3A

*100K_4

C34

22u/6.3V_8

LCD_VIN

C25

DMIC(ADO)

DMIC_CLK_L(24)
DMIC_DAT_L(24)

C208

*150p/50V_4

C206
1000p/50V_4

C207
*150p/50V_4

change to PIC fuse

eDP

VIN

EDP_HPD(4)

EDP_AUXN(4)
EDP_AUXP(4)

EDP_TXP0(4)
EDP_TXN0(4)

EDP_TXP1(4)
EDP_TXN1(4)

EDP_TXP2(4)
EDP_TXN2(4)

EDP_TXP3(4)
EDP_TXN3(4)

CCD

I2C_4_SDA(7)
I2C_4_SCL(7)

ALS_INT#(6)

F1
KMC5S150RY24

1 2

R326 *0_4_S
C20 0.1u/10V_4

C19 0.1u/10V_4
C18 0.1u/10V_4

C17 0.1u/10V_4
C27 0.1u/10V_4

C26 0.1u/10V_4
C22 0.1u/10V_4

C21 0.1u/10V_4
C24 0.1u/10V_4

C23 0.1u/10V_4

R7 600,0.3A

I2C_4_SDA
I2C_4_SCL

LCD_VIN

LCDVCC

EC_BL_PWM_CONN
EC_BL_EN_CONN
EDP_HPD_CONN

EDP_AUXN_C
EDP_AUXP_C

EDP_TXP0_C
EDP_TXN0_C

EDP_TXP1_C
EDP_TXN1_C

EDP_TXP2_C
EDP_TXN2_C

EDP_TXP3_C
EDP_TXN3_C

CCD_PWR

R11 *0_4_S
R10 *0_4_S

R13 *0_4_S

7

Max 1.5A

Max 1.5A

150mA

USBP2+_R
USBP2-_R

DMIC_CLK
DMIC_DAT

SEN_SDATA
SEN_SCLK

ALS_INT#_R

CN1

G_5

40
39
38
37
36
35
34
33
32

G_4

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

G_1
9
8
7
6
5
4
3
2
1

G_0

CVS3402M1RA-NH

8

0225 add R355 as a sense resistor

I2C_5_SDA(7)
I2C_5_SCL(7)

D D

225 unstuff D16, use cap delay instead host

0
reset, and change C392 to100pF for delay, this
value could be adjusted after sequence tuning

1

PP5000

TS_INT#(15)

TOUCH_RST_L(27)

R224 *TS@0_6

D16 *TS@RB500V-40

PP5000_TS
I2C_5_SDA
I2C_5_SCL
TS_INT#

SOC3V3_RSTOUT_L

2

CN12

1
2
3
4
567

8

*TS@Touch_Panel_6P_50208-00601-001

3

4

CCD power(CCD)

PP3300_DX

C33

1U/6.3V_4

5

C30
*10p/50V_4

C29
1000p/50V_4

R14 *0_6_S

6

CCD_PWR

0.5A

CCD USB(CCD)

USBP2+(7)

USBP2-(7)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

7

R8 *0_4_S

USBP2+_R
USBP2-_R

R9 *0_4_S

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

LVDS/CCD/DMIC/TS

LVDS/CCD/DMIC/TS

LVDS/CCD/DMIC/TS

NL6

NL6

NL6

of

17 41Friday, April 25, 2014

17 41Friday, April 25, 2014

17 41Friday, April 25, 2014

8

1A

1A

1A

5

4

3

2

1

PIN7 OD
PIN14 OD

GOOGLE Debug Port(MPC)

PIN19 OD
PIN22 OD
PIN28 OD

50 pin BTB is MUST, don't use 42 pin

D D

PCH_SPI_CS0#_R(6) PCH_SPI_SI_R (6)

PCH_SPI_SO_R(6)

SPI_HOLD#_BIOS(6)

C C

EC_JTAG_TCK(27) PWR_BTN_L (26,27)
EC_JTAG_TMS(27) EC_JTAG_TDI (27)

B B

SD3_CD#(5,16)

EC_JTAG_TDO(27)

PP3300_EC

EC_UART0_TX(27)

PP3300_INA

HDMI_MB_HP(19)

H_PROCHOT#(5,27,33)

R540 GD@0_4

R536 GD@0_4
R545 GD@0_4
R208 GD@0_4
R537 GD@10_4
R522 *GD@10_4

Socket part number AXK750147G

CN9

1

1

PCH_SPI_CS0#_R
PCH_SPI_SO_R
SPI_HOLD#_BIOS

SOC_UART_TX_R
GPIO_SD_DECT
EC_JTAG_TCK
EC_JTAG_TMS EC_JTAG_TDI

EC_JTAG_TDO EC_JTAG_RTCK

EC JTAG

EC UART

EC_UART_TXD
PP3300_INA_R
I2C_SDA_INA I2C_SCL_INA
GPO_HPD GPIO_SPI_WP
GPIO_PROC_HOT#

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

GD@AXK750147G

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

PIN30 OD
PIN37 OD
PIN38 OD

SOC SPI

PCH_SPI_CLK_R
PCH_SPI_SI_R

GPIO_EC_RST#
SOC_UART_RX_R
SOC_UART_PWR

GPIO_PWR_BTN#

SYS_RESET#
EC_UART_RXD

SOC UART

PIN39 OD
PIN41 OD
PIN43 OD
PIN44 OD
PIN45 OD
PIN46 OD
PIN47 OD
PIN48 OD

R544 GD@10_4

R506 GD@10_4
R525 *GD@0_4

R524 GD@0_4
R538 GD@0_4

R216 GD@0_4

PIN49 OD
PIN50 OD

PP1800_PCH_ME

EC_JTAG_TCK

PP3300_EC

18

PCH_SPI_CLK_R (6)

A130828

EC_RST# (26,27)

SOC_REST_BTN# (6,11)

EC_UART0_RX (27)

I2C_SCL_INA_R (29,31,32)I2C_SDA_INA_R(29,31,32)

GPIO_SPI_WP (6)
LID_OPEN_L (23,27)

1021 change footprint and PN

SOC_UART_TX(7)
PCH_UART_TXD(27)
SOC_UART_RX(7)
PCH_UART_RXD(27)

SOC_UART_PWR

A A

R505 GD@0_4
R532 *GD@0_4
R499 GD@0_4
R504 *GD@0_4

R543 *GD@0_4
R535 GD@0_4

SOC_UART_TX_R

SOC_UART_RX_R

PP3300_EC
PP1800_PCH

9/13 add pull up

PP3300_INA

R207 GD@4.7K_4
R199 GD@4.7K_4

I2C_SCL_INA_R
I2C_SDA_INA_R

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

9/6 using optional instead of
level shifted, defult is from
SoC

5

4

PROJECT :

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Google Debug

Google Debug

Google Debug

Date: Sheet of

Date: Sheet of

3

Date: Sheet

2

NL6

NL6

NL6

18 41Friday, April 25, 2014

18 41Friday, April 25, 2014

18 41Friday, April 25, 2014

1A

1A

1A

of

1

5

HDMI Cost Reduced level shift (HDM) H

INT_HDMITX2N(4)
INT_HDMITX2P(4)

INT_HDMITX1N(4)
INT_HDMITX1P(4)

D D

INT_HDMITX0N(4)
INT_HDMITX0P(4)

INT_HDMICLK+(4)
INT_HDMICLK-(4)

Layout Notes:
Place decoupling CAPs
close to Connector

C C

PP3300_DX

C42 0.1u/10V_4
C44 0.1u/10V_4

C56 0.1u/10V_4
C57 0.1u/10V_4

C40 0.1u/10V_4
C41 0.1u/10V_4

C53 0.1u/10V_4
C48 0.1u/10V_4

R74 *SHORT_4

1115 remove R60 and change
R74 to Short PAD and size
to 0402

PP3300_HDMI

INT_HDMITX0N_C
INT_HDMITX0P_C

INT_HDMICLK+_C
INT_HDMICLK-_C

2

4

3

2

1

DMI connector (HDM)

1128 change HDMI CMC L2, this part

INT_HDMITX2N_C
INT_HDMITX2P_C

INT_HDMITX1N_C
INT_HDMITX1P_C

R349

R345

R371

R366

R356

620/F_4

620/F_4

620/F_4

620/F_4

3

Q15

2N7002K

1

R362 620/F_4

R359 620/F_4

INT_HDMICLK+_CONN

INT_HDMICLK-_CONN

620/F_4

R352

620/F_4

is recommended by Intel
1202 change HDMI CMC L2 to

DLP11TB800UL2L as Intel's recommendation
1205 L2 change back to DLP11SA900HL2

INT_HDMICLK+_C
INT_HDMICLK-_C

PP5000

Q2

3

IN

AP2331SA-7

OUT

GND

R41 *0_4_S

R37 *0_4_S

1
2

C32
*220p/50V_4

INT_HDMICLK-_CONN

D1
*14V/38V/100P_4

INT_HDMITX2P_C
INT_HDMITX2N_C

INT_HDMITX1P_C
INT_HDMITX1N_C

INT_HDMITX0P_C
INT_HDMITX0N_C

INT_HDMICLK+_CONN
INT_HDMICLK-_CONN

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

HDMI_5V
HDMI_MB_HP

12

RV1

*5V/0.2p_4

*1000p/50V_4

C39

CN2

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

C128E5-K1909-L

C37
*1000p/50V_4

20140115 change footprint for
HDMI,need check layout file
again

SHELL1
SHELL3

SHELL4
SHELL2

20
22

23
21

19

HDMI DDC (HDM)

1030 HDMI DDC
pulled up to

1115 change R72/R73

B B

to short PAD

PP1800_PCH

1121 remove R72/R73

PP1800_PCH

HDMI_DDCCLK_SW(4)

PP1800_PCH

HDMI_DDCDATA_SW(4)

A A

5

HDMI_DDCDATA_SW

R66 4.7K_4

R64 4.7K_4

2

1

Q13 FDV301N

2

1

Q12 FDV301N

4

R50 4.7K_4

3

R52 4.7K_4

3

HDMI_5V by intel
request

D4

RB500V-40

HDMI_DDCCLK_MBHDMI_DDCCLK_SW

D3

RB500V-40

HDMI_DDCDATA_MB

HDMI_5V

HDMI_5V

EMI HDMI-detect (HDM)

PP1800_PCH

INT_HDMI_HPD(4)

INT_HDMITX2P_C
INT_HDMITX1P_C
INT_HDMITX0P_C
INT_HDMICLK+_CONN

3

R565 121/F_4
R567 121/F_4
R564 121/F_4
R566 121/F_4

INT_HDMITX2N_C
INT_HDMITX1N_C
INT_HDMITX0N_C
INT_HDMICLK-_CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet

R27
10K_4

3

2

HDMI_MB_HP

Q3
2N7002K

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

HDMI

HDMI

HDMI

1

R24
100K/F_4

NL6

NL6

NL6

HDMI_MB_HP (18)

of

19 41Friday, April 25, 2014

19 41Friday, April 25, 2014

19 41Friday, April 25, 2014

1A

1A

1A

1

2

3

4

5

6

7

8

WIFI/BT COMBO (NGFF E KEY)

PP3300_WLAN

R39 *0_8_S

C244

C52

0.1u/10V_4

1023 change NGFF E key footprint and PN

A A

TP27
TP26

R55 0_4
R46 *0_4_S

TP28

TP30

TP3

TP2

TP25

TP29
TP1
TP35

WLAN_OFF_L POWER DOWN LAN CHIP from EC?
WIFI_DISABLE_L disable Antenna from PCH?

(Low Active)

RF_EN(15)
WLAN_OFF_L(27)

PLTRST#(14,22,27)

WIFI_SUSCLK(15)

LTE_SOUT(23)
LTE_SIN(23)

1118 add TP on pin38 for NFC function

R47 *10K_4

+WL_VDD

B B

NFC pin list

1.pin68-->NFC_ANT_N

2.pin66-->NFC_ANT_P

3.pin42-->NFC_WI_IN (1.8V)

4.pin40-->NFC_SWP2_IO (1.8V)

5.pin38-->NFC_ACTIVE (3.3V)

5.pin73-->NFC_NOT_ALLOWED (3.3V)

LTE Coexistence pin list (based on V0.2 spec

1.pin48-->LTE_SOUT (3.3V)

2.pin46-->LTE_SIN (3.3V)

PDN#

NFC_ANT_N
NFC_ANT_P
NFC_VDDANT

PIN54: disable Antenna

RF_EN
PDN#
WLAN_RST

PIN52: power down CHIP

LTE_SOUT
LTE_SIN

NFC Security

NFC_WI_IN
NFC_SWP2_IO
NFC_ACTIVE

WIFI_UART_RX

WIFI_UART_TX

BT_LED

WLAN_LED1#

+WL_VDD

+WL_VDD

74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32

30
28
26
24

22
20
18
16
14
12
10

CN3

3.3Vaux

3.3Vaux
NC
NFC_ANT_N
NFC_ANT_P
NFC_VDDANT
ALERT
I2C_CLK
I2C_DATA
W_DISABLE
PDN#
PERST0#
SUSCLK_32KHz
LTE_SOUT
LTE_SIN
NC
NFC_WI_IN
NFC_SWP2_IO
NC
UART_CTS
UART_RTS
UART_Rx

KEY
KEY
KEY
KEY

UART_Tx
UART_Wake
GND
LED#2
PCM_IN
PCM_OUT
PCM_SYNC

8

PCM_CLK

6

LED#1

4

3.3Vaux

2

3.3Vaux

0829 A20

NGFF

RESERVED
RESERVED

PETn1
PETp1

PERn1
PERp1

PEWake0#

CLKREQ0#
REFCLKN0

REFCLKP0

PETn0
PETp0

PERn0
PERp0

SLOT A-SD

SDIO_RESET

SDIO_WAKE

SDIO_DAT3
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0

SDIO_CMD

SDIO_CLK

USB_D-

USB_D+

GND76GND

77

WLAN_NGFF CONN(Type 2230)_80152-1721

75

GND

73

NFC_NOT_ALLOWED

71
69

GND

67
65
63

GND

61
59

WAKE/REQ 53, 55 OD

57

GND

55

WLAN_WAKE_L

53
51

GND

49
47
45

GND

43
41
39

GND

37
35
33

GND

31

KEY

29

KEY

27

KEY

25

KEY

23
21
19
17
15
13
11
9
7

GND

5
3
1

GND

1118 add TP on pin73 for NFC function

TP39

WLAN_WAKE_L (15)

CLK_PCIE_WLANN (6)
CLK_PCIE_WLANP (6)

PCIE_RX0-_WLAN (5)

PCIE_RX0+_WLAN (5)

PCIE_TX0-_WLAN (5)

PCIE_TX0+_WLAN (5)

BT

USBP3- (7)
USBP3+ (7)

R42
*10K_4

+WL_VDD

Q10 *PJA138K

3

R44 0_4

10u/6.3V_6

PP1800_PCH

2

1

PCIE_CLKREQ_WLAN#PCIE_CLKREQ_WLAN#_Q

+WL_VDD

C50
*0.1u/10V_4

PCIE_CLKREQ_WLAN# (5)

C51
*0.1u/10V_4

20

Video Codec (M.2 LGA 1216-S3) (VGA)

PP3300_DX

C C

PCIE_CLKREQ_IMAGE#(5)

D D

R1 *VC@0_8

VC@10u/6.3V_6

1

C5

C6
VC@0.1u/10V_4

PP1800_PCH

PCIE_CLKREQ_IMAGE# PCIE_CLKREQ_IMAGE#_Q

C3
*VC@0.1u/10V_4

+IMAGE_VDD

2

1

Q1 *VC@PJA138K

R3 *VC@0_4

3

2

C2
*VC@0.1u/10V_4

R2

*VC@10K_4

PLTRST# IMAGE_RST

CLK_PCIE_IMAGEN(6)
CLK_PCIE_IMAGEP(6)

PCIE_TX1-_IMAGE(5)
PCIE_TX1+_IMAGE(5)

R12 *VC@0_4

+IMAGE_VDD+IMAGE_VDD

3

U1

1

UIM_Power_In

2

UIM_Power_Out

3

UIM_SWP

4

3.3V

5

3.3V

6

GND

7

Reserved

8

ALERT#

9

I2C_CLK

10

I2C_DATA

11

COEX1

12

COEX2

13

COEX3

14

SYSCLK

15

TX_Blanking

16

Reserved

17

GND

18

Reserved

19

Reserved

20

GND

21

Reserved

22

Reserved

23

GND

24

Reserved

25

Reserved

26

GND

27

SUSCLK (32KHz)

28

W_DISABLE#1

29

PEWake#

30

CLKREQ#

31

PERST#

32

GND

33

REFCLKN0

34

REFCLKP0

35

GND

36

PERn0

37

PERp0

38

GND

*VC@M.2 LGA 1216-S3

74

79

80

77

76

75

GND

GND78GND

GND

GND

GND

GND

W/L 802.11A/B/G/N BT/FM MODULE AW-AM691N

GND90GND91GND92GND93GND94GND95GND96GND97GND98GND99GND

4

GND81GND82GND83GND84GND85GND86GND87GND88GND

SDIO Reset
SDIO Wake
SDIO DAT3
SDIO DAT2
SDIO DAT1
SDIO DAT0

UART_WAKE

UART_RTS

UART_CTS

W_DISABLE#2

GND

GND

GND

100

101

102

103

104

89

PETn0
PETp0

Reserved
Reserved
Reserved

SDIO CMD

SDIO CLK

UART_Rx
UART_Tx

PCMFR1

PCMOUT

BT_PCMIN

PCMCLK

LED#2
LED#1

Reserved
Reserved

USB_D-

USB_D+

GND

GND

105

106

39
40
41

GND

42
43
44

45
46
47
48
49
50
51
52

53
54
55
56
57

58
59
60
61
62

GND

63
64
65
66

67
68

GND

69
70

71

GND

72

3.3V

73

3.3V

GND

GND

GND

107

108

+IMAGE_VDD

5

PCIE_RX1-_IMAGE (5)

PCIE_RX1+_IMAGE (5)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

Date: Sheet of

Friday, April 25, 2014

6

Date: Sheet

7

PROJECT :

WIFI / BT / Image Codec

WIFI / BT / Image Codec

WIFI / BT / Image Codec

NL6

NL6

NL6

8

1A

1A

1A

of

4120

4120

4120

5

4

3

2

1

21

D D

1025 Delete complete SSD(connector and caps)

C C

EMMC (CBS)

B B

push-pull mode

EMMC_D0(5)
EMMC_D1(5)
EMMC_D2(5)
EMMC_D3(5)
EMMC_D4(5)
EMMC_D5(5)
EMMC_D6(5)
EMMC_D7(5)

EMMC_CMD(5)
EMMC_CLK(5)

EMMC_RST#(5)

1029 remove pulled up resistors for eMMC data and cmd

A A

1211 add back pulled up resistors
1212 all Pulled up resistors of eMMC data/cmd to be un-stuffed,

and R361 change to 47K ohm as well

PP1800_PCH

R396 *47K_4
R401 *47K_4
R469 *47K_4
R393 *47K_4
R406 *47K_4
R405 *47K_4
R404 *47K_4
R417 *47K_4
R361 *47K_4

5

1029 change R358 to 0

hm by intel request

o
1121 remove R365

1128 remove R358 by
intel requst and has
confirmed with EMI

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7
EMMC_CMD

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7

EMMC_CMD
EMMC_CLK

4

H3
H4
H5

J2
J3
J4
J5
J6

W5
W6

U5

U27

DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7

CMD
CLK

RST_n

SDIN8DE2-16G

111-1003316

K6

VCCQ1

AA5

VCCQ2

W4

VCCQ3

Y4

VCCQ4

AA3

VCCQ5

T10

VCC1

U9

VCC2

M6

VCC3

N5

VCC4

K2

EMMC_VDDIEMMC_RST#

VDDI

iNAND's internal power node

M7

VSS1

P5

VSS2

R10

VSS3

U8

VSS4

K4

VSSQ1

Y2

VSSQ2

Y5

VSSQ3

AA4

VSSQ4

AA6

VSSQ5

for host interface

VCCQ_EMMC

C232

0.1U/10V_4

for internal flash memory, 250mA

VCC_EMMC

C243

0.1U/10V_4

C257

0.1U/10V_4

C234

0.1U/10V_4

R411 *0_4_S

C233

4.7U/6.3V_4

R355 *0_6_S

C241

4.7U/6.3V_4

SandisK (16G) 153 pin SDIN8DE2-16G (11.5x13mm) : QPN: AKE3RZ-T101

3

PP1800_PCH

PP3300_PCH

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

SSD NGFF/ EMMC

SSD NGFF/ EMMC

SSD NGFF/ EMMC

NL6

NL6

NL6

21 41Friday, April 25, 2014

21 41Friday, April 25, 2014

1

21 41Friday, April 25, 2014

1A

1A

1A

1

2

3

4

TPM (CLG)

4 x100nF (place close to device VDD/GND pins)

A A

B B

TPM_VDD

R43 *9655@4.7K_4

0411 FAE : install R342 value is 4K7,

nd PIN7 wo an internal PD

a

TPM_VDD

12

R38
*9655@20K_4

R51 *9655@0_4_S

TPM_GPIO

TPM_PP

C58
9655@0.1U/10V_4

pin5,6,9,19,25,28 are difference between both

6
2

7

13

14

U13

GPIO/NC6
NC2

PP
NC13

NC14

C45
9655@0.1U/10V_4

TPM SLB9655

8

NC8

12

NC12

3

NC3

1

C C

NC1

PROG IC OTHER(28P)SLB9655TT1.2FW4.32GOOG

GND[1]4GND[2]11GND[3]18GND[4]/NC25

25

R57 *9655@0_4_S

TPM_VDD

VDD[4]

VDD[3]/NC5

VDD[2]

VDD[1]/NC19

LCLK

LFRAME#

LAD3
LAD2
LAD1
LAD0

NC28/LPCPD#

LRESET#[1]

LRESET#[2]/NC9

SERIRQ

NC15

C245

0.1U/10V_4

If stuff ST TPM,C250
change to 10uF
(CH6101M9B02)

10
5

R60 *9655@0_4_S

24
19

R72 *9655@0_4_S

21
22

17
20
23
26

28
16

9
27

15

0411 FAE : a 0ohm between pin9 to LRESET signals

TPM_RST_R

SERIRQ_R

C250
SP@0.1U/10V_4

near pin 21 as possible

C246 *10p/50V_4

R56 9655@0_4

R28 10K_4
R353 *0_4

1128 add pullup 10K on
SERIRQ_R to TPM_VDD

PP3300_DX

R61

2.2_6

PCLK_TPM (7)

LPC_LFRAME# (7,27)

LPC_LAD3 (7,27)
LPC_LAD2 (7,27)
LPC_LAD1 (7,27)
LPC_LAD0 (7,27)

PLTRST# (14,20,27)

TPM_VDD

IRQ_SERIRQ (14,27)

22

20140210 R353 unstaff

1211 co-layout ST and Infineon TPM, if change to ST,
R56,R57,R60,R72,R38, ST PN is ST33ZP24AR28PVSM

LED(UIF)

BAT_LED0(27)
BAT_LED1(27)

D D

1

R246 300_4
R245 300_4

0319 Del Power LED

Battery LED

Green

2

3

1

Org

2

2014/03/19 modify

LED1
LED 3P ORG/BLUE

PP3300_DSW

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TPM SLB9655 / LED

TPM SLB9655 / LED

TPM SLB9655 / LED

Date: Sheet of

Date: Sheet of

3

Date: Sheet of

NL6

NL6

NL6

4

1A

1A

1A

22 41Friday, April 25, 2014

22 41Friday, April 25, 2014

22 41Friday, April 25, 2014

A

Thermal Sensor(THM)

PP3300_THM

C43 0.1u/10V_4

4 4

EC_SMB2_CLK(27)

EC_SMB2_DATA(27)

ALERT#(5)

3 3

2 2

USB Switch Current Control

1 1

USB_ILIM_SEL(25,27)

1022 change thermal IC
s

olution

ALERT#

OVERT#

U12 TMP432ADGSR

10

SCLK

9

SDA

8

ALERT#

7

OVERT#
GND6DN2

ADDR=0x4C

Place oo PCB BOT
Local Temp.

1030 Thermal IC VDD has two option, ome is PP3300_DSW(
=PP3300_EC), another is PP3300_DX, default is stuffing to
DSW rail

PP3300_THM

VCC
DP1
DN1
DP2

1
2
3
4
5

C46
2200p/50V_4

C86
2200p/50V_4

1025 remove Q31 becasue PU to PP3300_DSW at EC side already

EC_RST#_R(27)

2

1

Q18 2N7002K

A

3

R77 10K_4

USB2_ILIM_SEL

R370 *0_4_S

PP3300_DSW

R67 *0_4_S

B

H_THRMDA

H_THRMDC
H_THRMDA2

H_THRMDC2

R376 *0_4
R377 0_4

OVERT#EC_RST#_R

USB3_STATUS_L (25)

B

Place oo PCB TOP
Remote Temp.

Base: PIN 1
Emitter: PIN 2
Collector: PIN 3

Q52

1

MMBT3904LP-7

2 3

Q56

1

MMBT3904LP-7

2 3

Place oo PCB ?
Remote Temp.

PP3300_DX
PP3300_DSW

C

FUNCTION DB

LTE(MNC)

PP3300_DSW

C122

*3G@1U/6.3V_4

PP5000_DSW

PP3300_LTE_EN(27)

C

LTE_PWREN_R

C104

*3G@2200p/50V_4

C100 *3G@0.1u/10V_4

U23
*3G@TPS22965DSGR

1

VIN_01
VIN_022VOUT_01

3

ON

4

VBIAS

USBP1-(7)
USBP1+(7)

R194 *3G@0_4_S

R175
*3G@100K_4

D

VOUT_02

CT

GND

PAD

9

LTE_PWREN_R

12

C112
*3G@0.047u/25V_4

D

PP5000_DSW

8
7
6
5

LTE_SUSCLK(15)

PP3300_PCH_S5

E

23

+3V_LTE

MAX 2.5A

C121
*3G@0.1u/10V_4

C113
*3G@470p/50V_4

USB2_PWR_EN(27)

USB_CTL1(25,27)

USB2_STATUS_L(25)

4 3
1

L16 DLP11SN900HL2L

LID_OPEN_L(18,27)

LTE_SOUT(20)

LTE_SIN(20)

SIM_DET(15)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

USB_OC1#(7,14)

2

PP3300_DSW
PP3300_RTC

PP3300_DX

+3V_LTE

2.5A

LTE_SOUT
LTE_SIN
SIM_DET
LTE_SUSCLK

LTE_DISABLE_L(15)

LTE_WAKE_L(15)

DB/ALS/Thermal sensor

DB/ALS/Thermal sensor

DB/ALS/Thermal sensor

PP5000

2A

40 41
39
38

37

USB2_ILIM_SEL
USB2_PWR_EN
USB_CTL1
USB2_STATUS_L
USB_OC1#

USBP1-_C
USBP1+_C

R547 1K_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

LID_OPEN#

LTE_DISABLE_L
LTE_WAKE_L

E

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9
8
7
6
5
4
3
2
1

88511-4001_DB_CONN

NL6

NL6

NL6

23 41Friday, April 25, 2014

23 41Friday, April 25, 2014

23 41Friday, April 25, 2014

CN7

42

1A

1A

1A

of

5

AUDIO CODEC (ADO)

BOM Change to 0_4 due to material shortage

PP1800_PCH

R217 *0_6_S

C359

D D

C C

0.1U/10V_4

L13 60ohm@100MHz_4

C364
1U/16V_4

I2S_MCLK(6)

I2S_BCLK_R(5)

I2S_LRCLK_R(5)

I2S_DOUT_R(5)

I2S_DIN_R(5)

I2C_1_SDA_R(7)

I2C_1_SCL_R(7)

MUX_AUD_INT1#(6)

PP1800_CODEC_AVDD

DMIC_DAT_L(17)
DMIC_CLK_L(17)

C138
1U/10V_4

C358
1U/16V_4

C120 1U/10V_4

RCVN

C119 1U/10V_4

C135
1U/10V_4

C357
1U/16V_4

R228 *0_4_S

R219 *0_4_S
R225 10K_4

C133
1U/16V_4

PP1800_CODEC_AVDD

Close to PIN38Close to PIN26

C363

C360

10u/6.3V_4

0.1U/10V_4

CODEC_CLK_IN

CODEC_INT_OD_L

CODEC_MIC_L_PRCVP
CODEC_MIC_L_N

CODEC_C1P

CODEC_C1N

28

U25

DVDDIO

35

MCLK

33

BCLK

32

LRCLK

30

SDIN

31

SDOUT

37

SDA

36

SCL

34

IRQ_L

19

IN1/DMD

18

IN2/DMC

20

IN3

21

IN4

39

C1P

40

C1N

3

CPVDD

2

CPVSS

4

26

27

38

AVDD

DVDD

HPVDD

RCVP/LOUTL

RCVN/LOUTR

MAX98090AETL+T

13

14

SPKLVDD

SPKRVDD

SPKLP
SPKLN
SPKRP
SPKRN

MICBIAS

HPSNS

JACKSNS

DGND29AGND25HPGND1SPKRGND10SPKLGND

3

SOC DET

+5VA

C365

0.1U/10V_4

C118
1U/10V_4

C116
1U/10V_4

C367
10U/6.3V_4

R223 *0_4_S

R238 5.6_4
R239 5.6_4

C117

2.2U/6.3V_4

HPL
HPR

R240
*4.7K_4

MICBIAS

R237
*4.7K_4

C366
1U/16V_4

16

L_SPK+

15

L_SPK-

12

R_SPK+

11

R_SPK-

22

8
9

5

RCVN

7

MIC_DET

4

HPOUT-L

HPL

6

HPOUT-R

HPR

23

REF

24

BIAS

17

DET_TRIGGER(5) AJACK_MICPRES_L(5)

HEADPHONE/Mic combo(ADO)

SLEEVE SLEEVE_R
SLEEVE_SENSE

RING2_SENSE

HPR

HPL

2

PP1800_PCH

3

1

L9 80ohm@100MHz
R231 0_4

L8 80ohm@100MHz
R222 0_4

L11 0_6

L10 0_6

10P/50V_4

R176
330K_4

C132

2

Q38
2N7002K

C99
1U/6.3V_4

HP_JD_L

C137
10P/50V_4

RING2_RRING2

*100P/50V_4

1

24

PP1800_PCH

AJACK_MICPRES_LDET_TRIGGER

R124 10K_4

combo jack
Normal open

P/N: DFTJ06FR652
Normal Open
PIN1 --> L?
PIN2 --> R?
PIN3 --> GND/MIC?
PIN4 --> MIC/GND?
PIN5 --> JD?
PIN6 --> GND?
PIN7 --> Shielding?

20140115 change
headphone footprint
and PN, need check
pin out again

CN6

SLEEVE_R
HPR_SYS
HP_JD_L

HPL_SYS
RING2_R

C130

C124
*100P/50V_4

HP_JD_L
SLEEVE
HPR_SYS
HPL_SYS
RING2

ESD 2'nd CY00G050B00

ESD 2'nd CY00G050B00

4
2
6
5

1
3

COMBOJACK_2SJ3072-110111F

1 2

D24 *14V/38V/100P_4

1 2

D21 *14V/38V/100P_4

1 2

D22 *14V/38V/100P_4

1 2

D20 *14V/38V/100P_4

1 2

D19 *14V/38V/100P_4

B B

Audio Headset Switch

PP3300_RTC

1209 reserve R220
connection from RCVP to
MIC_DET as back up in
case driver needs to be
through codec using
JACKSNS pin

A A

10mils

L14 100ohm@100MHz

C368

0.1U/10V_4

MIC_DET

PP3300_RTC

PP3300_ADO_SW

MICBIAS

16

VDD1

VDD2

TS3A225E

4

15

SLEEVE_SENSE

14

6

SLEEVE
TIP_SENSE

RING2_SENSE

DET_TRIGGER

/MIC_PRESENT8ADDR_SEL

13

U26

R234

2.2K_4

R220 *0_4

R236 10K_4
R233 10K_4 R241 *0_6_S

RCVP

RCVN

R230 10K_4

I2C_MIC_SW_SDA
I2C_MIC_SW_SCL

AJACK_MICPRES_L

5

11

MICP

12

MICN

2

SDA

1

SCL

TS3A225ERTER (QFN)

SLEEVE_SENSE
RING2_SENSE
SLEEVE
RING2

7

R243 330K_4

R244 *0_4_S

PP3300_RTC PP3300_RTC

HP_JDDET_TRIGGER_SW

3

2

Q51
2N7002K

1

R242
330K_4

HP_JD_L

3

RING2

GND13PGND

10

9

HPL

5

GND2

17

4

C140
1U/6.3V_4

Codec PWR 5V(ADO)

PP5000

C125

C126
*10U/6.3V_6

*0.1u/10V_4

Internal Speaker

40mil for each signal

L_SPK+
L_SPK­R_SPK+

R229 *0_6_S
R232 *0_6_S
R235 *0_6_S

C128

10P/50V_4

C134
10P/50V_4

2

C136
10P/50V_4

DIGITAL

follow 0c1 pin define

ANALOG

L12 PBY160808T-181Y-N_2A_6

C370

0.1u/10V_4

L_SPK+_1
L_SPK-_1
R_SPK+_1

R_SPK-_1R_SPK-

C139
10P/50V_4

CN11

1
2
345

6

SPK_CONN_4P_88266-04001-06

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

AVDD1

+5VA

C369
10u/6.3V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

MAX98090/HP/SPK

MAX98090/HP/SPK

MAX98090/HP/SPK

Friday, April 25, 2014

Friday, April 25, 2014

Friday, April 25, 2014

NL6

NL6

NL6

1

1A

1A

1A

of

4124

4124

4124

5

USB3.0(USB)

USB3PWR

80 mils (Iout=2A)

D D

1121 remove R91,R92,R94,R85 for
cancelling non USB charger SKU

USB3_RXN0(7)
USB3_RXP0(7)

USB3_TXN0(7)
USB3_TXP0(7)

C C

C71 0.1u/10V_4
C67 0.1u/10V_4

1121 change USB3 CMC L5,L3, this part
is recommended by Intel

1202 change USB3 CMC L5,L3 to
DLP11TB800UL2L as Intel's recommendation

1205 Swap L3,L5 pin for layout smoothly

220U/6.3V/ESR25_7343

USBP0-_L
USBP0+_L

USB3_RXN0
USB3_RXP0

USB3_TXN0_C
USB3_TXP0_C

12

C78

R93 *0_4_S

R87 *0_4_S
R106 *0_4_S

R101 *0_4_S

R82 *0_4_S

R78 *0_4_S

4

+

USB3PWR

C66
1000p/50V_4

20140115 change footprint
for USB3,need check
layout file again

USB 3.0 Connector

USBP0-_C
USBP0+_C

USB3_RXN0_R
USB3_RXP0_R

USB3_TXN0_R
USB3_TXP0_R

USBP0-_C
USBP0+_C
USB3_RXN0_R
USB3_RXP0_R
USB3_TXN0_R
USB3_TXP0_R

USB3.0 CONN_2UB4032-010101F

D8 *5V/0.2p_4

1 2

D9 *5V/0.2p_4

1 2

D10 *5V/0.2p_4

1 2

D7 *5V/0.2p_4

1 2

D6 *5V/0.2p_4

1 2

D5 *5V/0.2p_4

1 2

3

2

1

USB Charger

PP5000

C73

0.1U/10V_4

USB3_STATUS_L(23)

USB_OC0#(7,14)

USB3_PWR_EN(27)

CN4

1

VBUS

1

2

D-

2

3

D+

3

4

4

GND

5

SSRX-

5

6

6

SSRX+

7

7

GND

8

8

SSTX-

9

SSTX+

9

11111010131312

12

RILIM_LO is optional and the ILIM_LO pin may be left

1. ILIM_SEL is always set high

2. Load Detection - Port Power Management is not used

3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

PP3300_EC

USB_CTL1(23,27)

80 mils (Iout=2A)

R69 10K_4
R68 10K_4

D23

BZT52-B5V6S(5.6V)

USB_OC0#
USB3_ILIM_SEL

USB3_PWR_EN

USB3_CTL2
USB3_CTL3

U15

1

2 1

IN

9

STATUS

13

FAULT

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2
CTL38DP_OUT

TPS2546RTER/GL887T-OCGO

R100
100K_4

USB_ILIM_SEL(23,27)

OUT

ILIM_LO

ILIM_HI

GND_PAD

GND

DM_IN
DP_IN

DM_OUT

12
15

16

17
14

11
10

2
3

1

Q14 2N7002K

80 mils (Iout=2A)

USB3PWR
ILIM_LO

ILIM_HI

(RILIM_HI 1.96A)

USBP0-_L
USBP0+_L

USBP0­USBP0+

2

3

unconnected if the following conditions are met:

IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}

USB3PWR

R105

25.5K/F_4

R70 10K_4

USB3_ILIM_SEL

USBP0- (7)

USBP0+ (7)

PP3300_EC

R390 *0_4_S

25

(RILIM_LO 1.07A)

R104
47K_4

USB2_STATUS_L (23)

HOLE(OTH)

HOLE1
*o-nl6-1

B B

1

HOLE11
*H-C236D98P2

1

HOLE3
*H-C236I217D98P2

1

HOLE4
*H-C236I138D98P2

1023 change footprint for
Hole3,4,5

HOLE5
*H-C236I217D98P2

1

1

1101 change Hole4 footprint

PAD1
*spad-re89x197

1

R85 *0_4

0221 change batt_en# function from hole1 to PAD1, PAD2

1212 Stuff NUT on Hole4,5

HOLE2
*H-C236i98D98P2

HOLE7
*H-C236D98G

67
5

8

4

9

123

1024 change footprint for
Hole1,7,9

1211 change footprint for

Hole9

A A

HOLE9
*HG-C236D98P2

8
9

123

5

67
5
4

1

HOLE8
*O-0C2A-4

1 3

HOLE6
*H-C236D98P2

1

SPI_WP_R

2

HOLE10
*O-0C2A-1

1

ROM WP#

R519 1K_4

4

1212 add 2 holes , leave N.C

SPI_WP_ME (6,27)

PAD2
*spad-re89x197

HOLE12
*H-C98D98N

1

1

BATT_EN# (26,28)

3

HOLE13
*H-C102X94D102X94N

1

VIN PP1000_PCH

C35
*1000p/50V_4

C36
*1000p/50V_4

C82
*1000p/50V_4

C330

*100P/50V_4

0218 reserve C330 for EMI request

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

NL6

NL6

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

USB3/Charger/Hole

USB3/Charger/Hole

USB3/Charger/Hole

NL6

1A

1A

25 41Friday, April 25, 2014

25 41Friday, April 25, 2014

25 41Friday, April 25, 2014

1

1A

5

4

3

K/B (KBC) Track PAD BOARD CONN (TPD)

2

1

CN10

7

66G1

5

8

5

G2

4

4

3

3

2

2

1

1

TRACK_PAD_6P

TP_PWR

26

0.5A

20140127 Change KB CONN for ME require

KB_CONN_51518-03001-001

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

CN8

7 8
5
3
1

CP2 *100p/50Vx4

31
32

KB_COL07

6

KB_COL06

4

KB_ROW07

2

KB_COL04

C111 *100p/50V_4
C110 *100p/50V_4

KB_COL01
KB_PWR_ON_L

Track Pad interrupt

TRACKPAD_INT#(6)

TRACKPAD_INT_DX(7)

DSW

DX

4/25 modify for leakage

D12

RB501V-40

VF = 0.34V

TP_PWR

2N7002K

Q44

3

1

L7 *0_6_S

TP_PWR

R623

4.7K_4

2

3

Q60

2N7002K

1

PP3300_DSW

C362

1U/6.3V_4

KB_ROW02_SW

KB_COL02_SW

KB_PWR_ON_L

KB_ROW03

6

KB_ROW06

4

KB_ROW05

2

KB_ROW10

KB_COL05

6

KB_ROW00

4

KB_COL02_SW

2

KB_COL03

KB_ROW12
KB_ROW08
KB_ROW09
KB_ROW11
KB_ROW10

KB_ROW05
KB_ROW06

KB_ROW03
KB_COL00

KB_ROW01
KB_ROW04
KB_COL03

KB_ROW00
KB_COL05
KB_COL04
KB_ROW07
KB_COL06
KB_COL07
KB_COL01

KB_ROW12(27)

D D

PWR_BTN_L(18,27)

C C

7 8
5
3
1

CP1 *100p/50Vx4

7 8
5
3
1

CP4 *100p/50Vx4

KB_ROW11

6

KB_ROW09

4

KB_ROW08

2

KB_ROW12

KB_ROW04

6

KB_ROW01

4

KB_COL00

2

KB_ROW02_SW

KB_ROW08(27)
KB_ROW09(27)
KB_ROW11(27)
KB_ROW10(27)

KB_ROW05(27)
KB_ROW06(27)

KB_ROW03(27)

KB_COL00(27)

KB_ROW01(27)
KB_ROW04(27)

KB_COL03(27)

KB_ROW00(27)
KB_COL05(27)
KB_COL04(27)

KB_ROW07(27)
KB_COL06(27)
KB_COL07(27)
KB_COL01(27)

R213 *0_4_S

7 8
5
3
1

CP5 *100p/50Vx4

7 8
5
3
1

CP3 *100p/50Vx4

I2C_0_SDA
I2C_0_SCL

C123

0.1u/10V_4

R624

4.7K_4

2

TOUCHPANEL_PWR_R

TP_SHDN_L(27)

1 2

D18 5V/0.2p_4

1 2

D17 5V/0.2p_4

30mil

I2C_0_SDA(15)
I2C_0_SCL(15)

TRACKPAD_INT_L_CONN

U24

A2
B2

IN

OUT

EN

GND

TPS22930

R227 *0_4_S

A1
B1

+TPVDD
I2C_0_SDA
I2C_0_SCL

C108
*10p/50V_4

TOUCHPANEL_PWR_R

R206 *0_6_S
C114
1000p/50V_4

R226
100K_4

HOLELESS RESET

B B

2-CHIP(KBC)

5/15 modify,PU already at EC side

PP3300_RTC

R144
*1M_4

BATT_ENABLE

C393

A A

*2.2U/6.3V_4

5

R454
*4.7K_4

BATT_EN#

3

Q33

2

*2N7002K

1

BATT_EN# (25,28)

ACIN(15,27,28)

R498 0_4

*100K/F_4

if not use ACIN, should tied to GND

PP3300_RTC

Pin 3,5,8,11 Open Drain

R476 4.7K_4
R451 *4.7K_4
R450 *4.7K_4

1023 EC_IN_RW is OD,
remove level shift and PU
to PP1800_PCH

4

R475

PWR_BTN_L
BATT_ENABLE
ACPRESENT_4137

KB_COL02_SW

KB_ROW02_SW
KB_COL02
EC_IN_RW

R474

10K_4

SLG4K4213VTR(TDFN-12)

U17

2

PWR_BTN_L

3

BATT_ENABLE

4

AC_PRESENT

5

KSO_SW

6

KSI_SW

PP3300_RTC

1

VDD

EC_ENTERING_RW

GND

PAD_GND

7

13

3

C345

0.1u/10V_4

12

EC_RST_L

EC_IN_RW

KSO_INV

KSI

EC_RST#

11

EC_IN_RW

10

EC_ENTERING_RW

9

KB_ROW02KB_ROW02_SW

8

KB_COL02

co-layout 4K4108 and 4K4137
SLG4K4108 (AL004108000)
SLG4K4137 (AL004137000)
4K4137 PIN3 is BATT_ENABLE
4K4137 PIN4 is AC_PRESENT

EC_RST# (18,27)
EC_IN_RW (15)

EC_ENTERING_RW (27)

KB_ROW02 (27)

KB_COL02 (27)

2

Connect to EC reset pin
Connect to GPIO on CPU

with PU to GPIO power
well

Connect to EC pin C5 (must
be low when EC IN RESET)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

NL6

NL6

PROJECT :

PROJECT :

PROJECT :

KB/TP/FAN/HW Reset

KB/TP/FAN/HW Reset

KB/TP/FAN/HW Reset

NL6

26 41Friday, April 25, 2014

26 41Friday, April 25, 2014

1

26 41Friday, April 25, 2014

1A

1A

1A

of

5

EC(KBC)

D D

1023 SWAP RP1 pin for layout

C C

SPI_WP_ME(6,25)

B B

PP3300_EC

A A

PP3300_EC

C327

C77

1u/6.3V_4

1u/6.3V_4

RP1 10K_10P8R

1

9

2

8

3

7 4

56

PP3300_EC

R518
100K_4

EC_LPCPD#PCH_SUS_STAT_L

KB_COL01
KB_COL02KB_COL07
KB_COL00
KB_COL03KB_COL04

R495100K_4

PP3300_EC

KB_COL06
KB_COL05

R126 *0_4

10

0206 Disconnect SPI SIO I/F

TP_SHDN_L(26)
BAT_LED0(22)
PP3300_DX_EN(30)

WLAN_OFF_L(20)
PP3300_PCH_PG(35)
IMVP_PWRGD_3V(32,33,35)

SUSP_VR_EN(32)

PP1050_PCH_PG(32,34)

PP1000_PCH_SX_PG(15)

PP5000_PGOOD(29)

R516

*100K_4

R490

100K_4

PP3300_DSW_EN(29)

PP3300_LTE_EN(23)
USB2_PWR_EN(23)

EC_ENTERING_RW(26)

USB3_PWR_EN(25)

EC_RST#(18,26)

EC_RST#_R(23)

EC_BRD_ID1
EC_BRD_ID2
EC_BRD_ID3

5

0206 Disconnect SPI SIO I/F

R520

R514

100K_4

*100K_4

R497

R493

*100K_4

100K_4

VCORE_EN(33)

USB_ILIM_SEL(23,25)
USB_CTL1(23,25)

PWR_BTN_L(18,26)

PP1350_EN(31)

PP5000_EN(29)

USB_OC1_L(14)

ICMNT(28)

USB_OC0_L(14)

C340

0.1U/10V_4

TP71
TP72

TP46

TP73
TP74

R164 0_4

C333

0.1U/10V_4

LPC_LAD0(7,22)
LPC_LAD1(7,22)
LPC_LAD2(7,22)
LPC_LAD3(7,22)

CLK_PCI_EC(7)

LPC_LFRAME#(7,22)

EC_SCI_L(14)

IRQ_SERIRQ(14,22)

KB_COL00(26)
KB_COL01(26)
KB_COL02(26)
KB_COL03(26)
KB_COL04(26)
KB_COL05(26)
KB_COL06(26)
KB_COL07(26)

KB_ROW00(26)
KB_ROW01(26)
KB_ROW02(26)
KB_ROW03(26)
KB_ROW04(26)
KB_ROW05(26)
KB_ROW06(26)
KB_ROW07(26)
KB_ROW08(26)
KB_ROW09(26)
KB_ROW10(26)
KB_ROW11(26)
KB_ROW12(26)

TP60
TP59
TP58
TP57

R173 *0_4_S
R169 *0_4_S

R162 SX@0_4

TP56
TP55

TP54

TP14
TP13

C320

0.1U/10V_4

PLTRST#(14,20,22)

C96 0.1U/10V_4

C321

C335

1000p/50V_4

0.1U/10V_4

EC_LPCPD#

KB_COL00
KB_COL01
KB_COL02
KB_COL03
KB_COL04
KB_COL05
KB_COL06
KB_COL07

KB_ROW00
KB_ROW01
KB_ROW02
KB_ROW03
KB_ROW04
KB_ROW05
KB_ROW06
KB_ROW07
KB_ROW08
KB_ROW09
KB_ROW10
KB_ROW11
KB_ROW12

PWR_BTN_L
LID_OPEN_R
EC_SPI_WP_D
EC_PA5
EC_PB0
EC_PB1
EC_PB4
PROCHOT_EC
SIO_SPI_MOSI_EC
SIO_SPI_MISO_EC

TP_SHDN_L
BAT_LED0
PP3300_DX_EN
PJ3_T2CCP1_U5TX
WLAN_OFF_L

PP3300_PCH_PG
VCORE_EN_R
IMVP_PWRGD_3V_R
SUSP_VR_EN
PP1050_PCH_PG
PP1350_EN
PP1000_PCH_SX_PG_R
PP5000_EN
PP5000_PGOOD
PP3300_DSW_EN

SIO_SPI_CLK_EC
SIO_SPI_CS_L
PP3300_LTE_EN
USB2_PWR_EN
EC_ENTERING_RW
EC_PD7
USB_OC1_L
EC_PE1
EC_PE2
ICMNT
USB3_PWR_EN
USB_ILIM_SEL
USB_CTL1
USB_OC0_L

EC_BRD_ID1
EC_BRD_ID2
EC_BRD_ID3

EC_RST#_R

Proto1/1.5/2.0 0
Proto2.0 0 0 1

1213 Board ID of proto2 change to 001

4

C344
1000p/50V_4

D7

E6

E8

E9

J10

U16

B13

PL3/LPC0AD0/T1CCP1/WT1CCP1

A13

PL2/LPC0AD1/T1CCP0/WT1CCP0

C12

PL1/LPC0AD2/T0CCP1/WT0CCP1

D11

PL0/LPC0AD3/T0CCP0/WT0CCP0

H12

PM5/LPC0CLK

D12

PL4/LPC0FRAME_L/T2CCP0/WT2CCP0

F13

PM0/LPC0PD_L/T4CCP0/WT4CCP0

C13

PL5/LPC0RESET_L/T2CCP1/WT2CCP1

F12

PM1/LPC0SCI_L/T4CCP1/WT4CCP1

H13

PM4/LPC0SERIRQ

G2

PK0/AIN16/SSI3CLK

G1

PK1/AIN17/SSI3FSS

H1

PK2/AIN18/SSI3RX

H2

PK3/AIN19/SSI3TX

B11

PK4/RTCCLK/U7RX

B12

PK5/U7TX

C11

PK6/FAN0PWM1/WT1CCP0

A12

PK7/FAN0TACH1/WT1CCP1

M13

PP0/T4CCP0

L12

PP1/T4CCP1

M5

PP2/T5CCP0

J12

PP3/T5CCP1

J13

PP4/WT0CCP0

L5

PP5/WT0CCP1

D8

PP6/WT1CCP0

K6

PP7/WT1CCP1

D4

PQ0/WT2CCP0

E4

PQ1/WT2CCP1

F5

PQ2/WT3CCP0

N5

PQ3/WT3CCP1

N6

PQ4/WT4CCP0

M2

PA2/SSI0CLK

M3

PA3/SSI0FSS

L4

PA4/SSI0RX

N1

PA5/SSI0TX

F11

PB0/T2CCP0/U1RX

E11

PB1/T2CCP1/U1TX

B6

PB4/AIN10/SSI2CLK/T1CCP0

A6

PB5/AIN11/SSI2FSS/T1CCP1

C2

PD2/AIN13/SSI1RX/SSI3RX/WT3CCP0

C1

PD3/AIN12/SSI1TX/SSI3TX/WT3CCP1

B8

PN1/AIN22

N11

PN6/FAN0PWM4/WT4CCP0

A9

PJ2/T2CCP0/U5RX

C8

PJ3/T2CCP1/U5TX

D5

PJ4/C2_P/T3CCP0/U6RX

L2

PC4/C1_M/U1RX/U4RX/WT0CCP0

L1

PC5/C1_P/U1TX/U4TX/WT0CCP1

K1

PC6/C0_P/U3RX/WT1CCP0

K2

PC7/C0_M/U3TX/WT1CCP1

J3

PH4/SSI2CLK/WT3CCP0

H4

PH5/SSI2FSS/WT3CCP1

H3

PH6/SSI2RX/WT4CCP0

G4

PH7/SSI2TX/WT4CCP1

A8

PN0/AIN23

M12

HIB_L

B2

PD0/AIN15/I2C3SCL/SSI1CLK/SSI3CLK/WT2CCP0

B1

PD1/AIN14/I2C3SDA/SSI1FSS/SSI3FSS/WT2CCP1

A4

PD4/AIN7/U6RX/WT4CCP0

B4

PD5/AIN6/U6TX/WT4CCP1

A3

PD6/AIN5/U2RX/WT5CCP0

B3

PD7/AIN4/NMI/U2TX/WT5CCP1

F1

PE0/AIN3/U7RX

F2

PE1/AIN2/U7TX

E1

PE2/AIN1

E2

PE3/AIN0

A5

PE4/AIN9/I2CSCL/U5RX

B5

PE5/AIN8/I2CSDA/U5TX

A7

PE6/AIN21

B7

PE7/AIN20

K5

PQ5/WT4CCP1

M6

PQ6/WT5CCP0

L6

PQ7/WT5CCP1

G12

OSC0

G13

OSC1

G10

RST_L

TM4E1G31H6ZRBI

F10

VDD1

VDD2

VDD3

VDD4

VDD5

PERIPHERAL INTF

D3

J9

J7

VDD8

VDD6

VDD7

LPC

KB

LOAD SW

VR CTRL

USB CHARGE CTRL

BRD ID

C343

2.2U/6.3V_4

K13

VDDA

SMBUS INTF

TO PCH

FAN

VDDC1D6VDDC2J1VDDC3J6VDDC4

PB2/I2C0SCL/T3CCP0

PB3/I2C0SDA/T3CCP1

PB6/I2C5SCL/SSI2RX/T0CCP0
PB7/I2C5SDA/SSI2TX/T0CCP1

PF0/NMI/SSI1RX/T0CCP0/TRD2

PF1/SSI1TX/T0CCP1/TRD1

PF2/NMI/SSI1CLK/T1CCP0/TRD0

PF3/SSI1FSS/T1CCP1/TRCLK

PF6/I2C2SCL/T3CCP0
PF7/I2C2SDA/T3CCP1
PG0/I2C3SCL/T4CCP0

PG1/I2C3SDA/T4CCP1

PG2/I2C4SCL/T5CCP0

PG3/I2C4SDA/T3CCP1

PG4/I2C1SCL/U2RX/WT0CCP0

PG5/I2C1SDA/U2TX/WT0CCP1

PG6/I2C5SCL/WT1CCP0

PG7/I2C5SDA/U2TX/WT1CCP0

PH0/SSI3CLK/WT2CCP0
PH1/SSI3FSS/WT2CCP1

PH2/FAN0PWM5/SSI3RX/WT5CCP0

PH3/FAN0TACH5/SSI3TX/WT5CCP1

PM2/LPC0CLKRUN_L/T5CCP0/WT5CCP0

PL6/T3CCP0/WT3CCP0
PL7/T3CCP1/WT3CCP1

PN2/FAN0PWM2/WT2CCP0

PN3/FAN0TACH2/WT2CCP1

PN4/FAN0PWM3/WT3CCP0

PN5/FAN0TACH3/WT3CCP1

PECI

PM3/T5CCP1/WT5CCP1

PM6/FAN0PWM0/WT0CCP0

UNUSED

PM7/FAN0TACH0/WT0CCP1
PN7/FAN0TACH4/WT4CCP1

PJ5/C2_M/T3CCP1/U6TX

UART

PC0/SWCLK/T4CCP0/TCK

JTAG

PC1/SWDIO/T4CCP1/TMS

PC3/SWO/T5CCP0/TDO

PF4/T2CCP0/TRD3

PJ0/T1CCP0/U4RX
PJ1/T1CCP1/U4TX

PC2/T5CCP1/TDI

C348
10u/6.3V_4

VREFA_P
VREFA_M

PA6/I2C1SCL
PA7/I2C1SDA

PF5/T2CCP1

PJ7/PECI0RX
PJ6/PECI0TX

PA0/U0RX
PA1/U0TX

VBAT

WAKE_L

XOSC1
XOSC0

GNDX

GNDA1
GNDA2

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

GND10

3

C347

0.1U/10V_4

D2
D1

E10
D13

M4
N2

F4
F3

M9
N9
L10
K10
L9
K9
N8
M8
L8
K8
N7
M7
K7
L7
N4
N3
K3
K4
J4
J2
G11
E12
E13

G3
D10
L11
N12

C4
C6

H10
H11
L13
M11
C9
B9
C5

L3
M1

C10
A10
A11
B10

A2

NC

K12
N13

N10
M10
K11

C3
E3

A1
C7
D9
E5
F9
H5
H9
J11
J5
J8

1212 change part number of EC ,which has a trial firmware inside

1211 add Test points on unused pins, need check layout to
see if all points are ok

EC_ID3Stage EC_ID2 EC_ID1

0 0

4

EC_SLP_SX_L
SUSP_VR_EN
VCORE_EN
PP1350_EN
PP5000_EN
PP3300_DSW_EN

3

BLM18AG121SN1D/0.2A/120ohm_6

C318
1u/6.3V_4

EC_SMB0_CLK
EC_SMB0_DATA

EC_PA6
EC_PA7

EC_SMB2_CLK
EC_SMB2_DATA

PCH_WAKE_L
PCH_RSMRST_L
EC_PF2
EC_REST_L
EC_SMI_L
CORE_PWROK_R
EC_PF6
EC_PF7
HWPG_S5
SOC_OVERRIDE#
PCH_SUSPWRDNACK
PCH_SLP_SX_L
PCH_UART_RXD
PCH_UART_TXD
PCH_SUS_STAT_L
PCH_SLP_S3_L
PCH_PWRBTN_L
PCH_SLP_S4_L
EC_PH2
EC_ACIN
LPC_CLKRUN_L
EC_SLP_SX_L
EC_PL7

EC_PN2
EC_PN3
BAT_LED1
PMU_BATLOW_L

EC_PECI_RX
EC_PECI_TX

KBD_IRQ#
EC_PM6
EC_BL_DISABLE_L
TOUCH_RST_L
PP3300_WLAN_EN
EC_PWROK
EC_PJ5

EC_UART0_RX
EC_UART0_TX

EC_JTAG_TCK
EC_JTAG_TMS
EC_JTAG_TDO
EC_JTAG_TDI

PP3300_RTC
EC_WAKE_L

R444 0_4

ECGND

R177
100K_4

PP3300_ECPP3300_EC_ANA

L6

PP3300_EC_ANA

C310

C319

0.01U/16V_4

0.1U/10V_4

ECGND

ECGND

TP50
TP47

TP44

TP43
TP42

TP41

TP40

TP12
TP24

TP11
TP45

TP52

TP53

1211 move EC_PWROK from PH2 to PJ1

PP3300_RTC

1121 by X'tal vender suggestion,
change C107/C109 from 15pF to 18pF

EC_SMB0_DATA (28)

EC_SMB2_CLK (23)

EC_SMB2_DATA (23)

PCH_WAKE_L (6)
PCH_RSMRST_L (14)

EC_REST_L (6)

EC_SMI_L (14)

CORE_PWROK_R (6,11)

SOC_OVERRIDE# (4)

PCH_UART_RXD (18)
PCH_UART_TXD (18)

BAT_LED1 (22)

TP21

1128 add a connection and name
to KBD_IRQ#, beside add pulled
high resistor at SoC side

EC_UART0_RX (18)
EC_UART0_TX (18)

EC_JTAG_TCK (18)
EC_JTAG_TMS (18)
EC_JTAG_TDO (18)
EC_JTAG_TDI (18)

EC32K_X1

R201
20M_4

EC32K_X2

R1192.2_6

C312

C316

1u/6.3V_4

0.1U/10V_4

EC_SMB0_CLK (28)

PCH_SUSPWRDNACK (14)
PCH_SLP_SX_L (14)

PCH_SUS_STAT_L (14)
PCH_SLP_S3_L (14)
PCH_PWRBTN_L (11,14)
PCH_SLP_S4_L (14)

LPC_CLKRUN_L (7)
EC_SLP_SX_L (34)

KBD_IRQ# (6)
EC_BL_DISABLE_L (17)

TOUCH_RST_L (17)
PP3300_WLAN_EN (30)

EC_PWROK (2)

C107 18p/50V_4

12

Y4

32.768KHZ
C109 18p/50V_4

SM BUS ARRANGEMENT TABLE

SM Bus 0

BATT and CHARGER

SM Bus 1 NA

SM Bus 2

THERMAL SENSOR

R149
100K_4

R153
100K_4

R190
100K_4

R461
100K_4

12

R435
100K_4

ECGND

2

PP3300_DSW

C317

0.01U/16V_4

0830

2

EC_ACIN
TOUCH_RST_L
EC_RST#
EC_LPCPD#
LID_OPEN_R

LID_OPEN_R

ACIN(15,26,28)

SM BUS/I2C PU(KBC)

1

030 Thermal IC VDD has two option, ome is
PP3300_DSW( =PP3300_EC), another is
PP3300_DX, default is stuffing to DSW rail

PROCHOT_EC

EC HIB WAKE SOURCES

PWR_BTN_L

TP51

ACIN

C361 0.1U/10V_4

HWPG(KBC)

PP3300_PCH_S5_PG(15)

OD pin list

EC_REST_L
BAT_LED0
BAT_LED1
PCH_RSMRST_L
SMBUS
IRQ_SERIRQ
EC_BL_DISABLE_L

1

PP3300_EC

R482 10K_4
R473 TS@10K_4
R155 10K_4
R135 10K_4

Add diode for leakage issue

BATT and CHARGER / LCD BL

EC_SMB0_CLK
EC_SMB0_DATA

THERMAL SENSOR

R534 10K_4

LID_OPEN_L

D15RB500V-40

R419 4.7K_4
R423 4.7K_4

R140 4.7K_4
R132 4.7K_4

3

Q19

2N7002K

1

LID_OPEN_L

Q50
PJA138K

R145 0_4

R477 10K_4

PP3300_EC

PP3300_THM

C354 0.01U/16V_4

LID_OPEN_L(18,23)

ACIN EC_ACIN

D11 RB500V-40

C356

0.1U/10V_4

EC_SMB2_CLK
EC_SMB2_DATA

2

R98
100K_4

D14 RB500V-40

3

2

R527
47K_4

1

EC_WAKE_L

For testing only

PWR_BTN_L

1030 add Power BTN for
Intel testing

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

KBC TI TM4E1G31H6ZRBI

KBC TI TM4E1G31H6ZRBI

KBC TI TM4E1G31H6ZRBI

1

27

PP3300_RTC

H_PROCHOT# (5,18,33)

PP3300_RTC

2

R494
47K_4

HWPG_S5

SW1

2
1 4

Power Switch

NL6

NL6

NL6

27 41Friday, April 25, 2014

27 41Friday, April 25, 2014

27 41Friday, April 25, 2014

3

1

R463
1K_4

Q39
PJA138K

3
5

6

1A

1A

1A

5

4

3

2

1

1129 add and stuff 470pF
on PC210 and reserve

EC1

PC1

0.1U/25V_4

4700pF on PC211 for EMI
solution
1212 stuff PC211

PC211

4700p/25V_4

P4SMAFJ20A
PC210
470p/50V_4

PD1

POWER_JACK_502 81-0050N-001

88266-05001-06 -5p-l-smt

1022 pin1 change to VA

PJ1

1
2

3

456

7

D D

C C

PC2

1000P/50V_4

*0.1U/25V_4

1212 reserve PR170 for battery cell selection

1129 change PQ1,PQ2 part number

VA

2 1

PC3

2200P/50V_4

DA2J10100L

412K/F_4

64.9K/F_4

PQ1
MDV1528Q

5 2

PD5

PR98

PR168

VA

21

4

24715LDO

ACIN(15,2 6,27)

ICMNT(27 )

1
3

*0.01U/25V_4

PD6

DA2J10100L

2 1

PC5

1U/25V_6

PC151

*0.01U/25V_4

EC_SMB0_DATA

EC_SMB0_CLK

PR171 10K/F_4

PR89
10_12

PC149

PC4

*0.1U/25V_4

PR90

4.02K/F_6

PR102 *0_4/S

PR103 *0_4/S

PR170 4.7K_4

PR167

12.4K/F_4

PR173 *0_4/S

+DC_IN_SS

12

PC160

PD7
RB500V-40

PR2

0.01/F_0612

1 2

PR1
*0_6/S

4

4

PQ17
MDV1595S

PR105 4.02K/F_6

VCHGR_IN

PR3
*0_6/S

VCHGR_IN2

PC201

PC200

*0.1U/25V_4

2.2uH_7X7X1.8

PR176
*4.7_6

PC202

*1000P/50V_4

2200P/50V_4

PL8

52

PQ16
MDV1528

3

1

52

3

1

PC163

0.1U/25V_4

10U/25V_8

10U/25V_8

PC158

PC141

+

10U/25V_8

PC137

PC159

PC134

+

10U/25V_8

PC145

*10U/25V_8

*10U/25V_8

PD10 *SS3040HE

21

PR107

0.01/F_0612

1 2

IN- IN+

PC146

0.1U/25V_6

0.1U/25V_4

PC165

PR100

0.01/F_0612

1 2

BAT-V_P2

PC164

0.1U/25V_4

PQ18
AOL1413

1

52

3

+

PC166

4

10U/25V_8

VIN

PC140

PC135

+

+

*10U/25V_8

*10U/25V_8

1213 un-stuff PR176,PC202 as snubber isnt needed

PQ2
MDV1528Q

1

52

3

PR91

4.02K/F_6

20

10

PC156

100P/50V_4

4

PC143

0.1U/25V_4

24715ACP

24715ACN

2

ACP

PU14

BQ24715RGRR

GND21GND22GND23GND24GND

PC199

0.1U/25V_4

1

ACN

16

REGN

17

BTST

18

HIDRV

19

PHASE

15

LODRV

14

GND

13

SRP

12

SRN

11

BATDRV#

25

24715LDO

24715BST

24715DHI

24715LX

24715DLO

24715SRP

24715SRN

24715BATDRV

PR92

*0_6/S

PR101

*0_6/S

24715LDO

1U/25V_6

PC152

0.047U/50V_6

PC198

0.1U/25V_4

3

CMSRC

4

ACDRV

VCC

6

ACDET

8

SDA

9

SCL

CELL

5

ACOK

7

IOUT

PC6

0.1U/25V_4

12

12

IOUT

28

BAT-V

PC212

*0.1U/25V_4

1202 PJ2 changes

PC170

1000P/50V_4

BATT_EN#(25,26)

PR185

PR184

100_4

100_4

PD11

PD12

2 1

2 1

BZT52-B5V6S(5.6V)

BZT52-B5V6S(5.6V)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Charger(BQ24715)

Charger(BQ24715)

Charger(BQ24715)

Date: Sheet of

Date: Sheet of

Date: Sheet of

footprint for layout

VBATT

BATT_EN#

MBCLK
MBDATA

PR183

PR186

100_4

*0_4

PR187
1M_4

PC204

0.1U/10V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

PJ2

8 9
7
6
5
4
3
2
1

10

PP3300_EC

28 40Friday, April 25, 2014

28 40Friday, April 25, 2014

28 40Friday, April 25, 2014

50458-00801-V01 _Batt_Conn

1A

1A

1A

PP5000_CHG

BAT-V

EC_SMB0_DATA(27)

EC_SMB0_CLK(27)

B B

10ms one-shot circuit

PC172

*0.1U/25V_4

PP5000_CHG

IN+

IN-

PR106
*0_4/S

6

OUT

INA199B1DCKR

REF

1

12

12

PR108

*0_4/S

PC174

PC178

*0.1U/25V_4

*0.1U/16V_4

4

5

IN-

IN+

PU18

V+3GND

2

PR112

*0_6/S

PC177

0.1U/25V_4

PD13

RB500V-40

2

PP5000_CHG

PP5000_CHG

PC173

0.01U/16V_4

PR180

1.5M_4

PC168
*100P/50V_4

PC171
*100P/50V_4

PQ15

2N7002K

PC175

PC176

*100P/50V_4

0.01U/16V_4

84

3

+

1

2

-

PU17A
LMV393IDR

PU16
NL27WZ00USG

1
2

3

PP5000_CHG

PR177

100K_4

PD8
DA2J10100L

2 1

2 1

DA2J10100L
PD9

1206 change PU16,PU17 part number

PP5000_CHG

PC161

0.01U/16V_4

3

2

PC154

0.1U/25V_4

1

PR99
221K/F_4

84

7

6
5

4

PR178
100K/F_4

PC167

PR179
34K/F_4

0.01U/16V_4

IOUT

IMVP7_PROCHOT#(5)

A A

5

12

PP5000_CHG

PR174
*0_4/S

LMV393IDR
PU17B

PR111

1.5M_4

7

PP5000_DSWPP5000

PC203
100P/50V_4

PR175
*0_4

-

6

+

5

PC169
100P/50V_4

3

PR182
412K/F_4

PR181

100K/F_4

5

670_ENLDO

PC61
10u/6.3V_6

670_EN

670_LDO

PR79
*499K/F_4

13

12

14

1

VIN

EN

4

PG

3

LP#

NB670GQ-Z

ENLDO

6

LDO
AGND

PR82 *0_4/S

PP3300_DSW_EN(27)

D D

12

PP3300_DSW

PR47
*100K/F_4

10/11 modify

PP3300_RTC

PR78
*0_4

C C

670_BST 670_BST1

10

BST

SW1
SW2
SW3

PU9

SW4

VOUT

PGND

CLK5VCC

11

PC109
1u/6.3V_4

4

3VPCU_VIN

PR77
1/F_6

PC108

0.1u/50V_6

8

670_SW

9
15
16
7
2

PC66

*0.1u/16V_4

PP5000_DSW

10/11 modify

0417 PC93,PC94,PC95,PC96
change to 10uF

PC92 2200p/50V_6

PL5

2.2uH_7X7X1.8

PR154

3.3_6

PC196
2200p/50V_4

PC96 10U/25V_8

PC94 10U/25V_8

PC72 0.1u/50V_6

PC95 10U/25V_8

PC93 10U/25V_8

3.3 Volt +/- 5%
TDC : 6A

PC98 22u/6.3V_6

PEAK : 8A
Width : 240mil

PC110 22u/6.3V_6

PC81 22u/6.3V_6

PC90 22u/6.3V_6

0417

PR36

*0_6/S

0417 PC42,PC43,PC48,PC49 change to 10uF ,
add PC214 10uF and PC45 change to 1uF

3

1 2

*POWER_JP

PP3300_DSW

2

JP12

VIN

VIN

3VPCU_VIN

PC191

0.1U/25V_4

PP3300_INA

PC192

0.1u/25V_4

1 2

4

PU22

INA219AIDCNR

Vs

5

SCL

6

SDA

7

A0
A1

Address: 0x42

8

(1000010)

GNDGND

2

VIN-

1

VIN+

3

GND

1

I2C_SCL_INA_R (18,31,32)
I2C_SDA_INA_R (18,31,32)

JP6

1 2

*POWER_JP

PC12 22u/6.3V_6

PC11 22u/6.3V_6

PC16 22u/6.3V_6

3

VIN

PP5000

5 Volt +/- 5%
TDC : 3A
PEAK : 4A
Width : 120mil

VIN

5VPCU_VIN

PC131

0.1U/25V_4

PP3300_INA

PC113

0.1u/25V_4

1 2

4

PU11

INA219AIDCNR

2

Vs

5

SCL

6

SDA

7

A0

8

A1

I2C_SCL_INA_R
I2C_SDA_INA_R

PP3300_INA

Address: 0x41
(1000001)

GNDGND

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SYSTEM 5V/3V (MPS670/671)

SYSTEM 5V/3V (MPS670/671)

SYSTEM 5V/3V (MPS670/671)

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

1

1A

1A

29 40Friday, April 25, 2014

29 40Friday, April 25, 2014

29 40Friday, April 25, 2014

1A

2

VIN-

1

VIN+

3

GND

671_BST 671_BST1

10

BST

SW1
SW2
SW3
SW4

VOUT

PGND

FB

12

PC62
1u/6.3V_4

VREF=0.604V

5VPCU_VIN

PR32
1/F_6

8
9
15
16
7
2

671_FB

0.1u/50V_6

671_SW

4

PC53

PC31

0.1u/16V_4

PR127

3.3_6

PC188
2200p/50V_4

PR39
11K/F_4

PC45 1U/25V_6

0417

PC42 10U/25V_8

PL2

3.3uH_7X7X1.8

PC43 10U/25V_8

PR38
82K/F_4

PR48

*0_6/S

PC49 10U/25V_8

PC48 10U/25V_8

PC214 10U/25V_8

PC9 0.1u/50V_6

PC10 22u/6.3V_6

PR136 *0_4/S

NB671_VCC

PR20
100K/F_4

PR188
200K/F_4

10/11 modify

5

12

PR137
*499K/F_4

1

VIN

13

EN

4

PG

3

LP#

PU4

5

NB671LGQ-Z

NC1

6

PR131
*0_4

1 2

PR189
*0_4/S

NB671_VCC

NC2

14

AGND

VCC

11

IMAX= 10mA

PP5000_EN(27)

PP5000_EN

10/11 modify

B B

PP5000_PGOOD(27)

1025 stuff PR188
due to 3.3V to EC
is more safe

A A

5

4

3

2

1

PP1800_PCH_S5_PG(35)
PP3300_DX_EN(27)

PP1800_PCH_S5_PG
PP3300_DX_EN

30

D D

C C

PP3300_DSW

PC162

B B

1u/10V_4

PP1800_PCH_S5_PG

1 2

PR95 *0_4/S

*100K/F_4

PR96

PP3300_DSW

A2
B2

PC148
*0.1u/50V_6

PR71 *0_8_S

PR63 *0_8

PU13

IN
EN

TPS22930

OUT

GND

A1
B1

PC82
1u/10V_4

PP3300_WLAN_R

PP3300_WLAN_EN(27)

PP3300_WLAN_EN

1 2

PR44 *0_4/S

PP3300_WLAN_EN_R

PR53

100K/F_4

DX should be earlier than VREN by EC.

PP3300_PCH_S5 PP3300_DX

PP3300_DSW

PC17

1u/10V_4

PP3300_DX_EN PP3300_DX_EN_R

1 2

PR15 *0_4/S

PR14

100K/F_4

PR60 *0_8

A2
B2

PC63
*0.1u/50V_6

PU1

A2

IN1

B2

IN2

C2

EN

TPS22964CYZPR

PU6

IN
EN

TPS22930

OUT1
OUT2

GND

OUT

GND

A1
B1

A1
B1
C1

PP3300_WLANPP3300_DX

Quanta Computer Inc.

Quanta Computer Inc.

A A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

Load Switch

Load Switch

Load Switch

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

of

of

of

30 40Friday, April 25, 2014

30 40Friday, April 25, 2014

30 40Friday, April 25, 2014

1

1A

1A

1A

5

TDC : 0.75A
PEAK : 1A
Width : 40mil

PC22

20

PGOOD

17

S3

16

S5

19

MODE

18

TRIP

26

PAD

51216_REF

PR125

10K/F_4

PR123

30.1K/F_4

10u/6.3V_6

22

6

TDC : 0.38A
PEAK : 0.5A

D D

PP1350_PGOOD(2)

0830

PP1350_EN(27)

C C

Width : 20mil

PR6 *0_4/S

PR119
100K/F_4

PR120

48.7K/F_4

PC30

0.22u/10V_4

PP3300_EC

PR5

*100K/F_4

1 2

PP1350_VREF

51216_S3

51216_S5

51216_MODE

51216_TRIP

VREF=1.8V

PC186

0.1u/10V_4

PR117 *0_4/S

1 2

VSFR_EN(34)

OCP=6A
L ripple current
=(19-1.35)*1.35/(2.2u*400k*19)
=1.425A
Vtrip=[6-(1.425/2)]*14mohm
=0.07402V
Rlimit=0.07402/10uA*8=59.22Kohm

B B

VSFR_EN

51216_S5

PR118 *0_4

51216_S3

+DDR_VTT_RUN

5

PAD21PAD

VTTREF

TPS51216RUKR

VDDQSNS9REFIN8REF

51216_REFIN

PC187

0.01u/25V_4

4

4

PU2

25

PC15
10u/6.3V_6

VTTGND

3

2

1

31

Greater than or equal 40mil

PP5000_DSW

PR122
*0_4/S

PC20

SW

PR124

*0_6/S

12

14

15

13

11

10

10u/6.3V_6

51216_DRVH

51216_VBST

51216_SW

51216_DRVL

PR10

2/F_6

3

1

2

VTT

VLDOIN

VTTSNS

V5IN

DRVH

VBST

DRVL

PGND

GND

PAD23PAD24PAD

7

Mode Frequency Discharge mode

200K 400K Tracking Discharge

100K 300K Tracking Discharge

1 2

PC23
1u/10V_4

PC21

0.1u/50V_6

PP5000

PQ5
MDV1595S

PR121
*0_4

PQ3
MDV1528

4

4

0417 PC13 change to 10uF ,
add 2x10uF PC215 , PC216

51216_VIN

52

3

1

52

3

1

PC14

2200p/50V_4

51216_SW

2.2uH_7X7X1.8

PR21

3.3_6

PC32
1200p/50V_6

0417 PR21 change to 3.3ohm ,
PC32 change to 1200uF , PC29
change to 10uF

S3 (mainon off)

PL1

S0

S4/S5

PC13

10U/25V_8

PC216

10U/25V_8

+1.35VSUS_SRC

PC29
10u/6.3V_6

Close to output cap

S3 S5
1
0

1
1

PC215

10U/25V_8

+

PC8

330u/2V_7343

JP1

1 2

*POWER_JP

ON

ON ON
ON ON
OFF

OFF OFF0 0

VIN

PP1350

1.35 Volt +/- 5%
TDC : 3.55A
PEAK : 4.73A
OCP : 6A
Width : 160mil

VTTREF+1.35VSUS

OFF

PP3300_INA

PC184

0.1u/25V_4

1 2

4

PU20

Vs

5

SCL
SDA

6

7

A0

8

A1

Address: 0x49

I2C_SCL_INA_R (18,29,32)
I2C_SDA_INA_R (18,29,32)

PP3300_INA

(1001001)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR 1.35V(TPS51216)

DDR 1.35V(TPS51216)

DDR 1.35V(TPS51216)

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

PROJECT :

1

1A

1A

31 40Friday, April 25, 2014

31 40Friday, April 25, 2014

31 40Friday, April 25, 2014

1A

GND

2

VIN-

1

VIN+

3

GND

INA219AIDCNR

51216_VIN

VIN

A A

PC185

0.1U/25V_4

5

5

VIN PP1050_PCH

JP5

1 2

*POWER_JP

PP3300_DX

10/11 modify

D D

PP1050_PCH_PG(27,34)

PP1000_PCH_PG

PR29

10K/F_4

PR43 *0_4/S

12

PC59

1000p/50V_4

PC26

3.3n/50V_4

PP1050_PCH_VIN

+

PC39
10U/25V_8

PC38

0.1u/25V_6

4

2.2uH_7X7X1.8

1.05V_VSNS

IMVP_PWRGD_3V

PL3

R1

R2

IMVP_PWRGD_3V(27,33,35)

PU24

TLV62150ARGTR

11

PVIN

12

PVIN

10

AVIN

4

PG

13

EN

9

SS/TR

8

DEF

7

FSW

PAD17PAD18PAD19PAD20PAD21PAD

AGND
PGND
PGND

22

1

SW

2

SW

3

SW

14

VOS

5

FB

6
15
16

V0=0.8*(R1+R2)/R2

PR13
100K/F_4

PR12
316K/F_4

3

JP4
*POWER_JP

PC69
22u/6.3V_6

1 2

PC68
22u/6.3V_6

PP1050_PCH_SRC

PC67

0.1u/10V_4

0417 PC68 & PC69 change to 22uF

1.05Volt +/- 5%
TDC : 0.75A
PEAK : 1A
Width : 40mil

2

1129 because of power
source of PU24,PU25 chagen
to VIN, so that need
change sensing power net

PP1050_PCH_VIN

VIN

2

VIN-

1

PC190

0.1U/25V_4

VIN+

3

GND

Address: 0x43

GND

(1000011)

PC189

0.1u/25V_4

1 2

PU21

INA219AIDCNR

PP3300_INA

4

Vs

1

32

5

SCL

6

SDA

7

A0

8

A1

GND

I2C_SCL_INA_R (18,29,31)
I2C_SDA_INA_R (18,29,31)

PP1050_PCH_SRC

VIN

JP8

1 2

*POWER_JP

PP3300_DSW

C C

PP1000_PCH_S5_PG(35)

SUSP_VR_EN(27)

B B

A A

PP1000_PCH_S5_PG
SUSP_VR_EN

PR83
100K/F_4

PR84 *0_4/S

PC121

1000p/50V_4

12

PC27

3.3n/50V_4

PP1000_PCH_S5_SRC

IMVP_PWRGD_3V

+

PC65
10U/25V_8

PP1000_PCH_S5_VIN

PR169 4.7K_4

DTC144EU

PR166 4.7K_4

PC80

0.1u/25V_6

2

PQ27

1 3

PR46 *0_4

PR49 *0_4

PP3300_INA

1.0Volt +/- 5%

JP10
*POWER_JP

TDC : 2.07A
PEAK : 2.75A
Width : 100mil

PP1000_PCH

PR199 4.7K_4

PP1000_PCH_S5_VIN

VIN

1.0V_PG_1

PC208
*1000P/50V_4

PC194

0.1U/25V_4

2

GND

PQ46
MMBT3904-7-F

1 3

PP1000_PCH_S5

PU25

TLV62130ARGTR

11

PVIN

12

PVIN

10

AVIN

4

PG

13

EN

9

SS/TR

8

DEF

7

FSW

PAD17PAD18PAD19PAD20PAD21PAD

VIN

PR31
1M_6

PR196
1M_6

PP1000_PCH

2

AGND
PGND
PGND

22

3

1

SW
SW
SW

VOS

FB

PR195
22_8

PQ30
2N7002K

1
2
3
14
5
6
15
16

PL6

2.2uH_7X7X1.8

1V_VSNS

V0=0.8*(R1+R2)/R2

VIN

PR28
1M_6

3

2

PQ28

2N7002K

PC28

1

*2.2n/50V_4

PC125
22u/6.3V_6

1 2

PC124
22u/6.3V_6

PP1000_PCH_S5_SRC

PR55

R1

100K/F_4

PC129

0.1u/10V_4

PR51

R2

390K/F_4

1129 change solution whiich
power source is VIN, it is
better for power efficiency
1202 change PC65 and PC39 from 4.7uF to 10uF

1202 add PR169,PR49 for Intel request,
stuff PR169 as default

1202 add PR166,PR46 for Intel request.
stuff PR166 as default

1202 revising pull up power rail of PR169 and
PR166

2

0

417 PC124 & PC125 change to 22uF

PP1000_PCH_S5

1129 PQ29 change MOSFET with lower Rdson
1202 PQ29 change back AO3404

3

PQ29
AO3404

1

PP1000_PCH

TDC : 2.07A
PEAK : 2.75A
Width : 100mil

PC193

0.1u/25V_4

1 2

4

PU23

INA219AIDCNR

Vs

SCL

SDA

2

VIN-

1

VIN+

3

GND

Address: 0x47
(1000111)

PP3300_PCH_S5

PR198

4.7K_4

PC207
1000P/50V_4

2

1.0V_PG_2

5
6

7

A0

8

A1

PR197

4.7K_4

PQ60

1 3

DTC144EUA

PP1000_PCH_PG

I2C_SCL_INA_R
I2C_SDA_INA_R

PP3300_INA

1129 PP1000_PCH changes from convert to power MOSFET type for power efficiency improvement

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

+1.05V/+1V(TPS54318)

+1.05V/+1V(TPS54318)

+1.05V/+1V(TPS54318)

1

1A

1A

32 40Friday, April 25, 2014

32 40Friday, April 25, 2014

32 40Friday, April 25, 2014

1A

5

4

3

2

1

1025 PC57 change from 68p to 120p
PC50 change from 150p to 2200p
for proto1 issue

1030 PR26 change to 16.9K
PR23 change 10 ohm
PC50 change 1200pF
PC40 change to 270pF

D D

+VCC_GFX

PR149
*0_4/S

PR150
*0_4/S

*499/F_4

PR65

*1.91K/F_4

PR157 *0_4

PR45 20/F_4

PR52
*0_4/S

PR54 16.9/F_4

12
12

PR27

12

VCC_AXG_SENSE(8)
VSS_AXG_SENSE(8)

Parallel

C C

PP1000_PCH

VRON PD 100K AT EC

VCORE_EN(27)

IMVP_PWRGD_3V(27,32,35)

H_PROCHOT#(5,18,27)

43p/50V_4

B B

VR_SVID_CLK(6)

VR_SVID_ALERT#(6)

VR_SVID_DATA(6)

PP1000_PCH

A A

PR35
*0_4/S

1 2

PC86

VR_SVID_CLK

VR_SVID_ALERT#

VR_SVID_DATA

1031 add 0.1u on
PP1000_PCH for power

PC205

request

0.1u/25V_4

Parallel

VCC_SENSE(8)
VSS_SENSE(8)

5

PR151

PR140
*10_4

PR141
*10_4

Close to the
CPU side.

1.91K/F_4

PR143
*0_4/S

PR148
*0_4/S

PC34

*330p/50V_4

VCC_AXG_SENSE_SRC
VSS_AXG_SENSE_SRC

PC55
*0.01u/50V_4

PP3300_DXPP3300_DX

PR132

*100K/F_4

2

VR_ON

15

PGOOD

27

PGOODG

6

VR_HOT#

3

SCLK

4

ALERT#

5

SDA

+VCC_CORE

12
12

33

PAD

ISEN28ISEN1

9

12

PR61
*0_4/S

PP5000

1025 PR155 change
from 300 to 340 ohm
for proto1 issue

PC123
*330p/50V_4

PR139
*10_4

PR142

PC102

*10_4

*0.01u/50V_4

Close to the

PU side.

C

un-stuff PR22,PC54

1031 un-stuff PR129 and PC37
1115 PR128 change to 1.62K

95833_ISUMNG

PR22

*649/F_4

PC54*4700P/25V_4

PR135

340/F_4

95833_NTCG

95833_ISUMPG

32

1

NTCG

NTC

7

95833_NTC

95833_ISUMN

31

ISUMPG

ISUMNG

PU7

ISL95833HRTZ-T

ISUMP10ISUMN11RTN12FB13COMP

95833_ISUMP

PC101

*4700P/25V_4

PR155

340/F_4

PR80

*649/F_4

4

PR128

1.62K/F_4

PR23

10/F_4

270p/50V_4

95833_COMPG

30

RTNG

28

29

FBG

BOOTG

UGATEG

PHASEG

LGATEG

LGATE1

PHASE1

UGATE1

14

PR86

10/F_4

PR159 1.78K/F_4

1025 PC99 change from 68p to 120p
PC106 change from 150p to 2200p
for proto1 issue

1030 PR76 change to 16.9K
PR86 change 10 ohm
PC106 change 1200pF
PC114 change to 270pF
un-stuff PR80,PC101

1031 un-stuff PR158 and PC118

20140321 Intel request change
PL4 & PL7 0.22uH to 0.47uH .
Change PR130 change to 124K ohm
& PR62 and PR30 change to 0 ohm
.

PR129
*2K/F_4

*330p/50V_4

PR26

16.9K/F_4

1200p/50V_4

22

21

26

25

24

23

20

19

18

17

16

PC57

120P/50V_4

PR144
*0_6/S

95833_BOOTG

95833_UGATEG

95833_PHASEG

95833_LGATEG

95833_LGATE1

95833_PHASE1

95833_UGATE1

95833_BOOT1

95833_COMP

120P/50V_4
PC99

PR76

16.9K/F_4

PR158
*2K/F_4

PC78

1u/16V_6

1200p/50V_4

*330p/50V_4

PC40

VCCP

COMPG

VDD

PWM2

BOOT1

PC114

270p/50V_4

PC37

PC50

PR145 *0_4

PC106

PC118

0417 PC87 &
PC88 change to
10uF

AXG

PC87

10U/25V_8

PL4

0.47uH_7X7X1.8

DCR=8.4mOhm

*2.2_6

*2200p/50V_6

PR138

C126 change to

PC88

10U/25V_8

*100K/F_4

2

D1D1D1

9

S2S2S2

567

PC46

0.1u/25V_4

VIN_VCC_GT

PC84

0.1u/50V_6

95833_PHASEG

PC58

4.7n/25V_4

Close with
AXG inductor

PR74

PC104

0417 PC119 &
P
10uF

PR30
*0_4/S

1 2

12

95833_BOOTG

95833_UGATEG

95833_PHASEG

95833_LGATEG

95833_ISUMPG

PP5000

PP5000_DSW

95833_ISUMNG

PR130

124K/F_4

PR147
*0_4/S

PR146

1/F_6

PC71

1u/10V_4

PC64

0.22u/25V_6

PQ9
FDMS3660S

*0.1u/25V_4

G1

1

S1/D2

8

G2

PC47

Close to the
VR side.

JP7

1 2

*POWER_JP

PC83

2200p/50V_4

PR57

0.001/F_3720

1 2

PR37 1K/F_4

PR40 1/F_4

VIN

12

+

PC44
15u/25V_7343

1209 remove JP9 for ACLL
improvement

+VCC_GFX

PC10722u/6.3V_6

PC10510u/6.3V_8

PC1110.1u/10V_4

PC11222u/6.3V_6

1213 un-stuff PR74,PC104 as snubber isnt needed

Core

JP14

2200p/50V_4

PC128

PR93 1K/F_4

1 2

*POWER_JP

PR88

0.001/F_3720

1 2

PR94 1/F_4

VIN

1209 remove JP13 for ACLL
improvement

+VCC_CORE

PC1200.1u/10V_4

PC10322u/6.3V_6

PC11622u/6.3V_6

PC11710u/6.3V_8

+

PC139330u/2V_7343

1213 un-stuff PR81,PC115 as snubber isnt needed

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCC_CORE(ISL95833)

+VCC_CORE(ISL95833)

+VCC_CORE(ISL95833)

Friday, April 25, 2014 33 40

Friday, April 25, 2014 33 40

Friday, April 25, 2014 33 40

PR153

64.9K/F_4

3

95833_BOOT1

95833_UGATE1

95833_PHASE1

95833_LGATE1

95833_ISUMP

95833_ISUMN

470K_4 NTC

PR62
*0_4/S

1 2

0.22u/25V_6

Close to the
VR side.

PR97

PC89

PQ14
FDMS3660S

*0.1u/25V_4

95833_NTC

PR164

3.83K/F_4

G1

1

S1/D2

8

G2

PC100

PR163

27.4K/F_4

2

D1D1D1

9

S2S2S2

567

PC197

0.1u/25V_4

0.1u/50V_6

PC127

95833_PHASE1

PC195

4.7n/25V_4

470K_4 NTC

PR33

VIN_VCC_CORE

PC126

10U/25V_8

0.47uH_7X7X1.8

DCR=8.4mOhm

PR81

*2.2_6

PC115

*2200p/50V_6

95833_NTCG

PR134

3.83K/F_4

2

PL7

PR133

27.4K/F_4

PC119

10U/25V_8

PR156

*100K/F_4

33

+VCC_GFX

PC77

PC60

+

+

330u/2V_7343

GFX_CORE Load Line :

-5.9mV/A for SDP=4.5W

VCORE Load Line :

-5.9mV/A for SDP=4.5W

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

PC138330u/2V_7343

+

1

+VCC_GFX
PEAK : 14A
OCP : 18A
Width : 600mil

330u/2V_7343

+VCC_CORE

+VCC_CORE
PEAK : 12A
OCP : 18A
Width : 500mil

1A

1A

1A

1

2

3

4

5

VSFR_EN(31)

1129 PP1000_PCH_S5 change from LDO to switching power

A A

PP1350_PCH

3

2

1

PC122
*1000P/50V_4

PR72
22_8

PQ22
2N7002K

2

1.35V_PG_2

PQ44
MMBT3904-7-F

1 3

PR11
1M_6

B B

C C

PP1050_PCH_PG

2

DTC144EU

PP1350_PCH

PQ19

1 3

PR190 4.7K_4

PR85
1M_6

1.35V_PG_1

VIN

3

2

1

PR152

4.7K_4

PC91
1000P/50V_4

PR17
1M_6

PQ20

2N7002K

2

PC24
*2.2n/50V_4

PP3300_PCH_S5

PR126

4.7K_4

PP1350_PCH_PG

PQ58

1 3

DTC144EUA

PP1350VIN

3

2

1

TDC : 0.315A
PEAK : 0.42A
Width : 20mil

PQ21
AO3404

PP1350_PCH

PP1350_PCH_PG

PP3300_DSW

PC182

10u/6.3V_6

PR110
*0_4/S

PC179 1u/16V_6

1 2

PR115 *0_4/S

PC181

0.1u/50V_6

SUSP_VR_EN(27,32)

PP1050_PCH_PG(27,32)

PP5000_DSWPP5000

12

PR109
*0_4

4
2
3

8
9

PC183
*0.1u/50V_6

VSFR_EN

PU19
G9661-25ADJF12U

VPP
VEN
VIN

GND
GND

PGOOD

ADJ

7

1
6

VO

5

NC

0.8V

Vout =0.8(1+R1/R2)
=1.8V

PR116 100K_4

R1

R2

PR114

43.2K/F_4

PR113
34K/F_4

34

PP3300_DX

PC180
10u/6.3V_6

PP1800_PCH_PG (35)

PP1800_PCH

TDC : 0.026A
PEAK : 0.035A
Width : 20mil

1129 PP1350_PCH change from LDO to power MOSFET

PP1350_PCH_SX

PR8
1M_6

PP1050_PCH_PG

EC_SLP_SX_L(27)

D D

EC_SLP_SX_L

1

1 2

PR18 *0_4/S

PR19 *SX@0_4

VSFR_EN

2

PQ6

DTC144EU

2

1 3

PR9
1M_6

PR7
22_8

3

2

PQ7
2N7002K

1

VIN

10/11 modify

PR16
1M_6

3

2

PQ8

2N7002K

1

3

PC19
*2.2n/50V_4

PP1350VIN

3

2

1

TDC : 0.28A

EAK : 0.375A

P
Width : 20mil

PQ4
AO3404

PP1350_PCH_SX

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

4

Date: Sheet of

PROJECT :

LDO (1V/1.35V/1.5V/1.8V)

LDO (1V/1.35V/1.5V/1.8V)

LDO (1V/1.35V/1.5V/1.8V)

5

1A

1A

34 40Friday, April 25, 2014

34 40Friday, April 25, 2014

34 40Friday, April 25, 2014

1A

1

2

3

PP1800_PCH_PG(34)

PP1000_PCH_S5_PG(32)

4

PP5000_DSW

12

PR165
*0_4/S

5

35

1
6

5

0.8V

R1

R2

PR87 100K_4

LDO(1.2V/3.3V/1.8V)

LDO(1.2V/3.3V/1.8V)

LDO(1.2V/3.3V/1.8V)

PP3300_DSW

PR161

43.2K/F_4

PC142
10u/6.3V_6

PR160
34K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

5

PP1800_PCH_S5_PG (30)

PP1800_PCH_S5

TDC : 0.049A
PEAK : 0.065A
Width : 20mil

35 40Friday, April 25, 2014

35 40Friday, April 25, 2014

35 40Friday, April 25, 2014

1A

1A

1A

A A

PP3300_PCH

PR25
1M_6

PP1800_PCH_PG

B B

C C

D D

1129 PP3300_PCH change from LDO to power MOSFET

IMVP_PWRGD_3V(27,32,33)

PP1350_PCH_SX_PG(15)

1

2

DTC144EU

PP3300_PCH

IMVP_PWRGD_3V
PP1350_PCH_SX_PG

1 3

PQ24

PR200 4.7K_4

1 2

PR58 *0_4/S

PR64 *SX@0_4

PR192
1M_6

2

PQ10

DTC144EU

2

3.3V_PG_1

1 3

PR191
22_8

3

1

PC209
*1000P/50V_4

2

PQ26
2N7002K

2

VIN

3.3V_PG_2

PQ45
MMBT3904-7-F

1 3

PR67
1M_6

PR66
1M_6

PP1000_PCH_SX

2

VIN

PR24
1M_6

3

2

PQ23

2N7002K

1

PR194

4.7K_4

PC206
1000P/50V_4

PR75
22_8

3

PQ11
2N7002K

1

PC25
*2.2n/50V_4

PP3300_EC

2

PQ59

1 3

DTC144EUA

PP3300_DSWVIN

3

2

PQ25
AO3404

1

TDC : 0.025A
PEAK : 0.033A
Width : 20mil

1213 change pull up power
of PP3300_PCH_PG to
PP3300_EC

PR193

4.7K_4

PP3300_PCH_PG (27)

VIN

10/11 modify

PR73
1M_6

3

2

PQ12

2N7002K

1

PC133
*2.2n/50V_4

3

PP3300_PCH

4

PP1000_PCH_S5

52

PQ13
AON7400AL

3

1

TDC : 1.43A

EAK : 1.9A

P
Width : 80mil

PP1000_PCH_S5_PG

PP3300_DSW

PC132

10u/6.3V_6

1202 PQ13 change to lower
Rdson part, besides source
of PQ13 changes to
PP1000_PCH_S5

PP1000_PCH_SX

PC144 1u/16V_6

1 2

PR162 *0_4/S

PC136

0.1u/50V_6

4

PC130
*0.1u/50V_6

PU12
G9661-25ADJF12U

4

PGOOD

VPP

2

VEN

3

VIN

8

GND

9

GND

VO

NC

ADJ

7

Vout =0.8(1+R1/R2)
=1.8V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

2

3

4

5

36

A A

B B

C C

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thermal protect

Thermal protect

Date: Sheet of

Date: Sheet of

1

2

3

Date: Sheet of

4

Thermal protect

PROJECT :

1A

1A

1A

36 41Friday, April 25, 2014

36 41Friday, April 25, 2014

36 41Friday, April 25, 2014

5

5

Support S0iX

1

BAT-VVIN

EC_ACIN

ACPRESENT

D D

PP3300_RTC

2

5

PP3300_DSW

PP3300_DSW_EN PP5000_EN

4

VIN

1

V1P0A
TLV62130A

C C

B B

EN

PP3300_DSW

5

V1P8A
G9661-25

EN

PP1000_PCH_S5_PGD

PP3300_DSW

5

V3P3A
TPS22930

EN

PP1800_PCH_S5_PGD

S5 PWR

VIN

1

DDR VDDQ
VR

S5 PG

S3

S5

PP1000_PCH_SX_PG

A A

3V/5V

EN2

VOUT

PG

SUSP_VR_EN

VOUT

PG

VOUT

PP1350_EN

5

CHARGER

1

VIN

VR

PP1350

PP1350_VREF

+DDR_VTT_RUN

PP1350_PGOOD

PP5000_DSW

PP5000

EN1

PG

8

PP1000_PCH_S5

PP1000_PCH_S5_PGD

7

10

PP1800_PCH_S5

PP1800_PCH_S5_PGD

9

12

PP3300_PCH_S5

MOS

PP3300_PCH_S5_PGD

11

48

22

20

PP5000_PGOOD

23

24

49

25

S0IX
S3 PWR

Battery

5

19

21

49

+DDR_VTT_RUN

9

VCC can follow in the CORE rail sequence
or at the same time

11

13

S3
S3
S0IX

S3

S0 PWR

4

PWR
BTN

6

PP3300_PCH_S5_PGD

13

PP3300_PCH_PG (ALL_S0_PGD)

42

PP1350_PGOOD

25

PP5000_PGOOD

18

VCORE_PGOOD

29

44

EC_SLP_SX_L

VTT_PWRGD

S0IX

MOS

please PP3300_DX_EN
early than VCORE_EN

VIN

1

IMVP
VR

SVID

CPU

4

+V1P0S

AON7400AL

ENENENENEN

+V1P05S

TLV62150ARGTR

+V1P35S

AO3404

+V1P8S

G9661-25

+V3P3S

AO3404

8

1

23

5

PP3300_DSW

5

50

S0 PWR

VCC

VNN

PG

EN

PG

PG

PG

PG

PG

PWR_BTN_L

HWPG_S5

HWPG_S0

EC_SLP_SX_L

S0IX_PGD

VCORE_EN

29

31

+VCORE

+VGFX

30

VCORE_PGOOD

VCORE_EN

PP1000_PCHPP1000_PCH_S5

PP1000_PCH_PG
MOS

IMVP_PWRGD_3V

35

PP1050_PCH_PG

36

PP1000_PCH_PG

34

PP1350_PCHPP1350

PP1350_PCH_PG

MOS

PP1050_PCH_PG

PP1800_PCHPP3300_DSW

PP1800_PCH_PG

PP1500_PCH_PG

PP3300_PCH

PP3300_PCH_PG

MOS

PP1800_PCH_PG

3

EC_ACIN

PCH_RSMRST_L

EC

14

16 PMC_SUSPWRDNACK

PCH_SLP_S4_L

18

PCH_SLP_S3_L

CORE_PWROK

EC_PWROK

PP5000_EN

PP1350_EN

SUSP_VR_EN

PP3300_DX_EN

7

28

2

32

29

33

34

32

PP1050_PCHVIN

192

PP3300_DSW_EN

4

PP1350

23

+VSFR
MOS AO3404

33

+V1P0SX
MOS AO3404

VOUT

EN

EC_SLP_SX_L

PP1000_PCH

VOUT

EN

PP1350_PCH_SX_PG

t1 : RTC_VCC to ILB_RTC_TEST# de-assertion 9ms -min (2-3)

t1 : RTC_VCC to PMC_RSMRST# de-assertion 9ms-min (2-11)

27

45

PP1350_PCH_SX

MOS

PP1350_PCH_SX_PG

44

47

PP1000_PCH_SX

MOS

PP1000_PCH_SX_PG

46

2

ILB_RTC_RST#

3

ILB_RTC_TEST#

3

ACPRESENT

PMC_SUSCLK[0]

15

PCH_PWRBTN_L

17

PMC_CORE_PWROK

52

PMC_SUS_STAT#

53

PLTRST#

54

CH_SLP_SX_L

43

P

ILB_RTC_RST#

ILB_RTC_TEST#

ACPRESENT

RSMRST#

PMC_SUSCLK[0]

SUSACK

PWRBTN#

SLP_S4#

SLP_S3#

PMC_CORE_
PWROK

PMC_SUS_
STAT#

PLTRST#

SLP_S0IX#

PCH

CPU

51

PP1350_PGOOD

25

DRAM_CORE_PWROK

46

DRAM_VDD_
S4_PWROK

DRAM_CORE_
PWROK

SVID

SVID

2

PP3300_RTC

VRTC

V1P0A

V1P24A

V1P8A

V3P3A

V1P0S

V1P05S

V1P35S

VAUD

V1P8S

VSDIO
VLPC
V3P3S

CORE PWR

VDDQ PWR

GPU PWR

1

37

PP1000_PCH_S5

PP1200_PCH_S5

PP1800_PCH_S5

PP3300_PCH_S5

PP1000_PCH

PP1050_PCH

PP1350_PCH

PP1500_PCH_TS

PP1800_PCH

PP3300_PCH

+VCORE

PP1350

+VGFX

S0IX

48

S0IX

t2 : V3P3A valid to PMC_RSMRST# de-assertion 10us -min (8-11)

37

38

36

39

40

38

t3 : PMC_RSMRST# to Internal RTC clock stable 100ms -max (11- RTC clock)
t4 : Internal RTC clock stable to PMC_SUSCLK[0] toggling 5ms -min (RTC clock - 12)
t5 : PMC_SLP_S4# de-assertion to PMC_SLP_S3# de-assertion 30us -min (15-25)
t6a : Core Well stable to DRAM_CORE_PWROK and PMC_CORE_PWROK assertion

(no PCIE device) 10ms -min (43-45)

t6b : Core Well stable to DRAM_CORE_PWROK and PMC_CORE_PWROK assertion
(for power rails needed by pcie device) 99ms -min (43-45)

t7 : DRAM/PMC_CORE_PWROK to PMC_SUS_STAT# 1ms -min (45-46)
t8 : PMC_SUS_STAT# de-assertion to PMC_PLTRST# de-assertion 60us -min (46-47)

a 10us to 2000us delay is required between rails to avoid inrush current caused by multiple loads
turning on simultaneously and fast charging of VR output decoupling

41

Quanta Computer Inc.

Quanta Computer Inc.

42

Size Document Number Rev

Size Document Number Rev

40

3

2

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Power Sequence

Power Sequence

Power Sequence

NL6

NL6

NL6

37 41Friday, April 25, 2014

37 41Friday, April 25, 2014

37 41Friday, April 25, 2014

1

1A

1A

1A

1

2

3

4

5

6

7

8

PP1800_PCH

38

2.2K2.2K

A A

SMBUS

AP2BH10
BG12

SMB_SOC_CLK
SMB_SOC_DAT

PP1800_PCH

XDP

Bay-trail M

BH22
BG23

I2C_0_SDA_C
I2C_0_SCL_C

4.7K4.7K

TRACK PAD

0x4bh

PP1800_PCH

4.7K4.7K

I2C_1_SDA_C

BG24

I2C_1_SCL_C

BH24

I2C

I2C_4_SDA_C

B B

BF27
BG27

I2C_4_SCL_C

Audio Codec

0x20h

PP1800_PCH

4.7K4.7K

ALS

0x44h

PP1800_PCH

4.7K4.7K

BH28
BG28

I2C_5_SDA_C
I2C_5_SCL_C

TOUCH SCREEN

0x4ah

PP3300_EC

C C

100

4.7K4.7K

Battery

100

EC_SMB0_CLK

E10

EC_SMB0_DATA

D3

Charger

PP3300_DX

KBC
TI

SMBUS

D D

1

F4

EC_SMB2_CLK

F3 EC_SMB2_DATA

2

3

4

4.7K4.7K

Thermal sensor

0x4ch

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

6

Date: Sheet of

7

PROJECT :

SMBUS_I2C

SMBUS_I2C

SMBUS_I2C

NL6

NL6

NL6

1A

1A

38 41Friday, April 25, 2014

38 41Friday, April 25, 2014

38 41Friday, April 25, 2014

8

1A

5

4

3

2

1

(G3/DSW)

I

EC

D D

PP3300_DSW_EN

EC

VREG5

EN1

PP3300_DSW
PP5000

EN2

Vin

PP5000_PGOOD

PWRGDPP5000_EN

TPS5122

VREG3

VIN

II

SUSP_VR_EN

EC

C C

III

EC

PP1350_EN

VSFR_EN

PP1000_PCH_S5

Vout

V1P0A

EN

TLV62130A

S5 EN

S3 EN

PWRGD

Vin

PP1350_PGOOD

PP1350 PWRGD

+VSM

TPS51216

Vin

PP5000_DSW

PP5000

S5_Vout

S3_Vout

(S3)

PP5000

(G3/DSW)

PP3300_DSW

(ALW)

PP3300_RTC

(S5) (S5)

PP1000_PCH_S5_PG PP1800_PCH_S5_PG

PP3300_DSWVIN

EC

S5_Vout

S3_Vout

PP1800_PCH_S5

Vout

V1P8A

EN

G9661-25

Vin

PP1350

(S3)

PP1350_VREF

+DDR_VTT_RUN

(S0IX)

(S3)

PWRGD

PP3300_PCH_S5_PG
HWPG_S5

PP3300_PCH_PG
ALL_S0_PG

PP1000_PCH_SX_PG
ALL_S0IX_PG

PP3300_DSW

VIN

EC_SLP_SX_L

(USB Charger)

EC

USB1_PWR_EN

EC

USB2_PWR_EN

V3P3A

EN Vout

TPS22930

Vin

PG0

EC_PWROK(PH2) DRAM_CORE_PWROK

EC

PC4

CORE_PWROK(PF5)

PL6

TPS2546

TPS2546

(S5)

PP3300_PCH_S5

PG3

USBPWR1

USBPWR2

HW_circuit
HWPG

PP3300_PCH_S5_PG

SOC

PMC_CORE_PWROK

PCH_SLP_SX_L

PP3300_DSW

PP3300_DX

EC

PCH

PCH

EC

EC

PP3300_DX_EN

PP3300_WLAN_EN

PP3300_LTE_EN

TP_SHDN_L

EC_EDP_VDD_EN

TPS22964CYZPR

TPS22930

TPS22965DSGR

TPS22930

G5243AT11U

39

(S0)

PP3300_DX

PP3300_WLAN

+3V_LTE

(S3)

TP_PWR

(S0)

LCDVCC

Vout

ISL95833

Vin

+VCORE

PGOODG

Vout

(S0)

IMVP_PWRGD_3V

+VGFX

PP1000_PCH

Vout

EN EN

+V1P0S

AON7400AL

(S0)

Vin

PP1000_PCH_S5

PWRGD

(S0)

PP1000_PCH_PG

VIN

PP1050_PCH

Vout

+V1P05S

TLV62150ARGTR

Vin

PWRGD

(S0)

PP1050_PCH_PG

PP1350

EN

PP1350_PCH

Vout

+V1P35S

AO3404

Vin

PWRGD

(S0)

PP1350_PCH_PG

PP3300_DSW

EN

PP1800_PCH

Vout

+V1P8S

G9661-25

Vin

PWRGD

(S0)

PP1800_PCH_PG

B B

IV

+VCORE / +VGFX

EC

VR_EN

EN

VIN

PP3300_PCH

A A

PP1800_PCH_PG

Vout

EN

+V3P3S

AO3404

PWRGD

Vin

PP3300_DSW

5

(S0)

PP3300_PCH_PG
ALL_S0_PG

EC

V

PP1050_PCH_PG

EC_SLP_SX_L

R

VSFR_EN

R

4

PP1350_PCH_SX

(S0iX)

PP1350

EN

Vout

+VSFR

MOS AO3404

Vin

HW_circuit
HWPG

VCORE_PWRGD

PP1350_PCH_SX_PG

3

R
R

V1P0SX_EN

PP1000_PCH

PP1000_PCH_SX

(S0iX)

Vout

EN

+V1P0SX

MOS AO3404

Vin

2

HW_circuit
HWPG

R

PP1000_PCH_SX_PG

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

BTM PWR CONTROL

BTM PWR CONTROL

BTM PWR CONTROL

NL6

NL6

NL6

39 41Friday, April 25, 2014

39 41Friday, April 25, 2014

1

39 41Friday, April 25, 2014

1A

1A

1A

5

Version

Model

10/11

1A

0CX

D D

C C

B B

A A

Change PU9 VCC, CLK, PG (Page 29)B01

B02

Change PU4 VCC, PG (Page 29)
Change PR29 from 100K/F_4 to 10K/F_4 (Page 32)B03

B04 Remove 15V, PR17. Mount PR16 (Page 34)

Remove 15V, PR72. Mount PR73 (Page 35)B05

10/14

Change U11 LVDS power switch footprint to sot23-5 (Page 17)B06

B07 Unstuff PR188 due to PP5000_PGOOD (PN0) is 5V tolerant input pin (Page 29)

10/16

B08

Change PJ1 from DFPJ06MR007 to DFHD05MR080 (Page 28)

10/17

Change C126 from *10U/6.3V_8 to *10U/6.3V_6 due to height limit (Page 24)B09
Change USB3.0 ESD D8,D9 route (Page 24)B10
Change R384 from 0_4 to 0_8, remove R376,R377. Merge UNCORE_V1P35_S0IX_A, UNCORE_V1P35_S0IX_B & UNCORE_V1P35_S0IX (Page 9)B11

B12 Change R354 from 0_4 to 0_8, remove R357. Merge CORE_V1P05_S3_PW, & CORE_V1P05. They are of the same power state and rail (Page 9)

10/18

B13

Correct BIOS Strap, mount R128 and dismount R434 (Page 4)

B14

Add R553 0_4, connect U12 pin 6 ALERT# to H_PROCHOT# (Page 5, 23)

B15 Change Y2 from BG332768224 to BG332768111 due to height limit, change C91,C92 from 18pf to 15pf (Page 6)

Add R554,R555 0_6 option S0 & S5 for PCU_V1P8_G3_V25 (Page 9)B16

B17 Change R469, EC_RST#_Q pull up from PP3300_DX to PP3300_DSW (Page 23)

Swap L4 vertically (Page 25)B18

B19 Power modified:

Change PD1 from BCMAJ22AZ00 to BCAFJ20AZ00 (Page 28)

10/21

B20

un-stuff R553 (Page 5)

B21

change SEL debugf footprint and PN(Page 18)

B22

change footprint and PN for HDMI (Page 19)

B23

change footprint and PN for USB3(Page 25)

B24

change footprint for Hole3,4,5,7 and add hole11(Page 25)

10/22

B25

un-stuff R182 for S5 leakage issue (Page 14)

B26

change thermal IC (Page 23)

B27

PJ1 pin1 change to VA (Page 28)

10/23

B28

unstuff R28 by Intel reques (Page 2)

B29

unstuff R29 by Intel reques (Page 3)

B30

RAM ID strap pin resistor change to 1K, would be stronger (Page 7)

B31

change cap C230 from 0.2pF to 3.3pF (Page 12)

B32

change cap C228 from 0.2pF to 3.3pF (Page 13)

B33

EC_IN_RW is OD,remove level shift and PU to PP1800_PCH (Page 15,26)
change NGFF E key footprint and PN (Page 20)

B34

change footprint for Hole3,4,5 and add 2 PAD for BATT_EN reserve (Page 25)

B35

SWAP L4 pin for layout (Page 25)

B36

SWAP RP1 pin for layout (Page 27)

B37

10/24

B38

change M_A_ODT0 PU to VTTby Intel request (Page 12)

B39

change M_B_ODT0 PU to VTTby Intel request (Page 13)

B40

correct schematic for R469 PU power rail (Page 23)

B41

SWAP L4 pin again for layout (Page 25)

B42

change footprint for Hole1,7,9 (Page 25)

10/25

B43

Delete complete SSD(connector and caps), unstuff R215 and add test points on SATA signals (Page 5,15,21)

B44

1025 add LTE SUSCLK feature (Page 6,15,23)

B45

the damping of SDIO change to 0 ohm by Intel request Page 16)

B46

add PU for SDIO WP by Intel request (Page 16)

B47

remove Q31 becasue PU to PP3300_DSW at EC side already (Page 23)

B48

change headphone CN6 footprint and PN (Page 24)

B49

stuff PR188 due to 3.3V to EC is more safe(Page 29)

B50

PR135 change from 300 to 348 ohm for proto1 issue (Page 33)

B51

PR155 change from 300 to 340 ohm for proto1 issue (Page 33)

B52

PC57 change from 68p to 120p PC50 change from 150p to 2200p for proto1 issue (Page 33)

B53 PC99 change from 68p to 120p PC106 change from 150p to 2200p for proto1 issue (Page 33)

10/29

B54

unstuff R128,R372,R386,R364 using SoC internal PU (Page 4,5)

B55

eDP power change to PIC fuse (Page 17)

B56

change R358 to 0 ohm by intel request( Page 21)

B57

remove pulled up resistors for eMMC data and cmd (Page 21)

10/30

B58

change C60 power netname for layout (Page 8)

B59

U10 change to 74AUP1G34 and stuff it (Page 11)

B60

remove PREQ# pulled up resistor R323( Page 11)

B61

stuff Q47,R531,R530 and un-stuff R533,R542 for Track Pad I2C (Page 15)

B62

HDMI DDC pulled up to HDMI_5V by intel request (Page 19)

B63

add Power LED for Intel testing (Page 22)

B64

Thermal IC VDD has two option, ome is PP3300_DSW(=PP3300_EC), another is PP3300_DX, default is stuffing to DSW rail( Page 23,27)

B65

add Power BTN for Intel testing(Page 27)

B66

for Gfx power, change C266,C289,C290 to 10uF and add 2 caps 10uF (Page 8)

B67

for core power, change C271,C281,C280,C278,C273 to 10uF( Page 8)

B68

for VR compensation, PR26 change to 16.9K,PR23 change 10 ohm,PC50 change 1200pF,PC40 change to 270pF,un-stuff PR22,PC54(Page 33)

B69 for VR compensation, PR76 change to 16.9K,PR86 change 10 ohm,PC106 change 1200pF,PC114 change to 270pF,un-stuff PR80,PC101(Page 33)

10/31

B70

remove TP44 and TP35 for GND vias adding (Page 8)

B71

remove C285( Page 9)

B72

N.C U10 pin1(Page 11)

B73

un-stuff PR129,PC37,PR158,PC118(Page 33)
stuff R273,R286,R289,R323 for Intel request(Page 11)

B74
B75

for layout suggestion by intel, VSS_AXG_SENSE didn't connect to VSS_SENSE, will connect the GND via near VCC_AXG_SENSE(Page 8)

B76

add 0.1u on PP1000_PCH for power request(Page 33)

B77

remove R417, PRDY should be direct connection between SoC and XDP by intel request (Page 6)

B78

for layout, add 0hm between GND and VSS_AXG_SENSE (Page 8)

11/1

B79

add option BOM R446,R449 for EC CLK for power saving by Intel request (Page 7)

B80

stuff C16(Page 11)
B81 correct C351 footprint(Page 16)
B82 change Hole4 footprint (Page 25)

11/4

Change PR135 from 348/F_4 to 340/F_4 (Page 33)B83

11/11

C01 Remove CH@ USB charge option,eMMC@ eMMC option (Page 25)
C02 Add CHB@ option for single channel SKU (Page 13)

11/15

C03 stuff R372, system can't boot if un-stuff R372 on proto1.5 board, need intel double confirm before proto2 (Page 4)
C04 stuff R386, it is required for eDP (Page4)
C05 U18 footprint change to 5 pin which is same as eDP power switch (Page 16)
C06 correct U11 orcad symbol, pin5 needs connect to power input (Page 17)
C07 remove R60 and change R74 to Short PAD and size to 0402 (Page 19)
C08

change R72/R73/R22 to short PAD(Page 19)
C09

PR128 change to 1.62K (Page 33)
C10 Revising block diagram (Page 1)

11/18

C11 add TP on pin38/73 for NFC function (Page 20)

11/21

C12 remove R28,R25,C35 (Page2)
C13 remove R29,R26,C36 (Page 3)
C14 by X'tal vender suggestion,change C105/C106 from 15pF to 12pF (Page 6)
C15 remove R22/R72/R73 (Page 19)
C16

remove R365(Page 21)
C17

remove R91,R92,R94,R85 for cancelling non USB charger SKU (Page 25)
C18 change USB3 CMC L5,L3, this part is recommended by Intel (Page 25)
C19 by X'tal vender suggestion, change C107/C109 from 15pF to 18pF (Page 27)

11/28

C20 add a connection and name to KBD_IRQ#, besides add pulled high resistor (Page6)
C21 remove R29,R26,C36 (Page 3)
C22 by X'tal vender suggestion,change C105/C106 from 15pF to 12pF (Page 6)
C23 remove R166, because SERIQR of TPM needs 3V (Page 14)
C24

reserve 0 ohm R387/R391 on VCCA and VCCB for debugging(Page 14)
C25

change HDMI CMC L2, this part is recommended by Intel (Page 19)
C26 remove HDMI EMI solution R30,R32,R40,R57 (Page 19)
C27 remove R358 by intel requst and has confirmed with EMI (Page 21)
C28 add pullup 10K on SERIRQ_R to TPM_VDD (Page 22)

11/29

C29 change PQ1,PQ2 part number (Page28)
C30 add and stuff 470pF on PC7 and reserve 4700pF on PC18 for EMI solution (Page 28)
C31 because of power source of PU24,PU25 change to VIN, so that need change sensing power net (Page 32)

PQ29 change MOSFET with lower Rdson(Page 32)

C32
C33

change solutions of PP1050_PCH and P1000_PCH_S5 ,which power sources are VIN, it is better for power efficiency (Page 32)

PP1000_PCH changes from convert to power MOSFET type for power efficiency improvement(Page 32)

C34

PP1350_PCH change from LDO to power MOSFET (Page 34)

C35

PP3300_PCH change from LDO to power MOSFET(Page 35)

C36
C37 Revising block diagram,power sequence, and power tree for power changes by Intel suggestion(Page 1,37,39)

12/02

add C285 for U18 input inrush current (Page16)C38
C39

PJ2 changes footprint for layout (Page 28)

change PC65 and PC39 from 4.7uF to 10uF (Page 32)C40

add PR169,PR49 for Intel request,stuff PR169 as default(Page 32)C41
C42 add PR166,PR46 for Intel request,stuff PR166 as default(Page 32)

PQ29 change back AO3404(Page 32)C43
C44 PQ13 change to lower Rdson part, besides source of PQ13 changes to PP1000_PCH_S5 (Page 32)
C45 revising pull up power rail of PR169 and PR166(Page 32)
C46 change L2,(HDMI CMC),L3,L5(USB3)to DLP11TB800UL2L as Intel's recommendation (Page 19,25)

12/04

for z-height issue, change C72,C75,C81 to 0.85mm cap (Page8)C47
C48

reserve 3x1000pF cap for EMI(Page 25)

change Hole1 to be battery enable function (Page 25)C49

for z-height issue changePC48,PC49 to 0.85mm cap(Page 29)C50
C51 del PAD1 and PAD2(Page 25)

12/05

add 0.1uFx2 on PP1350 for EMI request (Page12)C52
C53

To prevent the backlight flash, add a pull down on SoC_EDP_BLON_C and using double inverting OD FETs structure(Page 15)

R551 changes to 1K to isolate SD socket and servo/SoC (Page 16)C54

SD3_WP is 1.8V power rail in SoC,change external Pulled up power well of SD3_WP to 1.8V power(Page 16)C55
C56 L2 change back to DLP11SA900HL2(Page 19)
C57 Swap L3,L5 pin for layout smoothly(Page 25)

12/06

change PU16,PU17 part number(Page 28)

C58
C59 change C271,C273,C280,C266,C311,C315 to 0603 22uF for ACLL issue(Page 8)

12/09

reserve R220connection from RCVP to MIC_DET as back up in case driver needs to be through codec using JACKSNS pinr(Page 24)

C60
C61 remove JP9,JP13 for ACLL improvement(Page 33)

12/11

add pulled up resistors on SDIO data/cmd lines (Page16)C62
C63

add back pulled up resistors for eMMC I/F(Page 21)

co-layout ST and Infineon TPM, if change to ST,R56,R57,R60,R72,R38, ST PN is ST33ZP24AR28PVSM(Page 22)C64

change footprint for Hole9(Page 25)C65
C66 move EC_PWROK from PH2 to PJ1(Page 27)
C67 add Test points on unused pins, need check layout to see if all points are ok(Page 27)

12/12

add new RAMID 101 for single channel SKU (Page7)C68
C69

all Pulled up resistors of SDIO data/cmd to be un-stuffed(Page 16)

all Pulled up resistors of eMMC data/cmd to be un-stuffed,and R361 change to 47K ohm as well(Page 21)C70

add 2 holes , leave N.C(Page 25)C71

Stuff NUT on Hole4,5(Page 25)C72

change part number of EC ,which has a trial firmware inside(Page 27)C73

reserve PR170 for battery cell selection(Page 28)C74
C75 stuff PC211(Page 28)

12/13

swap CLKREQ_WLAN and CLKREQ_IMAGE for CLKREQ and CLK pins are aligned (Page5)C76
C77

change pull up power of PP3300_PCH_PG to PP3300_EC (Page 35)

Board ID of proto2 change to 001 (Page27)

C78
C79

un-stuff PR176,PC202 as snubber isnt needed (Page 28)

un-stuff PR74,PC104,PR81,PC115 as snubber isnt needed (Page33)C80

01/15

change CN15 USB3.0 connector typeC81

change CN6 Audio Jack connector typeC82

change CN2 HDMI connector typeC83

01/27

C84 change CN8 Keyboard connector type

02/10

unstuff U20, R156, R387, R391, R353 for SERIRQ leakage issue (Page14,22)C85

4

CHANGE LIST

3

2

1

40

PROJECT MODEL

DOC NO.

Chrome APPROVED BY:

:
PART NUMBER: DRAWING BY: REVISON:

5

4

Quanta Computer Inc.

Quanta Computer Inc.

DATE:

3

2

Quanta Computer Inc.

PROJECT :

NL6

PROJECT :

NL6

PROJECT :

Change list-1

Change list-1

Change list-1

NL6

40 41Friday, April 25, 2014

40 41Friday, April 25, 2014

40 41Friday, April 25, 2014

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1A

1A

1A

5

4

3

2

1

Model

NL6

D D

C C

Version

2/20

PVT1

1. un-stuff R156 for SERIRQ skipped (Page14)

2. change power rail of Q35,Q36,Q37,Q44 from PP1800_PCH_S5 to PP1800_PCH for PP1800_PCH leakage issue in S3 mode (Page14)
unstuff R337 for S3 leakage issue(Page 11)3.
Delete LED2, R127 (Page 22,27)

4.

5. Change LED1 type to right angle , same as 0C7 (Page22)
unstuff R454,Q33,Q144 for auto power on issue when insert battery first time(Page 26)

6.
change PR130 to 124K ohm for efficiency improvement (Page 33)

7.
change PL7/PL4 to 0.47uH and PR30/PR62 to 0ohm for efficiency improvement (Page 28)8.
unstuff NUT of Hole4,Hole5(Page 25)9.

3/19

PVT2

1. Disconnect SPI SIO I/F (Page6, 27)

2. Delete SPI_SIO Interface,Q35,Q36,Q37,Q44,R486,R484,R485,R483,R426,R429,R427,R428 (Page14)

3. reserve C377 on SD CLK for EMI (Page 5)

4.

reserve R483 for CLKRUN# disable (Page 7)
change level shifter of PMC_SUSCLK1,LTE_DISABLE#,LTE_WAKE#,PMC_SUSCLK0,SOC_PMC_WAKE#,WIFI_DISABLE# to double inverter for S3 leakage issue (Page 15)

5.
stuff C372 for EMI issue(Page 16)

6.
add PD13 for S3 leakage(Page 28)

7.
reserve C330 for EMI request (Page 25)8.
reserve placeholder R212,R218 for additional RAM ID (Page 7)9.

10. change bi-direction level shifter of LTE_DISABLE#,LTE_WAKE#,
SOC_PMC_WAKE#,WIFI_DISABLE# to double inverter for S3 leakage issue, and PMC_SUSCLK0 and
PMC_SUSCLK1 to buffer type (Page 15)

11. Reserve load switch(U1007,C391,R623) for touch screen power(Page 17)

12. reserve R91 0 ohm on SIM_DET line for difference design of various cards(Page 15)

13. Change below 0 ohm to short pad for cost saving:
0402: R180,R197,R204,R123,R131,R139,R455,R462,R103,R414,R383,R375,R381,R379,R183,R452,R457,R58,R165,R468,R448,R107,R424,
R449,R343,R385,R54,R378,R380,R430,R456,R110,R114,R121,R395,R400,R407,R453,R464,R460,R319,R320,R332,R263,R333,R171,R174,
R137,R10,R11,R13,R326,R341,R339,R20,R46,R411,R51,R60,R72,R57,R370,R67,R194,R244,R390,R213,R546,R227,R173,R169
0603: R116,R157,R193,R555,R14,R224,R355,R229,R232,R235,R241,R217,L7,R206
0805: R354,R384,R17,R39

Change LED1 to Green/Orange14.
Change C78 to 220uF15.
Add C393 2.2uF at Q33 pin2, change R414 to 1Mohm16.
Add D23 for Pp500017.

CHANGE LIST

41

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

Change list-2

Change list-2

Change list-2

0C2A

0C2A

0C2A

1

1A

1A

1A

41 41Friday, April 25, 2014

41 41Friday, April 25, 2014

41 41Friday, April 25, 2014